Unit 5

Basic I/O, Memory R/W and Interrupt Operations

 Memory mapped I/O, I/O Mapped I/O and Hybrid I/O
 Direct Memory Access (DMA)
o Introduction, Advantage and Application
o 8237 DMA Controller and Interfacing
 Interrupt
o 8085 Interrupt Pins and Priority
o Maskable and Non-maskable Interrupts
o RST Instructions
o Vector and Polled Interrupt
 8259 Interrupt Controller
o Block Diagram and Explanation
o Priority Modes and Additional Features

Memory mapped I/O, I/O Mapped I/O and Hybrid I/O

 As a CPU needs to communicate with the various memory and input-output devices (I/O) as we know data between
the processor and these devices flow with the help of the system bus.

 There are three ways in which system bus can be allotted to them:
1. Separate set of address, control and data bus to I/O and memory.
2. Have common bus (data and address) for I/O and memory but separate control lines.
3. Have common bus (data, address, and control) for I/O and memory.
 In first case it is simple because both have different set of address space and instruction but require more buses

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 Memory Mapped I/O
 In memory mapped I/O, every bus is common due to which the same set of instructions work for memory
and I/O. Hence, we manipulate I/O same as memory and both have same address space, due to which
addressing capability of memory become less because some part is occupied by the I/O.

 In Memory Mapped Input Output,

 We allocate a memory address to an Input-Output device.
 Any instructions related to memory can be accessed by this Input-Output device.
 The Input-Output device data are also given to the Arithmetic Logical Unit.
I/O Mapped I/O

 It is also known as Isolated I/O mapping and the reason for the same is that here the address space of
memory and I/O are separated from each other.
 I/O mapped I/O have common bus (data and address) for I/O and memory but separate read and write
control lines for I/O.

 So when CPU decode instruction then if data is for I/O then it places the address on the address line and
set I/O read or write control line on due to which data transfer occurs between CPU and I/O.
 As the address space of memory and I/O is isolated and the name is so.
 The address for I/O here is called ports. Here we have different read-write instruction for both I/O and
memory.

 Input-Output Mapped Input Output,

 We give an Input-Output address to an Input-Output device
 Only IN and OUT instructions are accessed by such devices.
 The ALU operations are not directly applicable to such Input-Output data.

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Example:
 Let's take an example of the 8085 processor. It has 16 address lines i.e. addressing capacity of 64 KB
memory. It supports I/O-mapped I/Os. It can address up to 256 I/Os.
 If we connect I/Os to it an I/O-mapped I/O then, it can address 256 I/Os + 64 KB memory. And special
instructions IN and OUT are used to access the peripherals. Here we fully utilize the addressing capacity
of the processor.
 If the peripherals are connected in memory mapped fashion, then total devices it can address is only
64K. This is underutilization of the resource. And only memory-accessing instructions like MVI, MOV,
LOAD, SAVE are used to access the I/O devices.
Hybrid I/O
 Combination of both previous I/O.
 Uses same address in some cases and two address space in some cases.

Difference between Memory-Mapped I/O Interfacing and I/O Mapped I/O Interfacing:

Direct Memory Access (DMA)

 DMA Transfer is a hardware controlled I/O Transfer technique. It is mainly used for high-speed block of
data transfer between I/O and Memory where the speed of the peripheral is generally faster than the µP.
 It is a method that allows an input/output (I/O) device to send or receive data directly to or from the main
memory, bypassing the CPU to speed up memory operations.
 The processor relinquishes the system bus for a few clock cycles. So, the DMA controller can
accomplish the task of data transfer via the system bus.
 In Program Controlled I/O, Status or interrupt driven I/O the speed of transfer is slow mainly because
instructions need to be decoded and then executed for the transfer. DMA transfer is software independent
and hence much faster.
 A device known as the DMA Controller (DMAC) is responsible for the DMA transfer

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  The below diagrams illustrates the DMA Controller System.

Fig: DMA
 DMA is a process of communication for data transfer between memory and input/output, controlled by an external
circuit called DMA controller, without involvement of CPU.
 8085 MP has two pins HOLD and HLDA which are used for DMA operation.
 First, DMA controller sends a request by making Bus Request (BR) control line high. When MP receives high
signal to HOLD pin, it first completes the execution of current machine cycle, it takes few clocks and sends HLDA
signal to the DMA controller.
 After receiving HLDA through Bus Grant (BG) pin of DMA controller, the DMA controller takes control over
system bus and transfers data directly between memory and I/O without involvement of CPU. During DMA
operation, the processor is free to perform next job which does not need system bus.
 At the end of data transfer, the DMA controller terminates the request by sending low signal to HOLD pin and
MP regains control of system bus by making HLDA low.

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 Fig: DMA Transfer

Advantages, Disadvantages & Applications of DMA

Advantages
 DMA allows a peripheral device to read from/write to memory without going through the CPU.
 DMA allows faster processing since the processor can be working on something else while the peripheral can be
populating memory.
 DMA enables more efficient use of interrupts.
 High transfer rates.
 DMA capable device can communicate directly with memory.
 Used in disk controllers, video/sound cards, printers etc., or between memory locations.

Disadvantages
 Cost of DMA hardware.
 Data has to be stored in continuous memory locations.
 DMA controller is slow in comparison to CPU.

Application of DMA
 DMA has been a built-in feature of PC architecture since the introduction of the original IBM PC.
 PC-based DMA was used for floppy disk I/O in the original PC and for hard disk I/O in later versions.
 PC-based DMA technology, along with high speed bus technology, is driven by data storage, communications, and
graphics needs-all of which require the highest rates of data transfer between system memory and I/O devices.
 Applications areas are: cinemas, theatres, hotels, railway stations, shopping centres, trade shows, museums & many
more.

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8237A DMA Controller

Features of 8237

 8237 is a programmable, high speed, Direct Memory Access (DMA) controller housed in a 40-pin package.

 It is actually a special-purpose microprocessor which is specially designed by Intel to transfer high-speed

data between memory and I/O
 It has four independent channels with each channel capable of transferring 64K bytes.
 It ia compactable with 8085,8088 and 8086 microprocessors.
 It is an I/O device to MPU.
 It is a data transfer processor for peripheral device.
 he 8237 is capable of DMA transfers at rates of up to 1.6 megabytes per second.
 Many of its signals that are input in the I/O mode become outputs in the processor mode
 The pin diagram of 8237A is as follows

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 AEN Address Enable
DACK DMA Acknowledgement
VCC +5-volt power supply
Vss Ground
NC Not Connected
CLK Input Clock Input controls the internal operations of the 8237A and its rate of data
transfers. The input may be driven at up to 5 MHz for the 8237A-5.

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Block diagram of 8237 DMA Controller
 The block diagram shows a logical pin out and internal registers of the 8237.
 It also shows the interface with the 8085 using a 3-to-8 decoder
 8237 has four independent channels CH0-CH3. Two 16-bit registers are internally associated with each channel
 These registers are determined by A3-A0 and the chip select line (CS)

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 The 8237 signals are divided into two groups:
1) signals on left (used to communicate with MPU)
2) signals on right (used to communicate with peripheral)
 Some of these signals are bidirectional and are determined by the DMA mode of operation (I/O or processor mode).
 To obtain DMA service, a request is generated by activating the DREQ line of the channel.
 DACK are output lines to inform the individual peripherals that DMA is granted. DREQ and DACK are equivalent
to handshake signals in I/O devices.
 AEN and ADSTB-Address Enable and Address Strobe are used to latch a high-order byte to generate a 16-bit
address.
 After receiving the HRQ (Hold request), the MPU completes the bus cycle in process and issues the HLDA (Hold
Acknowledgement) signal.
 When a transfer begins, the DMA places the low-order byte on the address bus and high-order byte on the data bus.
 Then 8237 asserts AEN (Address Enable) and ADSTB (Address Strobe).
 These two signals are used to latch the high-order byte from the data bus and 8237 places the 16-bit address on the
system bus.

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Interfacing 8237 with 8085
 Initially, when any device has to send data between the device and the memory, the device has to send DMA
request (DRQ) to DMA controller. The DMA controller sends Hold request (HRQ) to the CPU and waits for the
CPU to assert the HLDA. Then the microprocessor tri-states all the data bus, address bus, and control bus.
 8085 MP has two pins HOLD and HLDA which are used for DMA operation. First, DMA controller sends a
request by making Bus Request (BR) control line high. When MP receives high signal to HOLD pin, it first
completes the execution of current machine cycle, it takes few clocks and sends HLDA signal to the DMA
controller.

Interrupt Structure in 8085

 It is the process initiated by giving a signal by external devices / instruction in the main program, in which the
microprocessor shifts the control from main program to execute a special program.
 During Interrupt an external device can get the attention of the microprocessor.
 The process starts from the I/O device
 The process is asynchronous.
 Interrupt is signals send by an external device to the processor, to request the processor to perform a particular task
or work.
 Mainly in the microprocessor based system the interrupts are used for data transfer between the peripheral and the
microprocessor.
 The processor will check the interrupts always at the 2nd T-state of last machine cycle.
 If there is any interrupt it accepts the interrupt and send the INTA (active low) signal to the peripheral.

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  Diagrammatically, we can show the 8085 interrupts as follows

 Each interrupt will most probably have its own ISR.

 The vectored address of particular interrupt is stored in program counter.

 The processor executes an interrupt service routine (ISR) addressed in program counter.
 It returned to main program by RET instruction.

Flow chart of Interrupt:

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 Types of Interrupts:
 It supports two types of interrupts.
1. Hardware interrupts
2. Software interrupts

1. Hardware interrupts:
 An external device initiates the hardware interrupts and placing an appropriate signal at the interrupt pin of the
processor.
 If the interrupt is accepted, then the processor executes an interrupt service routine.
 The 8085 has five hardware interrupts:
(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 and (5) INTR

Fig 2 shows interrupt with Vector Address.

TRAP:
 This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable.
 TRAP has the highest priority and vectored interrupt.
 TRAP interrupt is edge and level triggered. This means that the TRAP must go high and remain high until it is
acknowledged.
 In sudden power failure, it executes a ISR and send the data from main memory to backup memory.
 The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD and TRAP at the same
time then HOLD is recognized first and then TRAP is recognized).

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  TRAP is usually used for power failure and emergency shutoff.
 There are two ways to clear TRAP interrupt.
o By resetting microprocessor (External signal)
o By giving a high TRAP ACKNOWLEDGE

RST 7.5:
 The RST 7.5 interrupt is a maskable interrupt.
 It has the second highest priority.
 It is edge sensitive. i.e. Input goes to high and no need to maintain high state until it recognized.
 Maskable interrupt.
 It is disabled by,
o DI instruction
o System or processor reset, After reorganization of interrupt.
 Enabled by EI instruction.

RST 6.5 and 5.5:

 The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
 The RST 6.5 and RST 5.5 both are level triggered i.e. Input goes to high and stay high until it recognized.
 Maskable interrupt.
 It is disabled by, DI, SIM instruction.
 Enabled by EI instruction.

INTR:
 INTR is a maskable interrupt. It is disabled by,
o DI, SIM instruction
o Enabled by EI instruction.
 Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the address of ISR.
 It has lowest priority.
 It is a level sensitive interrupts. i.e. Input goes to high and it is necessary to maintain high state until it recognized.
 The following sequence of events occurs when INTR signal goes high.
1. The 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal is high, then 8085 complete its current instruction and sends active low interrupt acknowledge
signal, if the interrupt is enabled.
3. In response to the acknowledge signal, external logic places an instruction OPCODE on the data bus.
In the case of multi byte instruction, additional interrupt acknowledge machine cycles are generated by
the 8085 to transfer the additional bytes into the microprocessor.
4. On receiving the instruction, the 8085 save the address of next instruction on stack and execute received
instruction.
 The hardware Interrupts can be further classified into two types:

 Maskable Interrupts (Can be delayed or Rejected)

 Non-Maskable Interrupts (Cannot be delayed or Rejected)
2. Software interrupts:
 The software interrupts are program instructions. These instructions are inserted at desired locations in a program.
 The 8085 has eight software interrupts from RST 0 to RST 7.
 The vector address for these interrupts can be calculated as follows.
Interrupt number * 8 = vector address
For RST 5.5 * 8 = 40 = 28H
Thus, Vector address for interrupt RST 5 is 0028H
 It can control 8 devices.

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  The Table shows the vector addresses of all interrupts.

 Interrupts can also be classified into:

o Vectored (the address of the service routine is hard-wired)
o Non-vectored (the address of the service routine needs to be supplied externally by the device)

Summary of Hardware Interrupt is tabulated below

Vectored and Polled Interrupt

Vectored Interrupt
 In a computer, a vectored interrupt is an I/O interrupt that tells the part of the computer that handles I/O interrupts
at the hardware level that a request for attention from an I/O device has been received and also identifies the device
that sent the request.

Fig: Vectored Interrupt

 The device is connected in a chain as shown in figure above for setting up the priority systems.
 Suppose that one or more devices interrupt the processor at a time. In response, the processor saves its current status and
then generates an interrupt acknowledge (INTA) signal to the highest priority device, which is device1, in this case.
 If this device has generated the interrupt, it will accept the INTA signal from the processor; otherwise, it will pass INTA
on to the next device until INTA is accepted by the interrupting device.

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Polled Interrupt

Fig: Polled Interrupt

 In a computer, a polled interrupt is a specific type of I/O interrupt that notifies the part of the computer containing the
I/O interface that a device is ready to be read or otherwise handled but does not indicate which device. The interrupt
controller must poll (send a signal out to) each device to determine which one made the request.
 Polled interrupts are handled using mostly software and are therefore slower compared to vectored (hardware) interrupts.
The processor responds to an interrupt by executing one general service routine for all devices. The priority of these
devices is determined by the order in which the routine polls each device. Once the processor determines the source of
interrupt, it branches to the service routine for that device. The typical configuration of the polled interrupt is shown in
figure above.
 As shown in figure, several external devices (Device1, Device2,…….., Device N) are connected to a single interrupt
line (INT) of the processor. When one or more devices activate the INT line high, the processor saves the content of the
PC and other registers and then branches to an address defined by the manufacturer of the processor. The user can write
a program at this address in order to poll each device starting with highest priority device in order to find the source of
the interrupt.
 Polled interrupts are very simple. But for a large number of devices, the time required to poll each device may exceed
the time to service the device.

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Programmable Interrupt Controller: The 8259A
 The 8259A is a programmable interrupt-managing device, specifically designed for use with the interrupt
signals (INTR/INT) of the 8085 MP.
Features
 It manages 8 interrupt requests.
 It can vector an interrupt request anywhere in the memory map through program control without additional hardware
for restart instructions. However, all 8 requests are spaced at the interval of either 4 locations or 8 locations.
 It can solve 8 levels of interrupt priorities in a variety of modes.
 With cascading additional 8259A devices, the priority scheme can be expanded to 64 levels.
 The 8259A has the abilities such as reading the status and changing the interrupt mode during a program execution.
 It can mask each interrupt request individually.
 It can be set up to work with either the 8085 MP mode or the 8086/8088 MP mode.

 The 8259A block diagram includes control logic, registers for interrupt requests, priority resolver, cascade logic, and
data bus. The registers manage interrupt requests; the priority resolver determines their priority. The cascade logic is
used to connect additional 8259A devices.

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 Fig: Block Diagram of 8259A PIC
Operation of 8259A
 The following steps take place during the operation of 8259A:
i One or more interrupt request lines go high requesting the service.
ii The 8259A resolves the priorities and sends an INT signal to the MP.
iii The MP acknowledges the interrupt by sending INTA(bar).
iv After the INTA(bar) has been received, the op-code for the call instruction (CDH) is placed on the data bus.
v Because of the CALL instruction, the MP sends two more INTA(bar) signals.
vi At the first INTA(bar), the 8259A places the low-order 8-bit address on the data bus and at the second INTA(bar),
it places the high-order 8-bit address of the interrupt vector. This completes the 3- byte CALL instruction.
vii The program sequence of the MP is transferred to the memory location specified by the CALL instruction.
1) Interrupt Request Register (IRR)
 8259 has 8 interrupt input lines IR7 … IR0.
 The IRR is an 8-bit register having one bit for each of the interrupt lines.
 When an interrupt request occurs on any of these lines, the corresponding bit is set in the Interrupt Request Register
(IRR).
2) In-Service Register (InSR)
 It is an 8-bit register, which stores the level of the Interrupt Request, which is currently being serviced.
3) Interrupt Mask Register (IMR)
 It is an 8-bit register, which stores the masking pattern for the interrupts of 8259. It stores one bit per interrupt level.
4) Priority Resolver
 It examines the IRR, InSR, and IMR and determines which interrupt is of highest priority and should be sent to the
µP.
5) Control Logic
 It has INT output connected to the INTR of the µP, to send the Interrupt to µP. It also has the INTA input signal
connected to the INTA of the µP, to receive the interrupt acknowledge. It is also used to control the remaining
blocks.
6) Data Bus Buffer
 It is a bi-directional buffer used to interface the internal data bus of 8259 with the external (system) data bus.

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7) Read/Write Logic
 It is used to accept the RD, WR, A0 and CS signal. It also holds the Initialization Command Words (ICW's) and
the Operational Command Words (OCW's).
8) Cascade Buffer / Comparator
 It is used in cascaded mode of operation.
 It has two components:
i.CAS2, CAS1, CAS0 lines:
 These lines are output for the master, input for the slave.
 The Master sends the address of the slave on these lines (hence output).
 The Salves read the address on these lines (hence input).
 As there are 8 interrupt levels for the Master, there are 3 CAS lines (23 = 8).
ii. SP / EN (Slave Program/Master Enable): BOTH ACTIVE LOW SIGNAL
 In Buffered Mode, it functions as the EN line and is used to enable the buffer.
 In Non buffered mode, it functions as the SP output line.
 For Master 8259 SP should be high, and for the Slave SP should be low

Priority modes
1. Fully Nested Mode(FNM)
 It is the default mode of 8259.
 It is a fixed priority mode.
 IR0 has the highest priority and IR7 has the lowest priority.
 It is preferred for “Single” 8259.
2. Special Fully Nested Mode (SFNM)
 This mode can be used for the Master 8259 in a cascaded configuration.
 Its priority structure is fixed and is the same as FNM (IR0 highest and IR7 lowest).
 Additionally, in SFNM, the Master would recognize a higher priority interrupt from a slave, whose
another interrupt is currently being serviced. This is possible only in SFNM.
3. Rotating Priority Modes
 There are two rotating priority modes: Automatic Rotation and Specific Rotation
 Automatic Rotation Mode
o This is a rotating priority mode.
o It is preferred when several interrupt sources are of equal priority.
o In this mode, after a device receives service, it gets the lowest priority.
o All other priorities rotate subsequently.
o Eg: If IR2 is has just been serviced, it will get the lowest priority.
 Specific Rotation Mode
o It is also a rotating priority mode, but here the user can select any IR level for lowest priority,
and thus fix all other priorities.
4. Special Mask Mode (SMM)
 Usually 8259 prevents interrupt requests lower or equal to the interrupt, which is currently in service.
 In SMM 8259 permits interrupts of all levels (lower or higher) except the one currently in service.
 As we are specially masking the current interrupt, it is called Special Mask Mode.
 This mode is preferred when we don’t want priority

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