L-8

Interrupt in 8085 Micro-Processor

1 Introduction
The interrupt allows the processor to
execute programs when an I/O device
needs attention, it asserts an interrupt signal
which is an input to the CPU.

What the CPU does?

• Recognise that an interrupt has occurred.

• Determine interrupting device.
• Switch control to the interrupt handler.
• When finished, return execution to the
interrupted program
• CPUs commonly check for an interrupt at
the end of each execution cycle.
• The state of the current program must be
saved, usually on the stack.
• Execute the interrupt handler.
• Return from interrupt instruction causes the
state of the interrupted program to be
restored.
2 Stack and Subroutines

The stack is an area of memory identified by

the programmer for
temporary storage of evidence.
The stack is a LIFO structure. – Last In First Out.

Given that the stack grows backwards into

memory, it is customary to place the bottom of the
stack at the end of memory to keep it as far away
from user programs as possible.

In the 8085, the stack is defined by setting the SP

(Stack Pointer) register

Interrupt

3 Operation of the Stack

LXI SP, FFFFH Information is saved on the
stack by pushing it on. It is retrieved from the
stack by Popping it off. The 8085 provides two
instructions: PUSH and POP for storing
information on the stack and retrieving it back.
Both PUSH and POP work with register pairs
ONLY. During pushing, the stack operates in a
“decrement then store” style. The stack pointer is
decremented first, then the information is placed
on the stack. During popping, the stack operates
in a “use then increment” style. The information
is retrieved from the top of the stack and then the
pointer is incremented. The SP pointer always
points to “the top of the stack”. The order of
PUSHs and POPs must be opposite of each other
in order to retrieve information back into its
original location.
PUSH B
PUSH D
4 Interrupts in 8085

Interrupts are the signals generated by the

external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e.
TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.

Interrupt are classified into following groups

based on their parameter −

Vector interrupt − In this type of interrupt, the

interrupt address is known to the processor. For
example: RST7.5, RST6.5, RST5.5, TRAP.

Non-Vector interrupt − In this type of interrupt,

the interrupt address is not known to the processor
so, the interrupt address needs to be sent
externally by the device to perform interrupts.

For example: INTR.

• The RTE Instruction

 • RTE – Retrieve the return address from the top
of the stack – Load the program counter with the
return address.
The 8085 has multilevel interrupt system. It
supports two Types of 8085 Interrupts:
• Hardware interrupt
• Software interrupt
Some pins on the 8085 allow, peripheral device to
interrupt the main program for I/O operations. •
When an interrupt occurs, the 8085 completes the
instruction it is currently executing and transfers
the program control to a subroutine’ that services
the peripheral device.
Upon completion of the service routine, the CPU
returns to the main program. These types of Types
of 8085 Interrupts, where CPU pins are used to
receive interrupt requests, are called hardware
interrupts.
• The 8085 has five hardware interrupts:
(a) TRAP
(b) RST 7
(c) RST 6
(d) RST 5
(e) INTR
When any of these pings, except INTR, is active,
the internal control circuit of the 8085 produces a
CALL to a predetermined memory location.
This memory location, where the subroutine
starts is referred to as vector location and such
interrupts are called vectored interrupts.
The INTR is not a vectored interrupt. It receives
the address of the subroutine from the external
device.
• The Types of 8085 Interrupts except TRAP are
maskable.
When logic signal is applied to a maskable
interrupt input, the 8085 is interrupted only if that
particular input is enabled. These interrupts can
be enabled or disabled under program control. If
disabled, 8085 disables an interrupt request. It is
unaffected by any mask or interrupt enable.

• TRAP has the highest priority. TRAP interrupt

is edge and level triggered. This means that the
TRAP must go high and remain high until it is
acknowledged. This avoids false triggering
caused by noise and transients.
• The interrupt TRAP is non maskable which
means that it is not maskable by program control.
• TRAP: This Types of 8085 Interrupts is a non-
maskable interrupt.
• TRAP: This Types of 8085 Interrupts is a non-
maskable interrupt.
• It is unaffected by any mask or interrupt enable.
• TRAP has the highest priority. TRAP interrupt
is edge and level triggered as in Fig 5.3. • This
means that the TRAP must go high and remain
high until it is acknowledged.
• This avoids false triggering caused by noise and
transients.
After recognition of TRAP interrupt.
• Thus RST 7.5, RST 6.5, RST 5.5 and INTR are
enabled using EI instruction. It is important to
note that when any interrupt is acknowledged,
interrupt enable flip flop resets and disables all
interrupts.
• To enable interrupt in further process it is
necessary to execute EI instruction within
interrupt service routine.
• DI: Disable Interrupt
The DI instruction resets the interrupt enable flip
flop, as shown in Fig. 5.2. Thus, it disables RST
7.5, RST 6.5, RST 5.5 and INTR interrupts.

• EI: Enable Interrupt

The EI instruction sets the interrupt enable flip
flop, as shown in Fig. 5.2.
Thus RST 7.5, RST 6.5, RST 5.5 and INTR are
enabled using EI instruction. It is important to
note that when any interrupt is acknowledged,
interrupt enable flip flop resets and disables all
interrupts. To enable interrupt in further process it
is necessary to execute EI instruction within
interrupt service routine.
• DI: Disable Interrupt The DI instruction resets
the interrupt enable flip flop, as Thus it disables
RST 7.5, RST 6.5, RST 5.5 and INTR interrupts.
1-SIM: Set Interrupt Mask This instruction is
used to set interrupt mask and to send serial
output.
It transfers the contents of accumulator to
interrupt control logic and serial I/O port. Thus, it
is necessary to load appropriate contents in the
accumulator before execution of SIM instruction.
2-SIM Instruction Format:
• Bits 0 – 2 will set/reset the mask bits for RST
5.5, RST 6.5, and RST 7:5 of the interrupt mask
register.
• Bit 3 enables the functioning of bits 0 – 2. It
enables or disables the masking control.
• Bit .4 is used to reset RST 7.5 request;
regardless of whether RST 7.5 is masked.
• Bit 5 is don’t care.
• Bit 6 enables the serial output if it is set. Bit 7
decides the data to be sent on the serial output pin
of 8085
Table 1 shows the summary of hardware
interrupts in 8085.
Bits 0-2 give the status of interrupt mask. Logic 1
indicates the interrupt is masked. Bit 3 gives the
status of interrupt enable flag. If 1, interrupts are
enabled. Bits 4-6 give the status of pending
interrupts. Bit 7 gives the status of serial input
data line.
Pending Interrupts:
• RIM:
Read Interrupt Mask The Read Interrupt Mask,
RIM, instruction loads the status of the interrupt
mask, the pending interrupts and the contents of
the serial input data line, SID, into the
accumulator.
Thus, it is possible to monitor status of interrupt
mask, pending interrupts and serial input. There
are number of Types of 8085 Interrupts. When
one interrupt is being serviced, other interrupt
requests may occur.
If the interrupt requests are of higher priority,
8085 branches program control to the requested
interrupt service routines. But when the interrupt
requests are of lower priority, 8085 stores the
information about these interrupt requests. Such
interrupts are called pending interrupts. The
status of pending interrupts can be monitored
using RIM instruction
Bits 0-2 give the status of interrupt mask.
• Logic 1 indicates the interrupt is masked.
• Bit 3 gives the status of interrupt enable flag. If
1, interrupts are enabled.
• Bits 4-6 give the status of pending interrupts.
• Bit 7 gives the status of serial input data line.
When none of the key is pressed, all input lines
are high and the output of 8 input NAND gate is
low. • If any key is pressed, the status of that line
becomes zero and the NAND gate output goes
high
which gives the interrupt signal to the 8085. Then
microprocessor executes the interrupt service
routine to check which key is pressed.
In this system, it is not necessary for
microprocessor to check whether key is pressed
or not in between the program execution. Here,
when key is pressed interrupt is automatically
generated and it initiates I/O data transfer so it is
referred as interrupt driven I/O.
- Maskable interrupt
In this type of interrupt, we can disable the
interrupt by writing some instructions into the
program.

For example: RST7.5, RST6.5, RST5.5.

- Non-Maskable interrupt
In this type of interrupt, we cannot disable the
interrupt by writing some instructions into the
program.

For example: TRAP.

- Software interrupt
In this type of interrupt, the programmer has to
add the instructions into the program to execute
the interrupt. There are 8 software interrupts in
8085, i.e. RST0, RST1, RST2, RST3, RST4,
RST5, RST6, and RST7.
- Hardware interrupt
There are 5 interrupt pins in 8085 used as
hardware interrupts, i.e. TRAP, RST7.5, RST6.5,
RST5.5, INTA.
Note − INTA is not an interrupt, it is used by the
microprocessor for sending acknowledgement.
TRAP has the highest priority, then RST7.5 and
so on.
- Interrupt Service Routine (ISR)
Interrupt Service Routine (ISR)
A small program or a routine that when
executed, services the corresponding
interrupting source is called an ISR.
- TRAP
• It is a non-maskable interrupt, having the
highest priority among all interrupts. By default,
it is enabled until it gets acknowledged. In case of
failure, it executes as ISR and sends the data to
backup memory. This interrupt transfers the
control to the location 0024H.
- RST7
It is a maskable interrupt, having the second
highest priority among all interrupts. When this
interrupt is executed, the processor saves the
content of the PC register into the stack and
branches to 003CH address.
- RST
It is a maskable interrupt, having the third highest
priority among all interrupts. When this interrupt
is executed, the processor saves the content of the
PC register into the stack and branches to 0034H
address.

- RST 5
It is a maskable interrupt. When this interrupt is
executed, the processor saves the content of the
PC register into the stack and branches to 002CH
address.
- INTR
It is a maskable interrupt, having the lowest
priority among all interrupts. It can be disabled by
resetting the microprocessor.
When INTR signal goes high, the following
events can occur −
The microprocessor checks the status of INTR
signal during the execution of each instruction.
When the INTR signal is high, then the
microprocessor completes its current instruction
and sends active low interrupt acknowledge
signal.
- Software Interrupt
In software interrupts,
The cause of the interrupt is an execution of the
instruction. These are special instructions
supported by the microprocessor. After execution
of these instructions’ microprocessor completes
the execution of the instruction it is currently
executing and transfers the program control to the
subroutine program. Upon completion of the
execution of the subroutine program, program
control returns to the main program.
The 8085 has eight software interrupts from RST
0 to RST 7. The vector address for these interrupts
can be calculated as follows. Interrupt number x
8 = vector address
- Masking / Unmasking of Interrupts:
As mentioned earlier, maskable interrupts are
enabled and disabled under program control. In
this section we will see how interrupts can be
masked or unmasked using program control.
There are four instructions used for control of
interrupts:
EI enable interrupt
DI disable interrupt
RIM reset interrupt mask
SIM set interrupt mask
address of the next instruction on stack and
executes the received instruction. Two types of
Software Interrupt:
- Unconditional branch. Go to a new location
no matter what.
- Conditional branch.
Go to a new location if the condition is true.
- Call, Return, and Restart
These instructions change the sequence of a
program either by calling a subroutine or
returning from a subroutine. The conditional Call
and Return instructions also can test condition
flags.

Unconditional Branch
JMP Address Jump to the address specified (Go
to).
CALL Address. Jump to the address specified but
treat it as a subroutine.
RET. Return from a subroutine. The addresses
supplied to all branch operations must be 16-bits.
8.3.3 Subroutines
A subroutine is a group of instructions that will be
used repeatedly in different locations of the
program.
• Rather than repeat the same instructions several
times, they can be grouped into a subroutine that
is called from the different locations. The 8085
has two instructions for dealing with subroutines.
– The CALL instruction is used to redirect
program execution to the subroutine.
• The RTE instruction is used to return the
execution to the calling routine.
• CALL 4000H
8.3.4 Conditional Branch
Go to new location if a specified condition is met.
JZ Address (Jump on Zero)
Go to address specified if the Zero flag is set.
JNZ Address (Jump on NOT Zero)
• Go to address specified if the Zero flag is not
set.
• JC Address (Jump on Carry)
• Go to the address specified if the Carry flag is
set.
• JNC Address (Jump on No Carry)
• Go to the address specified if the Carry flag is
not set. • JP Address (Jump on Plus)
• Go to the address specified if the Sign flag is
not set • JM Address (Jump on Minus)
• Go to the address specified if the Sign flag is
set.
8.6 Machine Control
HLT
• Stop executing the program.
• NOP
• No operation
• #Exactly as it says, do nothing. Usually used for
delay or to replace instructions during debugging.
 Exercise 8
1- Define the interrupt of 8085 Microprocessor
2- Mention the types of the interrupts in 8085
Microprocessor.
3- Explain the types of the Hardware interrupts
and its priority.
4- Compare between the Hardware and soft ware
interrupts from point of views: 1- Types
2- Instructions
3- Operation
5- Explain with instructions how the interrupts are
enable and disable.
6- Explain the conditional branch instructions.