Design and Simulation of QPSK Reconfigurable

Digital Receiver
Silva Cruz Eric Mario and Gordana Jovanovic Dolecek
Departament of Electronics
Institute INAOE
Puebla, México
Email: {ericmsc, gordana}@inaoep.mx

Abstract - This paper presents the design of a QPSK multirate 1/ T . To avoid aliasing is necessary to apply an antialiasing
radio receiver with non – synchronized Intermediate Frequency filter. The most simple antialiasing filter is the CIC (cascade-
(IF) and reconfigurable downsampling conversion. In order to integrator-comb filter) proposed by Hogenauer [3]. The
avoid the aliasing the compensated cascade of integrator comb
(CIC) filter is introduced. The non-synchronized samples need a
equivalent system function of the CIC filter is defined by,
K
timing synchronization correction, performed at the output of ⎡ 1 ⎛ 1 − z −M ⎞⎤
the matched filter using Farrow structure-based interpolator. H (z) = ⎢ ⎜ −1 ⎟ ⎥
, (2)
The receiver is simulated in Matlab and Simulink and results ⎣ M ⎝ 1 − z ⎠⎦
are verified by computation of the number of Erroneous bits where, M is the decimation factor and K is the number of
obtained during the simulation. stages in cascade.
However, this filter has a high passband droop which
I. INTRODUCTION increases with the increase of the number of the cascaded
The essence of the digital communication system design filters K , resulting in a considerable degradation of the
is to efficiently transmit digital bits and recover them from signal.
corruptions due the noise and other channel impairments. The obtained non-synchronized samples need the block
Digital modulation is a process that impresses a digital for the timing correction which is performed after the
symbol onto a signal suitable for transmission. There are matched filter, which serves to maximize the signal to noise
three main criteria of choosing a modulation scheme; power ratio (SNR) before the synchronization. Generally, the output
efficiency, bandwidth efficiency and system complexity, [1]. signal of the matched filter is sent to the Farrow structure-
based interpolator, [4] in a Digital Phase Locked Loop
The Quadrature Phase Shift Keying (QPSK) is one of the (DPLL), [5, 6], in order to find correct sampling intervals.
most used Phase Shift Keiying digital modulations, due to its There are different receiver structures proposed in the
simplicity, excellent power and bandwidth efficiency. The literature [7-14]. In [12] has been proposed the receiver
error performance degradation of the QPSK is measured in structures based on the configuration of a variable matched
term of the signal to noise ratio (SNR) for a given BER (Bit filter with a CIC anti-aliasing filter. The configuration of a
Error Rate) characteristic, [2]. CIC filter in cascade with an interpolator and a fixed matched
The received signal is defined by, [2] filter has been proposed in [13].
The main objective of this work is to improve the
⎡ a p ( t − kT − τ ) e j 2π f IF t e jθ ⎤ + n ( t ) ,
⎢⎣ ∑
r (t ) = 2 Es ℜ (1) characteristics of the receiver using the advantages of the
k
k
⎥⎦ structures [12, 13].
where, The rest of the paper is organized as follows. Next section
{ak } are the uncorrelated data symbols with symbol rate describes the proposed structure of the receiver and the
corresponding blocks. The simulations of the proposed
1/ T , structure in Matlab and Simulink are given in section III. The
Es is the energy per symbol, section IV provides the discussion of results.
p (t ) is the impulse response of the matched filter,
τ is the time delay of the signal in the channel, II. DESCRIPTION OF THE PROPOSED STRUCTURE
f IF is the carrier frequency,
The principal blocks of the proposed structure are shown
θ is the carrier phase delay, in Fig. 1.
n (t ) is additive Gaussian noise (AWGN), with power In the following we briefly describe the basic blocks of
spectral density equal to N 0 / 2 . the structure.
The received signal, sampled with a rate 1/ Ts , where Ts
is the carrier period, should be resampled with the bit rate

978-1-4244-7773-9/10/$26.00 ©2010 IEEE 656

 filter, and is defined by, [2],
B = (1 + α p ) / 2T , (4)
Timing Synchronizer
Figure 1. The proposed structure. Synchronization is required to define the correct timing of
the symbol in the receiver during each period. We adopt a
Analog to Digital Converter classical synchronization block Feedback DPLL (Digital
This block translates the input analog IF signal into digital Phase Locked Loop), which includes the following
form. components, [6],
- Gardner estimator,
Downconversion - Loop Filter,
Downconversion is the process of suppressing the carrier - Numerical controlled oscillator, (NCO),
frequency, by multiplying the received signal with an - Farrow interpolator.
exponential function. At the output of the downconversion Gardner estimator is defined by, [5],
block the baseband signal with a rate of 1/ Ts , is obtained u ( k + 1) = yI ( k − 1/ 2 ) ⎡⎣ yI ( k ) − yI ( k − 1) ⎤⎦
[15].
+ yQ ( k − 1/ 2 ) ⎡⎣ yQ ( k ) − yQ ( k − 1) ⎤⎦ , (5)
Decimation where,
In this block the sampling rate of the received signal is u ( k ) is the defined symbol in the k-th sample,
decreased by a decimation factor M. The CIC filter is used as
an anti-aliasing filter. In order to decrease the degradation of y ( k ) are the samples of the each transmitted symbol,
the signal a simple compensator is cascaded with the CIC I , Q are the components in-phase and quadrature,
filter. We adopted a wide-band compensation filter proposed respectively.
in [16]. The Loop filter is defined by, [8],
The system function of the compensator [16] is defined K2
by, F ( z ) = K1 + , (6)
1 − z −1
H comp ( z M ) = S ⎡⎣ Bz − M + Az 2 M + Bz −3 M ⎤⎦ , (3)
where, K1 and K 2 are constants.
where, the components A and B are integer coefficients, The purpose of the NCO is to determine the value of the
and S is a scaling factor, all shown in Table I for values of resampling of the signal and to provide the fractional delay
K=1, …, 5. Note that the characteristic of the compensator for the Farrow structure, [4].
filter does not depend on the decimation factor, [16]. The main objective of the Farrow structure is to resample
the symbol at a rate defined at the instants of the
Table I samples mT / N + τ , where m is the corresponding instant in a
Values of A, B and S for different values of K symbol rate, and τ is the fractional delay. The Farrow
Number of
K S B A dp[dB] structure is a Lagrange polynomial interpolator, with a
Additions
1 2-4 -1 24+21 0.142 3 configuration of parallel linear filters, defined with the
2 2-3 -1 23+21 0.234 3 coefficients given in Table II.
3 2-4 -2-20 2 +22+21
4
0.297 5 Table II
4 2-3 -1 22+21 0.342 3 Coefficients of the filters for the Farrow structure
5 2-4 -22-20 2 +23+21
4
0.377 5 Filter Coefficients
H0 1/6 -1/2 1/2 -1/6
This filter can be moved to a lower rate as shown in figure H1 0 -1/2 -1 1/2
2, and the coefficients A and B are expressed only using shifts H2 -1/6 1 -1/2 -1/3
H3 0 0 1 0
and adders.
Downsampling by a factor N
This block decreases the input sampling rate N / T by a
factor N to obtain the bit rate 1/ T . However here is not
Figure 2. Cascade configuration of the CIC and Compensator Filter. necessary an antialiasing filter because the transmitted signal
is oversampled, [15].
Matched Filter
Matched filter is used to maximize the signal to noise
III. SIMULATION OF THE PROPOSED STRUCTURE
ratio. The square root raised cosine filter is used to form the
symbol in a given period T . The bandwidth of the formed
symbol is defined by the roll-off factor α p of the matched The specification for the simulation realized in Matlab
and Simulink, [17], is;
This work is supported by CONACYT

657
 - The bit rate is rB = 5 × 106 bits / sec , Timing synchronizer stage is implemented in Simulink
- Each transmitted symbol is sampled 4 times, as is shown in the Fig. 6.
- Roll off factor of Matched filter is α p = 0.25 ,
- Carrier frequency is a multiple of the bit rate f c = 10 rB ,
- The Channel is modeled with Additive White Gaussian
Noise (AWGN) characterized by a signal to noise ratio (SNR)
in a range of 5-20dB,
- The fractional delay in the channel (e.g. τ = 0.45 ) is
simulated with a fractional delay interpolator.

The overall proposed structure, simulated in Simulink, is

shown in Fig. 3.
Figure 6. Timing Synchronization Block.

In the following we present all components of the timing

synchronization block simulated in Simulink.
The Gardner estimator is shown in the Fig.7.

Figure 3. Block diagram of the proposed structure simulated in

Simulink.

Figure 4 shows the detailed blocks of the CIC, the

Compensator and the Matched filter in a cascade
configuration realized in Simulink.
Figure 7. Gardner Estimator.

The parameters of the loop filter are K1 = −0.22537 and

K2=-1.5118e-3. The simulation of the loop filter is given in
Fig. 8.
Figure 4. Cascade of the filters: CIC, Compensator, and Matched.

The design of the compensator is directly related with the

CIC structure. The coefficients A, B, of the compensator
depend on K which is the number of stages of the CIC filter,
[16]. In the simulation the CIC is defined with a decimator
factor M=4 and K=4. The compensator is defined by the Figure 8. Loop Filter.
coefficients A = 22 + 21 , and B = −1 , the scaling factor is
defined as S = 2 −3 . The magnitude response of the resulting The simulated fractional interpolator is implemented
combination of the CIC and the compensator is shown in the using a Farrow structure (Fig. 9), with the configuration of
Fig. 5. the filters in parallel and coefficients defined in the Table II.

Figure 9. Farrow Structure.

IV. DISCUSSION OF RESULTS

The results of simulation are shown in the Figure 10. In

Figure 5. Magnitude Response of the CIC and Compensator Filter. upper plot is presented the in-phase component of the

658
received signal. The following plot shows the compensated received signal. Once realized the decimation process, the
CIC output. The matched filter is used to maximize the Matched filter determines the form of the symbol and is
amplitude of each symbol received with a reduced sampling followed by the DPLL synchronizer which corrects the
rate. The output of the matched filter is shown in the middle fractional delay time of symbols with the Farrow delay
plot of the Fig. 10. In the bottom plot is given the resulting interpolator. The results of the simulation show a reduced
output signal of the synchronizer, where the samples were number of erroneous bits.
adjusted to the corrected times within the Farrow fractional
interpolator. REFERENCES

[1] Fuqin Xiong. Digital Modulation Techniques. Artech

House, 2nd edition, 2006.
[2] S. Haykin. Communication System. John Wiley & Sons, Inc.
4th edition, 2001.
[3] E. Hogenauer. "An economical class of digital fillters for
decimation and interpolation". IEEE Transactions on Acoustics,
Speech and Signal Processing, Vol. 29, No. 2, January 2003, pp.
155-162.
[4] C. W. Farrow. “A Continuously Variable Digital Delay
Element”. In Proc. IEEE International Symposium on Circuits and
Systems (ISCAS ’88), Espoo, Finland, June 1988, pp. 2641–2645.
Figure 10. The Ouput Signals Decimated and Filtered with The [5] F. M. Gardner. A BPSK/QPSK Timing-Error Detector for
Matched Filter in each Simulated block. Sampled Receivers. IEEE, Transactions on communications, Vol.
com-34, No. 5, may 1986.
[6] F. M. Gardner. "Interpolation in Digital Modems – Part I:
In order to evaluate the simulation we determine the Fundamentals," IEEE Transactions on Communications, Vol. 41,
number of the received erroneous bits, applying different No. 3, March 1993, pp. 501-507.
values for signal to noise ratio (SNR=5, 10, 15, 20dB) and [7] U. Mengali and A. N. D'Andrea. Synchronization Techniques
fractional delay in the channel. The number of simulated bits for Digital Receivers. Plenum Press, 1997.
is 1 × 106 and the number of resulting erroneous bits is shown [8] H. Meyr, M. Moeneclaey, S. A. Fetchel. Digital
in the Fig. 11. Communication Receivers: Synchronization, Channel Estimation,
and Signal Processing, John Wiley & Sons, 1998.
[9] M. Henker and G. Fetweiss. "Combined Filter for Sample
Rate Conversion, Matched Filtering and Symbol Synchronization in
Software Radio Terminals". In Proceedings of the European
Wireless Conference, Berlin Offenbach, Germany, 12 – 14
September 2000, pp 61-66.
[10] H. Wymeersch, M. Moeneclaey, “BER performance of
software radio multirate receivers with nonsynchronized IF sampling
and digital timing correction”, In Proceedings of the International
Conference on Acoustics, Speech, and Signal Processing (ICASSP
2003), Vol 4, Hong Kong, April 2003 , pp 580-583.
[11] C. Mosquera, M. Cacheda, “Feedback timing
synchronization for IF-sampled systems”, in: Proceedings of the
Eighth International Workshop on Signal Processing for Space
Communications, SPSC 2003.
[12] H. Wymeersch and M. Moeneclaey. "Low complexity
multi-rate IF sampling receivers using CIC filters and polynomial
Figure 11. Simulation of proposed structure with different values of interpolation". In Proc. Sixth BaionaWorkshop on Signal Processing
SNR. in Communications, Baiona, Spain, September 2003.
As a result of simulation we can observe that with a low [13] H. Wymeersch and M. Moeneclaey. ”Multi-rate receiver
SNR (5dB) 48 erroneous bits are received. However the design with IF sampling and digital timing correction”. Elsevier,
number of erroneous bits is decreased with the increase of Signal Processing, Vol. 84, Issue 11, November 2004, pp 2067-
SNR. Particularly for SNR=25dB only 5 erroneous bits are 2079.
received. [14] H. Wymeersch. “Algoritmes voor Software Radio, geschikt
voor gecodeerde transmissie”, (Software Radio Algorithms for
Coded Transmission). PhD. Thesis, Gent University, 2005.
CONCLUSIONS [15] W. Tuttlebe, (Editor), Software Defined Radio: Enabling
Technologies, John Wiley & Sons, 1st Edition, 2002.
The proposed reconfigurable QPSK receiver structure [16] G. J. Dolecek, L. Dolecek., “Novel Multiplierless Wide-
improves the characteristics of a receiver by introducing the band CIC compensator,” accepted for IEEE ISCAS 2010, Paris,
wide-band CIC compensation filter. The application of the France.
selected compensator results in a decrease of the passband [17] Matlab® and Simulink® Versión 7.4.0.287 R2007a, Jan 29,
droop of the CIC filter, used to reduce the aliasing of the 2007, The Mathworks Inc.

659