CEA FPGA Lab

Complex Engineering Activity (CEA)
FPGA Based System Design Lab

BEE – 6 (A,B,C)
Instructor: Engr. Sohail / Engr. Talha
Objective:
The objective of this complex engineering activity is to explore, investigate, analyze, design, and
develop hands-on experience on complex engineering problems that mark the following attributes:
1. The activity involves research in engineering principles, problem solving and critical
analysis.
2. The activity also covers suitable software simulations for design purposes before
going into the process of design and development.
3. The activity inculcates within itself the already learnt and practiced engineering
approaches.
Outcomes:
The activity is mapped to CLO and your performance in this project will play an important role
in their attainment.
CLO Level PLO Outcome
02 P4 03 Construct a digital system using HDL(Verilog) and verify
results using testbench and simulation without any guideline.
03 A2 10 Be able to present and comply with key concepts and
procedures taught in FPGA lab.
Problem Statement
Implementation of 16 Bit processor on FPGA:
A processor is the logic circuitry that responds to and processes the basic instructions that drive a
computer. The processor is seen as the main and most crucial integrated circuitry (IC) chip in a
computer, as it is responsible for interpreting most of the computer’s commands. CPUs will
perform most basic arithmetic, logic, and I/O operations, as well as allocate commands for other
chips and components running in a computer.
Block Diagram of basic Processor:
Figure : Basic block diagram of processor

Design Constraints
Minimum hardware resources should be used for this design:
• A 16-bit processor needs to be designed with a total of 4 instructions.

• ADD: Two sixteen-bit numbers placed at two different memory locations be added and
resultant should be stored at distinct memory location ,
• SUBTRACT: Two sixteen-bit numbers placed at two different memory locations be
subtracted and resultant should be stored at distinct memory location ,
• MOV: Data can be moved to any memory location or register.
• COMPLIMENT: One’s compliment of data taken from memory and resultant to be
kept at distinct memory location
Depth of knowledge and Depth of Analysis is required to:

• Completely understand working principles involved in making a complete processor.
• Designing the program counter and deciding the width of PC
• Designing the Instruction register and deciding the width of Instruction register(IR)
• Designing ALU for addition ,subtraction and complement functions .
• Designing of Register File to store operand and results.
Possible Techniques to validate the design:

Designing a 16-bit processor ,Instruction from IR will move to PC ,after reading opcode the desired
instruction will be performed. For example, add instruction needs to be executed so after reading
the opcode the operands will be fetched from the register files to the ALU where the operation of
addition will be performed, and result should be sent back to resultant register.
Integrated Logic Analyzer (ILA)

The ILA core helps you easily probe internal signals inside your FPGA and bring them out into a
simulation-like environment to monitor them and verify their behavior.
The customizable Integrated Logic Analyzer (ILA) core is a logic analyzer core that can be used to
monitor the internal signals of a design. The ILA core includes many advanced features of modern
logic analyzers, including Boolean trigger equations, and edge transition triggers. Because the ILA
core is synchronous to the design being monitored, all design clock constraints that are applied to
your design are also applied to the components inside the ILA core.
Depth of knowledge and Depth of Analysis is required to,
i. Completely understand and devise an algorithm which can do all these
things effectively and efficiently.
ii. Utilize Range of Resources to test/debug and assess the performance of your
algorithm working.
Proposal Report
The proposal report should have the following parts.
• Cover page
• Including name and enrolment numbers, project name, instructor name, department,
and university name.
• Background of selected project.
• Conclusion
Use Times new roman format with heading of 16pts bold size, subheading of 14 pts bold size
and body of the text with 12 pts. Text should be justified with 1.15 line spacing.
Final Report
The final report should have the following parts.
• Cover Page
• Abstract
• Problem Statement
• Discussion: Complete discussion related to project parts. Flow chart/ Pseudo-
code must implement in Microsoft Visio.
• Results
• Conclusion
Submission of Report shall solely be via pdf generated by Latex Document Compiler
Only.
Deliverables
• CEA Proposal submission on LMS deadline by 2nd June 2023.

• CEA Software based implementation submission on LMS and Viva will be 15th June
2023.
• Demonstration of 16-bit processor on ARTY S7 FPGA kit including ILA core to be
evaluated along with Final Viva 22nd June 2023.
The project report should include objectives, background, abstract description, debugging,
simulation results/code ,test bench, ASM/State Diagram, and conclusion.
Marking Criteria
Proposal 2 Marks
Mid Evaluation 5 Marks

(Simulations)
Final Report 3 Marks
Final Evaluation 10 Marks

(Implementation
on FPGA Kit)

CEA FPGA Lab

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CEA FPGA Lab

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Complex Engineering Activity (CEA)

FPGA Based System Design Lab

Block Diagram of basic Processor:

Figure : Basic block diagram of processor

• A 16-bit processor needs to be designed with a total of 4 instructions.

Depth of knowledge and Depth of Analysis is required to:

Possible Techniques to validate the design:

Integrated Logic Analyzer (ILA)

• CEA Proposal submission on LMS deadline by 2nd June 2023.

Mid Evaluation 5 Marks

Final Report 3 Marks

Final Evaluation 10 Marks

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