Compactpci 9030rdk-Lite HRM With Schematic 19jan06

CompactPCI 9030RDK-LITE
Hardware Reference Manual

CompactPCI 9030RDK-LITE
Hardware Reference Manual
Version 1.2
October 2004
Website: http://www.plxtech.com
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Phone: 408 774-9060
800 759-3735
Fax: 408 774-2169
© 2004 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may
have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including
infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Order Number: CPCI 9030/LITE-RDK-HRM-P1-1.2
Printed in the USA, October 2004

PREFACE
NOTICE
This document contains PLX Confidential and Proprietary information. The contents of this document may
not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX
Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to
entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX
manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or
adequacy of this information. The information in this document is subject to change without notice.
Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for
any errors, incidental, or consequential damages in connection with the furnishing, performance, or use of
this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use
of this manual, for loss or claims by third parties, which may arise through the use of the RDK, or for any
damage or loss caused by deletion of data as a result of malfunction or repair.
ABOUT THIS MANUAL

This document describes the PLX CompactPCI 9030RDK-LITE, a Reference Design Kit, from a hardware
perspective. It contains a description of all major functional circuit blocks on the board and also is a
reference for the creation of software for this product. This manual also includes the complete schematics
and bill of materials.
REVISION HISTORY
Date Version Comments
Hardware Reference Manual release

May 2000 1.0 • Updated Schematics
• Other minor changes
• Updated Table 3-2 with new value for offset 7Ah
March 2003 1.1 • Updated Bill of Materials
• Updated Schematics
October 2004 1.2 • Updated EEPROM table, Manual and BOM
CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

© 2004 PLX Technology, Inc. All rights reserved. i
TABLE OF CONTENTS
1. GENERAL INFORMATION...................................................................................................1
1.1 FEATURES ...................................................................................................................................... 2
1.2 RDK INSTALLATION ........................................................................................................................ 2
2. SYSTEM ARCHITECTURE...................................................................................................3
3. HARDWARE ARCHITECTURE ............................................................................................5

3.1 HARDWARE MEMORY MAP .............................................................................................................. 6
3.2 PCI 9030....................................................................................................................................... 6
3.3 SERIAL EEPROM .......................................................................................................................... 7
3.4 SYNCHRONOUS DUAL-PORT RAM (DPRAM) ................................................................................ 10
3.5 HOT SWAP CONTROL CIRCUIT....................................................................................................... 10
3.5.1 Hardware Connection Control ............................................................................................. 10
3.5.2 Software Connection Control............................................................................................... 10
3.6 TEST HEADERS ............................................................................................................................ 11
3.7 PLX OPTION MODULE CONNECTOR .............................................................................................. 11
3.8 HARDWARE MODULES .................................................................................................................. 11
3.8.1 RS232 Serial Port ................................................................................................................ 11
3.8.2 Debug and Status LEDs ...................................................................................................... 11
3.8.3 Reset Circuitry ..................................................................................................................... 11
3.8.3.1 Power-on-Reset ...............................................................................................................................11
3.8.3.2 Reset Pushbutton Switch .................................................................................................................11
3.8.4 Flash ROM Socket............................................................................................................... 11
3.9 PROTOTYPING AREA ..................................................................................................................... 11
3.9.1 Thirty-three (33) Surface Mount Footprints ......................................................................... 12
3.9.2 The Common BGA Landscape............................................................................................ 13
3.10 CONFIGURING THE RDK BOARD .................................................................................................... 14
3.10 CONFIGURING THE RDK BOARD .................................................................................................... 14
3.11 MEMORY ACCESS TO THE DPRAM ............................................................................................... 14
4. PCB LAYOUT CONSIDERATION ......................................................................................15

4.1 REQUIREMENTS OF STANDARDS .................................................................................................... 15
4.2 μBGA FOOTPRINT LAYOUT ........................................................................................................... 15
5. CONVERTING THE 6U BOARD TO A 3U BOARD ...........................................................16
6. CUSTOMER SUPPORT......................................................................................................16
7. REFERENCES ....................................................................................................................16
8. ABEL CODE / BILL OF MATERIALS / SCHEMATICS ......................................................17

8.1 ABEL CODE FOR U13................................................................................................................... 17

© 2004 PLX Technology, Inc. All rights reserved. iii
Contents / Figures / Tables
LIST OF FIGURES
FIGURE 1-1. COMPACT PCI 9030RDK-LITE LAYOUT DIAGRAM (6U/4HP CARD) .......................... 1
FIGURE 2-1. COMPACTPCI 9030RDK-LITE SYSTEM ARCHITECTURE ........................................... 3
FIGURE 3-1. COMPACTPCI 9030RDK-LITE HARDWARE BLOCK DIAGRAM .................................... 5
FIGURE 3-2. BGA LANDSCAPES ................................................................................................ 13
LIST OF TABLES
TABLE 3-1. COMPACTPCI 9030RDK-LITE MEMORY MAP ............................................................. 6

TABLE 3-2. CONTENTS OF THE SERIAL EEPROM ......................................................................... 8
TABLE 3-3. PROTOTYPING FOOTPRINTS AND PROTOTYPING AREA ON THE
COMPACTPCI 9030RDK-LITE BOARD ..................................................................... 12
TABLE 8-1. BILL OF MATERIALS .................................................................................................. 19

iv © 2004 PLX Technology, Inc. All rights reserved.
1. General Information
208/144/80
176/100/48
PQFP
PQFP
25x25 0.1" through hole

footprints prototyping area
footprints
48 pin 48 pin
54 pin TSOP 54 pin TSOP
SSOP SSOP
20 pin 84/68/44/28
28 pin SOIC 28 pin SOIC 20 pin SOIC
SSOIC
26x26 0.05" PLCC
16 pin 16 pin 16 pin 20 pin 20 pin
SOIC SOIC SOIC pitch BGA
SOIC SOIC footprints
landscape
24 pin 16 pin 16 pin 20 pin

SSOP SSOP SSOP 16 pin
PLCC 5VCC
SOIC
GND
GND
44 pin 48 pin 48 pin
24 pin TQFP 3.3V
SSOP SSOP SSOP
3.3V
POM Connector LED's
DB 9
Connector Hot Swap
reset circuit LAH5 LAH3
Circuit
GAL
DPRAM LAH6 LAH4

U8
J
CPCI connector J1
RS232 Port DPRAM
U11
3
LAH1
LAH1
LAH2
LEDs
switch Flash DPRAM

ROM U12 PCI
Socket 9030
LAH2
Blue
LED Serial 60MHz
EEPROM OSC
Figure 1-1. CompactPCI 9030RDK-LITE Layout Diagram (6U/4HP Card)
The CompactPCI 9030RDK-LITE Reference Design Kit (RDK) is a CompactPCI bus target
prototyping kit, which can be used for custom design development such as networking, telecom,
imaging, industrial, and storage applications using the PLX PCI 9030 SMARTarget™ I/O Accelerator
chip. The reference design kit allows customers to create designs with or without a microprocessor.

© 2004 PLX Technology, Inc. All rights reserved. 1
Section 1
General Information RDK Installation
1.1 Features
The CompactPCI 9030RDK-LITE • Socketed oscillator for Local bus clock
Reference Design Kit (RDK) is a 6U and PLL, provide up to 60 MHz clock.
CompactPCI Bus Target Prototyping Kit,
which contains a six-layer, assembled PC • The Hot Swap control circuit allows the
board with the dimensions of 6.30” L x 9.19” orderly insertion and removal of the
W and the following features: board without adversely affecting
system operation.
• PLX PCI 9030 SMARTarget™ I/O • Six logic analyzer headers with
Accelerator in 180-pin 0.8mm pitch standard HP footprints allow easy
μBGA package. probing of Local bus signals.
• Socketed serial EEPROM for • PLX Multiplexed bus mode Option
configuring PCI 9030 Module (POM) connector provides
connection to other PLX POMs or
• Supports both multiplexed and non-
customer devices.
multiplexed bus modes
• A 25x25 0.1-inch grid through-hole area
• Thirty-three (33) surface mount
allows easy prototyping with through-
prototyping footprints and a 0.05” pitch
hole components.
BGA landscape, which can be used
with different FPGAs, CPLDs, • By cutting the 6U front panel to 3U and
SDRAMs, SRAMs, data transceivers detaching the upper portion of the PC
and general-purpose logic devices. board, the RDK can be converted to a
3U board
• Socketed 32-pin PLCC footprint
provides designers with a place for their
flash boot ROM. 1.2 RDK Installation
• On-board, up to 32-bit synchronous 1. Turn off the power of the
dual-port, SRAM plus a small 20-pin CompactPCI system.
programmable GAL demonstrating PCI 2. Wear user-suitable grounding
9030 continuous burst read/write straps.
features. It allows the user to plug the
board into a PCI system and be 3. Align the 6U board with the top and
operational immediately. bottom guide rails and slide the
board into an available single slot.
• Four (4) green user defined
status/debug LEDs and one (1) red 4. Make sure the board is completely
power on LED. plugged in and lock both handles at
the front panel.
• Built-in DB9 connector, RS232
transceiver, and UART for easy 5. Plug the power cord into the power
addition of a serial port to the Local receptacle again and turn on the
bus. power switch of the CompactPCI
system.
• A push button switch and a reset
generator are capable of generating
reset signals to any device on the
board.

2 © 2004 PLX Technology, Inc. All rights reserved.
2. System Architecture
Separate Bus
Synchronous Synchronous
Dual-port Dual-port Test POM Serial Reset
RAM RAM Headers Connector Port Circuit
4Kx18 4Kx18
Back End Power
LOCAL BUS
up to 32-bit, 60MHz
Users Prototyping
Flash ROM
Defined Area &
Socket
LEDs Footprints
Local
PCI 9030
Hot Swap reset
Control Circuit (µBGA)

EEPROM
Back End Controls Early Power Ejector Blue

Power Switch LED
CompactPCI BUS, 32-bit, 33MHz
Figure 2-1. CompactPCI 9030RDK-LITE System Architecture
As shown in Figure 2-1, the RDK board burst memory read/write from/to the left port
contains: of the DPRAM in direct slave mode.
Four hardware modules on the RDK provide
• A PCI 9030 SMARTarget™ I/O some basic hardware building blocks for
Accelerator almost any PCI 9030 design.
• Four components (two 4Kx18
Synchronous Dual-Port RAMs, Test The Hot Swap control circuit controls the
Headers, and POM connector) that current rise when the components and
connect to the PCI 9030 Local bus circuits receive power at the local bus,
providing backend power status to the
• Four commonly used hardware
system controller and the local reset signal
modules (Serial Port, Reset Circuit,
to the PCI 9030 device.
LEDs, and Flash ROM Socket)
• A Hot Swap control circuit The thirty-three (33) surface mount
• Many carefully selected prototyping footprints include many SOIC, SSOP and
footprints throughout 70% of the TSOP footprints for common logic ICs and
board area. many PLCC and PQFP footprints for
common FPGAs and CPLDs. Also, the BGA
The RDK is shipped with one Synchronous landscape and the through-hole prototyping
Dual-Port RAM (DPRAM) on the board as area provide additional flexibility.
the default. A PCI master adapter card
residing on the PCI bus can perform single
memory read/write cycles, and continuous

3. Hardware Architecture
This section provides a detailed description of the hardware of the CompactPCI 9030RDK-LITE.
Figure 3-1 shows the hardware block diagram of the RDK.
5 Volt Power
Hardware modules
To Back
BD_Select# 5V/3.3V 2A
MOSFET End Serial Port
Healthy# Hot Swap Control LDO
Circuits
Circuit
PCI_Reset# Reset Circuit Prototyping
Area &
POM Test Users defined LEDs
3.3V Early Power
Local_Reset# Connector Headers Footprints
Flash ROM Socket
Ejector
Switch Address Bus
Data bus
Blue
LOCAL BUS
LED
Control Bus Up to 32-bit, 60MHz
Address Bus
PCI 9030 Resistor Networks to configure

16 or 32 bit address bus
Data Bus
ADSL Synchronous Dual-Port RAM

CE0L
Control Bus LW/RL 4Kx18
CS0L 16V8 DPADSL
ENUM#
BLASTL GAL R/WL Left Port Right Port
Local Bus Synchronous Dual-Port RAM

Serial
EEPROM
Clock Circuit 4Kx18
60MHz
Left Port Right Port
CompactPCI BUS
32-bit, 33MHz Separate Bus
Figure 3-1. CompactPCI 9030RDK-LITE Hardware Block Diagram

Section 3
Hardware Architecture PCI 9030
3.1 Hardware Memory Map
Table 3-1. CompactPCI 9030RDK-LITE Memory Map

Address Range Device Chip Select Comments
FFF FFFF Can be assigned to
Unused Available
Programmable CS2#-CS3#
Programmable
POM connector CS1# Programmable
000 4000
000 3FFF Two DPRAM
CS0# 32-bit access
000 0000 (U11 and U12)
000 1FFF One DPRAM
CS0# 16-bit access
000 0000 (U11only)
Note: If two DPRAMs (U11 and U12) are used for 32-bit access, the address range will
be 000 0000 – 000 3FFFh.
3.2 PCI 9030

The PCI 9030, a 32-bit, 33MHz PCI Bus Target • PCI Target Delay Write: The PCI 9030
Interface chip with SMARTarget™ technology, is supports PCI Target Delay Write mode
the most advanced feature rich, general- where the PCI target write data is
purpose, bus target device available in the postponed in the PCI Target Write FIFO
market today. to allow uninterrupted burst
transactions on the Local bus. This
• PCI v2.2 Compliant: The PCI 9030 allows for a higher throughput for
enables up to 132 Mbytes/second in conditions in which the PCI clock
PCI burst transfers and up to 240 frequency is slower than the local clock
Mbytes/second burst transfers on the frequency or when Local bus bursting is
60MHz Local bus. desirable.
• PCI Target Read Ahead Mode: The • Posted Memory Write: A PCI memory
PCI 9030 will pre-fetch a programmable write can be posted to the PCI 9030 for
amount of data from the Local bus. The later transfer to the Local bus. This
pre-fetched data can then be burst allows for maximum PCI performance
transferred on the PCI bus from the PCI and avoids potential deadlock
9030 internal PCI Target Read FIFO. situations.
The pre-fetched size can be
programmed to match the PCI master • Programmable Local bus operates up
burst length or can be used as PCI to 60MHz and supports both non-
Target Read Ahead mode data. This multiplexed and multiplexed 32-bit
feature allows for increased bandwidth address/data and Dynamic Local Bus
and reduced read latency. width control allowing slave accesses to
8-, 16-, or 32-bit devices.
• PCI Target Programmable Burst: The
PCI 9030 may be programmed for • Supports 5 PCI to local address
several burst lengths, including spaces. These spaces (Space 0, 1, 2, 3
unlimited burst. This allows for and Expansion ROM space) allow a
maximum transfer rates on both PCI PCI Bus Master to access the local
and Local buses. memory spaces with individually
programmable wait states, bus widths,
and burst capabilities.
• Up to 9 programmable General
Purpose I/Os, which may be used for a
variety of purposes.
• Four programmable chip selects
eliminate external decode circuits.

Section 3
Serial EEPROM Hardware Architecture
• CompactPCI Hot Swap Ready: The 3.3 Serial EEPROM

PCI 9030 supports LEDon#, CPCISW,
BD_SEL# and ENUM# signals as well The CompactPCI 9030RDK-LITE board can
as Hot Swap capabilities registers – boot with or without the presence of the serial
HS_CNTL, HS_NEXT, and HS_CSR. EEPROM. The RDK is shipped with a 2K-bit,
3.3V serial EEPROM which is used for PCI 9030
• Supports automatic on-the-fly Big initialization. The serial EEPROM directly
Endian and Little Endian conversion for connects to the PCI 9030 through its four-pin
all operations and data types. interface. A total of 136 bytes of data is
preprogrammed to the EEPROM to bring up the
• Interrupt Generator can assert PCI
RDK after the system reset. The data includes
interrupts from external and internal
the device and functional information for plug-
sources
and-play (PnP), PCI memory resource allocation
• Fully supports the Vital Product Data and initial values of PCI 9030 internal registers.
(VPD) PCI v2.2 extension including Also, it includes the PCI 9030 chip select
New Capabilities Structure. Provides an programming, CS0L, which becomes active
alternate access method for user or when the DPRAM is selected at the address
system-defined parameters or range 0000000 to 0001FFFh and programs the
configuration data. wait states of DPRAM read/write cycles. Once
the RDK initializes correctly, customers can
perform memory read/write with the DPRAM,
®
using PLXMon to examine the serial EEPROM
contents or reprogram it with user defined data
files.

Hardware Architecture Serial EEPROM
Table 3-2. Contents of the Serial EEPROM

Serial
Register Register Values
EEPROM Register Description Register Bits Affected
Offset (Hex)
Offset
00h PCI 02h Device ID PCIIDR[31:16] 30C1
02h PCI 00h Vendor ID PCIIDR[15:0] 10B5
04h PCI 06h PCI Status PCISR[15:0] 0290
06h PCI 04h PCI Command Reserved 0000
08h PCI 0Ah Class Code PCICCR[23:8] 0680
0Ah PCI 08h Class Code / Revision PCICCR[7:0] / PCIREV[7:0] 0001
0Ch PCI 2Eh Subsystem ID PCISID[15:0] 9030
0Eh PCI 2Ch Subsystem Vendor ID PCISVID[15:0] 10B5
10h PCI 36h Reserved Reserved 0000
12h PCI 34h Reserved / New Capability Pointer Reserved / CAP_PTR[7:0] 0040
(Maximum Latency and Minimum Grant
14h PCI 3Eh Reserved 0000
are not loadable)
Interrupt Pin /
16h PCI 3Ch PCIIPR[7:0] / PCIILR [7:0] 0100
(Interrupt Line Routing is not loadable)
18h PCI 42h MSW of Power Management Capabilities PMC[14:11, 5, 3:0] 4802
Power Management Next Capability Pointer /
1Ah PCI 40h PMNEXT[7:0] / PMCAPID[7:0] 4801
Power Management Capability ID
Power Management Data /
1Ch PCI 46h Reserved 0000
PMCSR Bridge Support Extension
1Eh PCI 44h LSW of Power Management Control/Status PMCSR[14:8] 0000
20h PCI 4Ah Hot Swap Control/Status Reserved 0000
LSW of Hot Swap Next Capability Pointer /
22h PCI 48h HS_NEXT[7:0] / HS_CNTL[7:0] 4C06
Hot Swap Capability ID
24h PCI 4Eh PCI Vital Product Data Address Reserved 0000
PCI Vital Product Data Next Capability Pointer/
26h PCI 4Ch PVPD_NEXT[7:0] / PVPDCNTL[7:0] 0003
PCI Vital Product Data Capability ID
28h Local 02h MSW of Range for PCI-to-Local Address Space 0 LAS0RR[31:16] FFFF
2Ah Local 00h LSW of Range for PCI-to-Local Address Space 0 LAS0RR[15:0] E000
2Ch Local 06h MSW of Range for PCI-to-Local Address Space 1 LAS1RR[31:16] 0000
2Eh Local 04h LSW of Range for PCI-to-Local Address Space 1 LAS1RR[15:0] 0000
30h Local 0Ah MSW of Range for PCI-to-Local Address Space 2 LAS2RR[31:16] 0000
32h Local 08h LSW of Range for PCI-to-Local Address Space 2 LAS2RR[15:0] 0000
34h Local 0Eh MSW of Range for PCI-to-Local Address Space 3 LAS3RR[31:16] 0000
36h Local 0Ch LSW of Range for PCI-to-Local Address Space 3 LAS3RR[15:0] 0000
38h Local 12h MSW of Range for PCI-to-Local Expansion ROM EROMRR[31:16] 0000
3Ah Local 10h LSW of Range for PCI-to-Local Expansion ROM EROMRR[15:0] 0000
MSW of Local Base Address (Remap) for
3Ch Local 16h LAS0BA[31:16] 0000
PCI-to-Local Address Space 0
LSW of Local Base Address (Remap) for
3Eh Local 14h LAS0BA[15:0] 0001
40h Local 1Ah LAS1BA[31:16] 0000
42h Local 18h LAS1BA[15:0] 0000
44h Local 1Eh LAS2BA[31:16] 0000
46h Local 1Ch LAS2BA[15:0] 0000
48h Local 22h LAS3BA[31:16] 0000

Section 3
SERIAL EEPROM Hardware Architecture
Serial
Register Register Values
EEPROM Register Description Register Bits Affected
Offset (Hex)
Offset
4Ah Local 20h LAS3BA[15:0] 0000
4Ch Local 26h EROMBA[31:16] 0000
PCI-to-Local Expansion ROM
4Eh Local 24h EROMBA[15:0] 0000
PCI-to-Local Expansion ROM
MSW of Bus Region Descriptors for Local Address
50h Local 2Ah LAS0BRD[31:16] 0040
Space 0
LSW of Bus Region Descriptors for Local Address
52h Local 28h LAS0BRD[15:0] 2081
Space 0
54h Local 2Eh LAS1BRD[31:16] 0080
Space 1
56h Local 2Ch LAS1BRD[15:0] 0000
Space 1
58h Local 32h LAS2BRD[31:16] 0080
Space 2
5Ah Local 30h LAS2BRD[15:0] 0000
Space 2
5Ch Local 36h LAS3BRD[31:16] 0080
Space 3
5Eh Local 34h LAS3BRD[15:0] 0000
Space 3
MSW of Bus Region Descriptors for
60h Local 3Ah EROMBRD[31:16] 0000
Expansion ROM
LSW of Bus Region Descriptors for
62h Local 38h EROMBRD[15:0] 0000
Expansion ROM
64h Local 3Eh MSW of Chip Select (CS) 0 Base and Range CS0BASE[31:16] 0000
66h Local 3Ch LSW of Chip Select (CS) 0 Base and Range CS0BASE[15:0] 1001
68h Local 42h MSW of Chip Select (CS) 1 Base and Range CS1BASE[31:16] 0000
6Ah Local 40h LSW of Chip Select (CS) 1 Base and Range CS1BASE[15:0] 0000
6Ch Local 46h MSW of Chip Select (CS) 2 Base and Range CS2BASE[31:16] 0000
6Eh Local 44h LSW of Chip Select (CS) 2 Base and Range CS2BASE[15:0] 0000
70h Local 4Ah MSW of Chip Select (CS) 3 Base and Range CS3BASE[31:16] 0000
72h Local 48h LSW of Chip Select (CS) 3 Base and Range CS3BASE[15:0] 0000
74h Local 4Eh Serial EEPROM Write-Protected Address Boundary PROT_AREA[6:0] 0030
76h Local 4Ch Interrupt Control/Status Register INTCSR[15:0] 0000
MSW of PCI Target Response, Serial EEPROM,
78h Local 52h CNTRL[31:16] 807C
and Initialization Control
LSW of PCI Target Response, Serial EEPROM,
7Ah Local 50h CNTRL[15:0] 4000
and Initialization Control
7Ch Local 56h MSW of General Purpose I/O Control GPIOC[31:16] 0024
7Eh Local 54h LSW of General Purpose I/O Control GPIOC[15:0] 9000
PMDATA[7:0] hidden, D0 and D3hot
80h Local 72h MSW of Hidden 1 Power Management Data Select 0000
Power Dissipated
PMDATA[7:0] hidden, D0 and D3hot
82h Local 70h LSW of Hidden 1 Power Management Data Select 0000
Power Consumed
84h Local 76h MSW of Hidden 2 Power Management Data Scale Reserved 0000
PMCSR[14:13] hidden,
Bits [7:0] are used as follows:
[7:6] D3hot Power Dissipated,
86h Local 74h LSW of Hidden 2 Power Management Data Scale 0000
[5:4] D0 Power Dissipated,
[3:2] D3hot Power Consumed,
[1:0] D0 Power Consumed

Section 3
Hardware Architecture PLX Option Module Connector
3.4 Synchronous Dual-Port RAM 3.5 Hot Swap Control Circuit

(DPRAM) The RDK is a full Hot Swap board that includes
The PCI 9030 is connected to (2) two both hardware connection control and software
Synchronous Dual–Port RAMs, U11 and U12, connection control in accordance with the
on the RDK board. These DPRAMs are 3.3V, 9 CompactPCI Hot Swap specifications. It can
ns, 4Kx18 Cypress devices. However, the board work on a range of systems from non-Hot Swap
is assembled with one DPRAM (U11) on board systems to High Availability systems.
as a default.
3.5.1 Hardware Connection Control
The DPRAM serves two purposes on the RDK
board. First, the left port of DPRAM U11, The BD_SEL# signal at the J1 CompactPCI
connects to the lower 16-bit data bus of the PCI connector is connected to the BD_SELL input of
9030 with simple interface logic that resides in PCI 9030 chip and ON# signal input of the
the 5ns, 20-pin programmable GAL device. A Linear Technology LTC1643L Hot Swap
PCI bus master can perform 8- and 16-bit single Controller. An external 1.2K ohm pull-up resistor
memory cycles with the DPRAM through the PCI is connected to this signal pin and early VIO
9030. If the PCI bus master supports bursting, power. When the board is hot plugged into a
the PCI master can perform 16-bit continuous CompactPCI system, before the J1 connector
burst memory cycles with the DPRAM also. makes contact with the BD_SEL# pin on the
Second, the PCI 9030 is a PCI target chip with backplane, the PCI 9030 chip is already
an output only address bus. If a customer’s powered-up with early 3.3V. The 1.2K-ohm
design has a microprocessor or microcontroller, external pull-up will activate the PCI 9030
they can place these devices on the separate internal pre-charge regulator and built-in 10K
bus on the right port of the DPRAM. Also, if the ohm pull-up resistors to precharge all required
customer wants to have 32-bit DPRAM, they can PCI I/O signals on the RDK to one Volt. This
add the same Cypress chip to U12 and prevents erroneous system operation during Hot
rearrange the resistor networks RN34, RN36 Swap insertion of the board.
and RN38. (See page 5 of the Schematics for The Board Healthy signal, HEALTHYL, is
more details.) generated by the LTC1643L as the Power Good
The interface between the PCI 9030 and the signal for the 5V power output. The Power-Good
DPRAMs is very straightforward. The left port of Threshold voltage is 4.40 to 4.75V. As long as
the DPRAM is configured in the pipelined mode. the 5V power input reaches this range, the
Three control input signals, chip enable 1 Power-Good signal – HEALTHYL—will be
(CE1L), counter enable (CNTENLL), and output generated. Also the LTC1643L controls the
enable (OELL) are enabled and the counter current limit and the power up rate. In this RDK,
reset signal (CNTRSTL) is disabled with related the current limit is 3A (the capacity of the LDO of
pull-up and pull-down resistors. Only two control the LT1587CM-3.3) and the power up rate would
input signals, address strobe (ADSLL) and chip be dv/dt = 50uA/0.1uF, or determined by the
enable (CE0L), are converted from PCI 9030 current limit and the load capacitance,
control signals. If the PCI 9030 local clock is whichever is slower.
running at 60MHz, the PCI 9030 needs two wait With two logic gates, the Local PCI Reset signal,
states for the single or the first data read of a LOCAL_RSRL, was driven from the Platform
burst memory read cycle, and zero wait states Reset, PCIRSTL, from the system backplane
for the single or burst write cycle. and the Healthy signal, HEALTHYL from the
On the right port of the DPRAMs, all the input LTC1643L to reset the PCI 9030.
control signals are preset to idle states. A 29x2
header, J3, provides access to address, data, 3.5.2 Software Connection Control
and control signals on the right port and nearby A micro switch located at the lower ejector
prototyping pads provide the connections to the handle of the 6U RDK board is used to signal
customers’ designs in the separate bus on the the insertion or impending extraction of the RDK.
right port of the DPRAMs. When the handle is unlocked, the CPCISW is
pulled-up to 3.3V. That informs the PCI 9030
that the board is at the impending extraction
state. When the handle is locked, CPCISW is

Section 3
HARDWARE MODULES Hardware Architecture
pulled down to ground. This informs the PCI 3.8.1 RS232 Serial Port
9030 that the board is fully inserted. Also,
The RS232 Serial Port combines a DB9 male
ENUML is generated to signal the status of the
connector, a 3-output / 5 input DTE transceiver
handle to the system Host.
and a UART. The serial port provides the
A blue LED is located near the bottom handle of parallel interface to the PCI 9030 Local bus or
the 6U front panel. The anode is connected to a the separate bus at the dual-port memory.
5V power source through a 100-ohm series
resistor. The cathode is connected to the 3.8.2 Debug and Status LEDs
LEDonL PCI 9030 pin. The blue LED lights up
for a moment at the RDK power up, after which There are four green user-defined LEDs near
the top edge of the RDK board. Each LED
the blue LED is software driven.
anode is connected to 3.3VDC through a 150-
ohm ¼ watt resistor. The LED cathode is
3.6 Test Headers connected to a prototyping pad. As long as an
Six logic analyzer headers are implemented with active low signal can sink 16 – 20 mA of current,
a standard 0.1”, 2x10 Hewlett Packard it can directly drive the LEDs without changing
configuration. In this RDK, they serve two the resistor value.
different functions. One is for easy probing. All
PCI 9030 Local bus signals, configuration and 3.8.3 Reset Circuitry
status signals are well arranged within these
headers. Headers LAH1 and LAH2 contain 3.8.3.1 Power-on-Reset
Local bus address signals. Headers LAH3 and Power-on-reset is provided by an external
LAH4 contain Local bus data signals (or 3.3V power supply supervisor. The valid
multiplexed address/data signals in the power-on-reset period is 1ms, which is
multiplexed mode). Headers LAH5 and LAH6 hardwired into the supply supervisor IC.
carry Local bus control and status signals.
Designers can use these headers to connect to 3.8.3.2 Reset Pushbutton Switch
a standard board for additional prototyping. The
The Reset Pushbutton switch allows the
headers do not provide any power source;
user to reset the Local Bus side of the board
therefore, this must be connected separately for
only. When this pushbutton switch is
prototyping daughterboards.
pressed, a manual reset can be generated
to reset the devices on the PCI 9030 Local
3.7 PLX Option Module Connector bus.
The PLX Option Module Connector resides
directly on the 32-bit multiplexed mode Local 3.8.4 Flash ROM Socket
Bus. A slave device may be connected to this A 32-pin PLCC footprint and related PLCC
connector. A programmable chip select, CS1L, socket is provided on the RDK. This can be
is used to select the option module. A hardware used to install a 3.3V, 512KB byte-wide flash
interrupt, INTi1, is used for the option module to memory device. It can be used to store
generate an interrupt to the CompactPCI bus microprocessor or DSP code for booting the
master through the PCI 9030. The schematic Local bus master devices. The flash ROM
provides information for all of the 100-pin footprint is pre-connected to power and ground.
connector signals. If desired, this connector can The prototyping pads are provided for all control
be used for expansion and prototyping. signal pins as well as all address and data lines.
3.8 Hardware Modules 3.9 Prototyping Area

The RDK-LITE provides four hardware modules: The RDK board contains a huge prototyping
1) RS232 serial port, 2) debug and status LEDs, area as mentioned before. To make the
3) reset circuitry, and 4) flash ROM socket. prototyping area more user-friendly and cost
These four modules are in addition to the clock effective, three key features have been
generator used to provide up to 60MHz Local implemented. The first is 30+ surface mount
bus clock to the PCI 9030, synchronous Dual- footprints, the second is the 0.05” pitch common
Port RAM, and POM connector. BGA landscape and the last is a 25x25 0.1” grid
through-hole prototyping area.

Section 3
Hardware Architecture Prototyping Area
3.9.1 Thirty-three (33) Surface Mount Footprints
Table 3-3. Prototyping Footprints and Prototyping Area on the

CompactPCI 9030RDK-LITE Board
Package Qty. Wide & Pitch Destination Remark
32-pin PLCC 1 0.05” pitch FP1
FP2 to FP5
co-exist at a 84-pin
44-pin PLCC 1 0.05” pitch FB4
PLCC area
16-pin SOIC narrow 4 .150”wide, 0.05” pitch FP7, 8, 15, 16
54-pin TSOP 2 0.8mm pitch FP9, 10
28-pin SOIC wide 2 .300” wide, 0.05” pitch FP11, 12
48-pin SSOP 4 .300”wide, 0.025” pitch FP13,14,23,24
20-pin SOIC wide 4 .300”wide, 0.05” pitch FP17,18,19,20
24-pin SSOP 2 .150”wide, 0.025” pitch FP21, 22
44-pin TQFP 1 0.8mm pitch FP25
16-Pin SSOP 2 .150” wide, 0.025” pitch FP26,27
208-pin PQFP 1 0.5mm pitch FP28 FP28, 29, 30
144-pin TQFP 1 0.5mm pitch FP29 co-exist at a 208-
80-pin TQFP 1 0.5mm pitch FP30 pin PQFP area
176-pin PQFP 1 0.5mm pitch FP31 FP31,32,33
100-pin TQFP 1 0.5mm pitch FP32 co-exist at a 176-
48-pin TQFP 1 0.5mm pitch FP33 pin PQFP area
26x26 BGA matrix 1 0.05” pitch
25x25 0.1” through hole area
2 @ 1x30 0.1” through hole rails for 3.3VCC
2 @ 1x30 0.1” through hole rails for GND
1 @ 1x30 0.1” through hole rail for 5VCC
As shown in Table 3-3, the surface-mount

footprints are carefully selected based on three
factors.
1) The footprints can be used for industry

standard, surface-mount logic devices.
2) The footprints accommodate current CPLDs
and FPGAs.
3) If the designer wants to build a complex
design on the Local bus or separate the bus
at the DPRAMs, there are enough footprints
for a CPU, memory, programmable control
logic, bus transceivers and discrete devices.

Section 3
Prototyping Area Hardware Architecture
3.9.2 The Common BGA Landscape

This RDK provides a 0.05” common pitch BGA a)
landscape in the prototyping area. BGA1 is a full 1. Buy the Minigrid Socket and BGA Land
matrix of 26x26 @ 0.05” pitch with the plated- Socket.
hole size of 0.022” diameter +/- 0.001”.
2. Solder the Minigrid Socket to the PC
board.
We suggest using Ironwood Electronics (web
site: www.ironwoodelectronics.com) BGA Land 3. Solder the BGA device to the Land
Sockets and/or Minigrid Sockets. Designers can Socket and plug the Land Socket to the
convert a BGA to a PGA and prototype a BGA Minigrid Socket.
chip on this RDK. b)
1. Buy BGA Land Sockets only.
Refer to Figure 3-2; if designers use the BGA1
landscape; they can choose either 2. Solder the BGA device on the top of the
a) or b): Land Socket and solder the Land
Socket to the PC board.
BGA Device
Solder
Ironwood BGA
Land Socket
0.014"
Plug
Ironwood Minigrid
Socket (Optional)
Solder
0.018"
Target PCB
Figure 3-2. BGA Landscapes

Section 3
Hardware Architecture Configuring the RDK board
3.10 Configuring the RDK board
Multiplexed Mode Install R27

Non-Multiplexed
Install R29
Mode (default)
16-bit DPRAM Install RN33, RN35,
(default) RN37 and R47
Install RN34, RN36,
32-bit DPRAM
RN38 and R47
Enable left port
advanced counter of Install R59
DPRAM(s) (default)
Disable left port
advanced counter of R58
DPRAM(s)
Configure left port of
DPRAM to pipelined R61
mode (default)
Configure left port of
DPRAM to flow- R62
through mode
Active high local
Install R51 and R86
interrupts
Active low local
Install R49 and R50
interrupts (default)
3.11 Memory Access to the DPRAM

The data in the dual-port memory can be easily
viewed, monitored or modified by using the
function keys in the Memory Display dialog box.
Refer to the PLXMon Software instructions
included in the PLX PCI SDK for more
information.

4. PCB Layout Considerations
4.1 Requirements of Standards 4.2 μBGA Footprint Layout
In order to demonstrate the CompactPCI Hot The RDK is a six-layer CompactPCI board with
Swap functions, board design rules of multiple a 0.8mm μBGA pitch and it includes a 180-pin
standards have been considered in the RDK PCI 9030 μBGA device. To maintain low cost
PCB layout. These major design rules are listed 5mil trace/5mil gap requirements and to
as follows: successfully route the traces out in three routing
layers, the signals at the most outer two rings of
1. PCI bussed signals, AD[0:31], C/BE[0:3]#, the μBGA were routed on the component layer.
PAR, FRAME#, IRDY#, TRDY, STOP#, The first inner layer routed signals at the third
LOCK#, IDSEL, DEVSEL#, PERR#, SERR# ring of the μBGA. The second inner layer routed
and RST#, from the CompactPCI connector, the last two rings without the presence of vias on
J1, should pass through a 10 ohm stub the first inter layer (see the attached gerber files
termination resistor and connect to the for details). Also, the following pad, via and hole
PCI 9030. (CompactPCI and Hot Swap sizes were used.
Specifications)
2. The Trace length of PCI bussed signals from a. Pad size: 14mil (0.350mm)
the CompactPCI connector J1 to the stub b. Via on the component size: 20mil
terminal resistor shall not exceed 15.2mm or (0.508mm)
0.6 inch. (Hot Swap) c. Via on the internal routing layer: 25mil
3. The total trace length from connector J1 (0.635mm)
through stub terminal resistor to PCI 9030 d. Via on the solder side: 25mil (0.635mm)
shall not exceed 38.1mm or 1.5 inches. (Hot e. The plated through hole is 6mil in diameter
Swap)
4. The trace characteristic impedance of
CompactPCI signals shall be 65 ohm+/-10%
(Hot Swap)
5. On Peripheral boards, the PCI clock signal
length shall be 63.5mm+/-2.54mm (2.5
inches +/- 0.1 inches, and shall drive only
one load on the board. (CompactPCI)
6. The J1 connector shall shield at row F on
the board. (CompactPCI)
7. For unused power pins and power pin that
do not connect directly to low impedance
power planes, the decoupling shall be
between 0.01 to 0.2uF high frequency
ceramic capacitor per power pin. The trace
from pin to the capacitor pad shall not be
greater than 15.2mm or 0.6 inch with trace
width at least 0.5mm or 0.02 inch. (Hot
Swap)
8. A board that does not support the IEEE
standard 1149.1 interface must hardwire the
board’s TDI pin to its TDO pin (PCI
Specification)

5. Converting the 6U board to a 6. Customer Support
3U board Prior to contacting customer support, please
ensure you have the following information and
a. At the component side, unplug the micro are situated close to the computer that contains
switch from the Molex 3-pin header (A) the CompactPCI 9030RDK-LITE.
b. Turn the board to the solder side 1. Serial Number of the PLX
c. Unscrew the three mounting screws used to CompactPCI 9030RDK-LITE
hold the PC board with the front panel (C)
d. Follow the cut mark near the center of the 2. Type of processor on the evaluation board
front panel, use a metal saw to cut out the 3. Operating System and type
upper 6U portion of the front panel (E)
e. Bend the PC board along the marked line 4. Description of problem
near the metal strips until it separates into
upper and lower portions (D) You may contact PLX Technology, Inc.
f. Screw back the lower portion of the PC Customer Support at:
board with two screws (B)
Address: PLX Technology, Inc.
870 West Maude Avenue
Sunnyvale, CA 94085
Phone: 408-774-9060
800-759-3735
Fax: 408-774-2169
Email: USA;
http://www.plxtech.com/support/.
Europe, Middle East and South Africa;
euro-apps@plxtech.com
Asia Pacific, China & Australia;
asia-apps@plxtech.com
Website: http://www.plxtech.com
7. References
1. PLX Technology, Inc.
PCI 9030 Data Book
PLX Technology, Inc.,
870 West Maude Avenue,
Sunnyvale, CA 94085 USA
http://www.plxtech.com

8. ABEL Code / Bill of Materials / Schematics
The following pages contain the ABEL code, Bill of materials, and the schematics for the
CompactPCI 9030RDK-LITE circuit board.
8.1 ABEL code for U13

Module dpramctr
Title 'DPRAM controller'
"Special constants
x,c,z = .X.,.C.,.Z.;
"It is the control signals to the Dual-Port memory
"on the PCI 9030RDK-LITE board.
"2/9/2000
Declarations
"inputs
CLK,OE pin 1, 11;

CS0L,ADSL,BLASTL,LWRL pin 2, 4, 5, 9;
"outputs
CE0LL,RWLL pin 19,12;

CE0WL pin 18 is type 'reg';
DPRAMADSL pin 17 is type ' reg_d ';
Q1,Q0 pin 13,14 is type'reg,invert';
SREG = [Q1,Q0];
"State Values
S0 = [0,0];
S1 = [0,1];
S2 = [1,1];
Equations
RWLL = !LWRL;
DPRAMADSL := ADSL;
!CE0LL = (!LWRL & !CS0L) # (LWRL & !CE0WL);
[CE0WL,Q1,Q0,DPRAMADSL].CLK = CLK;
[CE0WL,Q1,Q0,DPRAMADSL].OE = !OE;
state_diagram SREG;
state S0: if (LWRL & !CS0L & !ADSL) then S1 with CE0WL:=0;
else S0 with CE0WL:=1;
state S1: if (LWRL & !CS0L & BLASTL) then S1 with CE0WL:=0;
if (LWRL & !CS0L & !BLASTL) then S2 with CE0WL:=1;
state S2: if (LWRL & !CS0L & !ADSL) then S1 with CE0WL:=0;
else S0 with CE0WL:=1;
END dpramctr

Section 8
ABEL Code / Bill of Materials / Schematics Bill of Materials
Table 8-1. Bill of Materials
Item Manufacturer's Part Component

Qty. Manufacturer Description Package Type Source
No. Number Designator(s)
SURFACE MOUNT COMPONENTS
1 1 Linear Technology LTC1643LCGN IC, PCI Hot Swap controller 16-pin 0.15" SSOP Marshall U1
IC, Tiny Logic single hex
2 1 Fairchild Semi. NC7SZ04M5 5-pin SOT23, SMT Arrow Elect. U2
inverter
IC, Tiny Logic two input NOR
3 1 Fairchild Semi. NC7SZ02M5 5-pin SOT23, SMT Arrow Elect. U3
gate
4 1 Fairchild Semi. FDR4420A IC, single N channel MOSFET Super SOT-8 Digi-Key U4
IC, 3A 5V to 3.3V LDO SMT, M package, 3-lead
5 1 Linear Technology LT1587CM-3.3 **Marshall U5
regulator plastic DD PAK
180-pin 0.8mm pitch
6 1 PLX PCI 9030-AA60BI IC, PCI I/O accelerator, 3.3V PLX provides U6
μBGA
IC, zero delay buffer, 3.3V,
7 1 Cypress CY2305SC-1 8-pin 150-mil SOIC FAI U9
250ps skew
IC, Dual-port SRAM,
100-pin TQFP, package
8 1 Cypress CY7C09349AV-9AC 9 ns delay, 3.3V, Package FAI U11
name A100
name A100
IC, Reset Controller, 140ms
9 1 Maxim MAX6306UK30D1-T SOT23-5 Digi-Key U15
reset
OSC, 3.3V 1.8432MHz 5.0x7.0x1.75mm,surface M-Tron 800-
10 1 M-Tron M213FGN1.8432MHz U16
oscillator mount 762-8800
Nu Horizons,
IC, UART with 16-byte FIFOs, 100-pin TQFP, 0.5mm
11 1 Exar ST16C550CQ48 Arrow, Future U17
3.3V pitch
Electronics
IC, RS232 transceiver, 3T/5R,
12 1 Maxim MAX3245CAI 28-pin SSOP Digi-Key U18
3.3V
SMA Case 403B-01 Avnet, 408-435-
13 1 Motorola 1SMA12CAT3 IC, 12V Zener diode D1
Plastic. SMT 3500
14 1 Panasonic LNG901CFBW LED, blue, 500mcd T1 3/4, through hole Digi-Key D2
15 5 Hewlett Packard HSMG-C650 LED, green, SMT, 1206 Digi-key D3-D7
Connector, 2mm hard metric
17 1 AMP 352068-1 Z-PACK 2mm HM Newark J1
PCB mount connector
18 1 SPC DE-9P-FRS Connector, 9-pin, D-type, Male Right angle PCB mount Digi-key J5
Header assembly, two row
19 1 AMP 1-104655-1 SMT Electrosonic J4
100-pin, 50 mil pitch
Terminal strip, 1x6, 0.1"oc,
20 1 Samtec TSM-106-01-T-SV SMT FAI J2
PCB mounted
21 6 Samtec TSM-110-01-T-DV SMT FAI LAH1 - LAH6
PCB mounted
22 1 Samtec TSM-129-01-T-DV SMT FAI J3
PCB mounted
Socket, 8-pin DIP, 300 mil, for
23 3 Samtec ICF-308-T-O SMT, 8-pin DIP FAI U8, U10, U14
serial EEPROM
24 1 Samtec PLCC-020-T-N Socket, 20-pin PLCC SMT, 20-pin PLCC FAI U13
25 1 Samtec PLCC-032-T-N Socket, 32-pin PLCC SMT, 32-pin PLCC FAI FP1
26 1 Molex 53398-0390 Header, 1.25mm pitch SMT, straight FAI S1
27 1 Omron B3S1002 Switch, Push Button SMT, Digi-key S2
Cap. ceramic, 0.047uF, 50V,
28 1 Kemet C0805C473M5UAC SMT, 0805 Electrosonic C12
20%
C1-C8, C28-C35,
Cap. ceramic, 0.01uF, 50V,
29 30 Kemet C0805C103M5UAC SMT, 0805 Electrosonic C50-C54, C60-
20%
C64, C70-C73

Section 8
C9-C11, C13,
C15, C18, C20-
Cap. ceramic, 0.1uF,
30 35 Kemet C0805C104M5UAC SMT, 0805 Electrosonic C27, C44-C49,
50V, 20%
C55-C59, C65-
C69, C75-C79
Cap. tantalum, 10uF, 20V, C14, C16, C19,
31 10 Panasonic ECS-T1DC106R SMT, Ccase Newark
Ccase C74, C91-C96
32 1 Steward L10805E400R Ferrite chip, 500mA SMT, 0805 Digi-Key L1
RN1-RN13,
Res. Network, 10 ohm, 5%,
33 16 CTS 742-08-3-100-J-BK SMT, Ccase Digi-Key RN33, RN35,
4R, isolated
RN37
RN14-RN32,
Res. Network, 10K, 5%,
34 24 CTS 742-08-3-103-J-BK SMT,Ccase Digi-Key RN39, RN41-
4R, isolated
RN44
Res. Network, 10K, 2%,
35 1 CTS 766-14-3-103-G-SP SMT, Ccase Digi-Key RN40
7R, isolated
R29, R46,
36 11 Panasonic ERJ-6GEYJ0R0V Res. zero ohm, 1/10W, 5% SMT, 0805 Digi-Key
R65-R72, R76
37 1 Vishay WSL1206R010FRE4 Res. 0.01 ohm, 1/4W, 1% SMT 1206 Electrosonic R13
38 1 Vishay WSL2010R018FB43 Res. 0.018 ohm, 1/2W, 1% SMT, 2010 Electrosonic R10
39 2 Vishay WSL1206R100FRE4 Res. 0.1 ohm 1/10W, 1% SMT, 1206 Electrosonic R1-R2
40 4 Panasonic ERJ-14RQJR22 Res. 0.2 ohm, 1/10W, 5% SMT, 1210 Digi-Key R3-R6
41 1 Panasonic ERJ-6GEYJ100V Res. 10 ohm, 1/10W, 5% SMT, 0805 Digi-Key R11
42 6 Panasonic ERJ-6GEYJ220V Res. 22 ohm, 1/10W, 5% SMT, 0805 Digi-Key R18-R22, R52
44 2 Panasonic ERJ-6GEYJ101V Res. 100 ohm, 1/10W, 5% SMT, 0805 Digi-Key R12, R16
45 5 Panasonic ERJ-6GEYJ151V Res. 150 ohm, 1/10W, 5% SMT, 0805 Digi-Key R36-R40
46 1 Panasonic ERJ-6GEYJ102V Res. 1K, 1/10W, 5% SMT, 0805 Digi-Key R15, R23
47 1 Panasonic ERJ-6GEYJ122V Res. 1.2K, 1/10W, 5% SMT, 0805 Digi-Key R8
48 2 Panasonic ERJ-6GEYJ202V Res. 2K, 1/10W, 5% SMT, 0805 Digi-Key R7, R9
49 1 Panasonic ERJ-6GEYJ302V Res. 3K, 1/10W, 5% SMT, 0805 Digi-Key R14
R17, R24-R25,
R30-R35, R42-
R45, R49, R51,
50 29 Panasonic ERJ-6GEYJ103V Res. 10K, 1/10W, 5% SMT, 0805 Digi-Key R53-R57, R59-
R61, R63, R73-
R74, R77-R78,
R83
R79-R82,
51 6 Panasonic ERJ-6GEYJ106V Re. 10M, 1/10W, 5% SMT, 0805 Digi-Key
R84-R85
MANUALLY INSERTED COMPONENTS
OSC, 60MHz clock oscillator,
52 1 Ecliptek EP1345HSPD-60.000M 3.3V, 50ppm, 40-60% duty 8-pin half size DIP Ecliptek U8
cycle
IC, PLD, 8in/8io, 5ns delay,
53 1 Lattice Semi. GAL16LV8-5LJ 20-pin PLCC FAI U13
3.3V
Avnet, Arrow,
54 1 Fairchild Semi. NM93CS56LN IC, 2Kb serial EEPROM, 3.3V 8-pin DIP Future U10
Electronics
MISCELLANEOUS COMPONENTS
PCB, CompactPCI 9030RDK-
56 1 90-0015-100-A
LITE Rev. 100
57 2 Kycon JS-1000 Screw, Hex, Jack, 4-40 Kycon
Front Panel, 6U, 4HP
One Stop
two type 4 handles,
58 1 One Stop Systems FP-6U-04HP-PLX01 Systems
micro switch assembly, and
(760)745-9883
center PCB holder
PARTS THAT SHOULD NOT BE ASSEMBLED

Section 8
IC, Dual-port SRAM, 9 ns

100-pin TQFP, package
8 0 Cypress CY7C09349V-9AC delay, 3.3V, Package name FAI U12
name A100
A100
Cap. Ceramic, 100pF, 50V,
60 0 Kemet C0805C101K5XAC SMT, 0805 Electrosonic C17
10%
Res. Network, 10 ohm, 5%, 4R, RN34, RN36,
33 0 CTS 742-08-3-100-J-BK SMT, Ccase Digi-Key
isolated RN38
R26-R27, R41,
50 0 Panasonic ERJ-6GEYJ103V Res. 1/10W, 10K, 5% SMT, 0805 Digi-Key R48, R50, R58,
R62, R64
36 0 Panasonic ERJ-6GEYJ0R0V Res. zero ohm, 1/10W, 5% SMT, 0805 Digi-Key R28, R47, R75
0.1" oc 2 pin single row jumper
61 0 - - 2-pin through hole type JP1-JP6
header
Second Source Information
OSC, 3.3V, 50ppm,
11 1 CTS CB3LV-3C-1.8432 5.0x7.0x1.8mm,SMT Digi-Key U16
1.8432MHz oscillator
IC, Dual-port SRAM, 9ns delay 100-pin TQFP

8 1 Cypress CY7C09349V-9AC FAI U11
3.3V, package name A100
Note 1: Insight: (800) 677-7716
Note 2: Marshall Industries: 408-942-4600
Note 3: Avnet Electronics Marketing: 408-435-3500
PLX Part #: 91-0015-105-A

Section 8

A B C D E
ECN HISTORY
ECN NUMBER DATE NOTE
000 4/12/2000 board was transferred to manufacturing

001 6/22/2001 changed R83 at TRST# from puii-up to pull-down
002 6/21/2002 Modified contents
4
CompactPCI 9030RDK-LITE BLOCK DIAGRAM 4
Signal Headers
PG5
Separate Bus
3 upto 32-bit 67MHz 3
Synchronous Prototyping
JPOM User Defined Prototype
Dual-Port RAM RS232 Port Testl Headers Flash ROM Socket Reset Circuit
Connector Status LEDs Footprints
& Interface PG6 PG7
PG 6
PG 6
PG6 PG 4 PG 8-11
PG5
LOCAL BUS
upto 32-bit 60MHz
3.3VDC
Hot Swap Control

Circuit PCI 9030
PG4
PG 3
2 2
5VDC
CPCI BUS (C PCI connector J1, PG 2)
32-bit 33MHz
1 1
PLX TECHNOLOGY, INC.

870 Maude Ave, Sunnyvale, CA 94085
www.plxtech.com
Title
Electrical Block Diagram
Size Document Number Rev
Custom CompactPCI 9030RDK-LITE 002
Date: Thursday, July 25, 2002 Sheet 1 of 12

A B C D E
A B C D E
Stub Terminal Resistors Compact PCI J1

TO PCI 9030 RN1 LONG_3.3V 3.3VCPCI
4 ENUML ENUML 1 8 PCI_ENUM#
AD0 2 7 PCI_AD0
AD1 3 6 PCI_AD1
AD[31:0] AD2 4 5 PCI_AD2 J1
4 AD[31:0]
R1
742-08-3-100-J 0.1 R2
AD0 C6 0.1
4 RN2 3.3VCCL 4
AD1 C22
3.3VCCL
AD2 AD5 1 8 PCI_AD5 A15
3.3VCC
AD3 3.3VCC
AD4 3 6 PCI_AD3 A19
3.3VCC C1 C2 LONG_5V 5VCPCI
3.3VCC
AD6 A23
742-08-3-100-J 3.3VCC 0.01uF 0.01uF
AD7 PCI_AD0 D24 C10
AD0 3.3VCC
AD8 PCI_AD1 A24 C18
RN3 AD1 3.3VCC
AD9 PCI_AD2 E23 D25
PCI_AD7 AD2 3.3VCC R3
AD10 AD7 1 8 PCI_AD3 C23
AD3 0.2 R4
AD11 AD9 2 7 PCI_AD9 PCI_AD4 B23
AD4 0.2
AD12 AD8 3 6 PCI_AD8 PCI_AD5 E22 D3
AD5 5VCCL
AD13 4 C/BE0L C/BE0L 4 5 PCI_C/BE0# PCI_AD6 D22 D23
AD6 5VCCL
AD14 PCI_AD7 A22 A1
742-08-3-100-J AD7 5VCC
AD15 PCI_AD8 C21 A25
AD8 5VCC
AD16 PCI_AD9 B21 B2
RN4 AD9 5VCC C3 C4 LONG_VIO VIOPCI
AD17 PCI_AD10 E20 B24
CompactPCI Connector J1
AD10 5VCC
AD18 AD10 1 8 PCI_AD10 PCI_AD11 D20 E1
AD11 5VCC 0.01uF 0.01uF
AD19 AD11 2 7 PCI_AD11 PCI_AD12 A20 E25
AD12 5VCC R5
AD20 AD12 3 6 PCI_AD12 PCI_AD13 E19
AD13 0.2 R6
AD21 AD13 4 5 PCI_AD13 PCI_AD14 C19
AD14 0.2
AD22 PCI_AD15 B19 C4
742-08-3-100-J AD15 VI/OL
AD23 PCI_AD16 C11 C24
AD16 VI/OL
AD24 PCI_AD17 B11 C8
RN5 AD17 VI/O
AD25 PCI_AD18 A11 C16
AD18 VI/O -12VCPCI +12VCPCI
AD26 AD14 1 8 PCI_AD14 PCI_AD19 E10 C20
AD19 VI/O
AD27 AD15 2 7 PCI_AD15 PCI_AD20 D10
AD20
AD28 4 C/BE1L C/BE1L 3 6 PCI_C/BE1# PCI_AD21 A10 B1
AD21 -12V
AD29 4 PAR PAR 4 5 PCI_PAR PCI_AD22 E9
AD22
AD30 PCI_AD23 C9 D1
742-08-3-100-J AD23 +12V
AD31 PCI_AD24 E8
AD24
PCI_AD25 D8 B6
RN6 AD25 GND C5 C6 C7 C8
3 PCI_AD26 A8 B8 3
PCI_SERR# AD26 GND
4 SERRL SERRL 1 8 PCI_AD27 E7 B10
AD27 GND 0.01uF 0.01uF 0.01uF 0.01uF
4 PERRL PERRL 2 7 PCI_PERR# PCI_AD28 C7 B16
AD28 GND
4 LOCKL LOCKL 3 6 PCI_LOCK# PCI_AD29 B7 B18
AD29 GND
4 STOPL STOPL 4 5 PCI_STOP# PCI_AD30 A7 B20
AD30 GND
PCI_AD31 E6 B22
742-08-3-100-J AD31 GND
D5
GNDL
D7
RN7 GNDL
PCI_C/BE0# E21 D9
C/BE0# GNDL
4 DEVSELL DEVSELL 1 8 PCI_DEVSEL# PCI_C/BE1# E18 D11
C/BE1# GNDL
4 TRDYL TRDYL 2 7 PCI_TRDY# PCI_C/BE2# E11 D17
C/BE2# GNDL
3,4 BD_SELL BD_SELL 3 6 PCI_BD_SEL# PCI_C/BE3# A9 D19
C/BE3# GNDL
4 IRDYL IRDYL 4 5 PCI_IRDY#
F1
742-08-3-100-J GND
PCI_INTA# A3 F2
INTA# GND
B3 F3
RN8 INTB# GND
C3 F4
INTC# GND
4 FRAMEL FRAMEL 1 8 PCI_FRAME# E3 F5
INTD# GND
4 C/BE2L C/BE2L 2 7 PCI_C/BE2# F6
GND
AD16 3 6 PCI_AD16 F7
GND
AD17 4 5 PCI_AD17 F8
GND
F9
742-08-3-100-J GND
PCI_FRAME# B15 F10
FRAME# GND
PCI_IRDY# C15 F11
RN9 IRDY# GND
PCI_DEVSEL# A16
DEVSEL#
AD18 1 8 PCI_AD18 F15
GND
AD19 2 7 PCI_AD19 F16
GND
AD20 3 6 PCI_AD20 PCI_TRDY# E15 F17
TRDY# GND
AD21 4 5 PCI_AD21 PCI_STOP# D16 F18
STOP# GND
PCI_IDSEL B9 F19
742-08-3-100-J IDSELS GND
PCI_LOCK# E16 F20
LOCK# GND
F21
RN10 GND
2
F22 2
GND
AD22 1 8 PCI_AD22 PCI_PAR D18 F23
PAR GND
AD23 2 7 PCI_AD23 PCI_PERR# E17 F24
PERR# GND
4 IDSEL IDSEL 3 6 PCI_IDSEL PCI_SERR# A18 F25
SERR# GND
4 C/BE3L C/BE3L 4 5 PCI_C/BE3#
E2
742-08-3-100-J TDI
PCI_RST# C5 C1
PCI_RST# TRST#
PCI_HEALTHY# B4 A2
RN11 HEALTHY# TCK
PCI_BD_SEL# D15 C2
BD_SEL#S TMS
AD24 1 8 PCI_AD24 PCI_ENUM# C25 D2
ENUM# TDO
AD25 2 7 PCI_AD25
AD26 3 6 PCI_AD26 C17
SBO#
AD27 4 5 PCI_AD27 D6 B17
CLK SDONE
D21
742-08-3-100-J M66EN
A6 E24
REQ# ACK64#
E5 B25
RN12 GNT# REQ64#
AD28 1 8 PCI_AD28 A4
BRSVP1A4
AD29 2 7 PCI_AD29 A5
BRSVP1A5
AD30 3 6 PCI_AD30 B5
BRSVP1B5
AD31 4 5 PCI_AD31 D4
INTP
E4
742-08-3-100-J INTS
RN13
3 PCIRSTL PCIRSTL 1 8 PCI_RST#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
3 HEALTHYL HEALTHYL 2 7 PCI_HEALTHY# Hot Swap PICMG 2.1 R1.0
4 INTAL INTAL 3 6 PCI_INTA#
4 5 Complied
D14
D13
D12
C14
C13
C12
F14
F13
F12
E14
E13
E12
B14
B13
B12
A14
A13
A12
742-08-3-100-J
1 1
PCLK
4 PCLK
PLX TECHNOLOGY
www.plxtech.com
Title
CompactPCI J1 Connector

A B C D E
A B C D E
LONG_VIO Hot Swap control circuit

4 4
R7 R8 R9
2K 1.2K 2K
5VCPCI
U1
5 9 R10 0.018, 1/2W, 1%

2,4 BD_SELL ON# 3VIN
13
5VIN U4 FDR4420A 5VCC
6 10 1
FAULT# 3VSENSE DRAIN1
12 2
5VSENSE DRAIN2
3 U5
R11 10 DRAIN3 3.3VCC
2 HEALTHYL 7 11 4 6
PWRGD# GATE GATE DRAIN4 LT1587CM-3.3
7
DRAIN5 R13
+12VCPCI 1 3
12VIN 3VOUT
14 5 3 2 3.3V_3A 1 2
5VOUT SOURCE1 VIN VOUT
-12VCPCI 2 8
ADJ
VEEIN SOURCE2
2
4 C13 C14 0K0 1/4W

D1 C10 TIMER
C9 16 +
1
C11 12VOUT +12V
0.1uF C16
12V 0.1UF 0.1UF 10UF
15 -12V R12 +
1
0.1UF VEEOUT C15
1
100
8
GND 0.1uF 10uF
2
1
1SMA12CAT3 C12
3 LTC1643L 3
0.047UF
2
LONG_VIO
U2 U3
1 5 1 5
NC VCC INA VCC
2 PCIRSTL PCIRSTL 2 4 2 4 LOCAL_RSTL LOCAL_RSTL 4

IN_A NOT_A INB NOR_Y
3 3
GND GND
NC7SZ04M5 NC7SZ02M5
SWITCH & LED

Handle is LONG_3.3V LONG_5V
2 unlocked 2
ESD Strip Circuits - 3 Places

1
R16
R14
3K
Molex 3-pin header R85 2 1 ESD_STRIP9
75 BLUE LEDS: ESD_STRIP8
2
3 1. PANASONIC, LNG91LCFBW or ESD_STRIP7 Top

CPCISW 1 10M 2 1
1
4 CPCISW LNG901CFBW or LNG992CFBW.
2 m279 m280 m283 m284
1
2
2. HP, HLMP-CB30 or
m281 R84 10M m282
1
1
S1 D2 HLMP-CB31
LONG_5V R15 BLUE_LED
1K
R79 2 1 ESD_STRIP6
2
R17 Handle is ESD_STRIP5

ESD_STRIP4 Middle
10K locked 10M 2 1
1
m277 m278 m273 m274
1
LEDonL m275 R80 10M m276
1
4 LEDonL
R81 1 2 10M ESD_STRIP3

ESD_STRIP2
ESD_STRIP1
2 1 Bottom
1
m269 m270 m271 m272
1
m267 R82 10M m268
1
1 1 1
PLX TECHNOLOGY
WWW.PLXTECH.COM
Title
Hot Swap Control Circuit

A B C D E
A B C D E
LONG_3.3V
LONG_VIO
P14
B13
K13
P12
F11
M8
N2
N5
P1
B2
B6
E1
U6
L5
J5
LD[31:0] AD[31:0]
NC
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VI/O
5,6,7 LD[31:0] AD[31:0] 2
LD0 J13 M4 AD0
LD0/LAD0 AD0
LD1 K14 P3 AD1
LD1/LAD1 AD1 3.3VCC 3.3VCC 3.3VCC
LD2 K12 P2 AD2
LD2/LAD2 AD2 RN14 RN15 RN16
LD3 L14 N3 AD3
LD3/LAD3 AD3
LD4 K11 M3 AD4 LBE3L 1 8 ADSL 1 8 LW/RL 1 8
LD4/LAD4 AD4
LD5 K10 M2 AD5 LBE2L 2 7 BLASTL 2 7 READYL 2 7
4 LD5/LAD5 AD5 4
LD6 L13 L4 AD6 LBE1L 3 6 WRL 3 6 BTERML 3 6
LD7 M14
LD6/LAD6
LD7/LAD7
PCI 9030 AD6
AD7
M1 AD7 LBE0L 4 5 RDL 4 5 CS0L 4 5
Multiplexed mode: install R27 LD8 N14
LD8/LAD8 AD8
L3 AD8
LD9 M13 L2 AD9 742-08-3-103-J-XX 742-08-3-103-J-XX 742-08-3-103-J-XX
non-multiplexed mode: install R29(default). LD10 M12
LD9/LAD9 AD9
K4 AD10 3.3VCC
LD10/LAD10 AD10
Non hot swap system: install R28. LONG_3.3V LD11 N13
LD11/LAD11 AD11
K1 AD11 3.3VCC 3.3VCC
LD12 N12 K3 AD12 RN17 RN18 RN19
LD12/LAD12 AD12
LD13 L11 K2 AD13 CS1L 1 8 LA2 1 8 LA6 1 8
LD13/LAD13 AD13
LD14 P11 J1 AD14 LREQ 2 7 LA3 2 7 LA7 2 7
R27 10K LD14/LAD14 AD14
MODE LD15 M11 J2 AD15 3 6 LA4 3 6 LA8 3 6
LD15/LAD15 AD15
LD16 N11 F1 AD16 4 5 LA5 4 5 LA9 4 5
LD16/LAD16 AD16
BD_SELL LD17 L10 PCI Signals F4 AD17
LD17/LAD17 AD17 742-08-3-103-J-XX 742-08-3-103-J-XX 742-08-3-103-J-XX
LD18 P10 F2 AD18
R28 R29 LD18/LAD18 AD18
LD19 M10 F3 AD19
LD20 P9 E2 AD20
0 0 LD20/LAD20 AD20 RN20 RN21 RN22
LD21 N9 E3 AD21
LD21/LAD21 AD21
LD22 L9 D1 AD22 LA10 1 8 LA14 1 8 LA18 1 8
LD22/LAD22 AD22
LD23 P8 E4 AD23 LA11 2 7 LA15 2 7 LA19 2 7
LD23/LAD23 AD23
LD24 N8 D3 AD24 LA12 3 6 LA16 3 6 LA20 3 6
LD24/LAD24 AD24
LD25 L8 C1 AD25 LA13 4 5 LA17 4 5 LA21 4 5
LD25/LAD25 AD25
LD26 P7 B1 AD26
LD26/LAD26 AD26 742-08-3-103-J-XX 742-08-3-103-J-XX 742-08-3-103-J-XX
LD27 M7 C2 AD27
LD27/LAD27 AD27
LD28 N7 C3 AD28
LD29 K7 B3 AD29
LD29/LAD29 AD29 RN23 RN24 RN25
LD30 P6 D4 AD30
LD30/LAD30 AD30
LD31 L6 A3 AD31 LA22 1 8 LA24/GPIO7 1 8 LD0 1 8
LA[23:2] LD31/LAD31 AD31
5,7 LA[23:2] LA23 2 7 LA25/GPIO6 2 7 LD1 2 7
LA2 J11 L1 C/BE0L C/BE0L 2 3 6 LA26/GPIO5 3 6 LD2 3 6
LA2 C/BE0#
LA3 J14 J4 C/BE1L C/BE1L 2 4 5 LA27/GPIO4 4 5 LD3 4 5
LA3 C/BE1#
LA4 H10 PCI Signals G5 C/BE2L C/BE2L 2
LA4 C/BE2# 742-08-3-103-J-XX 742-08-3-103-J-XX 742-08-3-103-J-XX
LA5 H13 D2 C/BE3L C/BE3L 2
LA5 C/BE3#
LA6 H12
LA6 3.3VCC 3.3VCC 3.3VCC
3 LA7 H11 G2 FRAMEL FRAMEL 2 3
LA7 FRAME# RN26 RN27 RN28
LA8 H14 G3 IRDYL IRDYL 2
LA8 IRDY#
LA9 G12 G4 TRDYL TRDYL 2 LD4 1 8 LD8 1 8 LD12 1 8
LA9 TRDY#
LA10 G10
LA10 PCI Signals STOP#
H4 STOPL STOPL 2 LD5 2 7 LD9 2 7 LD13 2 7
LA11 G14 G1 DEVSELL DEVSELL 2 LD6 3 6 LD10 3 6 LD14 3 6
LA11 DEVSEL#
LA12 F13 H3 PERRL PERRL 2 LD7 4 5 LD11 4 5 LD15 4 5
LA12 PERR#
LA13 F12 H5 SERRL SERRL 2
LA13 SERR# 742-08-3-103-J-XX 742-08-3-103-J-XX 742-08-3-103-J-XX
LA14 F10
LA14
LA15 F14 H2 LOCKL LOCKL 2
LA15 LOCK# 3.3VCC 3.3VCC 3.3VCC
LA16 E12 H1 PAR PAR 2
LA16 PAR RN29 RN30 RN31
LA17 E14 B4 INTAL INTAL 2
LA17 INTA#
Default settings for pin C12, B12, A12-A13 are LA18 E11 D5 LD16 1 8 LD20 1 8 LD24 1 8
LA18 PME# PA7
LA19 D12 PCI Signals N4 ENUML ENUML 2 LD17 2 7 LD21 2 7 LD25 2 7
address lines.Otherwise, pull-up or pull-down LA19 ENUM#
LA20 D14 LD18 3 6 LD22 3 6 LD26 3 6
LA20
resistors may be required. LA21 C14 K5 LEDonL LEDonL 3 LD19 4 5 LD23 4 5 LD27 4 5
LA21 LEDon#
LA22 D11 P4 CPCISW CPCISW 3
LA22 CPCISW 742-08-3-103-J-XX 742-08-3-103-J-XX 742-08-3-103-J-XX
LA23 C13
LA23
7 LA24/GPIO7 LA24/GPIO7 C12
LA24/GPIO7 3.3VCC
7 LA25/GPIO6 LA25/GPIO6 B12 B10 BTERML BTERML 6,7
LA25/GPIO6 BTERM# RN32
7 LA26/GPIO5 LA26/GPIO5 A13 C11 ADSL ADSL 5,6,7
LA26/GPIO5 ADS#
7 LA27/GPIO4 LA27/GPIO4 A12 M9 ALE ALE 6,7 LD28 1 8
LA27/GPIO4 ALE
B11 BLASTL BLASTL 5,6,7 LD29 2 7
BLAST#
GPIO8 L12 A11 LW/RL LW/RL 5,6,7 LD30 3 6
5,7 GPIO8 GPIO8 LW/R#
D10 RDL RDL 7 LD31 4 5
RD# LONG_3.3V
LBE0L N6 E10 WRL WRL 7
5,6,7 LBE0L LBE0# WR# 742-08-3-103-J-XX
LBE1L M6 C10 READYL READYL 6,7
5,6,7 LBE1L LBE1# READY#
LBE2L P5
5,6,7 LBE2L LBE2#
LBE3L M5 D9 LRESEToL LRESEToL 6,7
5,6,7 LBE3L LBE3# LRESETo# C20 C21 C22 C23 C24 C25 C26 C27
K8
BCLKo
J2
TCK A6 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
1 TCK
TMS B5 C9 CS0L CS0L 5,7
2 TMS CS0#
2 TDI A5 B9 CS1L CS1L 6,7 2
3 TDI CS1#
TRSTL E6 B7 GPIO3/CS3L GPIO3/CS3L 7
4 TRST# GPIO3/CS3# C28 C29 C30 C31 C32 C33 C34 C35
TDO C5 D7 GPIO2/CS2L GPIO2/CS2L 7
5 TDO GPIO2/CS2#
2,3 BD_SELL BD_SELL G11 A8 GPIO1/LLOCKoL GPIO1/LLOCKoL 6,7
6 BD_SEL#/TEST GPIO1/LLOCKo# 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
D8 GPIO0/WAITo# GPIO0/WAIToL 6,7
R83 GPIO0/WAITo#
E9
1x6 header 10K LCLK 3.3VCC
7 MODE MODE K9 E8 LREQ LREQ 6,7
MODE LREQ
7 LPMESET LPMESET J12 A9 LGNT LGNT 6,7
LPMESET LGNT
7 LPMINTL LPMINTL D13 B8 LINTi1 LINTi1 6,7
LPMINT# LINTi1
JTAG Port LINTi2
C8 LINTi2 LINTi2 7
R24
U10
PCLK A4 C7 EECS 1 8 10K
2 PCLK
3 LOCAL_RSTL LOCAL_RSTL C4
PCLK
PCI Signals
EECS
A7 EESK 2
CS VCC
7 PRE C44 User Defined Status LEDs
2 IDSEL
IDSEL E5
RST#
IDSEL
EESK
EEDI
D6 EEDI 3
SK
DI
PRE
PE
6 PE and Power LED
E7 EEDO 4 5 0.1uF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
EEDO DO GND R25

NC
NC
3.3VCC 93CS66L(8DIP-Socket) D3
R23 R36 150 VD1 2 GREEN
1 GD1
A1
A2
J3
K6
C6
L7
N1
N10
G13
A14
A10
B14
E13
F5
J10
P13
PCI9030-uBGA 1K 10K PA2

EEDO 7
R26 0.8mm pitch 180-pin EEDI 7
D4
R37 150 GREEN
3.3VCC EESK 7 VD2 2 1 GD2 PA3
10K 3.3VCC
R41 10K EECS 7
LCLK D5
R38 150 VD3 2 GREEN
1 GD3 PA4
C17 3.3VCC
100pF D6
GPIO0/WAIToL R31 10K R49 10K LINTi1 R39 150 VD4 2 GREEN
1 GD4 PA5
3.3VCC
L1 Clock Circuit GPIO1/LLOCKoL R32 10K D7 GREEN
Ferrite 500mA R40 150 VD5 2 1 GD5
LVCC GPIO2/CS2L R33 10K R51 10K LINTi2
1 U9 1
GPIO3/CS3L R34 10K R48 R50
6 3 R18 22
3.3VCC VDD CLK1
C18 GPIO8 R35 10K
+ C19 2 R19 22
10uF CLK2 DPRAMCLK 5
0.1uF LPMESET R30 10K 10K 10K
U8 1 5 R20 22 PLX TECHNOLOGY, INC.
REF CLK3 LCLOCK 7
8 5 OSCCLK
VCC OUT 22 870 Maude Ave, Sunnyvale, CA 94085
7 R21 POMCLK 6
CLK4 www.plxtech.com
4 1 4 8 R22 22 Install R49 and R51 (default) Title
GND NC GND CLKOUT PA1
60MHz OSC Do not install R48 and R50 PCI9030, Clock Circuit, E2PROM& LEDs
CY2305 Size Document Number Rev

A B C D E
A B C D E
16-bit bus: install RN33, RN35, and R37 (default) 3.3VCC

Dual-port RAM and 3.3VCC
32-bit bus: install RN34, RN36, and R38 Interface Circuits
LD[0:31] U11 U12
68
69
70
71
15
28
46
68
69
70
71
15
28
46
4,6,7 LD[0:31]
4
5
6
7
4
5
6
7
AR[11:0] AR[11:0]
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RN33 A0 92 83 AR0 A0 92 83 AR0
A0L A0R A0L A0R
4,6,7 LBE1L LBE1L 1 8 A0 A1 93 82 AR1 A1 93 82 AR1
A1L A1R A1L A1R
LA2 2 7 A1 A2 94 81 AR2 A2 94 81 AR2
A2L A2R A2L A2R
LA3 3 6 A2 A3 95 80 AR3 A3 95 80 AR3
A3L A3R A3L A3R
4 LA4 4 5 A3 A4 96 79 AR4 A4 96 79 AR4 4
A4L A4R A4L A4R
A5 97 78 AR5 A5 97 78 AR5
10 ohm 4R isolated A5L A5R A5L A5R
A6 98 77 AR6 A6 98 77 AR6
A6L A6R A6L A6R
A7 99 Synchronous 76 AR7 A7 99 Synchronous 76 AR7
RN34 A7L A7R A7L A7R
A8 100 75 AR8 A8 100 75 AR8
A8L Dual-Port SRAM A8R A8L Dual-Port SRAM A8R
LA2 1 8 A9 1 74 AR9 A9 1 74 AR9
A9L A9R A9L A9R
LA3 2 7 A10 2 4K x 18 73 AR10 A10 2 4K x 18 73 AR10
A10L A10R A10L A10R
LA4 3 6 A11 3 72 AR11 A11 3 72 AR11
A11L A11R A11L A11R
LA5 4 5 DR[31:0] LD[0:31] DR[31:0]
4,6,7 LD[0:31]
LD0 37 39 DR0 LD16 37 39 DR16
10 ohm 4R isolated IO0L IO0R IO0L IO0R
LD1 36 40 DR1 LD17 36 40 DR17
IO1L IO1R IO1L IO1R
LD2 34 41 DR2 LD18 34 41 DR18
RN35 IO2L IO2R IO2L IO2R
LD3 33 42 DR3 LD19 33 42 DR19
IO3L IO3R IO3L IO3R
LA5 1 8 A4 LD4 32 43 DR4 LD20 32 43 DR20
IO4L IO4R IO4L IO4R
LA6 2 7 A5 LD5 31 44 DR5 LD21 31 44 DR21
IO5L IO5R IO5L IO5R
LA7 3 6 A6 LD6 30 45 DR6 LD22 30 45 DR22
IO6L IO6R IO6L IO6R
LA8 4 5 A7 LD7 29 47 DR7 LD23 29 47 DR23
R42 10K IO7L IO7R R44 10K R53 10K IO7L IO7R R55 10K
27 48 27 48
10 ohm 4R isolated IO8L IO8R IO8L IO8R
LD8 26 49 DR8 LD24 26 49 DR24
IO9L IO9R IO9L IO9R
LD9 25 50 DR9 LD25 25 50 DR25
RN36 IO10L IO10R IO10L IO10R
LD10 24 51 DR10 LD26 24 51 DR26
IO11L IO11R IO11L IO11R
LA6 1 8 LD11 23 52 DR11 LD27 23 52 DR27
LA7 2 7 LD12 22 53 DR12 LD28 22 53 DR28
IO13L IO13R 3.3VCC IO13L IO13R
LA8 3 6 LD13 21 54 DR13 LD29 21 54 DR29
LA9 4 5 LD14 20 55 DR14 LD30 20 55 DR30
LD15 18 56 DR15 LD31 18 56 DR31
10 ohm 4R isolated IO16L IO16R R45 10K R54 10K IO16L IO16R R56 10K
17 58 3.3VCC 17 58
R43 10K IO17L IO17R IO17L IO17R 3.3VCC 3.3VCC
RN37 3.3VCC 3.3VCC RN39 RN40
LA9 1 8 A8 DPADSL 89 86 ADSRL 1 8 DPADSL 89 86 ADSRL 1 14
ADSL# ADSR# ADSL# ADSR#
LA10 2 7 A9 CE0LL 10 65 CE0RL 2 7 CE0LL 10 65 CE0RL 2 13
CE0L# CE0R# CE0L# CE0R# CE1R
LA11 3 6 A10 CE1L 11 64 CE1R 3 6 CE1L 11 64 3 12
CE1L CE1R CE1L CE1R
LA12 4 5 A11 PB1 CNTENLL 91 84 CNTENRL 4 5 CNTENLL 91 84 CNTENRL 4 11
3 CNTENL# CNTENR# CNTENL# CNTENR# 3
PB2 CNTRSTLL 12 63 CNTRSTRL CNTRSTLL 12 63 CNTRSTRL 5 10
10 ohm 4R isolated CNTRSTL# CNTRSTR# 3.3VCC 742-08-3-103-J-XX CNTRSTL# CNTRSTR#
6 9
4 DPRAMCLK CLKL 90 85 CLKR CLKL 90 85 CLKR 7 8
RN38 CLKL CLKR R57 10K CLKL CLKR
LA10 1 8 UBL0L 9 66 UBR0L 9 66 UBR1L 10K 7R Isolated
UBL# UBR# R58 10K UBL# UBR#
LA11 2 7 8 67 LBR0L 8 67 LBR1L
LBL# LBR# LBL# LBR#
LA12 3 6 R/WL 13 62 R/WRL R/WLL 13 62 R/WRL
R/WL# R/WR# R59 10K R/WL# R/WR#
LA13 4 5 PB3 OELL 14 60 OERL OELL 14 60 OERL
OEL# OER# OEL# OER#
LA[23:2] FTL/PIPEL 16 59 FTL/PIPER FTL/PIPEL 16 59 FTL/PIPER
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
4,7 LA[23:2] FT#/PIPEL FT#/PIPER FT#/PIPEL FT#/PIPER
10 ohm 4R isolated R60 10K
R46 0 R63 10K
4,6,7 LBE3L 3.3VCC
19
35
38
57
61
87
88
19
35
38
57
61
87
88
R47 0 CY7C09349V R61 10K CY7C09349V R64
4,6,7 LBE1L 3.3VCC
16-bit: install R46 (default) 4,6,7 LBE0L 4,6,7 LBE3L LBE3L
LBE2L R62 10K 10K
32-bit: install R47 4,6,7 LBE2L
3.3VCC R52
3.3VCC Install R57, R59, R60, and R61.
U14 22
8 5 Do not install R58 and R62
20
C65 VCC OUT

U13
CS0L 2 19 CE0LL
VCC
4,7 CS0L IN1 IO/Q1

GPIO8 3 18 0.1UF 4 1
4,7 GPIO8 IN2 IO/Q2 GND NC
4,6,7 ADSL ADSL 4 17 DPADSL
IN3 IO/Q3
4,6,7 BLASTL BLASTL 5 16 PB8
IN4 IO/Q4 OSC socket
PB5 6 15 PB9
IN5 IO/Q5
PB6 7 14 PB10
IN6 IO/Q6
PB7 8 13 PB11
IN7 IO/Q7
4,6,7 LW/RL LW/RL 9 12 R/WLL
IN8 IO/Q8
CLKL 1 AR[11:0] 3.3VCC
GND
IN/CLK
11
IN/OE#
2 2
GAL16LV8-5NS
10
J3 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54
PB12 ADSRL CLKR PB41
1 2 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
PB13 CNTENRL AR0 AR0 PB42
3 4
PB14 AR1 AR1 AR2 AR2 PB43
5 6
7 8
9 10
11 12
13 14
PB19 AR11 AR11 UBR1L PB48
15 16
PB20 UBR0L LBR1L PB49
LBR0L 17 18 3.3VCC
PB21 CE0RL PB50
19 20
PB22 CE1R R/WRL PB51
21 22
PB23 CNTRSTRL OERL PB52
23 24
PB24 DR0 DR0 DR1 DR1 PB53
25 26
27 28
29 30 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64
31 32
33 34 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
1 55 56 1
PB40 57 58
HEADER 29X2
DR[31:0]
www.plxtech.com
Title
DPRAM, Interface Circuits, & Test Header

A B C D E
A B C D E
PLX Option Module Connector Prototyping

(PCI 9030 Multiplexed Mode) Flash ROM Socket
3.3VCC
User Accessible
4,5,7 LD[31:0] Reset Circuit
32
FP1
4 4
VCC
PC36 F_A0 12 13 F_D0 3.3VCC
3.3VCC A0 I/O0 PC58
5VCC 5VCC PC37 F_A1 11 14 F_D1
A1 I/O1 PC59
PC38 F_A2 10 15 F_D2
A2 I/O2 PC60
PC39 F_A3 9 17 F_D3
A3 I/O3 PC61 R73
PC40 F_A4 8 18 F_D4
A4 I/O4 PC62 10K
J4 PC41 F_A5 7 19 F_D5
A5 I/O5 PC63
PC42 F_A6 6 20 F_D6
A6 I/O6 PC64 SW PUSHBUTTON U15 R74
4,5,7 ADSL ADSL 1 51 PC43 F_A7 5 21 F_D7
ADS# DMAREQ0# A7 I/O7 PC65 10K
2 52 PC44 F_A8 27 S2
GND DMAACK0# A8
4 POMCLK POMCLK 3 53 PC45 F_A9 26 1 3 MR# 3 5
PCLK DMAEOT0# A9 MR# VCC
4 54 PC46 F_A10 23
GND DMAREQ1# A10 PC66
4,5,7 BLASTL BLASTL 5 55 PC47 F_A11 25 1 RESET#
R65 0 BLAST# DMAACK1# A11 RESET#
4,7 GPIO1/LLOCKoL GPIO1/LLOCKoL 6 56 PC48 F_A12 4
LOCK# DMAEOT1# A12
4,5,7 LW/RL LW/RL 7 57 USER0 PC49 F_A13 28 4 2
0 W/R# USER0 PC2 A13 R75 RST_IN GND
4,7 READYL READYL R66 8 58 USER1 PC50 F_A14 29 4,7 LRESEToL
GND USER1 PC3 A14 0
4,7 LRESEToL LRESETL 9 59 PC51 F_A15 3
POM_RDY_IN# 5 VCC A15 3.3VCC R76
10 60 PC4 PC52 F_A16 2 MAX6306UK30D1-T
RESET# 3.3 VCC A16 0
4,5,7 LBE0L LBE0L 11 61 PC53 F_A17 30
BE0# 3.3 VCC R70 0 A17
4,5,7 LBE1L LBE1L 12 62 POMCSL CS1L 4,7 PC54 F_A18 1
BE1# ASYNC_SEL# A18
4,5,7 LBE2L LBE2L 13
BE2# PPC_ALE_H
63 ALE ALE 4,7 Do not install R63 ( default)
4,5,7 LBE3L LBE3L 14 64 PC5
BE3# LABS2
PC1 15 65 PC55 F_CE 22
SYNC_SEL# LABS3 PC6 CE
16 66 PC56 F_OE 24
R67 0 GND 3.3 VCC OE
4,7 LINTi1 LINTi1 17 67 PC57 F_WE 31
R68 0 IRQ_OUT# POM_SERR# PC7 WE
18 68
GND
IRQ_IN# 5 VCC
4,7 LREQ POMREQ 19 69
POM_REQ DEN#
4,7 LGNT POMGNT 20 70
POM_WAITL POM_GNT DT/R#
4,7 GPIO0/WAIToL 21 71
16
POM_WAIT# 3.3 VCC 32-pin PLCC
22 72
R69 0 GND RD_STRB# PC8
4,7 CS1L CS1L 23 73
5 VCC RESERVED
3 LD31 LAD31 24 74 3
AD31 RESERVED R71 0
LD30 LAD30 25 75 READYL READYL 4,7
AD30 POM_RDY_OUT#
LD29 LAD29 26 76
AD29 3.3 VCC 3.3VCC
LD28 LAD28 27 77
AD28 3.3 VCC
LD27 LAD27 28 78 PC9
AD27 POM_PRESENT#
LD26 LAD26 29 79
AD26 BREQ_IN
LD25 LAD25 30 80
AD25 BREQ_OUT
LD24 LAD24 31 81
AD24 BTERM_IN# 0
32 82 R72 BTERML
GND BTERM_OUT# BTERML 4,7 C66 C67 C68 C69 C70 C71 C72 C73
LD23 LAD23 33 83
AD23 5 VCC
LD22 LAD22 34 84 LAD7 LD7
AD22 AD07 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF
AD21 AD06
AD20 AD05
AD19 AD04
AD18 AD03
AD17 AD02
AD16 AD01
41 91 LAD0 LD0
GND AD00
LD15 LAD15 42 92
AD15 GND
LD14 LAD14 43 93
AD14 5 VCC
LD13 LAD13 44 94
AD13 3.3 VCC
LD12 LAD12 45 95
AD12 3.3 VCC
LD11 LAD11 46 96
AD11 GND
LD10 LAD10 47 97
AD10 EESDA
LD9 LAD9 48 98
AD09 EESCL
LD8 LAD8 49 99
50
AD08
GND
+12V
-12V
100
+12V
-12V
Serial Port (DTE)
PLX Option Module 1 (POM1)

2X50 Connector
2 2
3.3VCC
3.3VCC
3.3VCC U18
42
13
21
1
6
RN41 U17 26 28
R77 10K VCC C1+
DD0 1 8 ADD0 28 8 B0
VCC
PC10
NC
NC
NC
NC
A0 TX
1
DD1 2 7 PC11 ADD1 27 33 B1 C74 C75 1 2 22 C78
A1 DTR# 10uF + 0.1uF FORCEOFF#
DD2 3 6 PC12 ADD2 26 32 B2 23
A2 RTS# FORCEON 100nF
DD3 4 5
DD0 43 7 B3 27 24
PC13 UART
2
D0 RX V+ C1-
2
742-08-3-103-J-XX DD1 44 39 B4
PC14 D1 DSR#
DD2 45 38 B5 R78 3 1
PC15 D2 CTS# V- C2+
DD3 46 40 B6 10K
PC16 D3 CD#
3.3VCC DD4 47 41 B7 C76 C77 C79
PC17 D4 RI#
RN42 PC18 DD5 2
1
D5 100nF 100nF 100nF
DD4 1 8 PC19 DD6 3 5
D6 RCLK J5
DD5 2 7 PC20 DD7 4 12 25 2
D7 BAUDOUT# GND C2-
DD6 3 6
DD7 4 5 PC21 RST 35 34 OP1L B0 TX 14 9 5
RESET OP1# PC28 T1IN T1OUT
PC22 INT 30 31 OP2L B1 DTR# 13 10 RI 9
742-08-3-103-J-XX INT OP2# PC29 T2IN T2OUT
PC23 IORL 19 B2 RTS# 12 11 DTR 4
IOR# T3IN T3OUT
PC24 IOWL 16 20 IOR CTS 8
IOW# IOR PC30
17 IOW B[0:7] 20 21 TD 3
3.3VCC IOW PC31 R2OUTB INVALID#
PC25 CS0 9 B3 RX 19 4 RTS 7
RN43 CS0 R1OUT R1IN
PC26 CS1 10 22 DDISL B4 DSR# 18 5 RD 2
CS1 DDIS# PC32 R2OUT R2IN
IORL 1 8 PC27 CS2# 11 24 ASL B5 CTS# 17 6 DSR 6
CS2# AS# PC33 R3OUT R3IN
IOWL 2 7 B6 CD# 16 7 CD 1
R4OUT R4IN
DDISL 3 6 14 23 TXRDYL B7 RI# 15 8
X1 TXRDY# PC34 R5OUT R5IN
ASL 4 5 15 29 RXRDYL
3.3VCC X2 RXRDY# PC35 CONN DB9-MALE
GND
742-08-3-103-J-XX
NC
NC
NC
NC
MAX3245
1 U16 1
18
25
36
37
48
RN44 4 3 ST16C550
VCC OUT
RST 1 8
INT 2 7
IOR 3 6 2 1
GND NC
IOW 4 5 PLX TECHNOLOGY, INC.
1.8432MHz OSC
742-08-3-103-J-XX 870 Maude Ave, Sunnyvale, CA 94085
www.plxtech.com
Title
Serial Port, Flash, POM Connector, Reset Circuit,

A B C D E
A B C D E
Test Headers
Note: The test headers are designed to hook up directly
to HP logic analyzer termination adapter 01650-63203.
4 4
Local Address Bus -Upper Addresses

Control Signals in Local Bus (A)
4,5 LA[23:2] LA[23:2]
EECS EECS 4
4 EESK EESK EEDO EEDO 4
4 LA24/GPIO7 LA25/GPIO6 4 4 EEDI EEDI GPIO1/LLOCKoL GPIO1/LLOCKoL 4,6
LAH1 LAH5
LA27/GPIO4 4 4,6 GPIO0/WAIToL GPIO0/WAIToL GPIO3/CS3L GPIO3/CS3L 4
4 LA26/GPIO5 1 2 4 GPIO2/CS2L GPIO2/CS2L 1 2
+5V CLK2 +5V CLK2
3 4 LA27/GPIO4 PD16 3 4 PD80
CLK1 D15 CLK1 D15
PD1 LA26/GPIO5 5 6 LA25/GPIO6 PD15 PD65 5 6 PD79
D14 D13 D14 D13
PD2 LA24/GPIO7 7 8 LA23 LA23 PD14 PD66 7 8 PD78
D12 D11 D12 D11
PD3 LA22 LA22 9 10 LA21 LA21 PD13 PD67 9 10 PD77
D10 D9 D10 D9
D8 D7 D8 D7
D6 D5 D6 D5
D4 D3 D4 D3
D2 D1 D2 D1
PD8 LA12 LA12 19 20 PD72 19 20
D0 GND D0 GND
LINTi2 LINTi2 4
4,6 LINTi1 LINTi1 CS1L CS1L 4,6
Logic Analyzer Header CS0L Logic Analyzer Header LRESEToL
4,5 CS0L LRESEToL 4,6
4,5 GPIO8 GPIO8 LPMESET LPMESET 4
4 LPMINTL LPMINTL
Local Address Bus - Lower Addresses Control Signals in Local Bus (B)
4,5 LA[23:2] LA[23:2]
3 4 LCLOCK LCLOCK 3
LGNT LGNT 4,6
4,6 LREQ LREQ LW/RL LW/RL 4,5,6
LAH2
4,5,6 ADSL ADSL WRL WRL 4
LAH6
1 2 4 RDL RDL BTERML BTERML 4,6
+5V CLK2
3 4 LA11 LA11 PD32 4,5,6 BLASTL BLASTL 1 2
CLK1 D15 +5V CLK2
PD17 LA10 LA10 5 6 LA9 LA9 PD31 3 4 PD96
D14 D13 CLK1 D15
D12 D11 D14 D13
D10 D9 D12 D11
D8 D7 D10 D9
PD21 LA2 LA2 13 14 PD27 PD84 11 12 PD92
D6 D5 D8 D7
PD22 15 16 PD26 PD85 13 14 PD91
D4 D3 D6 D5
PD23 17 18 PD86 15 16 PD90
D2 D1 PD25 D4 D3
PD24 19 20 PD87 17 18 PD89
D0 GND D2 D1
PD88 19 20
D0 GND
Logic Analyzer Header
READYL Logic Analyzer Header LBE1L
4,6 READYL LBE1L 4,5,6
4 MODE MODE LBE3L LBE3L 4,5,6
4,5,6 LBE0L LBE0L ALE ALE
4,5,6 LBE2L LBE2L
Local Data Bus - Upper Half

4,5,6 LD[31:0] LD[31:0]
LAH3
1 2
+5V CLK2
2
3 4 LD31 LD31 PD48 2
CLK1 D15
PD33 LD30 LD30 5 6 LD29 LD29 PD47
D14 D13
PD34 LD28 LD28 7 8 LD27 LD27 PD46
D12 D11 3.3VCC
PD35 LD26 LD26 9 10 LD25 LD25 PD45
D10 D9
PD36 LD24 LD24 11 12 LD23 LD23 PD44
D8 D7
PD37 LD22 LD22 13 14 LD21 LD21 PD43
D6 D5
PD38 LD20 LD20 15 16 LD19 LD19 PD42
D4 D3
PD39 LD18 LD18 17 18 LD17 LD17 PD41
D2 D1
PD40 LD16 LD16 19 20
D0 GND
C91 C92 C93 C94 C95 C96
Logic Analyzer Header + + + + + +
10UF 10UF 10UF 10UF 10UF 10UF

16V 16V 16V 16V 16V 16V
Local Data Bus - Lower Half

4,5,6 LD[31:0] LD[31:0]
LAH4
1 2
+5V CLK2
3 4 LD15 LD15 PD64
CLK1 D15
PD49 LD14 LD14 5 6 LD13 LD13 PD63
D14 D13
PD50 LD12 LD12 7 8 LD11 LD11 PD62
D12 D11
PD51 LD10 LD10 9 10 LD9 LD9 PD61
D10 D9
PD52 LD8 LD8 11 12 LD7 LD7 PD60
D8 D7
PD53 LD6 LD6 13 14 LD5 LD5 PD59
1 D6 D5 1
PD54 LD4 LD4 15 16 LD3 LD3 PD58
D4 D3
PD55 LD2 LD2 17 18 LD1 LD1 PD57
D2 D1
PD56 LD0 LD0 19 20
D0 GND
Logic Analyzer Header PLX TECHNOLOGY, INC.

www.plxtech.com
Title
Logic Analyzer Test Headers

A B C D E
A B C D E
Note: Place four PLCC devices co-incident on the component

side of the board; that is, they share common pins and the 28
Prototyping Footprint A
PE11
PE10
fits inside the 44 which fits inside the 68 which fits inside the FP11
PE9
PE7
PE8
PE6
PE5
84.
PF141 1 28 PF168
FP5 1 28
All prototyping Footprints are located 2 27
28
27
26
PF142 2 27 PF167
4
3
2
1
PE104
PE102
PE101
PE100
PE103
3 26
on the component side of the PCB FP7 PF143
4
3 26
25
PF166
28
27
26
4
3
2
1
PF144 4 25 PF165
PE12 5 25 PE74 PF145 5 24 PF164
5 25 5 24
PE13 6 24 PE73 PF1 1 16 PF16 PF146 6 23 PF163
6 28 Pin PLCC24 1 16 6 23
PE14 7 23 PE72 PF2 2 15 PF15 PF147 7 22 PF162
7 23 2 15 7 22
PE15 8
8 Footprint 22 22 PE71 PF3 3
3 14
14 PF14 PF148 8
8 21
21 PF161
PE16 9 21 PE70 PF4 4 13 PF13 PF149 9 20 PF160
9 0.05" pitch 21 4 13 9 20
PE17 10 20 PE69 PF5 5 12 PF12 PF150 10 19 PF159
4 10 20 5 12 10 19 4
PE18 11 19 PE68 PF6 6 11 PF11 PF151 11 18 PF158
11 19 FP6 6 11 11 18
7 10 12 17
20
19
12
13
14
15
16
17
18
PF7 7 10 PF10 PF152 12 17 PF157
3
2
1
PF8 8 9 PF9 PF153 13 16 PF156
8 9 13 16
14 15
20
19
3
2
1
12
13
14
15
16
17
18
PF154 14 15 PF155
PE85 4
4 18
18 PE99 16-pin SOIC Narrow Footprint
PE86 5 17
5 20 Pin PLCC 17 PE98
PE33
PE34
PE36
PE38
PE39
PE35
PE37
PE87 6 16 0.150" wide, 0.05" pitch 28-pin SOIC Wide Footprint
PE11
PE10
6 16 PE97
7 Footprint 15
PE7
PE5
PE2
PE9
PE8
PE6
PE4
PE3
PE1
PE88 7 15 PE96
PE89 8
8 0.05" pitch 14
14
PE95 0.300" wide, 0.05" pitch
FP4
44
43
42
41
40
10
11
12
13
FP8 FP12
6
5
4
3
2
1
9
44
43
42
41
40
6
5
4
3
2
1
9
10
11
12
13
PE1 1 16 PF169 1 28
PE1 PF17 1 16 PF32 1 28 PF196
PE2 PE2 PE12 7 39 PE74 PF18 2 15 PF31 PF170 2 27 PF195
7 39 2 15 2 27
8 38 3 14 3 26
9 37 4 13 4 25
10 36 5 12 5 24
PE6 PE6 PE16 11
11 44 Pin PLCC 35
35 PE70 PF22 6
6 11
11 PF27 PF174 6
6 23
23 PF191
12 Footprint 34 7 10 7 22
PE90
PE92
PE93
PE91
PE94
13 33 8 9 8 21
PE9 PE9 PE19 14 0.05" pitch 32 PE67 PF177 9 20 PF188
14 32 9 20
PE10 PE10 PE20 15 31 PE66 PF178 10 19 PF187
15 31 10 19
PE11 PE11 PE21 16 30 PE65 16-pin SOIC Narrow Footprint PF179 11 18 PF186
16 30 11 18
PE12 PE12 PE22 17 29 PE64 PF180 12 17 PF185
17 29 12 17
PE13 PE13 0.150" wide, 0.05" pitch PF181 13
13 16
16 PF184
PE14 14 15
Power & Ground Rails
18
19
20
21
22
23
24
25
26
27
28
PE14 PF182 14 15 PF183

PE15 PE15
PE16 PE16
18
19
20
21
22
23
24
25
26
27
28
PE17 PE17
PE18 PE18 28-pin SOIC Wide Footprint
3 3
FP9 FP10
PE33
PE35
PE36
PE38
PE40
PE41
PE43
PE34
PE37
PE39
PE42
0.300" wide, 0.05" pitch

PE19 256Mb SDRAM 256Mb SDRAM
PE19
PE20 PE20 PF33 23 1 PF86 PF87 23 1 PF140
A0 VDD1 A0 VDD1
PE21 PE21 PF34 24 14 PF88 24 14
A1 VDD2 PF85 A1 VDD2 PF139 FP13
PE22 PE22 PF35 25 27 PF89 25 27
PE10
PE84
PE82
PE81
PE79
PE11
PE83
PE80
A2 VDD3 PF84 A2 VDD3 PF138

PE23 26 3 26 3 1 48
PE9
PE6
PE4
PE1
PE8
PE7
PE5
PE3
PE2
PE23 PF36 A3 VDDQ1 PF83 PF90 A3 VDDQ1 PF137 PF197 1 48 PF244

PE24 PE24 PF37 29 9 PF91 29 9 PF198 2 47 PF243
A4 VDDQ2 PF82 A4 VDDQ2 PF136 2 47
PE25 PE25 PF38 30 43 PF92 30 43 PF199 3 46 PF242
FP3 A5 VDDQ3 PF81 A5 VDDQ3 PF135 3 46
PE26 31 49 31 49 4 45
68
67
66
65
64
63
62
61
PE26 PF39 A6 VDDQ4 PF80 PF93 A6 VDDQ4 PF134 PF200 4 45 PF241

9
8
7
6
5
4
3
2
1
PE27 PE27 PF40 32 PF94 32 PF201 5 44 PF240

A7 A7 5 44
PE28 33 2 33 2 6 43
68
67
66
65
64
63
62
61
9
8
7
6
5
4
3
2
1
PE28 PF41 A8 DQ0 PF79 PF95 A8 DQ0 PF133 PF202 6 43 PF239

PE29 PE29 PF42 34 4 PF96 34 4 PF203 7 42 PF238
A9 DQ1 PF78 A9 DQ1 PF132 7 42
PE30 PE30 PE12 10 60 PE74 PF43 22 5 PF97 22 5 PF204 8 41 PF237
10 60 A10 DQ2 PF77 A10 DQ2 PF131 8 41
11 59 A11 DQ3 PF76 A11 DQ3 PF130 9 40
12 58 A12 DQ4 PF75 A12 DQ4 PF129 10 39
PE33 PE33 PE15 13 57 PE71 10 10 PF207 11 38 PF234
13 57 DQ5 PF74 DQ5 PF128 11 38
14 56 BA0 DQ6 PF73 BA0 DQ6 PF127 12 37
PE17 15 55 PE69 PF47 21 13 PF101 21 13 PF209 13 36 PF232
15 55 BA1 DQ7 PF72 BA1 DQ7 PF126 13 36
PE18 16 54 PE68 42 PF71 42 PF125 PF210 14 35 PF231
16 54 DQ8 DQ8 14 35
PE35 PE19 17 53 PE67 44 44 15 34
PE35
PE36 PE20 18
17 68 Pin PLCC 53
52 PE66 19
DQ9
45
PF70
19
DQ9
45
PF124 PF211
16
15 34
33
PF230
PE36 18 52 PF48 CS# DQ10 PF69 PF102 CS# DQ10 PF123 PF212 16 33 PF229
PE37 PE37 PE21 19 Footprint 51 PE65 PF49 18 47 PF103 18 47 PF213 17 32 PF228
19 51 RAS# DQ11 PF68 RAS# DQ11 PF122 17 32
20 0.05" pitch 50 CAS# DQ12 PF67 CAS# DQ12 PF121 18 31
21 49 WE# DQ13 PF66 WE# DQ13 PF120 19 30
PE40 PE40 PE24 22 48 PE62 51 51 PF216 20 29 PF225
22 48 DQ14 PF65 DQ14 PF119 20 29
23 47 UDMQ DQ15 PF64 UDMQ DQ15 PF118 21 28
PE42 PE42 PE26 24 46 PE60 PF53 15 PF107 15 PF218 22 27 PF223
24 46 LDMQ LDMQ 22 27
PE43 PE43 PE27 25 45 PE59 PF219 23 26 PF222
25 45 23 26
26 44 CLK VSS1 PF63 CLK VSS1 PF117 24 25
PE45 PE45 PF55 37 41 PF109 37 41
CKE VSS2 PF62 CKE VSS2 PF116
PE46 54 54 48-pin SSOP Footprint
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
PE46 VSS3 PF61 VSS3 PF115

2 PE47 PE47 6 6 2
VSSQ1 PF60 VSSQ1 PF114
PE48 12 12 0.300" wide, 0.025" pitch
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
PE48 VSSQ2 PF59 VSSQ2 PF113

PE49 PE49 46 46
VSSQ3 PF58 VSSQ3 PF112
PE50 PE50 PF56 40 52 PF110 40 52
NC/RFU VSSQ4 PF57 NC/RFU VSSQ4 PF111
PE51 PE51
PE34
PE36
PE37
PE39
PE41
PE42
PE44
PE46
PE47
PE49
PE33
PE35
PE38
PE40
PE43
PE45
PE48
FP14
54-pin TSOP Footprint 54-pin TSOP Footprint PF245 1
1 48
48 PE292
PE52 PE52 PF246 2 47 PE291
2 47
PE53 PE53 0.8mm 0.8mm PF247 3
3 46
46 PE290
PE54 PE54 PF248 4 45 PE289
4 45
PE11
PE83
PE81
PE80
PE78
PE76
PE75
PE10
PE84
PE82
PE79
PE77
PE55 5 44
PE8
PE5
PE3
PE9
PE7
PE6
PE4
PE2
PE1
PE55 PF249 5 44 PE288

PE56 5VCC 6 43
PE56 PF250 6 43 PE287
PE57 PE57 PF251 7 42 PE286
FP2 3.3VCC TB3 7 42
PE58 TB1 TB4 8 41
11
10
84
83
82
81
80
79
78
77
76
75
PE58 PF252 PE285

9
8
7
6
5
4
3
2
1
TB2 8 41
PE59 PE59 TB5 PF253 9 40 PE284
1 1 1 9 40
PE60 10 39
11
10
84
83
82
81
80
79
78
77
76
75
PE60
9
8
7
6
5
4
3
2
1
2 1 1 2 2 PF254 10 39 PE283
PE61 PE61 PE12 12 74 PE74 PF255 11 38 PE282
12 74 3 2 2 3 3 11 38
PE62 PE62 PE13 13
13 73
73 PE73 Jumpers to Join Top and Bottom 4 3 3 4 4 PF256 12
12 37
37 PE281
PE63 PE63 PE14 14 72 PE72 PF257 13 36 PE280
14 72 5VCC 5 4 4 5 5 13 36
PE64 PE64 PE15 15 71 PE71 PF258 14 35 PF279
15 71 6 5 5 6 6 14 35
PE65 PE65 PE16 16 70 PE70 PF259 15 34 PF278
16 70 JP1 7 6 6 7 7 15 34
PE66 PE66 PE17 17 69 PE69 JP2 PF260 16 33 PF277
17 69 8 7 7 8 8 16 33
PE67 PE67 PE18 18 68 PE68 PF261 17 32 PF276
18 68 1 1 9 8 8 9 9 17 32
PE68 PE68 PE19 19 67 PE67 PF262 18 31 PF275
19 67 2 2 10 9 9 10 10 18 31
PE20 20 66 PE66 PF263 19 30 PF274
20 66 HEADER 2 11 10 10 11 11 19 30
PE21 21 65 PE65 HEADER 2 20 29
PE69 PE22 22
21 84 Pin PLCC 65
64 PE64
12 11 11 12 12 PF264
21
20 29
28
PF273
PE69 22 64 13 12 12 13 13 PF265 21 28 PF272
PE70 PE23 23 63 PE63 3.3VCC 22 27
PE70
PE71 PE24 24
23 Footprint 63
62 PE62
14 13 13 14 14 PF266
23
22 27
26
PF271
PE71 24 62 15 14 14 15 15 PF267 23 26 PF270
PE72 PE72 PE25 25
25
0.05" pitch 61
61 PE61 JP3 JP4
16 15 15 16 16 PF268 24
24 25
25 PF269
PE73 PE73 PE26 26 60 PE60
26 60 1 1 17 16 16 17 17
PE74 PE74 PE27 27
27 59
59 PE59
2 2 18 17 17 18 18 48-pin SSOP Footprint
PE75 PE75 PE28 28 58 PE58
1 28 58 HEADER 2 19 18 18 19 19 1
PE76 PE76 PE29 29
29 57
57 PE57 HEADER 2
20 19 19 20 20 0.300" wide, 0.025" pitch
PE77 PE77 PE30 30 56 PE56
30 56 21 20 20 21 21
PE78 PE78 PE31 31 55 PE55
31 55 JP5 22 21 21 22 22
PE79 PE79 PE32 32 54 PE54 JP6
32 54 23 22 22 23 23
PE80
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
PE80 1 1 24 23 23 24 24
PE81 PE81
2 2 25 24 24 25 25 PLX TECHNOLOGY, INC.
PE82
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
PE82 26 25 25 26 26
PE83 HEADER 2 HEADER 2 870 Maude Ave, Sunnyvale, CA 94085
PE83 27 26 26 27 27
PE84 www.plxtech.com
PE84 28 27 27 28 28
PE38
PE40
PE41
PE53
PE39
PE42
PE33
PE35
PE36
PE43
PE45
PE46
PE48
PE50
PE51
PE34
PE37
PE44
PE47
PE49
PE52
JP7 JP8 Title

29 28 28 29 29
1 1 30 29 29 30 30 Prototyping Footprint A
2 2 HEADER 30 30 30 Size Document Number Rev
PE[1:84] HEADER 2 HEADER 2 HEADER 30 HEADER 30 HEADER 30 HEADER 30 Custom CompactPCI 9030RDK-LITE 002

A B C D E
A B C D E
Prototyping Footprint B
All prototyping footprints are located

on the component side of the PCB.
4 4
FP15 FP16 FP17 FP18

PG33 1 20 PG52 PG53 1 20 PG72
1 20 1 20
PG1 1 16 PG16 PG17 1 16 PG32 PG34 2 19 PG51 PG54 2 19 PG71
1 16 1 16 2 19 2 19
2 15 2 15 3 18 3 18
3 14 3 14 4 17 4 17
4 13 4 13 5 16 5 16
5 12 5 12 6 15 6 15
6 11 6 11 7 14 7 14
7 10 7 10 8 13 8 13
8 9 8 9 9 12 9 12
PG42 10 11 PG43 PG62 10 11 PG63
10 11 10 11
16-pin SOIC Narrow Footprint 16-pin SOIC Narrow Footprint 20 pin SOIC Wide Footprint
20 pin SOIC Wide Footprint
0.150" wide, 0.05" pitch 0.150" wide, 0.05" pitch 0.300" wide, 0.05" pitch
0.300" Wide, 0.05" pitch
FP21 FP22
FP19 FP20
PG113 1 24 PG136 PG137 1 24 PG160
1 24 1 24
3 PG73 1 20 PG92 PG93 1 20 PG112 PG114 2 23 PG135 PG138 2 23 PG159 3
1 20 1 20 2 23 2 23
2 19 2 19 3 22 3 22
3 18 3 18 4 21 4 21
4 17 4 17 5 20 5 20
5 16 5 16 6 19 6 19
6 15 6 15 7 18 7 18
7 14 7 14 8 17 8 17
8 13 8 13 9 16 9 16
9 12 9 12 10 15 10 15
10 11 10 11 11 14 11 14
PG124 12 13 PG125 PG148 12 13 PG149
12 13 12 13
20 pin SOIC Wide Footprint 20 pin SOIC Wide Footprint
0.300" wide, 0.05" pitch 0.300" wide, 0.05" pitch 24 pin SSOP Footprint 24 pin SSOP Footprint
0.150" wide, 0.025" pitch
0.150" wide, 0.025" pitch
FP26
PG300
PG299
PG298
PG297
PG296
PG295
PG294
PG293
PG292
PG291
PG290
PG301 1 16 PG316
1 16
PG302 2 15 PG315
2 15
PG303 3 14 PG314
3 14
PG304 4 13 PG313
4 13
PG305 5 12 PG312
FP23 FP24 5 12
PG306 6 11 PG311
6 11
2 PG161 1 48 PG208 PG209 1 48 PG256 PG307 7 10 PG310 2
1 48 1 48 7 10
PG162 2 47 PG207 PG210 2 47 PG255 PG308 8 9 PG309
2 47 2 47 FP25 8 9
3 46 3 46
44
43
42
41
40
39
38
37
36
35
34
PG163 3 46 PG206 PG211 3 46 PG254
PG164 4
4 45
45 PG205 PG212 4
4 45
45 PG253 16 pin SSOP Footprint
5 44 5 44
44
43
42
41
40
39
38
37
36
35
34
PG165 5 44 PG204 PG213 5 44 PG252
PG166 6
6 43
43 PG203 PG214 6
6 43
43 PG251 0.150" wide, 0.025" pitch
PG167 7 42 PG202 PG215 7 42 PG250 PG257 1 33 PG289
7 42 7 42 1 33
PG168 8 41 PG201 PG216 8 41 PG249 PG258 2 32 PG288
8 41 8 41 2 32
PG169 9 40 PG200 PG217 9 40 PG248 PG259 3 31 PG287
9 40 9 40 3 31
10 39 10 39 4 30
PG170
PG171 11
10 39
38
PG199 PG218
PG219 11
10 39
38
PG247 PG260
5
4 44 Pin TQFP 30
29
PG286
11 38 PG198 11 38 PG246 PG261 5 29 PG285
12 37 12 37 6 28
PG172
PG173 13
12
13
37
36
36
PG197
PG196
PG220
PG221 13
12
13
37
36
36
PG245
PG244
PG262
PG263 7
6
7
Footprint 28
27
27
PG284
PG283
PG174 14 35 PG195 PG222 14 35 PG243 PG264 8 26 PG282
14 35 14 35 8 26 FP27
PG175 15 34 PG194 PG223 15 34 PG242 PG265 9 0.8mm pitch 25 PG281
15 34 15 34 9 25
PG176 16 33 PG193 PG224 16 33 PG241 PG266 10 24 PG280
16 33 16 33 10 24
17 32 17 32 11 23 1 16
PG178 18 31 PG191 PG226 18 31 PG239 PG318 2 15 PG331
18 31 18 31 2 15
19 30 19 30 12 3 14
13
14
15
16
17
18
19
20
21
22
PG179 19 30 PG190 PG227 19 30 PG238 PG319 3 14 PG330
PG180 20 29 PG189 PG228 20 29 PG237 PG320 4 13 PG329
20 29 20 29 4 13
PG181 21 28 PG188 PG229 21 28 PG236 PG321 5 12 PG328
12
13
14
15
16
17
18
19
20
21
22
21 28 21 28 5 12
PG182 22 27 PG187 PG230 22 27 PG235 PG322 6 11 PG327
22 27 22 27 6 11
PG183 23 26 PG186 PG231 23 26 PG234 PG323 7 10 PG326
23 26 23 26 7 10
PG184 24 25 PG185 PG232 24 25 PG233 PG324 8 9 PG325
24 25 24 25 8 9
16 pin SSOP Footprint
48-pin SSOP Footprint 48-pin SSOP Footprint
0.150" wide, 0.025" pitch
PG268
PG269
PG270
PG271
PG272
PG273
PG274
PG275
PG276
PG277
PG278
0.300" wide, 0.025" pitch 0.300" wide, 0.025" pitch
1 1

www.plxtech.com
Title
Prototyping Footprint B

A B C D E
A B C D E
Prototyping Footprint C
PH208
PH207
PH206
PH205
PH204
PH203
PH202
PH201
PH200
PH199
PH198
PH197
PH196
PH195
PH194
PH193
PH192
PH191
PH190
PH189
PH188
PH187
PH186
PH185
PH184
PH183
PH182
PH181
PH180
PH179
PH178
PH177
PH176
PH175
PH174
PH173
PH172
PH171
PH170
PH169
PH168
PH167
PH166
PH165
PH164
PH163
PH162
PH161
PH160
PH159
PH158
PH157
PH200
PH199
PH198
PH197
PH196
PH195
PH194
PH193
PH192
PH191
PH190
PH189
PH188
PH187
PH186
PH185
PH184
PH183
PH182
PH181
PH180
PH179
PH178
PH177
PH176
PH175
PH174
PH173
PH172
PH171
PH170
PH169
PH168
PH167
PH166
PH165
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
FP28
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
FP29
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
PH1 1 156 PH156
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
4 1 156 4
PH2 2 155 PH155
2 155
PH9 1 108 PH148 PH3 3 154 PH154
1 108 3 154
PH10 2 107 PH147 PH4 4 153 PH153
2 107 4 153
PH11 3 106 PH146 PH5 5 152 PH152
3 106 5 152
PH12 4 105 PH145 PH6 6 151 PH151
4 105 6 151
PH13 5 104 PH144 PH7 7 150 PH150
5 104 7 150
PH14 6 103 PH143 PH8 8 149 PH149
6 103 8 149
PH15 7 102 PH142 PH9 9 148 PH148
7 102 9 148
PH16 8 101 PH141 PH10 10 147 PH147
8 101 10 147
PH17 9 100 PH140 PH11 11 146 PH146
9 100 11 146
PH18 10 99 PH139 PH12 12 145 PH145
10 99 12 145
PH19 11 98 PH138 PH13 13 144 PH144
11 98 13 144
PH20 12 97 PH137 PH14 14 143 PH143
12 97 14 143
PH21 13 96 PH136 PH15 15 142 PH142
PH22 14
13 144 Pin TQFP Footprint 96
95 PH135 PH16 16
15 142
141 PH141
14 95 16 141
PH23 15 94 PH134 PH17 17 140 PH140
15 94 17 140
PH24 16 93 PH133 PH18 18 139 PH139
16 93 18 139
PH25 17 92 PH132 PH19 19 138 PH138
17 92 19 138
PH26 18 0.5mm pitch 91 PH131 PH20 20 137 PH137
18 91 20 137
PH27 19 90 PH130 PH21 21 136 PH136
19 90 21 136
PH28 20 89 PH129 PH22 22 135 PH135
PH29 21
20 89
88 PH128 PH23 23
22 208 Pin PQFP Footprint 135
134 PH134
21 88 23 134
PH30 22 87 PH127 PH24 24 133 PH133
22 87 24 133
PH31 23 86 PH126 PH25 25 132 PH132
23 86 25 132
PH32 24 85 PH125 PH26 26 0.5mm pitch 131 PH131
24 85 26 131
PH33 25 84 PH124 PH27 27 130 PH130
25 84 27 130
PH34 26 83 PH123 PH28 28 129 PH129
26 83 28 129
PH35 27 82 PH122 PH29 29 128 PH128
27 82 29 128
PH36 28 81 PH121 PH30 30 127 PH127
28 81 30 127
PH37 29 80 PH120 PH31 31 126 PH126
29 80 31 126
PH38 30 79 PH119 PH32 32 125 PH125
30 79 32 125
PH39 31 78 PH118 PH33 33 124 PH124
31 78 33 124
3 PH40 32 77 PH117 PH34 34 123 PH123 3
32 77 34 123
PH41 33 76 PH116 PH35 35 122 PH122
33 76 35 122
PH42 34 75 PH115 PH36 36 121 PH121
34 75 36 121
PH43 35 74 PH114 PH37 37 120 PH120
35 74 37 120
PH44 36 73 PH113 PH38 38 119 PH119
36 73 38 119
PH39 39 118 PH118
39 118
PH40 40 117 PH117
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72 PH41 41
40 117
116 PH116
41 116
PH42 42 115 PH115
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
42 115
PH43 43 114 PH114
43 114
PH44 44 113 PH113
44 113
PH45 45 112 PH112
45 112
PH61
PH62
PH63
PH64
PH65
PH66
PH67
PH68
PH69
PH70
PH71
PH72
PH73
PH74
PH75
PH76
PH77
PH78
PH79
PH80
PH81
PH82
PH83
PH84
PH85
PH86
PH87
PH88
PH89
PH90
PH91
PH92
PH93
PH94
PH95
PH96
PH46 46 111 PH111

46 111
PH47 47 110 PH110
47 110
PH48 48 109 PH109
48 109
PH[1:208] PH49 49 108 PH108
49 108
PH50 50 107 PH107
50 107
PH51 51 106 PH106
51 106
PH52 52 105 PH105
52 105
100
101
102
103
104
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
PH1 PH1 PH51 PH51 PH101 PH101 PH151 PH151 PH201 PH201
PH100
PH101
PH102
PH103
PH104
PH53
PH54
PH55
PH56
PH57
PH58
PH59
PH60
PH61
PH62
PH63
PH64
PH65
PH66
PH67
PH68
PH69
PH70
PH71
PH72
PH73
PH74
PH75
PH76
PH77
PH78
PH79
PH80
PH81
PH82
PH83
PH84
PH85
PH86
PH87
PH88
PH89
PH90
PH91
PH92
PH93
PH94
PH95
PH96
PH97
PH98
PH99
PH6 PH6 PH56 PH56 PH106 PH106 PH156 PH206 PH206
PH156
PH7 PH7 PH57 PH57 PH107 PH107 PH157 PH207 PH207
PH157
PH192
PH191
PH190
PH189
PH188
PH187
PH186
PH185
PH184
PH183
PH182
PH181
PH180
PH179
PH178
PH177
PH176
PH175
PH174
PH173
PH9 PH9 PH59 PH59 PH109 PH109 PH159 PH159
2 PH10 PH10 PH60 PH60 PH110 PH110 PH160 PH160 2
PH11 PH11 PH61 PH61 PH111 PH111 PH161
PH161
PH13 PH63 PH113 PH163 FP30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PH13 PH63 PH113 PH163
PH15 PH65 PH115 PH165
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PH15 PH65 PH115 PH165
PH17 PH17 PH67 PH67 PH117 PH117 PH167 PH167 PH17 1 60 PH140
1 60
2 59
3 58
4 57
5 56
6 55
7 54
PH24 PH74 PH124 PH174 PH24 8 53 PH133
PH24
PH25
PH74
PH75
PH124
PH125
PH174
PH175 PH25 9
52 PH132
PH25 PH75 PH125 PH175 9 52
10 51
11 50
12 49
PH29 PH29 PH79 PH79 PH129 PH129 PH179 PH179 PH29 13 0.5mm pitch 48 PH128
13 48
14 47
15 46
16 45
17 44
18 43
19 42
20 41
PH38 PH88 PH138 PH188
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PH38 PH88 PH138 PH188
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1 1
PH69
PH70
PH71
PH72
PH73
PH74
PH75
PH76
PH77
PH78
PH79
PH80
PH81
PH82
PH83
PH84
PH85
PH86
PH87
PH88
PH44 PH44 PH94 PH94 PH144 PH194 PH194
PH144
PH47 PH47 PH97 PH97 PH147 PH197 PH197
PH147
PH48 PH48 PH98 PH98 PH148 PH148 PH198 PH198 PLX TECHNOLOGY, INC.
PH50 PH100 PH150 PH150 PH200 PH200 Note: three footprints are placed on the component 870 Maude Ave, Sunnyvale, CA 94085
PH50 PH100
www.plxtech.com
side of the PCB. They are arranged as FP30 inside of Title
FP29 and FP29 insde of FP28. All 208 holes for prototyping Prototyping Footprint C
are located outside of 208-pin PQFP footprint. Size Document Number Rev

A B C D E
A B C D E
Prototyping Footprint D
PI176
PI175
PI174
PI173
PI172
PI171
PI170
PI169
PI168
PI167
PI166
PI165
PI164
PI163
PI162
PI161
PI160
PI159
PI158
PI157
PI156
PI155
PI154
PI153
PI152
PI151
PI150
PI149
PI148
PI147
PI146
PI145
PI144
PI143
PI142
PI141
PI140
PI139
PI138
PI137
PI136
PI135
PI134
PI133
All prototyping footprints are located
on the component side of the PCB.
PI167
PI166
PI165
PI164
PI163
PI162
PI161
PI160
PI159
PI158
PI157
PI156
PI155
PI154
PI153
PI152
PI151
PI150
PI149
PI148
PI147
PI146
PI145
PI144
PI143
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
FP31
4 4
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PI1 1 132 PI132
1 132
PI2 2 131 PI131
2 131
100
FP32 PI3 3 130 PI130
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
3 130
PI4 4 129 PI129
4 129
PI5 5 128 PI128
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
100
5 128
PI10 1 75 PI123 PI6 6 127 PI127
1 75 6 127
PI11 2 74 PI122 PI7 7 126 PI126
2 74 7 126
PI12 3 73 PI121 PI8 8 125 PI125
3 73 8 125
PI13 4 72 PI120 PI9 9 124 PI124
4 72 9 124
PI14 5 71 PI119 PI10 10 123 PI123
5 71 10 123
PI15 6 70 PI118 PI11 11 122 PI122
6 70 11 122
PI16 7 69 PI117 PI12 12 121 PI121
7 69 12 121
PI17 8 68 PI116 PI13 13 120 PI120
8 68 13 120
PI18 9 67 PI115 PI14 14 119 PI119
9 67 14 119
PI19 10 66 PI114 PI15 15 118 PI118
10 66 15 118
PI20 11 65 PI113 PI16 16 117 PI117
PI21 12
64 PI112 PI17 17
16 117
116 PI116
PI22 13
12
13
64
63
63 PI111 PI18 18
17
18
176 Pin TQFP Footprint 116
115
115 PI115
PI23 14 62 PI110 PI19 19 114 PI114
PI24 15
14 0.5mm pitch 62
61 PI109 PI20 20
19 114
113 PI113
15 61 20 113
PI25 16 60 PI108 PI21 21 112 PI112
16 60 21 112
PI26 17 59 PI107 PI22 22 111 PI111
17 59 22 111
PI27 18 58 PI106 PI23 23 110 PI110
PI28 19
18 58
57 PI105 PI24 24
23 0.5mm pitch 110
109 PI109
19 57 24 109
PI29 20 56 PI104 PI25 25 108 PI108
20 56 25 108
PI30 21 55 PI103 PI26 26 107 PI107
21 55 26 107
PI31 22 54 PI102 PI27 27 106 PI106
22 54 27 106
PI32 23 53 PI101 PI28 28 105 PI105
23 53 28 105
PI33 24 52 PI100 PI29 29 104 PI104
24 52 29 104
3 PI34 25 51 PI99 PI30 30 103 PI103 3
25 51 30 103
PI31 31 102 PI102
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
31 102
PI32 32 101 PI101
32 101
PI33 33 100 PI100
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
33 100
PI34 34 99 PI99
34 99
PI35 35 98 PI98
35 98
PI36 36 97 PI97
36 97
PI37 37 96 PI96
37 96
PI38 38 95 PI95
38 95
PI39 39 94 PI94
PI54
PI55
PI56
PI57
PI58
PI59
PI60
PI61
PI62
PI63
PI64
PI65
PI66
PI67
PI68
PI69
PI70
PI71
PI72
PI73
PI74
PI75
PI76
PI77
PI78
39 94
PI40 40 93 PI93
40 93
PI41 41 92 PI92
41 92
PI42 42 91 PI91
42 91
PI[176:1] PI43 43 90 PI90
43 90
PI44 44 89 PI89
44 89
45
46
47
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PI1 PI1 PI51 PI51 PI101 PI101 PI151 PI151
PI5 PI55 PI105 PI155
PI45
PI46
PI47
PI48
PI49
PI50
PI51
PI52
PI53
PI54
PI55
PI56
PI57
PI58
PI59
PI60
PI61
PI62
PI63
PI64
PI65
PI66
PI67
PI68
PI69
PI70
PI71
PI72
PI73
PI74
PI75
PI76
PI77
PI78
PI79
PI80
PI81
PI82
PI83
PI84
PI85
PI86
PI87
PI88
PI5 PI55 PI105 PI155
PI6 PI6 PI56 PI56 PI106 PI106 PI156
PI156
PI7 PI7 PI57 PI57 PI107 PI107 PI157
PI157
2 PI11 PI11 PI61 PI61 PI111 PI111 PI161 PI161 2
PI15 PI65 PI115 PI165
PI160
PI159
PI158
PI157
PI156
PI155
PI154
PI153
PI152
PI151
PI150
PI149
PI15 PI65 PI115 PI165
PI16 PI16 PI66 PI66 PI116 PI116 PI166
PI166
PI17 PI17 PI67 PI67 PI117 PI117 PI167
PI167
PI22 PI72 PI122 PI172 FP33
48
47
46
45
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37
PI22 PI72 PI122 PI172
PI24 PI74 PI124 PI174
48
47
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37
PI24 PI74 PI124 PI174
PI25 PI25 PI75 PI75 PI125 PI125 PI175 PI175 PI17 1 36 PI116
1 36
PI26 PI26 PI76 PI76 PI126 PI126 PI176 PI18 2 35 PI115
PI176 2 35
PI27 PI27 PI77 PI77 PI127 PI127 PI19 3 34 PI114
3 34
4 33
5 32
PI30 PI30 PI80 PI80 PI130 PI130 PI22 6
6
48 pin TQFP Footprint 31
31 PI111
7 30
PI32 PI82 PI132 PI24 8 29 PI109
PI32
PI33 PI33
PI82
PI83 PI83
PI132
PI133 PI133 PI25 9
8 0.5mm pitch 29
28 PI108
9 28
10 27
11 26
12 25
PI37 PI87 PI137 13
14
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24
PI37 PI87 PI137
PI38 PI38 PI88 PI88 PI138 PI138
PI39 PI39 PI89 PI89 PI139 PI139
13
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24
PI40 PI40 PI90 PI90 PI140 PI140
PI41 PI41 PI91 PI91 PI141 PI141
PI42 PI42 PI92 PI92 PI142 PI142
PI43 PI43 PI93 PI93 PI143 PI143
1 1
PI44 PI44 PI94 PI94 PI144
PI144
PI45 PI95 PI145
PI61
PI62
PI63
PI64
PI65
PI66
PI67
PI68
PI69
PI70
PI71
PI72
PI45 PI95 PI145
PI46 PI46 PI96 PI96 PI146 PI146
PI47 PI47 PI97 PI97 PI147
PI147
PI48 PI48 PI98 PI98 PI148 PI148
PI49 PI49 PI99 PI99 PI149 PI149 PLX TECHNOLOGY, INC.
PI50 PI50 PI100 PI100 PI150 PI150
www.plxtech.com
Title
Prototyping Footprint D

A B C D E
A B C D E
4 4
Prototype Footprints
Area
3 3
233.35mm
POM connector
Reset Hot Swap
circuit Control
GAL
Circuit
LAH5 LAH3
RS232 U11 4Kx18 LAH6 LAH4

DB9 port DPRAM
Saperate bus
100mm
Handle
LAH1
2 2
Switch J1
header U12 4Kx18
DPRAM 9030
Flash
ROM
LAH2
serial 60MHz
BLUE EEPROM J2
LED OSC
160mm
Stub Terminal Resistors
1 1

www.plxtech.com
Title
Suggested Board Layout

A B C D E

Compactpci 9030rdk-Lite HRM With Schematic 19jan06

Uploaded by

Compactpci 9030rdk-Lite HRM With Schematic 19jan06

Uploaded by

CompactPCI 9030RDK-LITE

Hardware Reference Manual

Order Number: CPCI 9030/LITE-RDK-HRM-P1-1.2

Printed in the USA, October 2004

ABOUT THIS MANUAL

Date Version Comments

Hardware Reference Manual release

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

3. HARDWARE ARCHITECTURE ............................................................................................5

4. PCB LAYOUT CONSIDERATION ......................................................................................15

5. CONVERTING THE 6U BOARD TO A 3U BOARD ...........................................................16

8. ABEL CODE / BILL OF MATERIALS / SCHEMATICS ......................................................17

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

TABLE 3-1. COMPACTPCI 9030RDK-LITE MEMORY MAP ............................................................. 6

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

25x25 0.1" through hole

24 pin 16 pin 16 pin 20 pin

POM Connector LED's

DPRAM LAH6 LAH4

switch Flash DPRAM

Figure 1-1. CompactPCI 9030RDK-LITE Layout Diagram (6U/4HP Card)

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

Back End Power

Control Circuit (µBGA)

Back End Controls Early Power Ejector Blue

Figure 2-1. CompactPCI 9030RDK-LITE System Architecture

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

PCI 9030 Resistor Networks to configure

ADSL Synchronous Dual-Port RAM

Local Bus Synchronous Dual-Port RAM

Left Port Right Port

Figure 3-1. CompactPCI 9030RDK-LITE Hardware Block Diagram

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

3.1 Hardware Memory Map

Table 3-1. CompactPCI 9030RDK-LITE Memory Map

3.2 PCI 9030

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

• CompactPCI Hot Swap Ready: The 3.3 Serial EEPROM

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

Table 3-2. Contents of the Serial EEPROM

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

3.4 Synchronous Dual-Port RAM 3.5 Hot Swap Control Circuit

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

3.8 Hardware Modules 3.9 Prototyping Area

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

3.9.1 Thirty-three (33) Surface Mount Footprints

Table 3-3. Prototyping Footprints and Prototyping Area on the

As shown in Table 3-3, the surface-mount

1) The footprints can be used for industry

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

3.9.2 The Common BGA Landscape

Figure 3-2. BGA Landscapes

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

3.10 Configuring the RDK board

Multiplexed Mode Install R27

3.11 Memory Access to the DPRAM

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

8.1 ABEL code for U13

CLK,OE pin 1, 11;

CE0LL,RWLL pin 19,12;

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

Table 8-1. Bill of Materials

Item Manufacturer's Part Component

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

IC, Dual-port SRAM, 9 ns

IC, Dual-port SRAM, 9ns delay 100-pin TQFP

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

CompactPCI 9030RDK-LITE Hardware Reference Manual v1.2

ECN NUMBER DATE NOTE

000 4/12/2000 board was transferred to manufacturing

Hot Swap Control