ch3 Computer Architecture
ch3 Computer Architecture
3) Input/Output Instructions:
- for input output operations
Instruction Types
1) Functional instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND
2) Transfer instructions
- Data transfers between the main memory and the processor registers
- LDA, STA
3) Control instructions
- Program sequencing and control
- JMP, JNZ, JC
4) Input and output instructions
- Input and output operations
- INP, OUT
Computer Registers
• Register are used to quickly accept, store, and transfer data and
instructions that are being used immediately by the CPU, there are
various types of registers those are used for various purpose.
• Among of the some mostly used registers named as Accumulator,
Data Register, Address Register, Program Counter, Memory Data
Register, Index register, Memory Buffer Register.
Types of registers
Instruction Register (IR)
• Instruction Register (16 bits) holds the instruction code of the instruction currently executing.
• Outputs of this register are hardwired to specific logic in the control unit, which interprets the bits to
generate control signals.
Address Register (AR)
• Address Register (12 bits) is used to interface with the memory unit. All memory-references are
• initiated by loading the memory address into AR.
Temporary Register (TR)
• Temporary Register (16 bits) is an extra register for storing data or addresses.
Input and Output Registers
• The Basic Computer has one input device and one output device. The Input Register (INPR) holds an
• 8 bit character gotten from an input device.
• The Output Register (OUTR) holds an 8 bit character to be send to an output device.
Program Counter (PC)
• The program counter (PC) is commonly called the instruction pointer (IP) in
Intel x86
• microprocessors, and sometimes called the Instruction Address Register
(IAR), or just part of the instruction sequencer in some computers, is a
processor register.
• Program Counter (12 bits) holds memory address of current/next
instruction to be executed.
• Updated as part of the instruction cycle. Usually incremented, but may be
parallel loaded by jump/branch instructions.
• It keeps track of the next memory address of the instruction that is to be
executed once the execution of the current instruction is completed.
In other words, it holds the address of the memory location of the next
instruction when the current instruction is executed by the microprocessor.
Accumulator Register (AC)
• This Register is used for storing the Results those are produced by the
System. When the CPU will generate Some Results after the
Processing then all the Results will be Stored into the AC Register.
• Accumulator (16 bits) is used for all mathematical, logic, and shift
operations except incrementing and clearing other registers (most
have built-in increment and clear capability).
• It is the destination for all ALU operations, and a source for all dyadic
(two-operand) operations.
Data Register (DR)
• A register used in microcomputers to temporarily store data being
transmitted to or from a
• peripheral device. Data Register (16 bits) is used to contain a second
operand for dyadic operations such as Add, Sub, AND, OR.
Instruction cycle
• The CPU performs a sequence of micro-operations for each instruction.
• The sequence for each instruction of the Basic Computer can be refined
into 4 abstract phases:
1) Fetch an instruction from memory
2) Decode the instruction
3) Read the effective address from memory if the instruction has an indirect
address
4) Execute the instruction
After an instruction is executed, the cycle starts again at step 1, for the next
instruction.
Instruction Fetch and Decode
• Program execution begins with: PC ← address of first instruction, SC ← 0
• After this, the SC is incremented at each clock cycle until an instruction is
completed, and then it is cleared to begin the next instruction.
• This process repeats until a HLT instruction is executed, or until the power
is shut off.
• Everything that happens in this phase is driven entirely by timing variables
T0, T1 and T2.
• Hence, all control inputs in the CPU during fetch and decode are functions
of these three variables alone.
Determining the Instruction Type
Memory-Reference Instructions
• Each memory ref instruction is indicated by a unique Di signal.
1) AND operation
2) ADD operation
4) Store operation(STA)
5) Branch unconditionally (BUN)