Digital Controller Design for Buck and Boost Converter:sUsing Root Locus

Techniques

Liping Guo, John Y. Hung and R. M. Nelms

Department of Electrical & Computer Engineering
Auburn University
200 Broun Hall, Auburn, AL 36849-5201, USA
Phone (334) 844-1830, Fax (334) 844-1809
guolD@,enp.auburn.edu
with the results obtained using the frequency response
Abstract-Root locus techniques to design digital controllers for method. In the root locus (design, the duty cycle in steady state
buck and boost converters are discussed in this paper. The small doesn’t oscillate as much ,as in the frequency response method
signal models of both converters are first transformed into for both the buck and boo,jt converters, therefore no algorithm
discrete-time models using the matched pole-zero mapping modifications are required for the digital controllers. For
method. Digital controllers are designed based on the discrete-
time model using the root locus method. By selecting the poles, the buck converter, thma two design methods generate
zeros and gain of the digital controllers, the closed-loop poles are comparable results. For Ithe boost converter, the frequency
placed at desired locations in the z-plane. The digital controllers response method produces, experimental results that match the
are then implemented on a TI DSP. The root locus design method design better. The zero and complex poles of the boost
is compared with the frequency response design method. converter small signal model movs as a function of the duty
Experimental results from the buck converter indicate that the cycle D [l]. This makes the boost converter’s transfer function
results obtained using the root locus method are comparable to
the results obtained using the frequency response method, while a nonlinear function of D. The digital controller is only
results from the boost converter indicate the nonlinear nature of designed for a specific duty cycle. On the other band, change
the boost converter small signal model may degrade the of the duty cycle only affects the DC gain, but has no impact
performance of the design using the root locus method. on the poles and zeros of the buck converter’s small signal
model.
I. INTRODUCTION
Different methods can be utilized to design digital 11. CONVERTER SMALL SIGNAL MODELS
controllers for buck and boost converters. Analog PID
controllers were designed using converter small signal models A . Buck Converter
and frequency response methods [SI. The main criteria The small signal model of the buck converter is [I]:
considered in, the design were the gain at low frequency, the
crossover frequency and the phase margin. The analog
controllers were then transformed into digital controllers using
the backward integration method [4], and implemented on a
TI TMS320F240 DSP. With the regular PlD algorithm, the
duty cycle oscillated in steady state. The regular PID
algorithm was modified to reduce this oscillation and improve
The input voltage of the prototype buck converter is 20 V,
the controller’s stability while maintaining the fast transient
and the output voltage Vo is 12 V. The load resistance R is IO
response. Three algorithm modifications were applied to the
controller to improve the steady state performance. The
n, L is 150 p H and C is 1000 pF. The parasitic elements, Rc
and RL,are estimated to be 30 m n and 10 ma, respectively.
modifications were a dead zone, an averaging digital filter and
The actual frequency response of the buck converter is
two sets of gains.
measured using a Model 1028 analog network analyzer from
Another approach for the design of digital controllers for
AP Instruments, and compares favorably with the small signal
DC-DC converters is discussed in this paper. The small signal
model in (I).
models for the converters are first transformed into discrete-
The small signal modo1 is then transformed into the
time models using the matched pole-zero mapping method.
discrete-time model using the matched pole-zero mapping
The root locus technique is then utilized to design digital
method. The small signal model’s poles and zeros are mapped
controllers. The poles, zeros and gain of the digital controller
to the z plane according to !.he relation of z = eST.A finite pole
are designed to place the closed-loop poles at the desired
or zero at s = -a is mapped to z = e-aT,and an infinite pole or
positions. The digital controllers are then implemented on the
zero is mapped to z = -I [.3]. The sampling period T is 50 ps.
TI DSP. Experimental results are obtained and compared
It is the same as the sampling period in the frequency response
design method for the sake of comparison. The discrete-time

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model obtained using the matched pole-zero mapping method - 0 . 0 1 1 9 ~-1.0.02532
~ -0,0013
bas good accuracy to reproduce the transient response and G(z) = (5)
z* -1.95822 t 0.9596
relatively low sensitivity to coefficient variations [6]. The The root locus of the boost converter is shown in Fig. 2. The
discrete-time model obtained far the buck converter is: zeros of the z-plane model are 2.0832 and 0.0508. The poles
G(z) =
0.40582 0.0767 - are at 0.9791 +/- O.O299i, and are also very close to the unit
z2 -1.96542+0.9819 circle. The zeros don't affect the absolute stability of the
The zero of the discrete-time model is 0,1889, and the poles system[3].
are 0.9827 +/- 0.1271i. The root locus for the model is shown RX4LDiCS

in Fig. 1. The two poles are very close to the unit circle, which
results in the system being very close to critical stability. This
will he adjusted using the root locus design method in a later
section. :\
: \
Rm L m n

\/' ! 1

., .U?, -08 -0a -02 Y U 1 ".I " 5 us I

Re# AXb

Fig. 1. Root locus of the buck converter discrete-time model

B. Boost Converter
The small signal transfer function of the boost converter is
PI: (3)
d
(I - z ) ( r R , C + R,IR + I )
y) vo R
4 s ) DoL&' $2 +
( R L ID:)+ ( R c / D a )+L (R,ID,')+ ( & / D o )
+ +
'

L. CR LeCR L.C

where Le=L/(l-D)' and Do= 1-D.

For the experiment the input voltage is 5 V, the output controller is:
voltage Vo is 12 V, and the duty cycle D is 58%. C is 1056 UUUI ram1 0

pF, L is 250 pH, and R is 25 R. The parasitic elements, &

and RL, are estimated from data sheets to be 30 mR and 10
d, respectively. The frequency response of the boost
converter when operating at steady state is also obtained
using the analog network analyzer. There is a clear
discrepancy between the theoretical model and the frequency
response measured. By fitting the experimental frequency
response data using Matlab, a transfer function for the boost
converter is:
&(s)
-- - -5.6956*10"s2 - 2.5589*102~+4.9831*106(4)
&s, s2 + 8.2525*102s+ 5.4241*105
The discrete-time model for the boost converter is obtained
by converting this transfer function into the z-plane transfer "eo, U

function using the matched pole-zero mapping method. The Fig. 3. Root locus of the compensated buck converter
sampling period T is also 50 ps. The discrete-time transfer
function is:

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 Tek Run: IOokS/s Sample
3.62 * - 5.042 + 1.728 . (6)
Gc(z)= z 2 -1.132 +0.13
B. , Boost Converter Controller Design
A digital controller for the boost converter is also
designedusing the root locus method, based on the model in . . .
..
.
..
.
.
.
. .
(3, and the root locus in Fig. 2. The two poles of the
controller are chosen to be 1 and 0.13, respectively. The
controller's two zeros are placed at 0.85 and 0.9. By using
the root locus design tools in Matlab, the gain is adjusted to . . . .
.. . .
be 30 to provide the root locus in Fig. 4. The closed-loop . .. .. ..
. . . .
poles are 0.73 +/- 0.254i, 0.273 and 0.915. The digital .. .. .. ..
controller's transfer function is:
z 2 -1.752 + 0.765
Gc(z) (7)
. z2 -1.132 + 0.13 Fig. 5. Start up transient response of the buck converter
using root locus method
(2V/div, 5OOpddiv)
Tek 2.SOMSII 0 ACqS
-+
C1 Mean
.
.
.
.
.
.
.
.
12.08V
.. .. .. . .. .. . .
. . . . . .. .. C2 +Duty
72.80 x
LOW rlgnal
mplltude

. . .

I I
..._L,.. .. ,
.I5 -1 4 5 0 05 I 1.5 2 25 3 3s
Red *as
l o May 2001
Fig. 4. Root locus of the compensated boost converter 09:54:40

Fig. 6. Steady state reriponse of the buck converter using

IV. EXPERIMENTAL RESULTS root locus method
(5V/div, 20 ps/div)
A . Buck Converter T e k m tookS/s
I--F--cd----I
37 ACqS

The transfer function of the digital controller in (6) is

converted into a difference equation, which is utilized to
calculate a new duty cycle:
u(k)=1.13u(k-l)-0.13u(k-2)+3.6e(k)

,
(8)
- 5.04e(k - 1) + 1.728 e ( k 2) -
In the difference equation, u(k) is the controller's output for
the ktb sample, and e(k) is the error of the ktb sample. The

OLO
l I '-U
digital controller is implemented on the TI TMS320F240
DSP. The start up transient response of the buck converter' is
shown in Fig. 5. The settling time is about 1 ms with very .Vi. .. . .
little overshoot. The steady state response and PWM signal
. . . . .
are shown in Fig. 6. Fig. 7 shows the ripple in steady state. m w m lOMly2003
The magnitude of the ripple is about 200 mV. 10:01:07

Previous work was done to design digital PID controllers Fig. 7. Steady state ripple of the buck converter using root
for the buck and boost converters using the frequency locus
response technique [SI. The PID algorithm was modified to (IOOmVldiv, 500 ps/div)
reduce the oscillation of the duty cycle and improve the
controller's stability while maintaining the fast transient dead zone, averaging digital filter and two sets of gains.
response. Three algorithm modifications were added to the The digital controller monitors the output voltage error to
controller to improve the steady state response. They were determine if a modification should be employed to calculate

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the two sets of gains. The settling time is comparable to the Polel&2 Zero 1 Zero2
result in Fig. 5 D
50% 0.9954 + 0.0484i 0.2063 3.4782
63% 0.9963 +/- 0.03581 0.2063 2.3754
70% 0.9967 +/- 0.0291i 0.2063 1.5643
75% 0.9970 +/- 0.0242i 0.2063 1.3636

. .
7

Fig. 8. Start up transient response of the buck converter

using frequency response method
(2V/div, 500psidiv)
B. Boost Converter
According to the root locus design in Fig. 4, a digital
controller was implemented on the TI DSP. The difference
equation converted from the transfer function in (7) is :
4.::
........

,
2.60
,
v
":

I
7
..... j...i..:
I
,
.

, ,,. ,,,
M5.00ms Chl I
.

.
:I
.....
.
,
9 .I2
,
9 May2003
u ( k ) = 1.13u(k - 1) - 0.13u(k - 2 ) + e ( k ) 13:31:09
(9)
- 1.75 e ( k - 1) + 0.765 e ( k - 2 ) Fig. 9. Start up transient response of the boost converter
The start up transient response is shown in Fig. 9. The output with controller gain = 30
voltage is able to reach the reference in about I O ms, but there (ZVidiv, 5ms/div)
are oscillations in steady state. An expanded view of the
steady state response is shown in Fig. 10. The experimental Tnk Run: Io.Oks/s Sample
i..r-.,-- -
response is not stable, while the root locus in Fig. 4 shows the
system is stable. There is a mismatch between the
c1 Mean
experimental result and the design. The gain of the controller 12.12ov
is tuned to improve the performance. When the gain is
reduced to 1, a stable start up transient response is obtained, ~ . .
and is shown in Fig. 11. The settling time is about IO ms. The
steady state response and the corresponding PWM signal are
shown in Fig. 12. The steady state error is 40 mV. The steady
state ripple is shown in Fig. 13. The magnitude of the ripple is
about 60 mV. The root locus of the compensated system when
the controller's DC gain is 1 is shown in Fig. 14. The three
closed-loop poles are close to the unit circle, which makes the ...
system almost critically stable. The experimental results don't
correspond to the design. This may be due to the nonlinear
property of the boost converter's small signal model, which 13:32:06
severely complicates the control problem. The variation of the Fig. IO. Steady state response of the boost converter with
poles and zeros of the boost converter's discrete-time model is controller gain = 30
shown is Table I. With the increase of the duty cycle, the two (2V/div, 5ms/div)
complex conjugate poles move closer to the unit circle, and
the value of the zero outside of the unit circle decreases.

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 Fig. 11. Start up transient response of the boost converter Fig. 14. Root locus of th,: compensated boost converter with
with controller gain = 1 controller gain = 1
(2V/dm, 5"div)
TeK E" 2 SOMSlr 7 ACQr T s l Run: IO.OkS/s Sample
. . r . .
. . . . .
. .
. . . . . . . . . . . . . .. . . . . . .. . . .. . . .. . . . .
. . . . . . . . C I Mean
11.96V
. . . . .........
c 2 +Duly
60.53% ... . . . . . . . . . . . . . . . . . .:.
. .
. . . . .
. . .

4 . . . . . . . . . . .

: I
. .:
.

. ..
.
I : i :
.
f.

. . . . . . . . . . .: . . f " ' . " ' : ; .

.. . . : . . j...
. .
. ..
~
.
.

.
.

.~ ,
.

.
. .. . . . .

, .
:..I
,

,
M5.00mI Chl I 9 .12 sMay2003
10:52:29 10:59:37
Fig. 12. Steady state response and PWM signal of the boost Fig.15. Start up transient response of the boost converter
converter with controller gain = 1 using frequency response design method

?,lu;i
(5V/div, 20 pddiv) (2V/div, 5ms/div)

1 ..: ... .:. .I.. 4.. ...:... .

c2 +Duly
. . . . 62.4 %
. . . . . .. . "~t' ' .
' ' .
" " .
. . .
C1 Mean
12.isv
. .
+ .
+r-.-i..+-++.
.
, ++
.
.
.
. . . .
. . . . . . . . . . . . . . . . . . .
. . .
. . . . .
. . . . . . . . . . . . . . . . . . . . . . . .
2 .. . . . . . . . .
. . . . . .
. .
....
.., .
...* . . . . . .
' , ~ c h 2 " s o o v " M 2 ~>
L;soov ;n'! ;6,J

m . . U% 18 M I ? 2001
10:48:03
12:35:10
Fig. 13. Steady state ripple of the boost converter with Fig.16. Steady state response and PWM signal of the boost
controller gain = 1 converter using frequency response design method
(100mV/div, 20 ps/div) (SV/div, 20 Fs/div)

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 I...;. 1 .. .
. .i . .

. . . . . . . . . .. . .
.
.l . . . .j

.. . . . . . . . .
.
*
. . :. . .

. ..
I.
.

.
I
.
.

. .....
!.j
.
Vir. REFERENCES
[I] Sevems, R. P., and Bloom, G., 1985, Modern DC-to-DC
Switchmode Power Converter Circuits, Van Nostrand
Reinhold Company, New York.
. .
.
.
. . [2] Robert W. Erickson, Dragan Maksimovie, 2001,
Fundamental of Power Electronics, Kluwer Academic
Publishers
[3] Ogata, K., 1987, Discrete-Time Control Systems.
Prentice-Hall, Inc., New Jersey.
L.
1: .........
.
j
I .
; ,;
. . . . I . . I . . : . . . :. . . .
:.
i...:. :.I:.
i . . ::. . . . 1 . .
.
.
.........
.
.
’ 1
.i
[4]

[5]
Charles L Phillips, Royce D. Harbor, 1996, Feedback
Control Systems, Prentice Hall, New Jersey
K. Kit Sum, 1984, Switch Mode Power Conversion,
Marcel Dekker, Inc., New York and Basel
,7:2404
[6] A. Prodic, D. Maksimovic and R. W. Erickson, ‘‘Design
and implementation of a digital PWM controller for a
Fig. 17. Steady state ripple of the boost converter using
high-frequency switching DC-DC power converter”,
frequency response design,method
IEEE Industrial Electronics Society, 2001, Vol. 2, pp. 893
(100mV/div, 20 pddiv) -898
[7] A. V. Peterchev, S. R. Sanders, “Quantization resolution
v . CONCLUSION and limit cycling in digitally controlled PWM
This paper discusses using the root locus method to design converters”, IEEE Trans. On Power Electronics, Vol. 18.
digital controllers for the buck and boost converters. The No. 1, Jan 2003, pp. 301-308
matched pole-zero mapping method is used to convert the [SI L. Guo, 1. Y. Hung and R. M. Nelms, “PID controller
small signal models of both converters into discrete-time modifications to improve steady-state performance of
models. Closed-loop poles are placed at certain positions to digital controllers for buck and boost converters”, IEEE
ensure the system stability and achieve the desired transient Applied Power Electronics Conference and Exposition,
and steady state responses. The digital controllers are 2002, Vol. 1, pp. 381 -388
implemented on a TI TMS320F240 DSP. Experimental results [9] L. Guo, 1. Y. Hung and R. M. Nelms, “Design and
are evaluated and compared with the results achieved using implementation of digital PID controller for a buck
converter’?, Proceedings of the 36th Intersociety Energy
the standard frequency response ‘design method. In the
Conversion Engineering Conference, 2001, Vol.1, pp.
frequency response design method, a standard PID algorithm
187-192.
was first implemented. To reduce the oscillation in the duty
cycle and improve steady state response, three modifications
were added to the standard PID algorithm [8, 91. In the root
locus design method, these algorithm modifications are not
needed.
Experimental results show that, for the buck converter, both
design methods are able to generate comparable performance
with fast transient response and stable steady state response.
While for the boost converter, the frequency response method
achieves the result that matches the design better. In the root
locus design for the boost converter, the experimental results
and the design don’t match very well. The differences
between the experimental and theoretical results may be
caused b y the nonlinear character of the boost converter
dynamics, which are not well described by the small signal
model. This hypothesis is under further investigation.

VI. ACKNOWLEDGMENT
This research was supported by the Center for Space Power
and Advanced Electronics with funds from NASA grant
NCC3-511, Aubum University, and the Centers’ industrial
partners.

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