Verilog Posts

Introduction

 What is Verilog?

 Introduction to Verilog

 Chip Design Flow

 Chip Abstraction Layers

Data Types

 Verilog Syntax

 Verilog Data types

 Verilog Scalar/Vector

 Verilog Arrays

Building Blocks

 Verilog Module

 Verilog Port

 Verilog Module Instantiations

 Verilog assign statements

 Verilog assign examples

 Verilog Operators

 Verilog Concatenation

 Verilog always block

 Combo Logic with always

 Sequential Logic with always

 Verilog initial block

 Verilog in a nutshell

 Verilog generate

Behavioral modeling

 Verilog Block Statements

 Verilog Assignment Types

 Verilog Blocking/Non-blocking

 Verilog Control Flow

 Verilog if-else-if

 Verilog Conditional Statements

 Verilog for Loop

 Verilog case Statement

 Verilog Functions

 Verilog Tasks

 Verilog Parameters

 Verilog `ifdef `elsif

 Verilog Delay Control

 Verilog Inter/Intra Delay

 Verilog Hierarchical Reference

 Verilog Coding Style Effect

Gate/Switch modeling

 Gate Level Modeling

 Gate Level Examples

 Gate Delays

 Switch Level Modeling

 User-Defined Primitives

Simulation

 Verilog Simulation Basics

 Verilog Testbench

 Verilog Timescale

 Verilog Scheduling Regions

 Verilog Clock Generator

System Tasks and Functions

 Verilog Display tasks

 Verilog Math Functions

 Verilog Timeformat

 Verilog Timescale Scope

 Verilog File Operations

Code Examples

 Hello World!

 Flops and Latches

 JK Flip-Flop

 D Flip-Flop

 T Flip-Flop

 D Latch
 Counters

 4-bit counter

 Ripple Counter

 Straight Ring Counter

 Johnson Counter

 Mod-N Counter

 Gray Counter

 Misc

 n-bit Shift Register

 Binary to Gray Converter

 Priority Encoder

 4x1 multiplexer

 Full adder

 Single Port RAM

 Verilog Pattern Detector

 Verilog Sequence Detector

Verilog module

1. Syntax
2. Example
1. Hardware Schematic
3. What is the purpose of a module ?
1. Hardware Schematic
4. What are top-level modules ?
1. Design Top Level
2. Testbench Top Level
5. Hierarchical Names
A module is a block of Verilog code that implements a certain
functionality. Modules can be embedded within other modules
and a higher level module can communicate with its lower level
modules using their input and output ports.

Syntax

A module should be enclosed within module and

endmodule keywords. Name of the module should be given
right after the module keyword and an optional list of
ports may be declared as well. Note that ports declared in the
list of port declarations cannot be redeclared within the body of
the module.

1 module <name> ([port_list]);

2 // Contents of the module
3 endmodule
4
5 // A module can have an empty portlist
6 module name;
7 // Contents of the module
8 endmodule

All variable declarations, dataflow statements, functions or tasks

and lower module instances if any, must be defined within the
module and endmodule keywords. There can be multiple
modules with different names in the same file and can be
defined in any order.

Example

The module dff represents a D flip flop which has three input
ports d , clk , rstn and one output port q . Contents of the
module describe how a D flip flop should behave for different
combinations of inputs. Here, input d is always assigned to
output q at positive edge of clock if rstn is high because it is
an active low reset.
 1 // Module called "dff" has 3 inputs and 1 output
2 module dff ( input d,
3 input clk,
4 input rstn,
5 output reg q);
6
7 // Contents of the module
8 always @ (posedge clk) begin
9 if (!rstn)
10 q <= 0;
11 else
12 q <= d;
13 end
14 endmodule

Hardware Schematic

This module will be converted into the following digital circuit

during synthesis.

Note that you cannot have any code written outside a

module !

What is the purpose of a module ?

A module represents a design unit that implements certain

behavioral characteristics and will get converted into a digital
circuit during synthesis. Any combination of inputs can be given
to the module and it will provide a corresponding output. This
allows the same module to be reused to form bigger modules
that implement more complex hardware.

For example, the DFF shown above can be chained to form a

shift register.
 1 module shift_reg ( input d,
2 input c
3 input r
4 output q
5
6 wire [2:0] q_net;
7 dff u0 (.d(d), .clk(clk), .rstn(
8 dff u1 (.d(q_net[0]), .clk(clk), .rstn(rstn),
9 dff u2 (.d(q_net[1]), .clk(clk), .rstn(rstn),
10 dff u3 (.d(q_net[2]), .clk(clk), .rstn(rstn),
11
12 endmodule

Hardware Schematic

Note that the dff instances are connected together with wires
as described by the Verilog RTL module.

Instead of building up from smaller blocks to form bigger design

blocks, the reverse can also be done. Consider the breakdown of
a simple GPU engine into smaller components such that each
can be represented as a module that implements a specific
feature. The GPU engine shown below can be divided into five
different sub-blocks where each perform a specific functionality.
The bus interface unit gets data from outside into the design,
which gets processed by another unit to extract instructions.
Other units down the line process data provided by previous
unit.

Each sub-block can be represented as a module with a certain

set of input and output signals for communication with other
modules and each sub-block can be further divided into more
finer blocks as required.
What are top-level modules ?

A top-level module is one which contains all other modules. A

top-level module is not instantiated within any other module.

For example, design modules are normally instantiated within

top level testbench modules so that simulation can be run by
providing input stimulus. But, the testbench is not instantiated
within any other module because it is a block that encapsulates
everything else and hence is the top-level module.

Design Top Level

The design code shown below has a top-level module called

design . This is because it contains all other sub-modules
requried to make the design complete. The submodules can
have more nested sub-modules like mod3 inside mod1 and
mod4 inside mod2 . Anyhow, all these are included into the top
level module when mod1 and mod2 are instantiated. So this
makes the design complete and is the top-level module for the
design.
 1 //---------------------------------
2 // Design code
3 //---------------------------------
4 module mod3 ( [port_list] );
5 reg c;
6 // Design code
7 endmodule
8
9 module mod4 ( [port_list] );
10 wire a;
11 // Design code
12 endmodule
13
14 module mod1 ( [port_list] ); // This modul
15 wire y;
16
17 mod3 mod_inst1 ( ... ); // First
18 mod3 mod_inst2 ( ... ); // Second
19 endmodule
20
21 module mod2 ( [port_list] ); // This modul
22 mod4 mod_inst1 ( ... ); // First
23 mod4 mod_inst2 ( ... ); // Second
24 endmodule
25
26 // Top-level module
27 module design ( [port_list]); // From desig
28 wire _net;
29 mod1 mod_inst1 ( ... ); // si
30 mod2 mod_inst2 ( ... );
31 endmodule

Testbench Top Level

The testbench module contains stimulus to check functionality

of the design and is primarily used for functional verification
using simulation tools. Hence the design is instantiated and
called d0 inside the testbench module. From a simulator
perspective, testbench is the top level module.
 1 //-----------------------------------------------
2 // Testbench code
3 // From simulation perspective, this is the top-l
4 // because 'design' is instantiated within this m
5 //-----------------------------------------------
6 module testbench;
7 design d0 ( [port_list_connections] );
8
9 // Rest of the testbench code
10 endmodule

Hierarchical Names

A hierarchical structure is formed when modules can be

instantiated inside one another, and hence the top level module
is called the root. Since each lower module instantiations within
a given module is required to have different identifier names,
there will not be any ambiguity in accessing signals. A
hierarchical name is constructed by a list of these identifiers
separated by dots . for each level of the hierarchy. Any signal
can be accessed within any module using the hierarchical path
to that particular signal.

1 // Take the example shown above in top level modu

2 design.mod_inst1 // Access to
3 design.mod_inst1.y // Access sig
4 design.mod_inst2.mod_inst2.a // Access sig
5
6 testbench.d0._net; // Top level
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 Interview Questions

 Verilog Interview Set 1

 Verilog Interview Set 2

 Verilog Interview Set 3

 Verilog Interview Set 4

 Verilog Interview Set 5

 Verilog Interview Set 6

 Verilog Interview Set 7

 Verilog Interview Set 8

 Verilog Interview Set 9

 Verilog Interview Set 10

 Related Topics

 Digital Fundamentals

 Verilog Tutorial

 Verification

 SystemVerilog Tutorial

 UVM Tutorial

Verilog Testbench

Verilog Coding Style Effect

Verilog Conditional Statements

 Verilog Interview Set 10

Synchronous FIFO

SystemVerilog Interview Set 10

SystemVerilog Interview Set 9

SystemVerilog Interview Set 8

SystemVerilog Interview Set 7

SystemVerilog Interview Set 6

UVM Singleton Object

UVM Component [uvm_component]

UVM Object [uvm_object]

UVM Root [uvm_root]

UVM Interview Set 4

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