PAMANTASAN NG CABUYAO

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COURSE CODE: CPP 110

COURSE DESCRIPTION: INTRODUCTION TO HDL

COURSE INTENDED On the completion of the course, student is expected to be able to do the
LEARNING OUTCOMES: following:

1. The ability to code and simulate any digital function in HDL.

2. Understand library modeling, behavioral code and the differences
between them.
3. Understand the differences between simulator algorithms as well
as Logic verification using HDL software tool
4. Learn good coding techniques per current industrial practices

LEARNING MATERIAL FOR 8

WEEK NUMBER:

I. TITLE: Selection Statements

II. OBJECTIVES: By the end of this module you should be able to:

1. Solve different problem sets using selection statements in Verilog

2. Improve coding in Verilog by using these statements
3. Understand the importance of conditional statements with the
relation on “selection” using Icarus Verilog

III. INTRODUCTION:
The purpose of this module is to introduce a section of Verilog similar to
the “Switch” statement in programming. This would help the students in
manipulation of conditions using selection process.
IV. CONTENTS:

Lesson Coverage:

- Selection Statements

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INTRODUCTION

CASE STATEMENTS

The Verilog Case Statement works exactly the way that a switch statement in C works. Given an input,
the statement looks at each possible condition to find one that the input signal satisfies. They are useful
to check one input signal against many combinations.

Just like in C, the VHDL designer should always specify a default condition provided that none of the
case statements are chosen. This is done via the "default: " statement.

One thing to note with case statements is that Verilog does not allow the use of less than or greater
than relational operators in the test condition. Only values that are equal to the signal in the case test
can be used.

Note that the example below uses the brackets for concatenation.

module case_statement ();

reg r_VAL_1 = 1'b0;

reg r_VAL_2 = 1'b0;
reg r_VAL_3 = 1'b0;

reg [3:0] r_RESULT = 4'b0000;

// Uses r_VAL_1, r_VAL_2, and r_VAL_3 together to drive a case statement

// This always block is synthesizable
always @(*)
begin
case ({r_VAL_1, r_VAL_2, r_VAL_3})
3'b000 : r_RESULT <= 0;
3'b001 : r_RESULT <= 1;
3'b010 : r_RESULT <= 2;
default : r_RESULT <= 9;
endcase
end

// *Initial* is never synthesizable. Test code only!

initial begin
r_VAL_1 <= 1'b0;
r_VAL_2 <= 1'b0;
r_VAL_3 <= 1'b0;
#100;
r_VAL_2 <= 1'b0;
r_VAL_3 <= 1'b1;
#100;
r_VAL_2 <= 1'b1;
r_VAL_3 <= 1'b0;
#100;
r_VAL_2 <= 1'b1;
r_VAL_3 <= 1'b1;
#100;
#1000000;
end

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endmodule // case_statement

Syntax

The case statement compares an expression to a series of cases and executes the statement or
statement group associated with the first matching case:

• case statement supports single or multiple statements.

• Group multiple statements using begin and end keywords.

Syntax of a case statement look as shown below.

case ()
< case1 > : < statement >
< case2 > : < statement >
.....
default : < statement >
endcase

Example with Normal Case

1 module mux (a,b,c,d,sel,y);

2 input a, b, c, d;
3 input [1:0] sel;
4 output y;
5
6 reg y;
7
8 always @ (a or b or c or d or sel)
9 case (sel)
10 0 : y = a;
11 1 : y = b;
12 2 : y = c;
13 3 : y = d;
14 default : $display("Error in SEL");
15 endcase
16
17 endmodule

Example- case without default

1 module mux_without_default (a,b,c,d,sel,y);

2 input a, b, c, d;
3 input [1:0] sel;
4 output y;
5
6 reg y;
7
8 always @ (a or b or c or d or sel)
9 case (sel)
10 0 : y = a;
11 1 : y = b;
12 2 : y = c;
13 3 : y = d;

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14 2'bxx,2'bx0,2'bx1,2'b0x,2'b1x,
15 2'bzz,2'bz0,2'bz1,2'b0z,2'b1z : $display("Error in SEL");
16 endcase
17
18 endmodule

The example above shows how to specify multiple case items as a single case item.

The Verilog case statement does an identity comparison (like the === operator); one can use the case
statement to check for logic x and z values as shown in the example below.

Example- case with x and z

1 module case_xz(enable);
2 input enable;
3
4 always @ (enable)
5 case(enable)
6 1'bz : $display ("enable is floating");
7 1'bx : $display ("enable is unknown");
8 default : $display ("enable is %b",enable);
9 endcase
10
11 endmodule

The casez and casex statement

Special versions of the case statement allow the x ad z logic values to be used as "don't care":
• casez : Treats z as don't care.
• casex : Treats x and z as don't care.

Try ME.

1 module casez_example();
2 reg [3:0] opcode;
3 reg [1:0] a,b,c;
4 reg [1:0] out;
5
6 always @ (opcode or a or b or c)
7 casez(opcode)
8 4'b1zzx : begin // Don't care about lower 2:1 bit, bit 0 match with x
9 out = a;
10 $display("@%0dns 4'b1zzx is selected, opcode %b",$time,opcode);
11 end
12 4'b01?? : begin
13 out = b; // bit 1:0 is don't care
14 $display("@%0dns 4'b01?? is selected, opcode %b",$time,opcode);
15 end
16 4'b001? : begin // bit 0 is don't care
17 out = c;
18 $display("@%0dns 4'b001? is selected, opcode %b",$time,opcode);
19 end
20 default : begin
21 $display("@%0dns default is selected, opcode %b",$time,opcode);

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22 end
23 endcase
24
25 // Testbench code goes here
26 always #2 a = $random;
27 always #2 b = $random;
28 always #2 c = $random;
29
30 initial begin
31 opcode = 0;
32 #2 opcode = 4'b101x;
33 #2 opcode = 4'b0101;
34 #2 opcode = 4'b0010;
35 #2 opcode = 4'b0000;
36 #2 $finish;
37 end
38
39 endmodule

The output should be like this:

@0ns default is selected, opcode 0000

@2ns 4'b1zzx is selected, opcode 101x

@4ns 4'b01?? is selected, opcode 0101

@6ns 4'b001? is selected, opcode 0010

@8ns default is selected, opcode 0000

Try me 2:

1 module casex_example();
2 reg [3:0] opcode;
3 reg [1:0] a,b,c;
4 reg [1:0] out;
5
6 always @ (opcode or a or b or c)
7 casex(opcode)
8 4'b1zzx : begin // Don't care 2:0 bits
9 out = a;
10 $display("@%0dns 4'b1zzx is selected, opcode %b",$time,opcode);
11 end
12 4'b01?? : begin // bit 1:0 is don't care
13 out = b;
14 $display("@%0dns 4'b01?? is selected, opcode %b",$time,opcode);
15 end
16 4'b001? : begin // bit 0 is don't care
17 out = c;
18 $display("@%0dns 4'b001? is selected, opcode %b",$time,opcode);
19 end
20 default : begin
21 $display("@%0dns default is selected, opcode %b",$time,opcode);

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22 end
23 endcase
24
25 // Testbench code goes here
26 always #2 a = $random;
27 always #2 b = $random;
28 always #2 c = $random;
29
30 initial begin
31 opcode = 0;
32 #2 opcode = 4'b101x;
33 #2 opcode = 4'b0101;
34 #2 opcode = 4'b0010;
35 #2 opcode = 4'b0000;
36 #2 $finish;
37 end
38
39 endmodule

The output should be:

@0ns default is selected, opcode 0000

@2ns 4'b1zzx is selected, opcode 101x

@4ns 4'b01?? is selected, opcode 0101

@6ns 4'b001? is selected, opcode 0010

@8ns default is selected, opcode 0000

To avoid confusion and to see the process on those three, let’s have another one.

Example- Comparing case, casex, casez

1 module case_compare;
2
3 reg sel;
4
5 initial begin
6 #1 $display ("\n Driving 0");
7 sel = 0;
8 #1 $display ("\n Driving 1");
9 sel = 1;
10 #1 $display ("\n Driving x");
11 sel = 1'bx;
12 #1 $display ("\n Driving z");
13 sel = 1'bz;
14 #1 $finish;
15 end
16
17 always @ (sel)
18 case (sel)
19 1'b0 : $display("Normal : Logic 0 on sel");
20 1'b1 : $display("Normal : Logic 1 on sel");

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21 1'bx : $display("Normal : Logic x on sel");

22 1'bz : $display("Normal : Logic z on sel");
23 endcase
24
25 always @ (sel)
26 casex (sel)
27 1'b0 : $display("CASEX : Logic 0 on sel");
28 1'b1 : $display("CASEX : Logic 1 on sel");
29 1'bx : $display("CASEX : Logic x on sel");
30 1'bz : $display("CASEX : Logic z on sel");
31 endcase
32
33 always @ (sel)
34 casez (sel)
35 1'b0 : $display("CASEZ : Logic 0 on sel");
36 1'b1 : $display("CASEZ : Logic 1 on sel");
37 1'bx : $display("CASEZ : Logic x on sel");
38 1'bz : $display("CASEZ : Logic z on sel");
39 endcase
40
41 endmodule
The output should be like this:

Driving 0
Normal : Logic 0 on sel
CASEX : Logic 0 on sel
CASEZ : Logic 0 on sel

Driving 1
Normal : Logic 1 on sel
CASEX : Logic 1 on sel
CASEZ : Logic 1 on sel

Driving x
Normal : Logic x on sel
CASEX : Logic 0 on sel
CASEZ : Logic x on sel

Driving z
Normal : Logic z on sel
CASEX : Logic 0 on sel
CASEZ : Logic 0 on sel

The case statement starts with a case or casex or casez keyword followed by the case expression (in
parenthesis) and case items or default statement. It ends with the endcase keyword. The default
statement is optional and should be used only once. A case item contains a list of one or more case
item expressions, separated by comma, and the case item statement. The case item expression and
the case item statement should be separated by a colon.

During the evaluation of the case statement, all case item expressions are evaluated and compared in
the order in which they are given. If the first case item expression matches the case expression, then
the statement which is associated with that expression is executed and the execution of the case
statement is terminated. If comparison fails, then the next case item expression is evaluated and

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compared with the case expression. If all comparisons fail and the default section is given, then its
statements are executed. Otherwise none of the case items will be executed.

Both case expression and case item expressions should have the same bit length. None of the
expressions are required to be a constant expression.

The case expression comparison is effective when all compared bits are identical. Therefore, special
types of case statement are provided, which can contain don't-care values in the case expression and
in the case item expression. These statements can be used in the same way as the case statement,
but they begin with the keywords casex and casez.

The casez statement treats high-impedance (z) values as don't-care values and the casex statement
treats high-impedance and unknown (x) values as don't care values. If any of the bits in the case
expression or case item expression is a don't-care value then that bit position will be ignored.

The don't-care value can be also specified by the question mark (?), which is equal to z value.

Let’s have more examples.

Example 1

reg [1:0] address;

case (address)
2'b00 : statement1;
2'b01, 2'b10 : statement2;
default : statement3;
endcase

If the address value is 2'b00 then statement1 will be executed. Statement2 is executed when address
value equals 2'b01 or 2'b10. Otherwise statement3 is executed.

Example 2

reg a;
case (a)
1'b0 : statement1;
1'b1 : statement2;
1'bx : statement3;
1'bz : statement4;
endcase

In Example 2, the statements will be executed depending on the value of the 'a' variable (if a = 1'b0
then statement1 will be executed, etc). If we assign a question mark (?) to the 'a' variable, then
statement4 will be executed because the syntax concerning numbers defines the question mark as
equal to the z value.

Example 3

reg a;
casez (a)
1'b0 : statement1;
1'b1 : statement2;
1'bx : statement3;
1'bz : statement4;
endcase

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If value of variable 'a' is 1'b0 or 1'b1 or 1'bx then statement1, statement2 or statement3 will be executed
respectively. If 'a' equals 1'bz or 1'b? then statement1 will be executed because the casez statement
treats z and ? as the don't-care values. Statement4 will never be executed because only the first case
item, which matches with the case expression, is executed.

Example 4

reg a;
casex (a)
1'b0 : statement1;
1'b1 : statement2;
1'bx : statement3;
1'bz : statement4;
endcase

If variable 'a' is 1'b0 or 1'b1 then statement1 and statement2 will be executed respectively. If 'a' equals
1'bx or 1'bz or 1'b? then statement1 will be executed (x, z and ? are don't care values for the casex
statement). Statement3 and statement4 will never be executed.

Example 5

reg a;
case (1'b1)
a : statement1;
endcase

The case expression can be a constant expression. In Example 5, statement1 will be executed only if
'a' is equal to 1'b1.

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V. REFERENCES: Roth, C.H. Jr. And John, L. K. (2018). Digital Systems Design Using VHDL (3rd
ed.). Texas, USA: Cengage Unlimited

Brown, S. and Vranesic, Z. (2009). Fundamentals of Digital Logic with VHDL

Design. (3rd ed.). New York, NY: McGraw-Hill

Online Readings and Guide

Hardware Description Language | VLSI Tutorial | Mepits

VHDL || Electronics Tutorial (electronics-tutorial.net)

Index of /ece232/pdf (umass.edu)

VI. ASSESSMENT TASK:

See Attached file given by the instructor

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