@Pallavi Thammina

AXI protocol questions:

1. Difference between interleaving and out-of-order?

Interleaving is like dividing a big task into smaller pieces and working on them at the same time. In
computer memory, it means breaking down a big memory request into smaller parts and fetching data
from different places in memory simultaneously. This helps speed up the process of getting data from
memory.
Data interleaving is a technique used to make memory access faster in computers and other electronic
devices. Means data is stored and retrieved from different parts of the memory at the same time, making
the computer work more efficiently and quickly.

Out-of-order is like rearranging tasks in a to-do list to get things done faster. In a computer processor, it
means changing the order of instructions in a program so that independent tasks can be done at the same
time. This helps the processor work more efficiently and completes tasks quicker.

Both techniques aim to improve system performance but operate at different levels: memory access in
the case of interleaving and instruction execution in the case of out-of-order execution.

2. Difference between AXI3 and AXI4

WRITE DATA INTERLEAVING
• AXI- WID is supported. So write data interleaving is possible.
• AXI4 – no WID signal. So Write data interleaving is not supported.
BURST SUPPORT
• The AXI specification permits burst lengths of up to 4 bits that is 16 data beats.
• AXI4 specification permits large burst length of up to 8 bits that is 256 data
HANDSHAKE RULE
• AXI – there is a confusion in AXI write transfer that, write response can come before write address
but not before write data.
• AXI4 – write response can come only after write address and write data

3. Why IDs are used in channels?

IDs in channels are an essential part of communication protocols, enabling efficient and reliable data
transfer between different entities in a system. They provide a structured and organized approach to
manage data exchanges, making complex systems more manageable and predictable.

4. How Burst transaction is required, explain?

Burst transactions are required to efficiently transfer a large amount of data between components in a
computer system.
With burst transactions, the CPU can initiate a single read command, specifying the starting address of the
block and the number of data items it needs to read. The memory controller then automatically sends a
continuous stream of data items to the CPU without the need for additional address and command
transmissions between each data item. This reduces the overhead and increases the overall data transfer
efficiency.

5. What are Unaligned transfers?

The (AXI), unaligned transfers refer to data transfers where the starting address of the data does not align
with the natural boundary of the data bus width.
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Handling unaligned transfers in AXI is critical to ensure data integrity and proper communication between
components. AXI specification provides specific rules for it:
Data Strobes (WSTRB): indicate which bytes within the data bus are valid during a transfer.
Burst Length Extension (BLE): to indicate the number of data transfers within a burst.
Data Alignment and Padding: In some AXI implementations, unaligned transfers might be handled by
padding the data with extra bytes to make it aligned.

6. Explain handshake between Valid and Ready?

Valid signal
It indicates that the sender has valid data to transfer. When the "Valid" signal is asserted (high), it means
that the data present at the sender's output is valid.
Ready signal
It indicates that the receiver is ready to accept data. When the "Ready" signal is asserted (high), it means
that the receiver is prepared to receive data from the sender.
Handshake process:
• When both the "Valid" and "Ready" signals are asserted (high) simultaneously, it forms a handshake
agreement. This handshake condition indicates that data transfer can occur.
• At this point, the sender transfers the valid data to the receiver, which then processes the data.
• After the data transfer is completed, the sender de-asserts the "Valid" signal, indicating that it no longer
has valid data to send.
• The receiver, after processing the data, de-asserts the "Ready" signal, indicating that it is no longer ready
to receive data.

7. What is deadlock condition?

There are certain dependencies on how handshaking signals should be asserted. If it's violated
handshaking will not occur and the process will be stalled. It's called a deadlock scenario.
For ex: A deadlock condition can occur if the slave is waiting for WVALID before asserting AWREADY.

8. AXI has diff channels, explain it

There are 5 channels
Write Address Channel (AW):
This channel is used for write transactions initiated by the master.
It carries the write address (AWADDR) from the master to the slave, indicating the target memory
location where the write data should be stored.
Additional signals include AWVALID (validity of the write address), AWREADY (readiness of the slave to
accept the write address), AWID (write transaction identifier), AWLEN (number of data transfers within
the burst transaction), AWSIZE (size of the data transfer), AWBURST (type of burst transfer).
Write Data Channel (W):
This channel is used to send the write data (WDATA) from the master to the slave.
It also includes WSTRB (byte enables indicating which bytes are valid for writing), WVALID (validity of the
write data), WREADY (readiness of the slave to accept the write data), and WLAST (indicating the last
transfer of the burst transaction).
Write Response Channel (B):
This channel is used to send the write response from the slave to the master.
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It includes BRESP (response from the slave to the write transaction), BVALID (validity of the write
response), BREADY (readiness of the master to accept the write response), and BID (write transaction
identifier).
Read Address Channel (AR):
This channel is used for read transactions initiated by the master.
It carries the read address (ARADDR) from the master to the slave, indicating the target memory location
from where the read data should be fetched.
Additional signals include ARVALID (validity of the read address), ARREADY (readiness of the slave to
accept the read address), ARID (read transaction identifier), ARLEN (number of data transfers within the
burst transaction), ARSIZE (size of the data transfer), ARBURST (type of burst transfer)
Read Data Channel (R)
This channel is used to send the read data (RDATA) from the slave to the master.
It also includes RVALID (validity of the read data and response), RREADY (readiness of the master to
accept the read data and response), RLAST (indicating the last transfer of the burst transaction), and
RRESP (response from the slave to the read transaction).

9. Why there was no write response for each beat in burst write. But there is a separate read response for
each beat in a read burst?
For read transfers, the information and the response flow are from slave to master. But for a write
transaction, the information and the response are in different directions.

So individual responses for each transfer will involve more clock cycles and unnecessary traffic because of
the two-way flow between master and slave.

So it is better to have a single response for a write transaction compared to a response for each transfer
in a read transaction.

10. How testplan environment is planned with AXI transfer with some subsystem.
Planning a test environment with AXI transfers involving a subsystem typically involves the following
steps:
• Understand the Requirements
• Define Test Goals
• Create a Testplan
• Design Testbench Architecture
• AXI Verification Components
• Test Sequences
• Coverage Goals
• Randomization and Constraints
• Error Handling
• Assertions
• Scoreboarding and Functional Checking
• Debugging and Visualization
• Run Testcases
• Coverage Closure
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• Test Report
By following these steps, the test plan environment for AXI transfers with the subsystem can be
effectively planned, executed, and validated (just mentioned the outline if required will add the details).

11. What do you mean by multiple outstanding transactions? Why is it useful?

Master initiates a transaction and doesn't wait for it to complete (response to arrive) and initiates another
transaction. So the first transaction is an outstanding transaction. AXI supports multiple outstanding
transactions so an AXI master doesn't have to wait for a transaction to complete to initiate a new one. So
the performance is boosted.

12. If there are multiple outstanding transactions pending, how you will debug the issue?
When there are multiple outstanding transactions pending in a system, debugging the issue can be
challenging due to the complexity of interactions between various components. Here are some steps to
help debug the issue:
Waveform Debugging: Use waveform viewers to analyze the signals and transactions in the system.
Transaction Logs: Enable transaction logging in the test bench to capture details of each transaction.
Coverage Analysis: Monitor functional and code coverage to ensure that all scenarios and corner cases
are exercised during simulation.
Reduce Testcase Size: If the issue occurs in a large testcase, try reducing the testcase size to create a
minimal reproduction case.

13. What is the minimum and maximum data bus width supported in AXI?
The data bus width as per spec can be 8,16,32...,1024 bits. So the minimum is 8 and maximum is
1024 bits.

14. Why don’t we have separate Read response channel?

READ operation doesn't have a response channel because direction both the read data and read
response is from slave to master. With every beat, the slave will send a read response along with the
data in read data channel.

15. Difference between beat , burst, transaction?

Transaction - The complete set of required operations on the AXI bus.
Burst - Required payload data to is transferred.
Beats - Burst can comprise multiple data transfers.

16. What are burst types? diff between incr and wrap
Burst types refer to the data transfers occur between a master and a slave during a single AXI transaction.
There are 3 burst types
• FIXED - FIXED burst type is used when the master wants to perform multiple data transfers to the same
fixed address (e.g., for multiple write operations to the same register)
• INCR - INCR burst type is used for sequential data transfers, where addresses are accessed incrementally
from the initial address without wrapping around to the starting address.
INCR bursts are typically used for transferring consecutive data elements, like elements in an array or a
sequence of pixels in an image.
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• WRAP - WRAP burst type is used for circular or wrapped data transfers, where the address wraps around
to the starting address after reaching a certain boundary, allowing continuous circular access to the data.
WRAP bursts are commonly used in circular buffers or queues, where data needs to be continuously
processed without the need for additional address computations.

17. Real time example of wrap condition

Wrap conditions are commonly encountered in applications where data needs to be continuously
processed in a circular manner, such as audio or video streaming, data logging, or circular data buffers in
communication protocols.

Suppose we have a circular buffer with a size of 16 bytes, and the memory addresses range from 0x0000
to 0x000F. When accessing this buffer, the memory address will "wrap around" back to the starting
address (0x0000) once it reaches the maximum address (0x000F).

18. Lower and Upper boundary wrap calculation by giving starting addr=0x24, length=8, transfer
size=32bits
1)Lower boundary = [int(starting addr)/(awsize*awlen)]*[(awsize*awlen)]
2)Upper boundary=(lower boundary + total no. of transfers)
3)Total No. of transfers = awsize * awlen

Given str addr=0x24(hexa) -> 36(decimal), length=8, transfer bits =32

From equation 3 -> 32= awsize * 8
awsize =4
lower boundary = int(36/8*4)*(8*4) = 32(dec)= 0x20
upper boundary = 0x20+32= 0x40

19. what is lock signal/exclusive access in AXI w.r.t higher level

• In the AXI protocol, the "lock signal" or "exclusive access" feature allows a master to request exclusive
access to a memory location during a read-modify-write operation.
• It ensures atomicity, giving priority to the requesting master and preventing other masters from accessing
the same location simultaneously. Once the operation is completed, the lock is released, allowing other
masters to access the memory location.

20. Write an assertion on handshake signals - ready and valid, ready comes after 5 cycles
from the start of valid h i g h ?
Property valid_b_ready;
@(posedge clk) disable iff(rst)
$rose(valid)|->##5 $rose(ready);
endproperty