Digital System Design & Synthesis

Synthesis Techniques
Synthesis
 Verilog files aren’t hardware yet!
 Need to “synthesize” them
 Tool reads hardware descriptions
 Figures out what hardware to make
 Done automatically
 Faster!
 Easier!
 Designers still have to understand hardware!
 Avoid pre- vs. post-synthesis discrepancies
 Describe EFFICIENT hardware

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Useful Documentation
 Fairly complete documentation is available for the
Synopsys tools using:
/afs/engr.wisc.edu/apps/eda/synopsys/syn_Y-2006.06-
SP1/sold

 See especially (through Design Compiler link)

 Design Vision User Guide
 Design Compiler User Guide
 Design Compiler Reference Manuals
 HDL Compiler (Presto Verilog) Reference Manual
 HDL Compiler for Verilog Referernce Manual
 Use as references
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 HDL Compiler for
Verilog Reference
Manual, pg. 1-5.
 HDL Compiler is
called by Design
Compiler and
Design Vision

 Why do we need
to compare
synthesized code
to initial code?
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 Design Compiler
User Guide, pg. 2-17
 Design Vision is GUI
for Design Compiler:
use design_vision
 Can also run Design
Compiler directly
using dc_shell
 To compile using a
synthesis script use
dc_shell –tcl_mode –f
file_name

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Synthesis Script Example [1]
# To run, place in the directory with all the Verilog files
# and type: dc_shell -tcl_mode -f script.tcl

#Analyze input files.

analyze -library WORK -format verilog {./prob5.v ./prob1.v ./prob2.v}

#Elaborate the design.

elaborate GF_multiplier_mword -architecture verilog -library WORK

#Sets clock constraint of 2ns with 50% duty cycle on signal "clock".
create_clock -name "clk" -period 2 -waveform {0 1} {clock}
set_dont_touch_network [ find clock clk ]

#Sets the area constraint for the design

set_max_area 50000

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Synthesis Script Example [2]
#Check and compile the design
check_design > check_design.txt
uniquify
compile -map_effort medium

#Export netlist for post-synthesis simulation into synth_netlist.v

change_names -rule verilog -hierarchy
write -format verilog -hierarchy -output synth_netlist.v

#Generate reports
report_resources > resource_report.txt
report_area > area_report.txt
report_timing > timing_report.txt
report_constraint -all_violators > violator_report.txt
report_register -level_sensitive > latch_report.txt

exit 7
Internal Synthesizer Flow
HDL Description Structural
Representation
Parsing and
Syntax & Semantic Architectural Technology
Error Checking Optimization Library

Synthesizer Multi-Level Logic Technology

Policy Checking Optimization Mapping

Translation Technology-Based
(Elaboration) Implementation

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Initial Steps
 Parsing for Syntax and Semantics Checking
 Gives error messages and warnings to user
 User may modify the HDL description in response

 Synthesizer Policy Checking

 Check for adherence to allowable language constructs
 Check for usage recommendations

 This is where you find out you can’t use certain Verilog
constructs
 This is synthesizer-dependent
 Example: Design Vision allows indexed part-select
(guess[i*2 : 2]), but the Xilinx Foundation tool does not
 Certain things common to MOST synthesizers
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Translation (Elaboration)
 Builds a structural representation of the design
 Like a netlist, but includes larger components
 Not just gate-level, may include adders, etc.
 Gives additional errors or warnings to the user
 Issues in initial transformation to hardware.
 Affects quality achieved by optimization steps
 Structural representation depends on HDL quality
 Poor HDL can prevent optimization

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Optimization in Synthesis
 None of these are guaranteed!
 Most synthesizers will make at least some attempt

 Detect and eliminate redundant logic

 Detect combinational feedback loops
 Exploit don't-care conditions
 Try to detect unused states
 Detect and collapse equivalent states
 Make state assignments if not made already
 Synthesize optimal, multilevel realizations subject to:
 constraints on area and/or speed
 available technology (library)
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Optimization Process
 Optimization modifies the initial netlist resulting
from elaboration.
 Uses cells from the technology library
 Attempts to meet all specified constraints
 The process is divided into major phases
 All or some selection of the major phases may be
performed during optimization
 Phase selection can be controlled by the used

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Optimization Phases
 Architectural optimization
 High-level optimizations that occur before the design
is mapped to the logic-level
 Based on constraints and high-level coding style
 After optimization circuit function is represented by a
generic, technology-independent netlist (GTECH)

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Architectural Optimization
 In Synopsis, types include:
 Sharing common mathematical subexpressions
 Sharing resources
 Selecting DesignWare implementations
 Reordering operators
 Identifying arithmetic expressions for datapath
synthesis

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Architectural Optimization
 Examples:
 Replace an adder used as a counter with incrementer
 Replace adder and separate subtractor with
adder/subtractor if not used simultaneously
 Performs selection of pre-designed components
(Synopsys DesignWare)
 adders, multipliers, shifters, comparators, muxes, etc.

 Need good code for synthesizer to do this

 Designer still knows more about the project

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Logic/Gate-Level Optimization
 Works on the generic netlist created by logic
synthesis
 Produces a technology-specific netlist.
 In Synopsis, it consists of four stages:
 Mapping
 Delay optimization
 Design rule fixing
 Area optimization

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Logic/Gate-Level Optimization
 Mapping
 Generates a gate level implementation
 Tries to meet timing and area goals
 Delay optimization
 Tries to fix delay violations from mapping phase.
 Does not fix design rule violations or meet area constraints.
 Design rule fixing
 Tries to correct design rule violations
 Inserting buffers or resizing existing cells
 If necessary, violates optimization constraints
 Area optimization
 Tries to meet area constraints, which have lowest priority

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Combinational Optimization

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Gate-Level Optimization

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Logic-Level Optimizations

Verilog Technology
Description Libraries

TRANSLATION OPTIMIZATION MAPPING

ENGINE ENGINE ENGINE

Optimized
Two-level Technology
Multi-level Logic
Logic Functions Implementation
Functions

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Logic Optimizations
 Area
 Number of gates fewer == smaller
 Size of gates (# inputs) fewer == smaller
 Delay
 Number of logic levels fewer == faster
 Size of gates (# inputs) fewer == faster

 Note that examples that follow ignore NOT gates

for gate count / levels of circuits

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Logic Optimizations
 Decomposition
 Extraction
 Factoring
 Substitution
 Elimination

 You don’t have to remember the names of these

 But should understand logic optimization
 Different techniques targeting area vs. delay
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Decomposition
 Find common expressions
 Reduce redundancy
 Reduce area (number/size of gates)
 May increase delay
 More levels of logic

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Decomposition Example
 F = abc + abd + a’c’d’ + b’c’d’
~7 gates, ~3 levels
 F = ab(c + d) + c’d’(a’ + b’)
 F = ab(c + d) + (c + d)’(ab)’

 X = ab 1 gate, 1 level
 Y=c+d 1 gate, 1 level
 F = XY + X’Y’ 3 gates, 3 levels
G(original) = 16
G(decomposed) = 10
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Extraction
 Find common sub-expressions in functions
 Like decomposition, but across more than one
function
 Reduce redundancy
 Reduce area (number/size of gates)
 May increase delay if more logic levels
introduced

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Extraction Example
 F = (a + b)cd + e 3 gates, 3 levels
 G = (a + b) e’ 2 gates, 2 levels
 H = cde 1 gate, 1 level

 X = a + b, Y = cd 1 gate, 1 level (each)

 F = XY + e 4 gates, 3 levels
 G = Xe’ 2 gate, 2 levels
 H = Ye 2 gate, 2 levels

 Before:
 (3) 2-input ORs, (2) 3-input ANDs, (1) 2-input AND
 G(orginal) = 7 + 4 + 3 = 14
 After
 (2) 2-input Ors, (4) 2-input ANDs
 G(extracted) = 2 + 2 + 4 + 2 + 2 = 12
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Factoring
 Traditional two-level logic is sum-of-products
 Sometimes better expressed by product-of-sums
 Fewer literals => less area
 May increase delay if logic equation not
completely factored (becomes multi-level)

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Factoring Example
 Definitely good:
 F = ac + ad + bc + bd ~7+ gates, ~3 levels
 F = (a + b)(c + d) 3 gates, 2 levels
 Maybe good:
 F = ac + ad + e 3 gates, 2 levels
 F = a(c + d) + e 3 gates, 3 levels

 This one may improve area...

 But will likely increase delay (tradeoff)

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Substitution
 Similar to Extraction
 When one function is subfunction of another
 Reduce area
 Fewer gates
 Can increase delay if more logic levels

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Substitution Example
 G=a+b 1 gate, 1 level
 F=a+b+c 1 gate, 1 level

 F=G+c 2 gate, 2 levels

 Before:
 (1) 2-input OR, (1) 3-input OR
 After
 (2) 2-input ORs (but increased levels)

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Elimination (Flattening)
 Opposite of previous optimizations
 Goal is to reduce delay
 Make signals travel though as few logic levels as
possible
 But will likely increase area
 Gate replication / redundant logic

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Elimination Example
 G=c+d 1 gate, 1 level
 F = Ga + G' b 3 gates, 3 levels

 G=c+d 1 gate, 1 level

 F = ac + ad + bc’d’ 4 gates, 2 levels

 Before:
 (2) 2-input ORs, (2) 2-input ANDs
 After:
 (1) 2-input OR, (1) 3-input OR, (2) 2-input ANDs,
(1) 3-input AND (but fewer levels)

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