Addressing Modes

The different ways that a microprocessor can access data are referred to as addressing modes.
There are five types of addressing modes in 8085 microprocessor.
➢ Direct addressing mode
➢ Immediate addressing mode
➢ Register addressing mode
➢ Register indirect addressing mode
➢ Implicit (or) implied addressing mode

✓ Direct addressing mode

In direct addressing mode, the address of the operand is directly specified in the instruction. In
this addressing mode, the instruction is two or three bytes long. The first byte is the Opcode. The
operand may be a 16-bit (2 bytes) memory address or an 8-bit (1 byte) port address.
Example

Immediate addressing mode

In immediate addressing mode, the operand itself is immediately given after the Opcode. The
instruction is two or three bytes long. The first byte is the Opcode. The operand may be a 16-bit
(2 bytes) immediate data or an 8-bit (1 byte) immediate data.
Examples:

Register addressing mode

In register addressing mode, a register is specified as the operand in the instruction. The
instruction is one byte long. The register name is specified in the Opcode itself.
Examples:
register indirect addressing mode
In register indirect addressing mode, the content of the register pair is used as the address of the
operand in the instruction. The instruction is one byte long. The register pair contains the 16-bit
address of the memory location where the actual operand is stored.
Examples:

Implicit or Implied addressing mode

In implicit addressing mode, a particular register is implicitly specified as the operand in the
instruction. The instruction is one byte long. This addressing mode is also known as implied
addressing mode and inherent addressing mode.
Examples:

8085 INTERRUPTS
Interrupt is a signal send by an external device to the processor, to the processor to perform a
particular task or work
Need for interrupts
- Mainly in the microprocessor based system the interrupts are used for data transfer between the
peripheral and the microprocessor.
- When a peripheral is ready for data transfer, it interrupts the processor by sending an appropriate
signal to the interrupt pin of the processor.
- If the processor accepts the interrupt then the processor suspends its current activity and executes
an interrupt service subroutine to complete the data transfer between the peripheral and processor.
- After executing the interrupt service routine the processor resumes its current activity.
- This type of data transfer scheme is called interrupt driven data transfer scheme.

Interrupt Structure:
- Interrupt is the mechanism by which the processor is made to transfer control from its current
program execution to another program having higher priority.
- The interrupt signal may be given to the processor by any external peripheral device.
- The program or the routine that is executed upon interrupt is called interrupt service routine (ISR).
After execution of ISR, the processor must return to the interrupted program.
- Key features in the interrupt structure of any microprocessor are as follows:
o Number and types of interrupt signals available.
o The address of the memory where the ISR is located for a particular interrupt signal. This
address is called interrupt vector address (IVA).
o Masking and unmasking feature of the interrupt signals.
o Priority among the interrupts.
o Timing of the interrupt signals.
o Handling and storing of information about the interrupt program (status information).

Types of Interrupts:
- Interrupts are classified based on their maskability, IVA and source. They are classified as:
a) Software and Hardware Interrupts
Software interrupts
- Software interrupts are special instructions, after execution transfer the control to predefined ISR.
- The software interrupts are program instructions. When the instruction is executed, the processor
executes an interrupt service routine stored in the vector address of the software interrupt
instruction. The software interrupts of 8085 are RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6 and
RST 7.
- The vector addresses of software interrupts are given in table below.

- The software interrupt instructions are included at the appropriate (or required) place in the main
program.
- When the processor encounters the software instruction, it pushes the content of PC (Program
Counter) to stack.
- Then loads the Vector address in PC and starts executing the Interrupt Service Routine (ISR) stored
in this vector address. At the end of ISR, a return instruction - RET will be placed.
- When the RET instruction is executed, the processor POP the content of stack to PC. Hence the
processor control returns to the main program after servicing the interrupt.
- Execution of ISR is referred to as servicing of interrupt.
- All software interrupts of 8085 are vectored interrupts. The software interrupts cannot be masked
and they cannot be disabled

Hardware interrupts
- Hardware interrupts are signals given to the processor, for recognition as an interrupt and execution
of the corresponding ISR.
- An external device, initiates the hardware interrupts of 8O85 by placing an appropriate signal at the
interrupt pin of the processor.
- The processor keeps on checking the interrupt pins at the second T -state of last machine cycle of
every instruction.
- If the processor finds a valid interrupt signal and if the interrupt is unmasked and enabled, then the
processor accepts the interrupt.
- The acceptance of the interrupt is acknowledged by sending an INTA signal to the interrupted
device.
- The processor saves the content of PC (program Counter) in stack and then loads the vector address
of the interrupt in PC. (If the interrupt is non-vectored, then the interrupting device has to supply
the address of ISR when it receives INTA signal).
- It starts executing ISR in this address. At the end of ISR, a return instruction, RET will be placed.
When the processor executes the RET instruction, it POP the content of top of stack to PC. Thus the
processor control returns to main program after servicing interrupt.
- The hardware interrupts of 8085 are TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.

b) Vectored and Non-Vectored Interrupts

- Vectored interrupts require the IVA to be supplied by the external device that gives the interrupt
signal. This technique is vectoring, is implemented in number of ways.
- The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts.
- Non-vectored interrupts have fixed IVA for ISRs of different interrupt signals.The INTR is a non-
vectored interrupt. Hence when a device interrupts through INTR, it has to supply the address of ISR
after receiving interrupt acknowledge signal.

c) Maskable and Non-Maskable Interrupts

The hardware vectored interrupts are classified into maskable and non-maskable interrupts
- Maskable interrupts are interrupts that can be blocked. Masking can be done by software or
hardware means. RST 7.5, RST 6.5 and RST 5.5 are maskable interrupt.
- Non-maskable interrupts are interrupts that are always recognized; the corresponding ISRs are
executed.TRAP is non-maskable interrupt.

- Masking is preventing the interrupt from disturbing the main program. When an interrupt is masked
the processor will not accept the interrupt signal.
- The interrupts can be masked by moving an appropriate data (or code) to accumulator and then
executing SIM instruction. (SIM - Set Interrupt Mask).
- SIM Instruction: The SIM instruction is used to mask or unmask RST hardware interrupts. When
executed, the SIM instruction reads the content of accumulator and accordingly mask or unmask the
interrupts.
- The status of maskable interrupts can be read into accumulator by executing RIM instruction (RIM -
Read Interrupt Mask).
- RIM Instruction: RIM instruction is used to read the status of the interrupt mask bits. When RIM
instruction is executed, the accumulator is loaded with the current status of the interrupt masks and
the pending interrupts.
- All the hardware interrupts, except TRAP are disabled, when the processor is resetted. They can also
be disabled by executing Dl instruction. (Dl-Disable Interrupt).
- When an interrupt is disabled, it will not be accepted by the processor. (i.e., INTR, RST 5.5, RST 6.5
and RST 7.5 are disabled by DI instruction and upon hardware reset).
- To enable (to allow) the disabled interrupt, the processor has to execute El instruction(El-Enable
Interrupt).

Interrupt Handling Procedure:

- The following sequence of operations takes place when an interrupt signal is recognized:
a. Save the PC content and information about current state (flags, registers etc) in the
stack.
b. Load PC with the beginning address of an ISR and start to execute it.
c. Finish ISR when the return instruction is executed.
d. Return to the point in the interrupted program where execution was interru