MASMReference

CSCI 240 - Assembly Language Programming - MASM & Intel Docs
Microsoft MASM 6.1 Reference Guide

Title Page Copyright Page Table of Contents Introduction Ch. 1 - Tools Ch. 2 - Directives Ch. 3 - Symbols and Operators Ch. 4 - Processor Ch. 5 - Coprocessor Ch. 6 - Macros Ch. 7 - Tables
file:///D|/Kip/AsmBookRelated/MASM_Manuals_PDF/ReferenceGuide.htm [9/8/2002 11:24:03 AM]
Reference
Microsoft MASM
Assembly-Language Development System Version 6.1 For MS-DOS and Windows Operating System
Microsoft Corporation
Filename: LMARFTTL.DOC Project: Template: FRONTA1.DOT Author: Launi Lockard Last Saved By: Mike Eddy Revision #: 4 Page: 1 of 1 Printed: 10/02/00 04:17 PM
Information in this document is subject to change without notice. Companies, names, and data used in examples herein are fictitious unless otherwise noted. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of Microsoft Corporation.
1987, 1991, 1992 Microsoft Corporation. All rights reserved.
Microsoft, MS, MS-DOS, XENIX, CodeView, and QuickC are registered trademarks and Windows and Windows NT are trademarks of Microsoft Corporation in the USA and other countries. U.S. Patent No. 4955066 IBM is a registered trademark of International Business Machines Corporation. Intel is a registered trademark and 386, 387, 486 are trademarks of Intel Corporation. Timings and encodings in this manual are used with permission of Intel and come from the following publications: Intel Corporation, iAPX 86, 88, 186, and 188 Users Manual, Programmers Reference. Santa Clara, Calif. 1985. Intel Corporation, iAPX 286 Programmers Reference Manual including the iAPX 286 Numeric Supplement. Santa Clara, Calif. 1985. Intel Corporation. 80386 Programmers Reference Manual. Santa Clara, Calif. 1986. Intel Corporation. 80387 80-bit CHMOS III Numeric Processor Extension. Santa Clara, Calif. 1987. Intel Corporation. i486 Microprocessor Data Sheet. Santa Clara, Calif. 1989.
Document No. DB35749-1292 Printed in the United States of America.
Filename: LMARFCPY.DOC Project: Template: FRONTA1.DOT Author: Launi Lockard Last Saved By: Launi Lockard Revision #: 3 Page: 2 of 1 Printed: 10/02/00 04:16 PM
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Introduction
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Document Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x Chapter 1 Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Microsoft CodeView Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 CVPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 EXEHDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 EXP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 HELPMAKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 H2INC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 IMPLIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 LIB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 LINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 MASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 NMAKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PWB (Programmers WorkBench) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PWBRMAKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 QuickHelp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 RM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 UNDEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Chapter 2 Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Topical Cross-reference for Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Chapter 3 Symbols and Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Topical Cross-reference for Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Topical Cross-reference for Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Predefined Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Run-Time Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 4 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Topical Cross-reference for Processor Instructions . . . . . . . . . . . . . . . . . . . . . . . . Interpreting Processor Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 40 41 43 44 48 49 50 53 53
Filename: LMARFTOC.DOC Project: Template: FRONTA1.DOT Author: Launi Lockard Last Saved By: Launi Lockard Revision #: 4 Page: 3 of 1 Printed: 10/02/00 04:13 PM
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Clock Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timings on the 8088 and 8086 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . Timings on the 8028680486 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . Interpreting Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interpreting 80386/486 Encoding Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-Bit Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-Bit Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address-Size Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operand-Size Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Encoding Differences for 32-Bit Operations . . . . . . . . . . . . . . . . . . . . . . . . Scaled Index Base Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AAA ASCII Adjust After Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AAD ASCII Adjust Before Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AAM ASCII Adjust After Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AAS ASCII Adjust After Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Add With Carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD Add. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AND Logical AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ARPL Adjust Requested Privilege Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BOUND Check Array Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BSF/BSR Bit Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BSWAP Byte Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BT/BTC/BTR/BTS Bit Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CALL Call Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CBW Convert Byte to Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDQ Convert Double to Quad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLC Clear Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLD Clear Direction Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLI Clear Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLTS Clear Task Switched Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMC Complement Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMP Compare Two Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMPS/CMPSB/CMPSW/CMPSD Compare String . . . . . . . . . . . . . . . . . . . . . CMPXCHG Compare and Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CWD Convert Word to Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CWDE Convert Word to Extended Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAA Decimal Adjust After Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAS Decimal Adjust After Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DEC Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54 55 56 56 59 60 60 60 60 60 61 64 64 64 65 65 66 67 68 69 69 70 71 72 73 74 75 75 76 76 76 77 77 79 80 80 81 81 82 82
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DIV Unsigned Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ENTER Make Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 HLT Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 IDIV Signed Divide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 IMUL Signed Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 IN Input from Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 INC Increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 INS/INSB/INSW/INSD Input from Port to String. . . . . . . . . . . . . . . . . . . . . . . 89 INT Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 INTO Interrupt on Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 INVD Invalidate Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 INVLPG Invalidate TLB Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 IRET/IRETD Interrupt Return. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Jcondition Jump Conditionally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 JCXZ/JECXZ Jump if CX is Zero. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 JMP Jump Unconditionally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 LAHF Load Flags into AH Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 LAR Load Access Rights. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 LDS/LES/LFS/LGS/LSS Load Far Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 LEA Load Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 LEAVE High Level Procedure Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 LES/LFS/LGS Load Far Pointer to Extra Segment . . . . . . . . . . . . . . . . . . . . . . 99 LGDT/LIDT/LLDT Load Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 LMSW Load Machine Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 LOCK Lock the Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 LODS/LODSB/LODSW/LODSD Load Accumulator from String . . . . . . . 101 LOOP/LOOPW/LOOPD Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 LOOPcondition/LOOPconditionW/LOOPconditionD Loop Conditionally . 102 LSL Load Segment Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 LSS Load Far Pointer to Stack Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 LTR Load Task Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 MOV Move Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 MOV Move to/from Special Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 MOVS/MOVSB/MOVSW/MOVSD Move String Data . . . . . . . . . . . . . . . . . 108 MOVSX Move with Sign-Extend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 MOVZX Move with Zero-Extend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 MUL Unsigned Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 NEG Twos Complement Negation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 NOP No Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 NOT Ones Complement Negation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
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OR Inclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUT Output to Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUTS/OUTSB/OUTSW/OUTSD Output String to Port . . . . . . . . . . . . . . . . POP Pop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POPA/POPAD Pop All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POPF/POPFD Pop Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PUSH/PUSHW/PUSHD Push . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PUSHA/PUSHAD Push All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PUSHF/PUSHFD Push Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RCL/RCR/ROL/ROR Rotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REP Repeat String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPcondition Repeat String Conditionally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RET/RETN/RETF Return from Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROL/ROR Rotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAHF Store AH into Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAL/SAR Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SBB Subtract with Borrow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCAS/SCASB/SCASW/SCASD Scan String Flags . . . . . . . . . . . . . . . . . . . . . SETcondition Set Conditionally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SGDT/SIDT/SLDT Store Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . SHL/SHR/SAL/SAR Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SHLD/SHRD Double Precision Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMSW Store Machine Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STC Set Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STD Set Direction Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STI Set Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOS/STOSB/STOSW/STOSD Store String Data . . . . . . . . . . . . . . . . . . . . . STR Store Task Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUB Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST Logical Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VERR/VERW Verify Read or Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WAIT Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WBINVD Write Back and Invalidate Data Cache . . . . . . . . . . . . . . . . . . . . . . XADD Exchange and Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XCHG Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XLAT/XLATB Translate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOR Exclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
112 113 113 114 115 116 116 117 118 118 120 122 123 124 124 125 125 126 127 128 129 131 133 134 134 134 135 136 136 137 138 139 140 140 141 141 142
Chapter 5 Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Topical Cross-reference for Coprocessor Instructions . . . . . . . . . . . . . . . . . . . . . 146
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Interpreting Coprocessor Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 F2XM1 2X1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 FABS Absolute Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 FADD/FADDP/FIADD Add. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 FBLD Load BCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 FBSTP Store BCD and Pop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 FCHS Change Sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 FCLEX/FNCLEX Clear Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 FCOM/FCOMP/FCOMPP/FICOM/FICOMP Compare . . . . . . . . . . . . . . . . 152 FCOS Cosine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 FDECSTP Decrement Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 FDISI/FNDISI Disable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 FDIV/FDIVP/FIDIV Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 FDIVR/FDIVRP/FIDIVR Divide Reversed. . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 FENI/FNENI Enable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 FFREE Free Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 FIADD/FISUB/FISUBR/FIMUL/FIDIV/FIDIVR Integer Arithmetic . . . . . 157 FICOM/FICOMP Compare Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 FILD Load Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 FINCSTP Increment Stack Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 FINIT/FNINIT Initialize Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 FIST/FISTP Store Integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 FLD/FILD/FBLD Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 FLD1/FLDZ/FLDPI/FLDL2E/FLDL2T/FLDLG2/FLDLN2 Load Constant159 FLDCW Load Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 FLDENV/FLDENVW/FLDENVD Load Environment State . . . . . . . . . . . . 161 FMUL/FMULP/FIMUL Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 FNinstruction No-Wait Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 FNOP No Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 FPATAN Partial Arctangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 FPREM Partial Remainder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 FPREM1 Partial Remainder (IEEE Compatible) . . . . . . . . . . . . . . . . . . . . . . . 164 FPTAN Partial Tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 FRNDINT Round to Integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 FRSTOR/FRSTORW/FRSTORD Restore Saved State . . . . . . . . . . . . . . . . . 166 FSAVE/FSAVEW/FSAVED/FNSAVE/FNSAVEW/FNSAVED Save Coprocessor State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 FSCALE Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 FSETPM Set Protected Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 FSIN Sine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
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Contents
FSINCOS Sine and Cosine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSQRT Square Root . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FST/FSTP/FIST/FISTP/FBSTP Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSTCW/FNSTCW Store Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSTENV/FSTENVW/FSTENVD/FNSTENV/FNSTENVW/FNSTENVD Store Environment State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSTSW/FNSTSW Store Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSUB/FSUBP/FISUB Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSUBR/FSUBRP/FISUBR Subtract Reversed . . . . . . . . . . . . . . . . . . . . . . . . . FTST Test for Zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FUCOM/FUCOMP/FUCOMPP Unordered Compare . . . . . . . . . . . . . . . . . . FWAIT Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FXAM Examine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FXCH Exchange Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FXTRACT Extract Exponent and Significand . . . . . . . . . . . . . . . . . . . . . . . . . . FYL2X Y log2(X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FYL2XP1 Y log2(X+1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 6 Macros. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIOS.INC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMACROS.INC, CMACROS.NEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MS-DOS.INC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MACROS.INC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROLOGUE.INC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WIN.INC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 7 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASCII Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MS-DOS Program Segment Prefix (PSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Color Display Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hexadecimal-Binary-Decimal Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
168 169 169 170 170 171 171 172 173 173 174 175 176 176 176 177 179 180 180 180 183 184 185 185 187 188 190 192 193 194
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Introduction
This Microsoft Macro Assembler Reference lists all MASM instructions, directives, statements, and operators. It also serves as a quick reference to the Programmers WorkBench commands, and the commands for Microsoft utilities such as LINK and LIB. This book documents features of MASM version 6.1, and is part of a complete MASM documentation set. Other titles in the set are: Getting Started Explains how to perform all the tasks necessary to install and begin running MASM 6.1 on your system. Environment and Tools Describes the development tools that are included with MASM 6.1: the Programmers WorkBench, CodeView debugger, LINK, EXEHDR, NMAKE, LIB, and other tools and utilities. A detailed tutorial on the Programmers WorkBench teaches the basics of creating and debugging MASM code in this full-featured programming environment. A complete list of utilities and error messages generated by ML is also included. Programmers Guide Provides information for experienced assemblylanguage programmers on the features of the MASM 6.1 language. The appendixes cover the differences between MASM 5.1, MASM 6.0, and MASM 6.1, and the Backus-Naur Form for grammar notation to use in determining the syntax for any MASM language component.
Filename: LMARFINT.DOC Template: MSGRIDA1.DOT Revision #: 16 Page: 9 of 2
Project: Author: Terri Sharkey Last Saved By: Launi Lockard Printed: 10/02/00 04:14 PM
Reference
Document Conventions
The following document conventions are used throughout this book:

Example SAMPLE 2ASM KEY TERMS Description Uppercase letters indicate filenames, segment names, registers and terms used at the command line. Bold type indicates text that must be typed exactly as shown. This includes assembly-language instructions, directives, symbols, operators, and keywords in other languages. Italics indicate variable information supplied by the user. This typeface indicates example programs, user input, and screen output. Double brackets indicate that the enclosed item is optional. Braces and a vertical bar indicate a choice between two or more items. You must choose one of the items unless double square brackets surround the braces. Three dots following an item indicate that you may type more items having the same form. Small capital letters indicate key names.
placeholders
Examples
[ [optional items] ] {choice1 | choice2}
Repeating elements...
SHIFT+F1
Filename: LMARFINT.DOC Project: Template: MSGRIDA1.DOT Author: Terri Sharkey Last Saved By: Launi Lockard Revision #: 16 Page: 10 of 2 Printed: 10/02/00 04:14 PM
C H A P T E R
Tools
CodeView. . . . CVPACK . . . . EXEHDR . . . . EXP . . . . . . . . HELPMAKE . H2INC . . . . . . IMPLIB . . . . . LIB . . . . . . . . LINK . . . . . . . MASM . . . . . . ML. . . . . . . . . NMAKE . . . . . PWB . . . . . . . PWBRMAKE . QuickHelp. . . . RM . . . . . . . . UNDEL . . . . .
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Filename: LMARFC01.DOC Project: MASM 6.1 Template: MSGRIDA1.DOT Author: Mike Eddy Last Saved By: Launi Lockard Revision #: 54 Page: 1 of 1 Printed: 10/02/00 04:13 PM
Reference
Microsoft CodeView Debugger

The Microsoft CodeView debugger runs the assembled or compiled program while simultaneously displaying the program source code, program variables, memory locations, processor registers, and other pertinent information. Syntax CV [[options]] executablefile [[arguments]] CVW [[options]] executablefile [[arguments]] Options
Option /2 /8 /25 /43 /50 /B /Ccommands /F /G /I[ | 1] [0 ] /Ldllfile /K /M /N[ | 1] [0 ] /R /S /TSF Action Permits the use of two monitors. Uses 8514/a as Windows display, and VGA as debugger display (CVW only). Starts in 25-line mode. Starts in 43-line mode. Starts in 50-line mode. Starts in black-and-white mode. Executes commands on startup. Exchanges screens by flipping between video pages (CV only). Eliminates refresh snow on CGA monitors. Turns nonmaskable-interrupt and 8259-interrupt trapping on ( / I1) or off ( / I0). Loads DLL dllfile for debugging (CVW only). Disables installation of keyboard monitors for the program being debugged (CV only). Disables CodeView use of the mouse. Use this option when debugging an application that supports the mouse. /N0 tells CodeView to trap nonmaskable interrupts; /N1 tells it not to trap. Enables 80386/486 debug registers (CV only). Exchanges screens by changing buffers (primarily for use with graphics programs) (CV only). Toggles TOOLS.INI entry to read/not read the CURRENT.STS file. Description Specifies path of help files or list of help filenames. Specifies path for TOOLS.INI and CURRENT.STS files.
Environment Variables
Variable HELPFILES INIT
Error! Style not defined.
CVPACK
The CVPACK utility reduces the size of an executable file that contains CodeView debugging information. Syntax Options CVPACK [[options]] exefile
Option /HELP /P /? Action Calls QuickHelp for help on CVPACK. Packs the file to the smallest possible size. Displays a summary of CVPACK command-line syntax.
EXEHDR
The EXEHDR utility displays and modifies the contents of an executable-file header. S yntax Options EXEHDR [[options]] filenames
Option /HEA:number /HEL /MA:number /MI:number /NE /NO /PM:type Action Option name: /HEA[ ]. Sets the heap allocation field to [P] number bytes for segmented-executable files. Option name: /HEL[ ]. Calls QuickHelp for help on [P] EXEHDR. Option name: /MA[ ]. Sets the maximum memory allocation [X] to number paragraphs for DOS executable files. Option name: /MI[ ]. Sets the minimum memory allocation to [N] number paragraphs for DOS executable files. Option name: /NE[ [WFILES] Enables support for HPFS. ]. Option name: /NO[ [LOGO] Suppresses the EXEHDR ]. copyright message. Option name: /PM[ [TYPE] Sets the application type for ]. Microsoft Windows, where type is one of the following: PM (or WINDOWAPI), VIO (or WINDOWCOMPAT), or NOVIO (or NOTWINDOWCOMPAT). Option name: /R[ [ESETERROR] Clears the error bit in the ]. header of a Windows executable file. Option name: /S[ [TACK] Sets the stack allocation to number ]. bytes.
/R /S:number
EXP Option /V Action Option name: /V[ [ERBOSE] Provides more information ]. about segmented-executable files, including the default flags in the segment table, all run-time relocations, and additional fields from the header. Option name: /?. Displays a summary of EXEHDR commandline syntax.
/?
EXP
The EXP utility deletes all files in the hidden DELETED subdirectory of the current or specified directory. EXP is used with RM and UNDEL to manage backup files. Syntax Options EXP [[options]] [[directories]]
Option /HELP /Q /R /? Action Calls QuickHelp for help on EXP. Suppresses display of deleted files. Recurses into subdirectories of the current or specified directory. Displays a summary of EXP command-line syntax.
HELPMAKE
The HELPMAKE utility creates help files and customizes the help files supplied with Microsoft language products. Syntax Options HELPMAKE {/ E[[n]] | / D[[c]] | / H | /?} [[options]] sourcefiles
Option /Ac Action Specifies c as an application-specific control character for the help database, marking a line that contains special information for internal use by the application. Indicates that the context strings are case sensitive so that at run time all searches for help topics are case sensitive. Fully decodes the help database.
/C /D
Error! Style not defined. Option /DS Action Splits the concatenated, compressed help database into its components, using their original names. No decompression occurs. Decompresses the database and removes all screen formatting and cross-references.
/DU /E[ ] [n]
Creates (encodes) a help database from a specified text file (or files). The optional n indicates the amount of compression to take place. The value of n can range from 0 to 15. Calls the QuickHelp utility. If HELPMAKE cannot find QuickHelp or the help file, it displays a summary of HELPMAKE command-line syntax. Specifies a file containing word-separator characters. This file must contain a single line of characters that separate words. ASCII characters from 0 to 32 (including the space) and character 127 are always separators. If the /K option is not specified, the following characters are also considered separators: !#&( )*+-,/:;<=>?@[\]^_`{\}~ Locks the generated file so that it cannot be decoded by HELPMAKE at a later time. Suppresses the HELPMAKE copyright message. Specifies outfile as the name of the help database. The name outfile is optional with the /D option. Specifies the type of input file, according to the following values for n: /S1 /S2 /S3 Rich Text Format QuickHelp Format Minimally Formatted ASCII
/H[ [ELP] ]
/Kfilename
/L /NOLOGO /Ooutfile /Sn
/T
During encoding, translates dot commands to applicationspecific commands. During decoding, translates application commands to dot commands. The /T option forces /A:. Sets the verbosity of the diagnostic and informational output, depending on the value of n. The value of n can range from 0 to 6. Sets the fixed width of the resulting help text in number of characters. The value of width can range from 11 to 255. Displays a summary of HELPMAKE command-line syntax.
/V[ ] [n]
/Wwidth /?
H2INC
H2INC
The H2INC utility converts C header (.H) files into MASM-compatible include (.INC) files. It translates declarations and prototypes, but does not translate code. Syntax Options H2INC [[options]] filename.H
Option* /C /Fa[ [filename] ] /Fc[ [filename] ] Action Passes comments in the .H file to the .INC file. Specifies that the output file contain only equivalent MASM statements. This is the default. Specifies that the output file contain equivalent MASM statements plus original C statements converted to comment lines. Calls QuickHelp for help on H2INC. Enables generation of text equates. By default, text items are not translated. Instructs H2INC to explicitly declare the distances for all pointers and functions. Suppresses the expansion of nested include files. Adds string to all names generated by H2INC. Used to eliminate name conflicts with other H2INC-generated include files. Makes all structure and union tag names unique. Displays a summary of H2INC command-line syntax.
/HELP /Ht /Mn /Ni /Zn string
/Zu /?
*H2INC also supports the following options from Microsoft C, version 6.0 and higher: /AC, /AH, /AL, /AM, /AS, /AT, / D, / F, / Fi, /G0, /G1, /G2, /G3, /G4, /Gc, /Gd, /Gr, / I, /J, / Tc, /U, /u, / W0, / W1, / W2, / W3, / W4, / X, / Za, / Zc, / Ze, / Zp1, / Zp2, / Zp4.
Variable CL H2INC INCLUDE
Description Specifies default command-line options. Specifies default command-line options. Appended after the CL environment variable. Specifies search path for include files.
IMPLIB
The IMPLIB utility creates import libraries used by LINK to link dynamic-link libraries with applications. Syntax Options IMPLIB [[options]] implibname {dllfile... | deffile...}
Option /H /NOI /NOL /? Action Option name: /H[ [ELP] Calls QuickHelp for help on ]. IMPLIB. Option name: /NOI[ [GNORECASE] Preserves case for ]. entry names in DLLs. Option name: /NOL[ [OGO] Suppresses the IMPLIB ]. copyright message. Option name: /?. Displays a summary of IMPLIB commandline syntax.
LIB
The LIB utility helps create, organize, and maintain run-time libraries. Syntax Options LIB inlibrary [[options]] [[commands]] [[, [[listfile]] [[, [[outlibrary]] ]] ]] [[;]]
Option /H /I Action Option name: /H[ [ELP] Calls QuickHelp for help on LIB. ]. Option name: /I[ [GNORECASE] Tells LIB to ignore case ]. when comparing symbols (the default). Use to combine a library marked /NOI with an unmarked library to create a new case-insensitive library. Option name: NOE[ [XTDICTIONARY] Prevents LIB from ]. creating an extended dictionary. Option name: /NOI[ [GNORECASE] Tells LIB to preserve ]. case when comparing symbols. When combining libraries, if any library is marked /NOI, the output library is case sensitive, unless /IGN is specified. Option name: /NOL[ [OGO] Suppresses the LIB copyright ]. message. Action Option name: /P[ [AGESIZE] Specifies the page size (in ]. bytes) of a new library or changes the page size of an existing library. The default for a new library is 16.
/NOE /NOI
/NOL Option /P:number
LINK /? Option name: /?. Displays a summary of LIB command-line syntax. Action Appends an object file or library file. Deletes a module. Replaces a module by deleting it and appending an object file with the same name. Copies a module to a new object file. Moves a module out of the library by copying it to a new object file and then deleting it.
Commands
Operator +name name +name *name *name
LINK
The LINK utility combines object files into a single executable file or dynamiclink library. Syntax Options LINK objfiles [[, [[exefile]] [[, [[mapfile]] [[, [[libraries]] [[, [[deffile]] ]] ]] ]] ]] [[;]]
Option /A:size Action Option name: /A[ [LIGNMENT] Directs LINK to align ]. segment data in a segmented-executable file along the boundaries specified by size bytes, where size must be a power of two. Option name: /B[ [ATCH] Suppresses prompts for library or ]. object files not found. Option name: /CO[ [DEVIEW] Adds symbolic data and line ]. numbers needed by the Microsoft CodeView debugger. This option is incompatible with the /EXEPACK option. Option name: /CP[ [ARMAXALLOC] Sets the programs ]. maximum memory allocation to number of 16-byte paragraphs. Option name: /DO[ [SSEG] Orders segments in the default ]. order used by Microsoft high-level languages.
/B /CO
/CP:number
/DO
Error! Style not defined. Option /DS Action Option name: /DS[ [ALLOCATE] Directs LINK to load all ]. data starting at the high end of the data segment. The /DSALLOC option is for assembly-language programs that create MS-DOS .EXE files.
/E
Option name: /E[ [XEPACK] Packs the executable file. The ]. /EXEPACK option is incompatible with /INCR and /CO. Do not use /EXEPACK on a Windows-based application. Option name: /F[ [ARCALLTRANSLATION] Optimizes far ]. calls. The /FARCALL option is automatically on when using /TINY. The /PACKC option is not recommended with /FARCALL when linking a Windows-based program. Option name: /HE[ ]. Calls QuickHelp for help on LINK. [LP] Option name: /HI[ [GH] Places the executable file as high in ]. memory as possible. Use /HIGH with the /DSALLOC option. This option is for assembly-language programs that create MSDOS .EXE files. Option name: /INC[ [REMENTAL] Prepares for incremental ]. linking with ILINK. This option is incompatible with /EXEPACK and /TINY. Option name: /INF[ [ORMATION] Displays to the standard ]. output the phase of linking and names of object files being linked. Option name: /LI[ [NENUMBERS] Adds source file line ]. numbers and associated addresses to the map file. The object file must be created with line numbers. This option creates a map file even if mapfile is not specified. Option name: /M[ ]. Adds public symbols to the map file. [AP] ]. Option name: /NOD[ [EFAULTLIBRARYSEARCH] Ignores the specified default library. Specify without libraryname to ignore all default libraries. Option name: /NOE[ [XTDICTIONARY] Prevents LINK ]. from searching extended dictionaries in libraries. Use /NOE when redefinition of a symbol causes error L2044. Option name: /NOF[ [ARCALLTRANSLATION] Turns off ]. far-call optimization. Option name: /NOI[ [GNORECASE] Preserves case in ]. identifiers. Option name: /NOL[ [OGO] Suppresses the LINK copyright ]. message.
/F
/HE /HI
/INC
/INF
/LI
/M /NOD[ [:libraryname] ]
/NOE
/NOF /NOI /NOL
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LINK Option /NON Action Option name: /NON[ [ULLSDOSSEG] Orders segments as ]. with the /DOSSEG option, but with no additional bytes at the beginning of the _TEXT segment (if defined). This option overrides /DOSSEG. Option name: /NOP[ [ACKCODE] Turns off code segment ]. packing. Option name: /PACKC[ [ODE] Packs neighboring code ]. segments together. Specify number bytes to set the maximum size for physical segments formed by /PACKC. Option name: /PACKD[ [ATA] Packs neighboring data ]. segments together. Specify number bytes to set the maximum size for physical segments formed by /PACKD. This option is for Windows only. Option name: /PAU[ ]. Pauses during the link session for [SE] disk changes. Option name: /PM[ [TYPE] Specifies the type of Windows]. based application where type is one of the following: PM (or WINDOWAPI), VIO (or WINDOWCOMPAT), or NOVIO (or NOTWINDOWCOMPAT). Option name: /ST[ [ACK] Sets the stack size to number ]. bytes, from 1 byte to 64K. Option name: /T[ [INY] Creates a tiny-model MS-DOS ]. program with a .COM extension instead of .EXE. Incompatible with /INCR. Option name: /?. Displays a summary of LINK command-line syntax.
/NOP /PACKC[ [:number] ]
/PACKD[ [:number] ]
/PAU /PM:type
/ST:number /T
/?
Note Several rarely used options not listed here are described in Help. Environment Variables
Variable INIT LIB LINK TMP Description Specifies path for the TOOLS.INI file. Specifies search path for library files. Specifies default command-line options. Specifies path for the VM.TMP file.
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MASM
The MASM program converts command-line options from MASM style to ML style, adds options to maximize compatibility, and calls ML.EXE. Note MASM.EXE is provided to maintain compatibility with old makefiles. For new makefiles, use the more powerful ML driver. Syntax Options MASM [[options]] sourcefile [[, [[objectfile]] [[, [[listingfile]] [[, [[crossreferencefile]] ]] ]] ]] [[;]]
Option /A /B /C /D /Dsymbol[ [=value] ] /E /H /HELP /I pathname /L /LA /ML /MU /MX /N /P /S /T /V Action Orders segments alphabetically. Results in a warning. Ignored. Sets internal buffer size. Ignored. Creates a cross-reference file. Translated to /FR. Creates a Pass 1 listing.Translated to F1/ST. Defines a symbol. Unchanged. Emulates floating-point instructions. Translated to /FPi. Lists command-line arguments. Translated to /help. Calls QuickHelp for help on the MASM driver. Specifies an include path. Unchanged. Creates a normal listing. Translated to /Fl. Lists all. Translated to /Fl and /Sa. Treats names as case sensitive. Translated to /Cp. Converts names to uppercase. Translated to /Cu. Preserves case on nonlocal names. Translated to /Cx. Suppresses table in listing file. Translated to /Sn. Checks for impure code. Use OPTION READONLY. Ignored. Orders segments sequentially. Results in a warning. Ignored. Enables terse assembly. Translated to /NOLOGO. Enables verbose assembly. Ignored.
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ML Option /Wlevel /X /Z /ZD /ZI Action Sets warning level, where level = 0, 1, or 2. Lists false conditionals. Translated to /Sx. Displays error lines on screen. Ignored. Generates line numbers for CodeView. Translated to /Zd. Generates symbols for CodeView. Translated to /Zi. Description Specifies default path for .INC files. Specifies default command-line options. Specifies path for temporary files.
Variable INCLUDE MASM TMP
ML
The ML program assembles and links one or more assembly-language source files. The command-line options are case sensitive. Syntax Options ML [[options]] filename [[ [[options]] filename]]... [[/ link linkoptions]]
Option /AT Action Enables tiny-memory-model support. Enables error messages for code constructs that violate the requirements for .COM format files. Note that this is not equivalent to the .MODEL TINY directive. Selects an alternate linker. Assembles only. Does not link. Preserves case of all user identifiers. Maps all identifiers to uppercase (default). Preserves case in public and extern symbols. Defines a text macro with the given name. If value is missing, it is blank. Multiple tokens separated by spaces must be enclosed in quotation marks. Generates a preprocessed source listing (sent to STDOUT). See /Sf. Sets stack size to hexnum bytes (this is the same as /link /STACK:number). The value must be expressed in hexadecimal notation. There must be a space between /F and hexnum.
/Bl filename /c /Cp /Cu /Cx /Dsymbol[ [=value] ]
/EP /Fhexnum
Error! Style not defined. Option /Fefilename /Fl[ [filename] ] /Fm[ [filename] ] /Fofilename /FPi /Fr[ [filename] ] /FR[ [filename] ] /Gc Action Names the executable file. Generates an assembled code listing. See /Sf. Creates a linker map file. Names an object file.
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Generates emulator fixups for floating-point arithmetic (mixedlanguage only). Generates a Source Browser .SBR file. Generates an extended form of a Source Browser .SBR file. Specifies use of FORTRAN- or Pascal-style function calling and naming conventions. Same as OPTION LANGUAGE:PASCAL. Specifies use of C-style function calling and naming conventions. Same as OPTION LANGUAGE:C. Restricts external names to number significant characters. The default is 31 characters. Calls QuickHelp for help on ML. Sets path for include file. A maximum of 10 /I options is allowed. Suppresses messages for successful assembly. Turns on listing of all available information. Adds instruction timings to listing file. Adds first-pass listing to listing file. Turns on listing of assembly-generated code. Sets the line width of source listing in characters per line. Range is 60 to 255 or 0. Default is 0. Same as PAGE width. Turns off symbol table when producing a listing. Sets the page length of source listing in lines per page. Range is 10 to 255 or 0. Default is 0. Same as PAGE length. Specifies text for source listing. Same as SUBTITLE text. Specifies title for source listing. Same as TITLE text. Turns on false conditionals in listing. Assembles source file whose name does not end with the .ASM extension. Same as /W0. Sets the warning level, where level = 0, 1, 2, or 3.
/Gd /H number /help /I pathname /nologo /Sa /Sc /Sf /Sg /Sl width /Sn /Sp length /Ss text /St text /Sx /Ta filename /w /Wlevel
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NMAKE Option /WX /Zd /Zf /Zi /Zm /Zp[ [alignment] ] /Zs /? Action Returns an error code if warnings are generated. Generates line-number information in object file. Makes all symbols public. Generates CodeView information in object file. Enables M510 option for maximum compatibility with MASM 5.1. Packs structures on the specified byte boundary. The alignment may be 1, 2, or 4. Performs a syntax check only. Displays a summary of ML command-line syntax.
QuickAssembler Support
For compatibility with QuickAssembler makefiles, ML recognizes these options:

Option /a Action Orders segments alphabetically in QuickAssembler. MASM 6.1 uses the .ALPHA directive for alphabetical ordering and ignores /a. Equivalent to /Cp. Prints the source for error lines to the screen. MASM 6.1 ignores this option. Performs one-pass assembly. MASM 6.1 ignores this option. Performs two-pass assembly. MASM 6.1 ignores this option. Orders segments sequentially. MASM 6.1 uses the .SEQ directive for sequential ordering and ignores /s. Equivalent to /Sl0 /Sp0. Description Specifies search path for include files. Specifies default command-line options. Specifies path for temporary files.
/Cl /Ez /P1 /P2 /s /Sq
Variable INCLUDE ML TMP
NMAKE
The NMAKE utility automates the process of compiling and linking project files. Syntax NMAKE [[options]] [[macros]] [[targets]]
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Options
Option /A /C /D /E /F filename
Action Executes all commands even if targets are not out-of-date. Suppresses the NMAKE copyright message and prevents nonfatal error or warning messages from being displayed. Displays the modification time of each file when the times of targets and dependents are checked. Causes environment variables to override macro definitions within description files. Specifies filename as the name of the description file to use. If a dash () is entered instead of a filename, NMAKE reads the description file from the standard input device. If /F is not specified, NMAKE uses MAKEFILE as the description file. If MAKEFILE does not exist, NMAKE builds command-line targets using inference rules. Calls QuickHelp for help on NMAKE. Ignores exit codes from commands in the description file. NMAKE continues executing the rest of the description file despite the errors. Displays but does not execute commands from the description file. Suppresses the NMAKE copyright message. Displays all macro definitions, inference rules, target descriptions, and the .SUFFIXES list. Checks modification times of command-line targets (or first target in the description file if no command-line targets are specified). NMAKE returns a zero exit code if all such targets are up-to-date and a nonzero exit code if any target is out-of-date. Only preprocessing commands in the description file are executed. Ignores inference rules and macros that are predefined or defined in the TOOLS.INI file. Suppresses display of commands as they are executed. Changes modification times of command-line targets (or first target in the description file if no command-line targets are specified) to the current time. Only preprocessing commands in the description file are executed. The contents of target files are not modified. Sends all error output to filename, which can be either a file or a device. If a dash () is entered instead of a filename, the error output is sent to the standard output device. Internal option for use by the Microsoft Programmers WorkBench (PWB). Displays a summary of NMAKE command-line syntax. Description Specifies path for TOOLS.INI file, which may contain macros, inference rules, and description blocks.
/HELP /I /N /NOLOGO /P /Q
/R /S /T
/X filename
/Z /?
Environment Variable
Variable INIT
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PWB (Programmers WorkBench)
PWB (Programmers WorkBench)

The Microsoft Programmers WorkBench (PWB) provides an integrated environment for developing programs in assembly language. The command-line options are case sensitive. Syntax Options PWB [[options]] [[files]]
Option /D[ [init] ] Action Prevents PWB from examining initialization files, where init is one or more of the following characters: A S T Disable autoload extensions (including languagespecific extensions and Help). Ignore CURRENT.STS. Ignore TOOLS.INI.
If the /D option does not include an init character, it is equivalent to specifying /DAST (all files and extensions ignored). /e cmdstr Executes the command or sequence of commands at start-up. The entire cmdstr argument must be placed in double quotation marks if it contains a space. If cmdstr contains literal double quotation marks, place a backslash ( \) in front of each double quotation mark. To include a literal backslash in the command string, use double backslashes ( \\). Moves the cursor to the specified mark instead of moving it to the last known position. The mark can be a line number. Specifies a program list for PWB to read, where init can be: Ffile L Pfile /r Read a foreign program list (one not created using PWB). Read the last program list. Use this option to start PWB in the same state you left it. Read a PWB program list.
/m mark /P[ [init] ]
Starts PWB in no-edit mode. Functions that modify files are disallowed.
Error! Style not defined. Option [ ] file... [/t] Action
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Loads the specified file at startup. The file specification can contain wildcards. If multiple files are specified, PWB loads only the first file. When the Exit function is invoked, PWB saves the current file and loads the next file in the list. Files specified with /t are temporary; PWB does not add them to the file history on the File menu. No other options can follow /t on the command line. Each temporary file must be specified in a separate /t option.
/?
Displays a summary of PWB command-line syntax. Description Specifies path of help files or list of help filenames. Specifies path for TOOLS.INI and CURRENT.STS files. Specifies path for temporary files.
Variable HELPFILES INIT TMP
PWBRMAKE
PWBRMAKE converts the .SBR files created by the assembler into database .BSC files that can be read by the Microsoft Programmers WorkBench (PWB) Source Browser. The command-line options are case sensitive. Syntax Options PWBRMAKE [[options]] sbrfiles
Option /Ei filename /Ei (filename...) /Em /Es Action Excludes the contents of the specified include files from the database. To specify multiple filenames, separate them with spaces and enclose the list in parentheses. Excludes symbols in the body of macros. Use /Em to include only macro names. Excludes from the database every include file specified with an absolute path or found in an absolute path specified in the INCLUDE environment variable. Calls QuickHelp for help on PWBRMAKE. Includes unreferenced symbols. Forces a nonincremental build and prevents truncation of .SBR files. Specifies a name for the database file. Displays verbose output. Displays a summary of PWBRMAKE command-line syntax.
/HELP /Iu /n /o filename /v /?
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QuickHelp
QuickHelp
The QuickHelp utility displays Help files. All MASM reserved words and error messages can be used for topic. Syntax Options QH [[options]] [[topic]]
Option /d filename /lnumber /mnumber /p filename /pa[ [filename] ] /q /r command Action Specifies either a specific database name or a path where the databases are found. Specifies the number of lines the QuickHelp window should occupy. Changes the screen mode to display the specified number of lines, where number is in the range 25 to 60. Sets the name of the paste file. Specifies that pasting operations are appended to the current paste file (rather than overwriting the file). Prevents the version box from being displayed when QuickHelp is installed as a keyboard monitor. Specifies the command that QuickHelp should execute when the right mouse button is pressed. The command can be one of the following letters: l i w b e t /s Display last topic Display history of help topics Hide window Display previous topic Find next topic Display contents
Specifies that clicking the mouse above or below the scroll box causes QuickHelp to scroll by lines rather than pages.
Error! Style not defined. Option /t name Action Directs QuickHelp to copy the specified section of the given topic to the current paste file and exit. The name may be: All Syntax Example Paste the entire topic Paste the syntax only Paste the example only
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If the topic is not found, QuickHelp returns an exit code of 1. /u Specifies that QuickHelp is being run by a utility. If the topic specified on the command line is not found, QuickHelp immediately exits with an exit code of 3. Description Specifies path of help files or list of help filenames. Specifies default command-line options. Specifies directory of default paste file.
Variable HELPFILES QH TMP
RM
The RM utility moves a file to a hidden DELETED subdirectory of the directory containing the file. Use the UNDEL utility to recover the file and the EXP utility to mark the hidden file for deletion. Syntax Options RM [[options]] [[files]]
Option /F /HELP /I /K /R directory /? Action Deletes read-only files without prompting. Calls QuickHelp for help on RM. Inquires for permission before removing each file. Keeps read-only files without prompting. Recurses into subdirectories of the specified directory. Displays a summary of RM command-line syntax.
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UNDEL
UNDEL
The UNDEL utility moves a file from a hidden DELETED subdirectory to the parent directory. UNDEL is used along with EXP and RM to manage backup files. Syntax Options UNDEL [[{option | files}]]
Option /HELP /? Action Calls QuickHelp for help on UNDEL. Displays a summary of UNDEL command-line syntax.
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C H A P T E R
Directives
Topical Cross-reference for Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Filename: LMARFC02.DOC Project: Template: MSGRIDA1.DOT Author: Mike Eddy Last Saved By: Launi Lockard Revision #: 24 Page: 21 of 1 Printed: 10/02/00 04:14 PM
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Reference
Topical Cross-reference for Directives

Code Labels
ALIGN LABEL EVEN ORG
Conditional Assembly
ELSE ENDIF IFB/IFNB IFE ELSEIF IF IFDEF/IFNDEF IFIDN/IFIDNI ELSEIF2 IF2 IFDIF/IFDIFI
Conditional Control Flow

.BREAK .ELSEIF .IF .UNTILCXZ .CONTINUE .ENDIF .REPEAT .WHILE .ELSE .ENDW .UNTIL/
Conditional Error
.ERR .ERRDEF .ERRIDN/.ERRIDNI .ERRNZ .ERR2 .ERRDIF/.ERRDIFI .ERRNB .ERRB .ERRE .ERRNDEF
Data Allocation
ALIGN EVEN ORG REAL8 WORD/SWORD BYTE/SBYTE FWORD QWORD REAL10 DWORD/SDWORD LABEL REAL4 TBYTE
Equates
= EQU TEXTEQU
Directives
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Listing Control
.CREF .LISTIF .NOCREF .NOLISTMACRO .TFCOND .LIST .LISTMACRO .NOLIST PAGE TITLE .LISTALL .LISTMACROALL .NOLISTIF SUBTITLE
Macros
ENDM LOCAL EXITM MACRO GOTO PURGE
Miscellaneous
ASSUME END OPTION .RADIX COMMENT INCLUDE POPCONTEXT ECHO INCLUDELIB PUSHCONTEXT
Procedures
ENDP PROTO INVOKE USES PROC
Processor
.186 .287 .387 .8086 .286 .386 .486 .8087 .286P .386P .486P .NO87
Repeat Blocks
ENDM GOTO FOR REPEAT FORC WHILE
Scope
COMM INCLUDELIB EXTERN PUBLIC EXTERNDEF
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Reference
Segment
.ALPHA END SEGMENT ASSUME ENDS .SEQ .DOSSEG GROUP
Simplified Segment
.CODE .DATA? .FARDATA .STACK .CONST .DOSSEG .FARDATA? .STARTUP .DATA .EXIT .MODEL
String
CATSTR SIZESTR INSTR SUBSTR
Structure and Record

ENDS TYPEDEF RECORD UNION STRUCT
Directives
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Directives
name = expression Assigns the numeric value of expression to name. The symbol may be redefined later. .186 Enables assembly of instructions for the 80186 processor; disables assembly of instructions introduced with later processors. Also enables 8087 instructions. .286 Enables assembly of nonprivileged instructions for the 80286 processor; disables assembly of instructions introduced with later processors. Also enables 80287 instructions. .286P Enables assembly of all instructions (including privileged) for the 80286 processor; disables assembly of instructions introduced with later processors. Also enables 80287 instructions. .287 Enables assembly of instructions for the 80287 coprocessor; disables assembly of instructions introduced with later coprocessors. .386 Enables assembly of nonprivileged instructions for the 80386 processor; disables assembly of instructions introduced with later processors. Also enables 80387 instructions. .386P Enables assembly of all instructions (including privileged) for the 80386 processor; disables assembly of instructions introduced with later processors. Also enables 80387 instructions. .387 Enables assembly of instructions for the 80387 coprocessor. .486 Enables assembly of nonprivileged instructions for the 80486 processor. .486P Enables assembly of all instructions (including privileged) for the 80486 processor. .8086 Enables assembly of 8086 instructions (and the identical 8088 instructions); disables assembly of instructions introduced with later processors. Also enables 8087 instructions. This is the default mode for processors.
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Reference
.8087 Enables assembly of 8087 instructions; disables assembly of instructions introduced with later coprocessors. This is the default mode for coprocessors. ALIGN [[number]] Aligns the next variable or instruction on a byte that is a multiple of number. .ALPHA Orders segments alphabetically. ASSUME segregister:name [[, segregister:name]]... ASSUME dataregister:type [[, dataregister:type]]... ASSUME register:ERROR [[, register:ERROR]]... ASSUME [[register:]] NOTHING [[, register:NOTHING]]... Enables error-checking for register values. After an ASSUME is put into effect, the assembler watches for changes to the values of the given registers. ERROR generates an error if the register is used. NOTHING removes register error-checking. You can combine different kinds of assumptions in one statement. .BREAK [[.IF condition]] Generates code to terminate a .WHILE or .REPEAT block if condition is true. [[name]] BYTE initializer [[, initializer]] ... Allocates and optionally initializes a byte of storage for each initializer. Can also be used as a type specifier anywhere a type is legal. name CATSTR [[textitem1 [[, textitem2]] ...]] Concatenates text items. Each text item can be a literal string, a constant preceded by a %, or the string returned by a macro function. .CODE [[name]] When used with .MODEL, indicates the start of a code segment called name (the default segment name is _TEXT for tiny, small, compact, and flat models, or module_TEXT for other models). COMM definition [[, definition]] ... Creates a communal variable with the attributes specified in definition. Each definition has the following form: [[langtype]] [[NEAR | FAR]] label:type[[:count]] The label is the name of the variable. The type can be any type specifier (BYTE, WORD, and so on) or an integer specifying the number of bytes. The count specifies the number of data objects (one is the default). COMMENT delimiter [[text]] [[text]] [[text]] delimiter [[text]] Treats all text between or on the same line as the delimiters as a comment.
Directives
27
.CONST When used with .MODEL, starts a constant data segment (with segment name CONST). This segment has the read-only attribute. .CONTINUE [[.IF condition]] Generates code to jump to the top of a .WHILE or .REPEAT block if condition is true. .CREF Enables listing of symbols in the symbol portion of the symbol table and browser file. .DATA When used with .MODEL, starts a near data segment for initialized data (segment name _DATA). .DATA? When used with .MODEL, starts a near data segment for uninitialized data (segment name _BSS). .DOSSEG Orders the segments according to the MS-DOS segment convention: CODE first, then segments not in DGROUP, and then segments in DGROUP. The segments in DGROUP follow this order: segments not in BSS or STACK, then BSS segments, and finally STACK segments. Primarily used for ensuring CodeView support in MASM stand-alone programs. Same as DOSSEG. DOSSEG Identical to .DOSSEG, which is the preferred form. DB Can be used to define data like BYTE. DD Can be used to define data like DWORD. DF Can be used to define data like FWORD. DQ Can be used to define data like QWORD. DT Can be used to define data like TBYTE. DW Can be used to define data like WORD. [[name]] DWORD initializer [[, initializer]]... Allocates and optionally initializes a doubleword (4 bytes) of storage for each initializer. Can also be used as a type specifier anywhere a type is legal.
28
Reference
ECHO message Displays message to the standard output device (by default, the screen). Same as %OUT. .ELSE See .IF. ELSE Marks the beginning of an alternate block within a conditional block. See IF. ELSEIF Combines ELSE and IF into one statement. See IF. ELSEIF2 ELSEIF block evaluated on every assembly pass if OPTION:SETIF2 is TRUE. END [[address]] Marks the end of a module and, optionally, sets the program entry point to address. .ENDIF See .IF. ENDIF See IF. ENDM Terminates a macro or repeat block. See MACRO, FOR, FORC, REPEAT, or WHILE. name ENDP Marks the end of procedure name previously begun with PROC. See PROC. name ENDS Marks the end of segment, structure, or union name previously begun with SEGMENT, STRUCT, UNION, or a simplified segment directive. .ENDW See .WHILE. name EQU expression Assigns numeric value of expression to name. The name cannot be redefined later. name EQU <text> Assigns specified text to name. The name can be assigned a different text later. See TEXTEQU. .ERR [[message]] Generates an error.
Directives
29
.ERR2 [[message]] .ERR block evaluated on every assembly pass if OPTION:SETIF2 is TRUE. .ERRB <textitem> [[, message]] Generates an error if textitem is blank. .ERRDEF name [[, message]] Generates an error if name is a previously defined label, variable, or symbol. .ERRDIF[[I]] <textitem1>, <textitem2> [[, message]] Generates an error if the text items are different. If I is given, the comparison is case insensitive. .ERRE expression [[, message]] Generates an error if expression is false (0). .ERRIDN[[I]] <textitem1>, <textitem2> [[, message]] Generates an error if the text items are identical. If I is given, the comparison is case insensitive. .ERRNB <textitem> [[, message]] Generates an error if textitem is not blank. .ERRNDEF name [[, message]] Generates an error if name has not been defined. .ERRNZ expression [[, message]] Generates an error if expression is true (nonzero). EVEN Aligns the next variable or instruction on an even byte. .EXIT [[expression]] Generates termination code. Returns optional expression to shell. EXITM [[textitem]] Terminates expansion of the current repeat or macro block and begins assembly of the next statement outside the block. In a macro function, textitem is the value returned. EXTERN [[langtype]] name [[(altid)]] :type [[, [[langtype]] name [[(altid)]] :type]]... Defines one or more external variables, labels, or symbols called name whose type is type. The type can be ABS, which imports name as a constant. Same as EXTRN. EXTERNDEF [[langtype]] name:type [[, [[langtype]] name:type]]... Defines one or more external variables, labels, or symbols called name whose type is type. If name is defined in the module, it is treated as PUBLIC. If name is referenced in the module, it is treated as EXTERN. If name is not referenced, it is ignored. The type can be ABS, which imports name as a constant. Normally used in include files.
30
Reference
EXTRN See EXTERN. .FARDATA [[name]] When used with .MODEL, starts a far data segment for initialized data (segment name FAR_DATA or name). .FARDATA? [[name]] When used with .MODEL, starts a far data segment for uninitialized data (segment name FAR_BSS or name). FOR parameter [[:REQ | :=default]] , <argument [[, argument]]...> statements ENDM Marks a block that will be repeated once for each argument, with the current argument replacing parameter on each repetition. Same as IRP. FORC parameter, <string> statements ENDM Marks a block that will be repeated once for each character in string, with the current character replacing parameter on each repetition. Same as IRPC. [[name]] FWORD initializer [[, initializer]]... Allocates and optionally initializes 6 bytes of storage for each initializer. Also can be used as a type specifier anywhere a type is legal. GOTO macrolabel Transfers assembly to the line marked :macrolabel. GOTO is permitted only inside MACRO, FOR, FORC, REPEAT, and WHILE blocks. The label must be the only directive on the line and must be preceded by a leading colon. name GROUP segment [[, segment]]... Add the specified segments to the group called name. .IF condition1 statements [[.ELSEIF condition2 statements]] [[.ELSE statements]] .ENDIF Generates code that tests condition1 (for example, AX > 7) and executes the statements if that condition is true. If an .ELSE follows, its statements are executed if the original condition was false. Note that the conditions are evaluated at run time.
Directives
31
IF expression1 ifstatements [[ELSEIF expression2 elseifstatements]] [[ELSE elsestatements]] ENDIF Grants assembly of ifstatements if expression1 is true (nonzero) or elseifstatements if expression1 is false (0) and expression2 is true. The following directives may be substituted for ELSEIF: ELSEIFB,
32
Reference
ELSEIFDEF, ELSEIFDIF, ELSEIFDIFI, ELSEIFE, ELSEIFIDN, ELSEIFIDNI, ELSEIFNB, and ELSEIFNDEF. Optionally, assembles elsestatements if the previous expression is false. Note that the expressions are evaluated at assembly time. IF2 expression IF block is evaluated on every assembly pass if OPTION:SETIF2 is TRUE. See IF for complete syntax. IFB textitem Grants assembly if textitem is blank. See IF for complete syntax. IFDEF name Grants assembly if name is a previously defined label, variable, or symbol. See IF for complete syntax. IFDIF[[I]] textitem1, textitem2 Grants assembly if the text items are different. If I is given, the comparison is case insensitive. See IF for complete syntax. IFE expression Grants assembly if expression is false (0). See IF for complete syntax. IFIDN[[I]] textitem1, textitem2 Grants assembly if the text items are identical. If I is given, the comparison is case insensitive. See IF for complete syntax. IFNB textitem Grants assembly if textitem is not blank. See IF for complete syntax. IFNDEF name Grants assembly if name has not been defined. See IF for complete syntax. INCLUDE filename Inserts source code from the source file given by filename into the current source file during assembly. The filename must be enclosed in angle brackets if it includes a backslash, semicolon, greater-than symbol, less-than symbol, single quotation mark, or double quotation mark. INCLUDELIB libraryname Informs the linker that the current module should be linked with libraryname. The libraryname must be enclosed in angle brackets if it includes a backslash, semicolon, greater-than symbol, less-than symbol, single quotation mark, or double quotation mark. name INSTR [[position,]] textitem1, textitem2 Finds the first occurrence of textitem2 in textitem1. The starting position is optional. Each text item can be a literal string, a constant preceded by a %, or the string returned by a macro function.
Directives
33
INVOKE expression [[, arguments]] Calls the procedure at the address given by expression, passing the arguments on the stack or in registers according to the standard calling conventions of the language type. Each argument passed to the procedure may be an expression, a register pair, or an address expression (an expression preceded by ADDR). IRP See FOR. IRPC See FORC. name LABEL type Creates a new label by assigning the current location-counter value and the given type to name. name LABEL [[NEAR | FAR | PROC]] PTR [[type]] Creates a new label by assigning the current location-counter value and the given type to name. .LALL See .LISTMACROALL. .LFCOND See .LISTIF. .LIST Starts listing of statements. This is the default. .LISTALL Starts listing of all statements. Equivalent to the combination of .LIST, .LISTIF, and .LISTMACROALL. .LISTIF Starts listing of statements in false conditional blocks. Same as .LFCOND. .LISTMACRO Starts listing of macro expansion statements that generate code or data. This is the default. Same as .XALL. .LISTMACROALL Starts listing of all statements in macros. Same as .LALL. LOCAL localname [[, localname]]... Within a macro, LOCAL defines labels that are unique to each instance of the macro. LOCAL label [[ [count ] ]] [[:type]] [[, label [[ [count] ]] [[type]]]]... Within a procedure definition (PROC), LOCAL creates stack-based variables that exist for the duration of the procedure. The label may be a simple variable or an array containing count elements.
34
Reference
name MACRO [[parameter [[:REQ | :=default | :VARARG]]]]... statements ENDM [[value]] Marks a macro block called name and establishes parameter placeholders for arguments passed when the macro is called. A macro function returns value to the calling statement. .MODEL memorymodel [[, langtype]] [[, stackoption]] Initializes the program memory model. The memorymodel can be TINY, SMALL, COMPACT, MEDIUM, LARGE, HUGE, or FLAT. The langtype can be C, BASIC, FORTRAN, PASCAL, SYSCALL, or STDCALL. The stackoption can be NEARSTACK or FARSTACK. NAME modulename Ignored. .NO87 Disallows assembly of all floating-point instructions. .NOCREF [[name[[, name]]...]] Suppresses listing of symbols in the symbol table and browser file. If names are specified, only the given names are suppressed. Same as .XCREF. .NOLIST Suppresses program listing. Same as .XLIST. .NOLISTIF Suppresses listing of conditional blocks whose condition evaluates to false (0). This is the default. Same as .SFCOND. .NOLISTMACRO Suppresses listing of macro expansions. Same as .SALL. OPTION optionlist Enables and disables features of the assembler. Available options include CASEMAP, DOTNAME, NODOTNAME, EMULATOR, NOEMULATOR, EPILOGUE, EXPR16, EXPR32, LANGUAGE, LJMP, NOLJMP, M510, NOM510, NOKEYWORD, NOSIGNEXTEND, OFFSET, OLDMACROS, NOOLDMACROS, OLDSTRUCTS, NOOLDSTRUCTS, PROC, PROLOGUE, READONLY, NOREADONLY, SCOPED, NOSCOPED, SEGMENT, and SETIF2. ORG expression Sets the location counter to expression. %OUT See ECHO. PAGE [[[[length]], width]] Sets line length and character width of the program listing. If no arguments are given, generates a page break.
Directives
35
PAGE + Increments the section number and resets the page number to 1. POPCONTEXT context Restores part or all of the current context (saved by the PUSHCONTEXT directive). The context can be ASSUMES, RADIX, LISTING, CPU, or ALL. label PROC [[distance]] [[langtype]] [[visibility]] [[<prologuearg>]] [[USES reglist]] [[, parameter [[:tag]]]]... statements label ENDP Marks start and end of a procedure block called label. The statements in the block can be called with the CALL instruction or INVOKE directive. label PROTO [[distance]] [[langtype]] [[, [[parameter]]:tag]]... Prototypes a function. PUBLIC [[langtype]] name [[, [[langtype]] name]]... Makes each variable, label, or absolute symbol specified as name available to all other modules in the program. PURGE macroname [[, macroname]]... Deletes the specified macros from memory. PUSHCONTEXT context Saves part or all of the current context: segment register assumes, radix value, listing and cref flags, or processor/coprocessor values. The context can be ASSUMES, RADIX, LISTING, CPU, or ALL. [[name]] QWORD initializer [[, initializer]]... Allocates and optionally initializes 8 bytes of storage for each initializer. Also can be used as a type specifier anywhere a type is legal. .RADIX expression Sets the default radix, in the range 2 to 16, to the value of expression. name REAL4 initializer [[, initializer]]... Allocates and optionally initializes a single-precision (4-byte) floating-point number for each initializer. name REAL8 initializer [[, initializer]]... Allocates and optionally initializes a double-precision (8-byte) floating-point number for each initializer. name REAL10 initializer [[, initializer]]... Allocates and optionally initializes a 10-byte floating-point number for each initializer.
36
Reference
recordname RECORD fieldname:width [[= expression]] [[, fieldname:width [[= expression]]]]... Declares a record type consisting of the specified fields. The fieldname names the field, width specifies the number of bits, and expression gives its initial value. .REPEAT statements .UNTIL condition Generates code that repeats execution of the block of statements until condition becomes true. .UNTILCXZ, which becomes true when CX is zero, may be substituted for .UNTIL. The condition is optional with .UNTILCXZ. REPEAT expression statements ENDM Marks a block that is to be repeated expression times. Same as REPT. REPT See REPEAT. .SALL See .NOLISTMACRO. name SBYTE initializer [[, initializer]]... Allocates and optionally initializes a signed byte of storage for each initializer. Can also be used as a type specifier anywhere a type is legal. name SDWORD initializer [[, initializer]]... Allocates and optionally initializes a signed doubleword (4 bytes) of storage for each initializer. Also can be used as a type specifier anywhere a type is legal. name SEGMENT [[READONLY]] [[align]] [[combine]] [[use]] [['class']] statements name ENDS Defines a program segment called name having segment attributes align (BYTE, WORD, DWORD, PARA, PAGE), combine (PUBLIC, STACK, COMMON, MEMORY, AT address, PRIVATE), use (USE16, USE32, FLAT), and class. .SEQ Orders segments sequentially (the default order). .SFCOND See .NOLISTIF. name SIZESTR textitem Finds the size of a text item.
Directives
37
.STACK [[size]] When used with .MODEL, defines a stack segment (with segment name STACK). The optional size specifies the number of bytes for the stack (default 1,024). The .STACK directive automatically closes the stack statement. .STARTUP Generates program start-up code. STRUC See STRUCT. name STRUCT [[alignment]] [[, NONUNIQUE]] fielddeclarations name ENDS Declares a structure type having the specified fielddeclarations. Each field must be a valid data definition. Same as STRUC. name SUBSTR textitem, position [[, length]] Returns a substring of textitem, starting at position. The textitem can be a literal string, a constant preceded by a %, or the string returned by a macro function. SUBTITLE text Defines the listing subtitle. Same as SUBTTL. SUBTTL See SUBTITLE. name SWORD initializer [[, initializer]]... Allocates and optionally initializes a signed word (2 bytes) of storage for each initializer. Can also be used as a type specifier anywhere a type is legal. [[name]] TBYTE initializer [[, initializer]]... Allocates and optionally initializes 10 bytes of storage for each initializer. Can also be used as a type specifier anywhere a type is legal. name TEXTEQU [[textitem]] Assigns textitem to name. The textitem can be a literal string, a constant preceded by a %, or the string returned by a macro function. .TFCOND Toggles listing of false conditional blocks. TITLE text Defines the program listing title. name TYPEDEF type Defines a new type called name, which is equivalent to type.
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Reference
name UNION [[alignment]] [[, NONUNIQUE]] fielddeclarations [[name]] ENDS Declares a union of one or more data types. The fielddeclarations must be valid data definitions. Omit the ENDS name label on nested UNION definitions. .UNTIL See .REPEAT. .UNTILCXZ See .REPEAT. .WHILE condition statements .ENDW Generates code that executes the block of statements while condition remains true. WHILE expression statements ENDM Repeats assembly of block statements as long as expression remains true. [[name]] WORD initializer [[, initializer]]... Allocates and optionally initializes a word (2 bytes) of storage for each initializer. Can also be used as a type specifier anywhere a type is legal. .XALL See .LISTMACRO. .XCREF See .NOCREF. .XLIST See .NOLIST.
Directives
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C H A P T E R
Symbols and Operators
Topical Cross-reference for Symbols . . Topical Cross-reference for Operators . Predefined Symbols . . . . . . . . . . . . . . Operators . . . . . . . . . . . . . . . . . . . . . Run-Time Operators . . . . . . . . . . . . .
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Reference
Topical Cross-reference for Symbols

Date and Time Information
@Date @Time
Environment Information
@Cpu @Environ @Interface @Version
File Information
@FileCur @FileName @Line
Macro Functions
@CatStr @InStr @SizeStr @SubStr
Miscellaneous
$ @B ? @F @@:
Segment Information
@code @data @fardata? @WordSize @CodeSize @DataSize @Model @CurSeg @fardata @stack
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Topical Cross-reference for Operators

Arithmetic
* . MOD + / []
Control Flow
! && == || != < > & <= >=
Logical and Shift

AND SHL NOT SHR OR XOR
Macro
! ;; % <> &
Miscellaneous
:: DUP SIGN? ; OVERFLOW? ZERO? : CARRY? PARITY?
Record
MASK WIDTH
Relational
EQ LE GE LT GT NE
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Reference
Segment
: LROFFSET OFFSET SEG
Type
HIGH LENGTHOF OPATTR SIZE TYPE HIGHWORD LOW PTR SIZEOF LENGTH LOWWORD SHORT THIS
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Predefined Symbols
$ The current value of the location counter. ? In data declarations, a value that the assembler allocates but does not initialize. @@: Defines a code label recognizable only between label1 and label2, where label1 is either start of code or the previous @@: label, and label2 is either end of code or the next @@: label. See @B and @F. @B The location of the previous @@: label. @CatStr( string1 [[, string2...]] ) Macro function that concatenates one or more strings. Returns a string. @code The name of the code segment (text macro). @CodeSize 0 for TINY, SMALL, COMPACT, and FLAT models, and 1 for MEDIUM, LARGE, and HUGE models (numeric equate). @Cpu A bit mask specifying the processor mode (numeric equate). @CurSeg The name of the current segment (text macro). @data The name of the default data group. Evaluates to DGROUP for all models except FLAT. Evaluates to FLAT under the FLAT memory model (text macro). @DataSize 0 for TINY, SMALL, MEDIUM, and FLAT models, 1 for COMPACT and LARGE models, and 2 for HUGE model (numeric equate). @Date The system date in the format mm/dd/yy (text macro). @Environ( envvar ) Value of environment variable envvar (macro function). @F The location of the next @@: label. @fardata The name of the segment defined by the .FARDATA directive (text macro).
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Reference
@fardata? The name of the segment defined by the .FARDATA? directive (text macro). @FileCur The name of the current file (text macro). @FileName The base name of the main file being assembled (text macro). @InStr( [[position]], string1, string2 ) Macro function that finds the first occurrence of string2 in string1, beginning at position within string1. If position does not appear, search begins at start of string1. Returns a position integer or 0 if string2 is not found. @Interface Information about the language parameters (numeric equate). @Line The source line number in the current file (numeric equate). @Model 1 for TINY model, 2 for SMALL model, 3 for COMPACT model, 4 for MEDIUM model, 5 for LARGE model, 6 for HUGE model, and 7 for FLAT model (numeric equate). @SizeStr( string ) Macro function that returns the length of the given string. Returns an integer. @SubStr( string, position [[, length]] ) Macro function that returns a substring starting at position. @stack DGROUP for near stacks or STACK for far stacks (text macro). @Time The system time in 24-hour hh:mm:ss format (text macro). @Version 610 in MASM 6.1 (text macro). @WordSize Two for a 16-bit segment or 4 for a 32-bit segment (numeric equate).
Operators
expression1 + expression2 Returns expression1 plus expression2. expression1 expression2 Returns expression1 minus expression2. expression1 * expression2 Returns expression1 times expression2.
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expression1 / expression2 Returns expression1 divided by expression2. expression Reverses the sign of expression. expression1 [expression2] Returns expression1 plus [expression2]. segment: expression Overrides the default segment of expression with segment. The segment can be a segment register, group name, segment name, or segment expression. The expression must be a constant. expression. field [[. field]]... Returns expression plus the offset of field within its structure or union. [register]. field [[. field]]... Returns value at the location pointed to by register plus the offset of field within its structure or union. <text> Treats text as a single literal element. text Treats text as a string. text Treats text as a string. !character Treats character as a literal character rather than as an operator or symbol. ;text Treats text as a comment. ;;text Treats text as a comment in a macro that appears only in the macro definition. The listing does not show text where the macro is expanded. %expression Treats the value of expression in a macro argument as text. &parameter& Replaces parameter with its corresponding argument value. ABS See the EXTERNDEF directive. ADDR See the INVOKE directive. expression1 AND expression2 Returns the result of a bitwise AND operation for expression1 and expression2.
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Reference
count DUP (initialvalue [[, initialvalue]]...) Specifies count number of declarations of initialvalue. expression1 EQ expression2 Returns true (1) if expression1 equals expression2, or returns false (0) if it does not. expression1 GE expression2 Returns true (1) if expression1 is greater-than-or-equal-to expression2, or returns false (0) if it is not. expression1 GT expression2 Returns true (1) if expression1 is greater than expression2, or returns false (0) if it is not. HIGH expression Returns the high byte of expression. HIGHWORD expression Returns the high word of expression. expression1 LE expression2 Returns true (1) if expression1 is less than or equal to expression2, or returns false (0) if it is not. LENGTH variable Returns the number of data items in variable created by the first initializer. LENGTHOF variable Returns the number of data objects in variable. LOW expression Returns the low byte of expression. LOWWORD expression Returns the low word of expression. LROFFSET expression Returns the offset of expression. Same as OFFSET, but it generates a loader resolved offset, which allows Windows to relocate code segments. expression1 LT expression2 Returns true (1) if expression1 is less than expression2, or returns false (0) if it is not. MASK {recordfieldname | record} Returns a bit mask in which the bits in recordfieldname or record are set and all other bits are cleared. expression1 MOD expression2 Returns the integer value of the remainder (modulo) when dividing expression1 by expression2.
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expression1 NE expression2 Returns true (1) if expression1 does not equal expression2, or returns false (0) if it does. NOT expression Returns expression with all bits reversed. OFFSET expression Returns the offset of expression. OPATTR expression Returns a word defining the mode and scope of expression. The low byte is identical to the byte returned by .TYPE. The high byte contains additional information. expression1 OR expression2 Returns the result of a bitwise OR operation for expression1 and expression2. type PTR expression Forces the expression to be treated as having the specified type. [[distance]] PTR type Specifies a pointer to type. SEG expression Returns the segment of expression. expression SHL count Returns the result of shifting the bits of expression left count number of bits. SHORT label Sets the type of label to short. All jumps to label must be short (within the range 128 to +127 bytes from the jump instruction to label). expression SHR count Returns the result of shifting the bits of expression right count number of bits. SIZE variable Returns the number of bytes in variable allocated by the first initializer. SIZEOF {variable | type} Returns the number of bytes in variable or type. THIS type Returns an operand of specified type whose offset and segment values are equal to the current location-counter value. .TYPE expression See OPATTR. TYPE expression Returns the type of expression.
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Reference
WIDTH {recordfieldname | record} Returns the width in bits of the current recordfieldname or record. expression1 XOR expression2 Returns the result of a bitwise XOR operation for expression1 and expression2.
Run-Time Operators
The following operators are used only within .IF, .WHILE, or .REPEAT blocks and are evaluated at run time, not at assembly time: expression1 == expression2 Is equal to. expression1 != expression2 Is not equal to. expression1 > expression2 Is greater than. expression1 >= expression2 Is greater than or equal to. expression1 < expression2 Is less than. expression1 <= expression2 Is less than or equal to. expression1 || expression2 Logical OR. expression1 && expression2 Logical AND. expression1 & expression2 Bitwise AND. !expression Logical negation. CARRY? Status of carry flag. OVERFLOW? Status of overflow flag. PARITY? Status of parity flag. SIGN? Status of sign flag. ZERO? Status of zero flag.
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C H A P T E R
Processor
Topical Cross-reference for Processor Instructions . Interpreting Processor Instructions . . . . . . . . . . . . Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Speeds . . . . . . . . . . . . . . . . . . . . . . . . . Timings on the 8088 and 8086 Processors . . Timings on the 80286-80486 Processors . . . Interpreting Encodings . . . . . . . . . . . . . . . . . . . . . Interpreting 8038680486 Encoding Extensions . . . 16-bit Encoding. . . . . . . . . . . . . . . . . . . . . . . . 32-bit Encoding. . . . . . . . . . . . . . . . . . . . . . . . Address-Size Prefix . . . . . . . . . . . . . . . . . . Operand-Size Prefix . . . . . . . . . . . . . . . . . . Encoding Differences for 32-Bit Operations . Scaled Index Base Byte . . . . . . . . . . . . . . . Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Filename: LMARFC04.DOC Project: Template: MSGRIDA1.DOT Author: Mike Eddy Last Saved By: Mike Eddy Revision #: 67 Page: 49 of 1 Printed: 10/02/00 04:15 PM
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Reference
Topical Cross-reference for Processor Instructions

Arithmetic
ADC DIV INC SBB ADD IDIV MUL SUB DEC IMUL NEG XADD#
BCD Conversion
AAA AAS AAD DAA AAM DAS
Bit Operations
AND BT BTS RCL ROR SHLD XOR BSF BTC NOT RCR SAR SHR BSR BTR OR ROL SHL/SAL SHRD
Compare
BT BTS CMPXCHG# BTC CMP TEST BTR CMPS
Conditional Set
SETA/SETNBE SETBE/SETNA SETG/SETNLE SETLE/SETNG SETNO SETO
* 8018680486 only. 8038680486 only.
SETAE/SETNB SETC SETGE/SETNL SETNC SETNP/SETPO SETP/SETPE

8028680486 only. # 80486 only.
SETB/SETNAE SETE/SETZ SETL/SETNGE SETNE/SETNZ SETNS SETS
Processor
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Conditional Transfer
BOUND* JAE/JNB JC JG/JNLE JLE/JNG JNO JO INTO JB/JNAE JCXZ/JECXZ JGE/JNL JNC JNP/JPO JP/JPE JA/JNBE JBE/JNA JE/JZ JL/JNGE JNE/JNZ JNS JS
Data Transfer
BSWAP# LEA MOV MOVZX XCHG CMPXCHG# LFS/LGS/LSS MOVS STOS XLAT/XLATB LDS/LES LODS MOVSX XADD#
Flag
CLC CMC PUSHF STD CLD LAHF SAHF STI CLI POPF STC
Input/Output
IN OUT INS* OUTS*
Loop
JCXZ/JECXZ LOOPE/LOOPZ
* 8018680486 only. 8038680486 only.
LOOP LOOPNE/LOOPNZ
8028680486 only. # 80486 only.
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Reference
Process Control
ARPL LGDT/LIDT/LLDT LTR STR MOV special WBINVD#
CLTS LMSW SGDT/SIDT/SLDT VERR INVD#
LAR LSL SMSW VERW INVLPG#
Processor Control
HLT NOP LOCK WAIT
Stack
PUSH PUSHAD* POPA* LEAVE* PUSHF POP POPAD* PUSHA* POPF ENTER*
String
MOVS SCAS OUTS* REPNE/REPNZ LODS CMPS REP STOS INS* REPE/REPZ
Type Conversion
CBW CWDE BSWAP# CWD CDQ
Unconditional Transfer
CALL RET
* 8018680486 only. 8038680486 only.
INT RETN/RETF
8028680486 only. # 80486 only.
IRET JMP
Processor
53
Interpreting Processor Instructions

The following sections explain the format of instructions for the 8086, 8088, 80286, 80386, and 80486 processors. Those instructions begin on page 64.
Flags
Only the flags common to all processors are shown. If none of the flags is affected by the instruction, the flag line says No change. If flags can be affected, a two-line entry is shown. The first line shows flag abbreviations as follows:
Abbreviation O D I T S Z A P C Flag Overflow Direction Interrupt Trap Sign Zero Auxiliary carry Parity Carry
The second line has codes indicating how the flag can be affected:
Code 1 0 ? blank Effect Sets the flag Clears the flag May change the flag, but the value is not predictable No effect on the flag Modifies according to the rules associated with the flag
54
Reference
Syntax
Each encoding variation may have different syntaxes corresponding to different addressing modes. The following abbreviations are used: reg A general-purpose register of any size.
segreg One of the segment registers: DS, ES, SS, or CS (also FS or GS on the 8038680486). accum An accumulator register of any size: AL or AX (also EAX on the 8038680486). mem label src,dest immed A direct or indirect memory operand of any size. A labeled memory location in the code segment. A source or destination memory operand used in a string operation. A constant operand.
In some cases abbreviations have numeric suffixes to specify that the operand must be a particular size. For example, reg16 means that only a 16-bit (word) register is accepted.
Examples
One or more examples are shown for each syntax. Their position is not related to the clock speeds in the right column.
Clock Speeds
Column 3 shows the clock speeds for each processor. Sometimes an instruction may have more than one clock speed. Multiple speeds are separated by commas. If several speeds are part of an expression, they are enclosed in parentheses. The following abbreviations are used to specify variations: EA Effective address. This applies only to the 8088 and 8086 processors, as described in the next section. b,w,d pm Byte, word, or doubleword operands. Protected mode.
n Iterations. Repeated instructions may have a base number of clocks plus a number of clocks for each iteration. For example, 8+4n means 8 clocks plus 4 clocks for each iteration. noj No jump. For conditional jump instructions, noj indicates the speed if the condition is false and the jump is not taken.
Processor
55
m Next instruction components. Some control transfer instructions take different times depending on the length of the next instruction executed. On the 8088 and 8086, m is never a factor. On the 80286, m is the number of bytes in the instruction. On the 8038680486, m is the number of components. Each byte of encoding is a component, and the displacement and data are separate components. W88,88 8088 exceptions. See Timings on the 8088 and 8086 Processors, following. Clocks can be converted to nanoseconds by dividing 1 microsecond by the number of megahertz (MHz) at which the processor is running. For example, on a processor running at 8 MHz, 1 clock takes 125 nanoseconds (1000 MHz per nanosecond / 8 MHz). The clock counts are for best-case timings. Actual timings vary depending on wait states, alignment of the instruction, the status of the prefetch queue, and other factors.
Timings on the 8088 and 8086 Processors

Because of its 8-bit data bus, the 8088 always requires two fetches to get a 16bit operand. Therefore, instructions that work on 16-bit memory operands take longer on the 8088 than on the 8086. Separate 8088 timings are shown in parentheses following the main timing. For example, 9 (W88=13) means that the 8086 with any operands or the 8088 with byte operands take 9 clocks, but the 8088 with word operands takes 13 clocks. Similarly, 16 (88=24) means that the 8086 takes 16 clocks, but the 8088 takes 24 clocks. On the 8088 and 8086, the effective address (EA) value must be added for instructions that operate on memory operands. A displacement is any direct memory or constant operand, or any combination of the two. The following shows the number of clocks to add for the effective address:
Components Displacement Base or index Displacement plus base or index Base plus index (BP+DI, BX+SI) EA Clocks 6 5 9 7 Examples
mov mov mov mov mov mov mov mov ax,stuff ax,stuff+2 ax,[bx] ax,[di] ax,[bp+8] ax,stuff[di] ax,[bx+si] ax,[bp+di]
56
Reference Components Base plus index (BP+SI, BX+DI) Base plus index plus displacement (BP+DI+disp, BX+SI+disp) Base plus index plus displacement (BP+SI+disp, BX+DI+disp) Segment override EA Clocks 8 11 12 Examples
mov mov mov mov mov mov mov mov ax,[bx+di] ax,[bp+si] ax,stuff[bx+si] ax,[bp+di+8] ax,stuff[bx+di] ax,[bp+si+20] ax,es:stuff ax,ds:[bp+10]
EA+2
Timings on the 8028680486 Processors

On the 8028680486 processors, the effective address calculation is handled by hardware and is therefore not a factor in clock calculations except in one case. If a memory operand includes all three possible elements a displacement, a base register, and an index register then add one clock. On the 80486, the extra clock is not always used. Examples are shown in the following.
mov mov mov ax,[bx+di] ax,array[bx+di] ax,[bx+di+6] ;No extra ;One extra ;One extra
Note 80186 and 80188 timings are different from 8088, 8086, and 80286 timings. They are not shown in this manual. Timings are also not shown for protected-mode transfers through gates or for the virtual 8086 mode available on the 8038680486 processors.
Interpreting Encodings
Encodings are shown for each variation of the instruction. This section describes encoding for all processors except the 8038680486. The encodings take the form of boxes filled with 0s and 1s for bits that are constant for the instruction variation, and abbreviations (in italics) for the following variable bits or bitfields: d Direction bit. If set, do memory to register; the reg field is the destination. If clear, do register to memory or register to register; the reg field is the source. a Accumulator direction bit. If set, move accumulator register to memory. If clear, move memory to accumulator register. w Word/byte bit. If set, use 16-bit or 32-bit operands. If clear, use 8-bit operands.
Processor
57
Sign bit. If set, sign-extend 8-bit immediate data to 16 bits.
mod Mode. This 2-bit field gives the register/memory mode with displacement. The possible values are shown below:
mod 00 Meaning This value can have two meanings: If r/m is 110, a direct memory operand is used. If r/m is not 110, the displacement is 0 and an indirect memory operand is used. The operand must be based, indexed, or based indexed. An indirect memory operand is used with an 8-bit displacement. An indirect memory operand is used with a 16-bit displacement. A two-register instruction is used; the reg field specifies the destination and the r/m field specifies the source.
01 10 11
reg
reg 000 001 010 011 100 101 110 111
Register. This 3-bit field specifies one of the general-purpose registers:

16/32-bit if w=1 AX/EAX CX/ECX DX/EDX BX/EBX SP/ESP BP/EBP SI/ESI DI/EDI 8-bit if w=0 AL CL DL BL AH CH DH BH
The reg field is sometimes used to specify encoding information rather than a register. sreg
sreg 000 001 010 011 100 101
Segment register. This field specifies one of the segment registers:

Register ES CS SS DS FS GS
58
Reference
r/m Register/memory. This 3-bit field specifies a register or memory r/m operand. If the mod field is 11, r/m specifies the source register using the reg field codes. Otherwise, the field has one of the following values:
r/m 000 001 010 011 100 101 110 111 Operand Address DS:[BX+SI+disp] DS:[BX+DI+disp] SS:[BP+SI+disp] SS:[BP+DI+disp] DS:[SI+disp] DS:[DI+disp] SS:[BP+disp]* DS:[BX+disp]
* If mod is 00 and r/m is 110, then the operand is treated as a direct memory operand. This means that the operand [BP] is encoded as [BP+0] rather than having a short-form like other register indirect operands. Encoding [BX] takes one byte, but encoding [BP] takes two.
disp Displacement. These bytes give the offset for memory operands. The possible lengths (in bytes) are shown in parentheses. data Data. These bytes give the actual value for constant values. The possible lengths (in bytes) are shown in parentheses. If a memory operand has a segment override, the entire instruction has one of the following bytes as a prefix:
Prefix 00101110 (2Eh) 00111110 (3Eh) 00100110 (26h) 00110110 (36h) 01100100 (64h) 01100101 (65h) Segment CS DS ES SS FS GS
Example
As an example, assume you want to calculate the encoding for the following statement (where warray is a 16-bit variable):
add warray[bx+di], -3
Processor
59
First look up the encoding for the immediate-to-memory syntax of the ADD instruction: 100000sw mod,000,r/m disp (0, 1, or 2) data (0, 1, or 2) Since the destination is a word operand, the w bit is set. The 8-bit immediate data must be sign-extended to 16 bits to fit into the operand, so the s bit is also set. The first byte of the instruction is therefore 10000011 (83h). Since the memory operand can be anywhere in the segment, it must have a 16bit offset (displacement). Therefore the mod field is 10. The reg field is 000, as shown in the encoding. The r/m coding for [bx+di+disp] is 001. The second byte is 10000001 (81h). The next two bytes are the offset of warray. The low byte of the offset is stored first and the high byte second. For this example, assume that warray is located at offset 10EFh. The last byte of the instruction is used to store the 8-bit immediate value 3 (FDh). This value is encoded as 8 bits (but sign-extended to 16 bits by the processor). The encoding is shown here in hexadecimal: 83 81 EF 10 FD You can confirm this by assembling the instruction and looking at the resulting assembly listing.
Interpreting 8038680486 Encoding Extensions

This book shows 8038680486 encodings for instructions that are available only on the 8038680486 processors. For other instructions, encodings are shown only for the 16-bit subset available on all processors. This section tells how to convert the 80286 encodings shown in the book to 8038680486 encodings that use extensions such as 32-bit registers and memory operands. The extended 8038680486 encodings differ in that they can have additional prefix bytes, a Scaled Index Base (SIB) byte, and 32-bit displacement and immediate bytes. Use of these elements is closely tied to the segment word size. The use type of the code segment determines whether the instructions are processed in 32-bit mode (USE32) or 16-bit mode (USE16). Current versions of MS-DOS and Microsoft Windows use 16-bit mode only. Windows NT uses 32-bit mode. The bytes that can appear in an instruction encoding are:
60
Reference
16-Bit Encoding
Opcode (1-2) mod-reg-r/m (0-1) disp (0-2) immed (0-2)
32-Bit Encoding
AddressSize (67h) (0-1) OperandSize (66h) (0-1) Opcode (1-2) mod-regr/m (0-1) Scaled Index Base (0-1) disp (0-4) immed (0-4)
Additional bytes may be added for a segment prefix, a repeat prefix, or the LOCK prefix.
Address-Size Prefix
The address-size prefix determines the segment word size of the operation. It can override the default size for calculating the displacement of memory addresses. The address prefix byte is 67h. The assembler automatically inserts this byte where appropriate. In 32-bit mode (USE32 or FLAT code segment), displacements are calculated as 32-bit addresses. The effective address-size prefix must be used for any instructions that must calculate addresses as 16-bit displacements. In 16-bit mode, the defaults are reversed. The prefix must be used to specify calculation of 32-bit displacements.
Operand-Size Prefix
The operand-size prefix determines the size of operands. It can override the default size of registers or memory operands. The operand-size prefix byte is 66h. The assembler automatically inserts this byte where appropriate. In 32-bit mode, the default sizes for operands are 8 bits and 32 bits (depending on the w bit). For most instructions, the operand-size prefix must be used for any instructions that use 16-bit operands. In 16-bit mode, the default sizes are 8 bits and 16 bits. The prefix must be used for any instructions that use 32-bit operands. Some instructions use 16-bit operands, regardless of mode.
Encoding Differences for 32-Bit Operations

When 32-bit operations are performed, the meaning of certain bits or fields is different from their meaning in 16-bit operations. The changes may affect default operations in 32-bit mode, or 16-bit mode operations in which the address-size prefix or the operand-size prefix is used. The following fields may
Processor
61
have a different meaning for 32-bit operations from their meaning as described in the Interpreting Encodings section: w s Word/byte bit. If set, use 32-bit operands. If clear, use 8-bit operands. Sign bit. If set, sign-extend 8-bit and 16-bit immediate data to 32 bits.
mod Mode. This field indicates the register/memory mode. The value 11 still indicates a register-to-register operation with r/m containing the code for a 32-bit source register. However, other codes have different meanings as shown in the tables in the next section. reg Register. The codes for 16-bit registers are extended to 32-bit registers. For example, if the reg field is 000, EAX is used instead of AX. Use of 8-bit registers is unchanged. sreg Segment register. The 80386 has the following additional segment registers:
sreg 100 101 Register FS GS
r/m Register/memory. If the r/m field is used for the source register, 32-bit registers are used as for the reg field. If the field is used for memory operands, the meaning is completely different from the meaning used for 16-bit operations, as shown in the tables in the next section. disp data Displacement. This field is 4 bytes for 32-bit addresses. Data. Immediate data can be up to 4 bytes.
Scaled Index Base Byte

Many 8038680486 extended memory operands are too complex to be represented by a single mod-reg-r/m byte. For these operands, a value of 100 in the r/m field signals the presence of a second encoding byte called the Scaled Index Base (SIB) byte. The SIB byte is made up of the following fields: ss index base ss Scaling Field. This two-bit field specifies one of the following scaling factors:
ss 00 01 10 Scale 1 2 4
62
Reference 11 8
index Index Register. This three-bit field specifies one of the following index registers:
index 000 001 010 011 100 101 110 111 Register EAX ECX EDX EBX no index EBP ESI EDI
Note ESP cannot be an index register. If the index field is 100, the ss field must be 00. base Base Register. This 3-bit field combines with the mod field to specify the base register and the displacement. Note that the base field only specifies the base when the r/m field is 100. Otherwise, the r/m field specifies the base. The possible combinations of the mod, r/m, scale, index, and base fields are as follows:
Processor
63
If a memory operand has a segment override, the entire instruction has one of the prefixes discussed in the preceding section, Interpreting Encodings, or one of the following prefixes for the segment registers available only on the 80386 80486:
Prefix 01100100 (64h) 01100101 (65h) Segment FS GS
Example
Assume you want to calculate the encoding for the following statement (where warray is a 16-bit variable). Assume that the instruction is used in 16-bit mode.
add warray[eax+ecx*2], -3
First look up the encoding for the immediate-to-memory syntax of the ADD instruction: 100000sw mod,000,r/m disp (0, 1, or 2) data (1 or 2)
This encoding must be expanded to account for 8038680486 extensions. Note that the instruction operates on 16-bit data in a 16-bit mode program. Therefore, the operand-size prefix is not needed. However, the instruction does use 32-bit
64
Reference
registers to calculate a 32-bit effective address. Thus the first byte of the encoding must be the effective address-size prefix, 01100111 (67h). The opcode byte is the same (83h) as for the 80286 example described in the Interpreting Encodings section. The mod-reg-r/m byte must specify a based indexed operand with a scaling factor of two. This operand cannot be specified with a single byte, so the encoding must also use the SIB byte. The value 100 in the r/m field specifies an SIB byte. The reg field is 000, as shown in the encoding. The mod field is 10 for operands that have base and scaled index registers and a 32-bit displacement. The combined mod, reg, and r/m fields for the second byte are 10000100 (84h). The SIB byte is next. The scaling factor is 2, so the ss field is 01. The index register is ECX, so the index field is 001. The base register is EAX, so the base field is 000. The SIB byte is 01001000 (48h). The next 4 bytes are the offset of warray. The low bytes are stored first. For this example, assume that warray is located at offset 10EFh. This offset only requires 2 bytes, but 4 must be supplied because of the addressing mode. A 32bit address can be safely used in 16-bit mode as long as the upper word is 0. The last byte of the instruction is used to store the 8-bit immediate value 3 (FDh). The encoding is shown here in hexadecimal: 67 83 84 48 00 00 EF 10 FD
Instructions
This section provides an alphabetical reference to the instructions for the 8086, 8088, 80286, 80386, and 80486 processors.
AAA ASCII Adjust After Addition

Adjusts the result of an addition to a decimal digit (09). The previous addition instruction should place its 8-bit sum in AL. If the sum is greater than 9h, AH is incremented and the carry and auxiliary carry flags are set. Otherwise, the carry and auxiliary carry flags are cleared. Flags O D I ? T S Z A P C ? ? ?
AAD ASCII Adjust Before Division
65
Encoding
00110111
Syntax AAA Examples
aaa
CPU 88/86 286 386 486
Clock Cycles 8 3 4 3
AAD ASCII Adjust Before Division

Converts unpacked BCD digits in AH (most significant digit) and AL (least significant digit) to a binary number in AX. This instruction is often used to prepare an unpacked BCD number in AX for division by an unpacked BCD digit in an 8-bit register. Flags Encoding O D I ? T S Z A P C ? ? 00001010
Examples
aad
11010101
Syntax AAD
CPU 88/86 286 386 486
66
AAM ASCII Adjust After Multiply
AAM ASCII Adjust After Multiply

Converts an 8-bit binary number less than 100 decimal in AL to an unpacked BCD number in AX. The most significant digit goes in AH and the least significant in AL. This instruction is often used to adjust the product after a MUL instruction that multiplies unpacked BCD digits in AH and AL. It is also used to adjust the quotient after a DIV instruction that divides a binary number less than 100 decimal in AX by an unpacked BCD number. Flags Encoding O D I ? T S Z A P C ? ? 00001010
Examples
aam
11010100
Syntax AAM
CPU 88/86 286 386 486
AAS ASCII Adjust After Subtraction

Adjusts the result of a subtraction to a decimal digit (09). The previous subtraction instruction should place its 8-bit result in AL. If the result is greater than 9h, AH is decremented and the carry and auxiliary carry flags are set. Otherwise, the carry and auxiliary carry flags are cleared. Flags Encoding O D I ? T S Z A P C ? ? ?
00111111
Syntax AAS Examples
aas
CPU 88/86 286 386 486
ADC Add with Carry
67
ADC Add with Carry

Adds the source operand, the destination operand, and the value of the carry flag. The result is assigned to the destination operand. This instruction is used to add the more significant portions of numbers that must be added in multiple registers. Flags Encoding O D I T S Z A P C mod,reg,r/m disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486 Clock Cycles 3 2 2 1 16+EA (W88=24+EA) 7 7 3 9+EA (W88=13+EA) 7 6 2
000100dw
Syntax ADC reg,reg
Examples
adc dx,cx
ADC mem,reg
adc
WORD PTR m32[2],dx
ADC reg,mem
adc
dx,WORD PTR m32[2]
Encoding
100000sw
Syntax
mod, 010,r/m
disp (0, 1, or 2)
data (1 or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 4 3 2 1 17+EA (W88=23+EA) 7 7 3
Examples
adc dx,12
ADC reg,immed
ADC mem,immed
adc
WORD PTR m32[2],16
Encoding
0001010w
Syntax
data (1 or 2)
Examples
adc ax,5
CPU 88/86 286 386 486
ADC accum,immed
68
ADD Add
ADD Add
Adds the source and destination operands and puts the sum in the destination operand. Flags Encoding O D I T S Z A P C mod,reg,r/m disp (0, 1, or 2)
000000dw
Syntax ADD reg,reg
Examples
add ax,bx
ADD mem, reg
add add
total, cx array[bx+di], dx
ADD reg,mem
add add
cx,incr dx,[bp+6]
Encoding
100000sw
Syntax
mod, 000,r/m
disp (p,1, or2)
data (1or2)
Examples
add bx,6
ADD reg,immed
ADD mem,immed
add add
amount,27 pointers[bx][si],6
Encoding
0000010w
Syntax
data (1 or 2)
Examples
add ax,10
CPU 88/86 286 386 486
ADD accum,immed
AND Logical AND
69
AND Logical AND

Performs a bitwise AND operation on the source and destination operands and stores the result in the destination operand. For each bit position in the operands, if both bits are set, the corresponding bit of the result is set. Otherwise, the corresponding bit of the result is cleared. Flags Encoding O D I 0 T S Z A P C ? 0 mod,reg,r/m disp (0, 1, or 2)
001000dw
Syntax AND reg,reg
Examples
and dx,bx
AND mem,reg
and and
bitmask,bx [bp+2],dx
AND reg,mem
and and
bx,masker dx,marray[bx+di]
Encoding
100000sw
Syntax
mod, 100, r/m
disp (0, 1, or 2)
data (1 or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 4 3 2 1 17+EA(W88=24+EA) 7 7 3
Examples
and dx,0F7h
AND reg,immed
AND mem,immed
and
masker, 100lb
Encoding
0010010w
Syntax
data (1 or 2)
Examples
and ax,0B6h
CPU 88/86 286 386 486
AND accum,immed
70
ARPL Adjust Requested Privilege Level
ARPL Adjust Requested Privilege Level

8028680486 Protected Only Verifies that the destination Requested Privilege Level (RPL) field (bits 0 and 1 of a selector value) is less than the source RPL field. If it is not, ARPL adjusts the destination RPL to match the source RPL. The destination operand should be a 16-bit memory or register operand containing the value of a selector. The source operand should be a 16-bit register containing the test value. The zero flag is set if the destination is adjusted; otherwise, the flag is cleared. ARPL is useful only in 8028680486 protected mode. See Intel documentation for details on selectors and privilege levels. Flags Encoding O D I T S Z A P C mod,reg,r/m disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 10 20 9 11 21 9
01100011
Syntax
Examples
arpl ax,cx
ARPL reg,reg
ARPL mem,reg
arpl
selector,dx
BOUND Check Array Bounds

8028680486 Only Verifies that a signed index value is within the bounds of an array. The destination operand can be any 16-bit register containing the index to be checked. The source operand must then be a 32-bit memory operand in which the low and high words contain the starting and ending values, respectively, of the array. (On the 8038680486 processors, the destination operand can be a 32-bit register; in this case, the source operand must be a 64bit operand made up of 32-bit bounds.) If the source operand is less than the first bound or greater than the last bound, an interrupt 5 is generated. The instruction pointer pushed by the interrupt (and returned by IRET) points to the BOUND instruction rather than to the next instruction. Flags No change
BSF/BSR Bit Scan
71
Encoding
01100010
Syntax
mod,reg, r/m
disp (2)
Examples
bound di,base-4
CPU 88/86 286 386 486
Clock Cycles noj=13 noj=10 noj=7
BOUND reg16,mem32 BOUND reg32,mem64*
* 8038680486 only. See INT for timings if interrupt 5 is called.
BSF/BSR Bit Scan

8038680486 Only Scans an operand to find the first set bit. If a set bit is found, the zero flag is cleared and the destination operand is loaded with the bit index of the first set bit encountered. If no set bit is found, the zero flag is set. BSF (Bit Scan Forward) scans from bit 0 to the most significant bit. BSR (Bit Scan Reverse) scans from the most significant bit of an operand to bit 0. Flags Encoding O D I T S Z A P C 10111100 mod, reg, r/m disp (0, 1, 2, or 4)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 10+3n* 642 10+3n* 743
00001111
Syntax
Examples
bsf cx,bx
BSF reg16,reg16 BSF reg32,reg32
BSF reg16,mem16 BSF reg32,mem32
bsf
ecx,bitmask
72
BSWAP Byte Swap
Encoding
00001111
Syntax
10111101
mod, reg, r/m
disp (0, 1, 2, or 4)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 10+3n* 103 3n# 10+3n* 104 3n#
Examples
bsr cx,dx
BSR reg16,reg16 BSR reg32,reg32
BSR reg16,mem16 BSR reg32,mem32
bsr
eax,bitmask
* n = bit position from 0 to 31. clocks = 6 if second operand equals 0. Clocks = 8 + 4 for each byte scanned + 3 for each nibble scanned + 3 for each bit scanned in last nibble or 6 if second operand equals 0. Same as footnote above, but add 1 clock. # n = bit position from 0 to 31. clocks = 7 if second operand equals 0.
BSWAP Byte Swap

80486 Only Takes a single 32-bit register as operand and exchanges the first byte with the fourth, and the second byte with the third. This instruction does not alter any bit values within the bytes and is useful for quickly translating between 8086-family byte storage and storage schemes in which the high byte is stored first. Flags Encoding No change 00001111
Syntax BSWAP reg32
11001 reg
Examples
bswap bswap eax ebx
CPU 88/86 286 386 486
Clock Cycles 1
BT/BTC/BTR/BTS Bit Tests
73
BT/BTC/BTR/BTS Bit Tests

8038680486 Only Copies the value of a specified bit into the carry flag, where it can be tested by a JC or JNC instruction. The destination operand specifies the value in which the bit is located; the source operand specifies the bit position. BT simply copies the bit to the flag. BTC copies the bit and complements (toggles) it in the destination. BTR copies the bit and resets (clears) it in the destination. BTS copies the bit and sets it in the destination. Flags Encoding O D I T S Z A P C 10111010 mod, BBB*,r/m
Examples
bt ax,4
00001111
Syntax
disp (0, 1, 2, or 4)
CPU 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486
data (1)
Clock Cycles 3 3 6 6 6 3 8 8
BT reg16,immed8
BTC reg16,immed8 BTR reg16,immed8 BTS reg16,immed8 BT mem16,immed8
bts btr btc
ax,4 bx,17 edi,4
btr DWORD PTR [si],27 btc color[di],4 btc DWORD PTR [bx],27 btc maskit,4 btr color[di],4
BTC mem16,immed8 BTR mem16,immed8 BTS mem16,immed8
Encoding
00001111
Syntax
10BBB011*
mod, reg, r/m

Examples
bt ax,bx
disp (0, 1, 2, or 4)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 3 3 6 6
BT reg16,reg16
BTC reg16,reg16 BTR reg16,reg16 BTS reg16,reg16
btc bts btr
eax,ebx bx,ax cx,di
74
CALL Call Procedure Syntax BT mem16,reg16 Examples

bt [bx],dx
CPU 88/86 286 386 486 88/86 286 386 486
BTC mem16,reg16 BTR mem16,reg16 BTS mem16,reg16
bts btr btc
flags[bx],cx rotate,cx [bp+8],si
* BBB is 100 for BT, 111 for BTC, 110 for BTR, and 101 for BTS. Operands also can be 32 bits (reg32 and mem32).
CALL Call Procedure

Calls a procedure. The instruction pushes the address of the next instruction onto the stack and jumps to the address specified by the operand. For NEAR calls, the offset (IP) is pushed and the new offset is loaded into IP. For FAR calls, the segment (CS) is pushed and the new segment is loaded into CS. Then the offset (IP) is pushed and the new offset is loaded into IP. A subsequent RET instruction can pop the address so that execution continues with the instruction following the call. Flags Encoding No change 11101000
Syntax CALL label
disp (2)
Examples
call upcase
CPU 88/86 286 386 486
Clock Cycles 19 (88=23) 7+m 7+m 3
Encoding
10011010
Syntax CALL label
disp (4)
Examples
call call FAR PTR job distant
CPU 88/86 286 386 486
Clock Cycles 28 (88=36) 13+m,pm=26+m* 17+m,pm=34+m* 18,pm=20*
CBW Convert Byte to Word
75
Encoding
11111111
Syntax CALL reg
mod,010,r/m
Examples
call ax
CPU 88/86 286 386 486 88/86 286 386 486
Clock Cycles 16 (88=20) 7+m 7+m 5 21+EA (88=29+EA) 11+m 10+m 5
CALL mem16 CALL mem32
call call
pointer [bx]
Encoding
11111111
Syntax
mod,011,r/m
Examples
call call far_table[di] DWORD PTR [bx]
CPU 88/86 286 386 486
Clock Cycles 37+EA (88=53+EA) 16+m,pm=29+m* 22+m,pm=38+m* 17,pm=20*
CALL mem32 CALL mem48
* Timings for calls through call and task gates are not shown, since they are used primarily in operating systems. 8038680486 32-bit addressing mode only.
CBW Convert Byte to Word

Converts a signed byte in AL to a signed word in AX by extending the sign bit of AL into all bits of AH. Flags Encoding No change 10011000*
Syntax CBW Examples
cbw
CPU 88/86 286 386 486
* CBW and CWDE have the same encoding with two exceptions: in 32-bit mode, CBW is preceded by the operand-size byte (66h) but CWDE is not; in 16-bit mode, CWDE is preceded by the operand-size byte but CBW is not.
76
CDQ Convert Double to Quad
CDQ Convert Double to Quad

8038680486 Only Converts the signed doubleword in EAX to a signed quadword in the EDX:EAX register pair by extending the sign bit of EAX into all bits of EDX. Flags Encoding No change 10011001*
Syntax CDQ Examples
cdq
CPU 88/86 286 386 486
Clock Cycles 2 3
* CWD and CDQ have the same encoding with two exceptions: in 32-bit mode, CWD is preceded by the operand-size byte (66h) but CDQ is not; in 16-bit mode, CDQ is preceded by the operand-size byte but CWD is not.
CLC Clear Carry Flag

Clears the carry flag. Flags Encoding O D I T S Z A P C 0
11111000
Syntax CLC Examples
clc
CPU 88/86 286 386 486
CLTS Clear Task-Switched Flag
77
CLD Clear Direction Flag

Clears the direction flag. All subsequent string instructions will process up (from low addresses to high addresses) by increasing the appropriate index registers. Flags Encoding O D I 0 T S Z A P C
11111100
Syntax CLD Examples
cld
CPU 88/86 286 386 486
CLI Clear Interrupt Flag

Clears the interrupt flag. When the interrupt flag is cleared, maskable interrupts are not recognized until the flag is set again with the STI instruction. In protected mode, CLI clears the flag only if the current tasks privilege level is less than or equal to the value of the IOPL flag. Otherwise, a general-protection fault occurs. Flags Encoding O D I T S Z A P C 0 11111010
Syntax CLI Examples
cli
CPU 88/86 286 386 486
CLTS Clear Task-Switched Flag

8028680486 Privileged Only Clears the task-switched flag in the Machine Status Word (MSW) of the 80286, or the CR0 register of the 8038680486. This instruction can be used only in system software executing at privilege level
78
CMC Complement Carry Flag
0. See Intel documentation for details on the task-switched flag and other privileged-mode concepts. Flags Encoding No change 00001111
Syntax CLTS
00000110
Examples
clts
CPU 88/86 286 386 486
Clock Cycles 2 5 7
CMC Complement Carry Flag

Complements (toggles) the carry flag. Flags Encoding O D I T S Z A P C
11110101
Syntax CMC Examples
cmc
CPU 88/86 286 386 486
CMP Compare Two Operands

Compares two operands as a test for a subsequent conditional-jump or set instruction. CMP does this by subtracting the source operand from the destination operand and setting the flags according to the result. CMP is the same as the SUB instruction, except that the result is not stored. Flags O D I T S Z A P C
CMP Compare Two Operands
79
Encoding
001110dw
Syntax CMP reg,reg
mod, reg, r/m
disp (0, 1, or 2)
Examples
cmp cmp di,bx dl,cl
CMP mem,reg
cmp cmp
maximum,dx array[si],bl
CMP reg,mem
cmp cmp
dx,minimum bh,array[si]
Encoding
100000sw
Syntax
mod, 111,r/m
disp (0, 1, or 2)
data (1 or 2)
Examples
cmp bx,24
CMP reg,immed
CMP mem,immed
cmp cmp
WORD PTR [di],4 tester,4000
Encoding
0011110w
Syntax
data (1 or 2)
Examples
cmp ax,1000
CPU 88/86 286 386 486
CMP accum,immed
80
CMPS/CMPSB/CMPSW/CMPSD Compare String
CMPS/CMPSB/CMPSW/CMPSD Compare String

Compares two strings. DS:SI must point to the source string and ES:DI must point to the destination string (even if operands are given). For each comparison, the destination element is subtracted from the source element and the flags are updated to reflect the result (although the result is not stored). DI and SI are adjusted according to the size of the operands and the status of the direction flag. They are increased if the direction flag has been cleared with CLD, or decreased if the direction flag has been set with STD. If the CMPS form of the instruction is used, operands must be provided to indicate the size of the data elements to be processed. A segment override can be given for the source (but not for the destination). If CMPSB (bytes), CMPSW (words), or CMPSD (doublewords on the 8038680486 only) is used, the instruction determines the size of the data elements to be processed. CMPS and its variations are normally used with repeat prefixes. REPNE (or REPNZ) is used to find the first match between two strings. REPE (or REPZ) is used to find the first mismatch. Before the comparison, CX should contain the maximum number of elements to compare. After a REPNE CMPS, the zero flag is clear if no match was found. After a REPE CMPS, the zero flag is set if no mismatch was found. When the instruction finishes, ES:DI and DS:SI point to the element that follows (if the direction flag is clear) or precedes (if the direction flag is set) the match or mismatch. If CX decrements to 0, ES:DI and DS:SI point to the element that follows or precedes the last comparison. The zero flag is set or clear according to the result of the last comparison, not according to the value of CX. Flags Encoding
Syntax CMPS [ [segreg:] src, [ ] [ES:] dest ] CMPSB [ [segreg:[ src, ] [[ [ ]ES:] dest] ] ] CMPSW [ [segreg:[ src, ] [[ [ ]ES:] dest] ] ] CMPSD [ [segreg:[ src, ] [[ [ ]ES:] dest] ] ]
O D I
T S Z A P C
1010011w
Examples
cmps repne repe repne source,es:dest cmpsw cmpsb cmpsd
CPU 88/86 286 386 486
Clock Cycles 22 (W88=30) 8 10 8
CWD Convert Word to Double
81
CMPXCHG Compare and Exchange

80486 Only Compares the destination operand to the accumulator (AL, AX, or EAX). If equal, the source operand is copied to the destination. Otherwise, the destination is copied to the accumulator. The instruction sets flags according to the result of the comparison. Flags Encoding O D I 00001111
Syntax CMPXCHG mem,reg
T S Z A P C 1011000b mod, reg, r/m

Examples
cmpxchg cmpxchg warr[bx],cx string,bl
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 710 6
CMPXCHG reg,reg
cmpxchg cmpxchg
dl,cl bx,dx
CWD Convert Word to Double

Converts the signed word in AX to a signed doubleword in the DX:AX register pair by extending the sign bit of AX into all bits of DX. Flags Encoding O D I T S Z A P C
10011001*
Syntax CWD Examples
cwd
CPU 88/86 286 386 486
* CWD and CDQ have the same encoding with two exceptions: in 32-bit mode, CWD is preceded by the operand-size byte (66h) but CDQ is not; in 16-bit mode, CDQ is preceded by the operand-size byte but CWD is not.
82
CWDE Convert Word to Extended Double
CWDE Convert Word to Extended Double

8038680486 Only Converts a signed word in AX to a signed doubleword in EAX by extending the sign bit of AX into all bits of EAX. Flags Encoding No change 10011000*
Syntax CWDE Examples
cwde
CPU 88/86 286 386 486
Clock Cycles 3 3
* CBW and CWDE have the same encoding with two exceptions: in 32-bit mode, CBW is preceded by the operand-size byte (66h) but CWDE is not; in 16-bit mode, CWDE is preceded by the operand-size byte but CBW is not.
DAA Decimal Adjust After Addition

Adjusts the result of an addition to a packed BCD number (less than 100 decimal). The previous addition instruction should place its 8-bit binary sum in AL. DAA converts this binary sum to packed BCD format with the least significant decimal digit in the lower four bits and the most significant digit in the upper four bits. If the sum is greater than 99h after adjustment, the carry and auxiliary carry flags are set. Otherwise, the carry and auxiliary carry flags are cleared. Flags Encoding O D I ? T S Z A P C
00100111
Syntax DAA Examples
daa
CPU 88/86 286 386 486
DEC Decrement
83
DAS Decimal Adjust After Subtraction

Adjusts the result of a subtraction to a packed BCD number (less than 100 decimal). The previous subtraction instruction should place its 8-bit binary result in AL. DAS converts this binary sum to packed BCD format with the least significant decimal digit in the lower four bits and the most significant digit in the upper four bits. If the sum is greater than 99h after adjustment, the carry and auxiliary carry flags are set. Otherwise, the carry and auxiliary carry flags are cleared. Flags Encoding O D I ? T S Z A P C
00101111
Syntax DAS Examples
das
CPU 88/86 286 386 486
DEC Decrement
Subtracts 1 from the destination operand. Because the operand is treated as an unsigned integer, the DEC instruction does not affect the carry flag. To detect any effects on the carry flag, use the SUB instruction. Flags Encoding O D I T S Z A P C mod, 001,r/m disp (0, 1, or 2)
1111111w
Syntax DEC reg8
Examples
dec cl
DEC mem
dec
counter
84
DIV Unsigned Divide
Encoding
01001 reg
Syntax DEC reg16 DEC reg32* Examples
dec ax
CPU 88/86 286 386 486
* 8038680486 only.
DIV Unsigned Divide

Divides an implied destination operand by a specified source operand. Both operands are treated as unsigned numbers. If the source (divisor) is 16 bits wide, the implied destination (dividend) is the DX:AX register pair. The quotient goes into AX and the remainder into DX. If the source is 8 bits wide, the implied destination operand is AX. The quotient goes into AL and the remainder into AH. On the 8038680486, if the source is EAX, the quotient goes into EAX and the remainder into EDX. Flags Encoding O D I ? T S Z A P C ? ? ? ? ? mod, 110,r/m disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486
* Word memory operands on the 8088 take (158176)+EA clocks.
1111011w
Syntax DIV reg
Examples
div div cx dl
Clock Cycles b=8090,w=144162 b=14,w=22 b=14,w=22,d=38 b=16,w=24,d=40 (b=8696,w=150 168)+EA* b=17,w=25 b=17,w=25,d=41 b=16,w=24,d=40
DIV mem
div div
[bx] fsize
HLT Halt
85
ENTER Make Stack Frame

80286-80486 Only Creates a stack frame for a procedure that receives parameters passed on the stack. When immed16 is 0, ENTER is equivalent to push bp, followed by mov bp,sp. The first operand of the ENTER instruction specifies the number of bytes to reserve for local variables. The second operand specifies the nesting level for the procedure. The nesting level should be 0 for languages that do not allow access to local variables of higherlevel procedures (such as C, Basic, and FORTRAN). See the complementary instruction LEAVE for a method of exiting from a procedure. Flags Encoding No change 11001000
Syntax ENTER immed16,0
data (2)
data (1)
Examples
enter 4,0
CPU 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486
Clock Cycles 11 10 14 15 12 17 12+4(n 1) 15+4(n 1) 17+3n
ENTER immed16,1
enter 0,1
ENTER immed16,immed8
enter 6,4
HLT Halt
Stops CPU execution until an interrupt restarts execution at the instruction following HLT. In protected mode, this instruction works only in privileged mode. Flags No change
86
HLT Halt
Encoding
11110100
Syntax HLT Examples
hlt
CPU 88/86 286 386 486
IMUL
Signed Multiply
87
IDIV Signed Divide

Divides an implied destination operand by a specified source operand. Both operands are treated as signed numbers. If the source (divisor) is 16 bits wide, the implied destination (dividend) is the DX:AX register pair. The quotient goes into AX and the remainder into DX. If the source is 8 bits wide, the implied destination is AX. The quotient goes into AL and the remainder into AH. On the 8038680486, if the source is EAX, the quotient goes into EAX and the remainder into EDX. Flags Encoding O D I ? T S Z A P C ? ? ? ? ? mod, 111,r/m disp (0, 1, or 2)
CPU 88/86 286 386 486 IDIV mem
idiv itemp
1111011w
Syntax IDIV reg
Examples
idiv idiv bx dl
Clock Cycles b=101112,w= 165184 b=17,w=25 b=19,w=27,d=43 b=19,w=27,d=43 (b=107118,w=171 190)+EA* b=20,w=28 b=22,w=30,d=46 b=20,w=28,d=44
88/86 286 386 486
* Word memory operands on the 8088 take (175194)+EA clocks.
IMUL Signed Multiply

Multiplies an implied destination operand by a specified source operand. Both operands are treated as signed numbers. If a single 16-bit operand is given, the implied destination is AX and the product goes into the DX:AX register pair. If a single 8-bit operand is given, the implied destination is AL and the product goes into AX. On the 8038680486, if the operand is EAX, the product goes into the EDX:EAX register pair. The carry and overflow flags are set if the product is sign-extended into DX for 16-bit operands, into AH for 8-bit operands, or into EDX for 32-bit operands.
88
IMUL
Signed Multiply
Two additional syntaxes are available on the 8018680486 processors. In the two-operand form, a 16-bit register gives one of the factors and serves as the destination for the result; a source constant specifies the other factor. In the three-operand form, the first operand is a 16-bit register where the result will be stored, the second is a 16-bit register or memory operand containing one of the factors, and the third is a constant representing the other factor. With both variations, the overflow and carry flags are set if the result is too large to fit into the 16-bit destination register. Since the low 16 bits of the product are the same for both signed and unsigned multiplication, these syntaxes can be used for either signed or unsigned numbers. On the 8038680486, the operands can be either 16 or 32 bits wide. A fourth syntax is available on the 8038680486. Both the source and destination operands can be given specifically. The source can be any 16- or 32bit memory operand or general-purpose register. The destination can be any general-purpose register of the same size. The overflow and carry flags are set if the product does not fit in the destination. Flags Encoding O D I T S Z A P C ? ? ? ? mod, 101,r/m disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles b=8098,w=128154 b=13,w=21 b=914,w=922,d=938* b=1318,w=1326,d=1342 (b=86104,w=134160)+EA b=16,w=24 b=1217,w=1225,d=1241* b=1318,w=1326, d=1342
1111011w
Syntax IMUL reg
Examples
imul dx
IMUL mem
imul
factor
* The 8038680486 processors have an early-out multiplication algorithm. Therefore, multiplying an 8-bit or 16-bit value in EAX takes the same time as multiplying the value in AL or AX. Word memory operands on the 8088 take (138164)+EA clocks.
Encoding
011010s1
Syntax
mod, reg, r/m
disp (0, 1, or 2)
Examples
imul cx,25
data (1 or 2)
CPU 88/86 286 386 486 Clock Cycles 21 b=914,w=922,d=938 b=1318,w=1326,d=1342
IMUL reg16,immed IMUL reg32,immed*
IMUL IMUL reg16,reg16,immed IMUL reg32,reg32,immed*

imul dx,ax,18
Signed Multiply
89
88/86 286 386 486
21 b=914,w=922,d=938 b=1318,w=1326,d=1342
90
IN Input from Port Syntax IMUL reg16,mem16,immed IMUL reg32,mem32,immed* Examples

imul bx,[si],60
CPU 88/86 286 386 486
Clock Cycles 24 b=1217,w=1225,d=1241 b=1318,w=1326,d=1342
Encoding
00001111
Syntax
10101111
mod,reg,r/m
Examples
imul
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles w=922,d=938 b=1318,w=1326,d=1342 w=1225,d=1241 b=1318,w=1326,d=1342
IMUL reg16,reg16 IMUL reg32,reg32*
cx,ax
IMUL reg16,mem16 IMUL reg32,mem32*
imul dx,[si]
* 8038680486 only. The variations depend on the source constant size; destination size is not a factor.
IN Input from Port

Transfers a byte or word (or doubleword on the 8038680486) from a port to the accumulator register. The port address is specified by the source operand, which can be DX or an 8-bit constant. Constants can be used only for port numbers less than 255; use DX for higher port numbers. In protected mode, a general-protection fault occurs if IN is used when the current privilege level is greater than the value of the IOPL flag. Flags Encoding No change 1110010w
Syntax IN accum,immed
data (1)
Examples
in ax,60h
CPU 88/86 286 386 486
Clock Cycles 10 (W88=14) 5 12,pm=6,26* 14,pm=9,29*
INC Increment
91
Encoding
1110110w
Syntax IN accum,DX Examples
in in ax,dx al,dx
CPU 88/86 286 386 486
Clock Cycles 8 (W88=12) 5 13,pm=7,27* 14,pm=8,28*
* First protected-mode timing: CPL IOPL. Second timing: CPL > IOPL. Takes 27 clocks in virtual 8086 mode.
INC Increment
Adds 1 to the destination operand. Because the operand is treated as an unsigned integer, the INC instruction does not affect the carry flag. If a signed carry requires detection, use the ADD instruction. Flags Encoding O D I T S Z A P C mod,000,r/m disp (0, 1, or 2)
1111111w
Syntax INC reg8
Examples
inc cl
INC mem
inc
vpage
Encoding
01000 reg
Syntax INC reg16 INC reg32* Examples
inc bx
CPU 88/86 286 386 486
* 8038680486 only.
92
INS/INSB/INSW/INSD Input from Port to String
INS/INSB/INSW/INSD Input from Port to String

80286-80486 Only Receives a string from a port. The string is considered the destination and must be pointed to by ES:DI (even if an operand is given). The input port is specified in DX. For each element received, DI is adjusted according to the size of the operand and the status of the direction flag. DI is increased if the direction flag has been cleared with CLD or decreased if the direction flag has been set with STD. If the INS form of the instruction is used, a destination operand must be provided to indicate the size of the data elements to be processed, and DX must be specified as the source operand containing the port number. A segment override is not allowed. If INSB (bytes), INSW (words), or INSD (doublewords on the 8038680486 only) is used, the instruction determines the size of the data elements to be received. INS and its variations are normally used with the REP prefix. Before the repeated instruction is executed, CX should contain the number of elements to be received. In protected mode, a general-protection fault occurs if INS is used when the current privilege level is greater than the value of the IOPL flag. Flags Encoding No change 0110110w
Syntax INS [ [ES:] dest, DX ] INSB [ [ES:] dest, DX] [[ ] ] INSW [ [ES:] dest, DX] [[ ] ] INSD [ [ES:] dest, DX] [[ ] ] Examples
ins rep rep rep es:instr,dx insb insw insd
CPU 88/86 286 386 486
Clock Cycles 5 15,pm=9,29* 17,pm=10,32*
* First protected-mode timing: CPL IOPL. Second timing: CPL > IOPL.
INT Interrupt
Generates a software interrupt. An 8-bit constant operand (0 to 255) specifies the interrupt procedure to be called. The call is made by indexing the interrupt number into the Interrupt Vector Table (IVT) starting at segment 0, offset 0. In real mode, the IVT contains 4-byte pointers to interrupt procedures. In privileged mode, the IVT contains 8-byte pointers. When an interrupt is called in real mode, the flags, CS, and IP are pushed onto the stack (in that order), and the trap and interrupt flags are cleared. STI can be
INTO Interrupt on Overflow
93
used to restore interrupts. See Intel documentation and the documentation for your operating system for details on using and defining interrupts in privileged mode. To return from an interrupt, use the IRET instruction. Flags Encoding O D I T S Z A P C 0 0 11001101
Syntax INT immed8
data (1)
Examples
int 25h
CPU 88/86 286 386 486
Clock Cycles 51 (88=71) 23+m,pm=(40,78)+m* 37,pm=59,99* 30,pm=44,71*
Encoding
11001100
Syntax INT 3 Examples
int 3
CPU 88/86 286 386 486
Clock Cycles 52 (88=72) 23+m,pm=(40,78)+m* 33,pm=59,99* 26,pm=44,71*
* The first protected-mode timing is for interrupts to the same privilege level. The second is for interrupts to a higher privilege level. Timings for interrupts through task gates are not shown.
INTO Interrupt on Overflow

Generates Interrupt 4 if the overflow flag is set. The default MS-DOS behavior for Interrupt 4 is to return without taking any action. For INTO to have any effect, you must define an interrupt procedure for Interrupt 4. Flags Encoding O D I T S Z A P C 11001110
Syntax INTO Examples
into
CPU 88/86 286 386 486
Clock Cycles 53 (88=73),noj=4 24+m,noj=3,pm=(40, 78)+m* 35,noj=3,pm=59,99* 28,noj=3,pm=46,73*
* The first protected-mode timing is for interrupts to the same privilege level. The second is for interrupts to a higher privilege level. Timings for interrupts through task gates are not shown.
94
INVD Invalidate Data Cache
INVD Invalidate Data Cache

80486 Only Empties contents of the current data cache without writing changes to memory. Proper use of this instruction requires knowledge of how contents are placed in the cache. INVD is intended primarily for system programming. See Intel documentation for details. Flags Encoding No change 00001111
Syntax INVD
00001000
Examples
invd
CPU 88/86 286 386 486
Clock Cycles 4
INVLPG Invalidate TLB Entry

80486 Only Invalidates an entry in the Translation Lookaside Buffer (TLB), used by the demand-paging mechanism in virtual-memory operating systems. The instruction takes a single memory operand and calculates the effective address of the operand, including the segment address. If the resulting address is mapped by any entry in the TLB, this entry is removed. Proper use of INVLPG requires understanding the hardware-supported demand-paging mechanism. INVLPG is intended primarily for system programming. See Intel documentation for details. Flags Encoding No change 00001111
Syntax INVLPG
00000001
mod, reg, r/m
disp (2)
CPU 88/86 286 386 486 Clock Cycles 12*
Examples
invlpg invlpg pointer[bx] es:entry
* 11 clocks if address is not mapped by any TLB entry.
Jcondition
Jump Conditionally
95
IRET/IRETD Interrupt Return

Returns control from an interrupt procedure to the interrupted code. In real mode, the IRET instruction pops IP, CS, and the flags (in that order) and resumes execution. See Intel documentation for details on IRET operation in privileged mode. On the 8038680486, the IRETD instruction should be used to pop a 32-bit instruction pointer when returning from an interrupt called from a 32-bit segment. The F suffix prevents epilogue code from being generated when ending a PROC block. Use it to terminate interrupt service procedures. Flags Encoding O D I T S Z A P C 11001111
Syntax IRET IRETD* IRETF IRETDF*
* 8038680486 only. The first protected-mode timing is for interrupts to the same privilege level within a task. The second is for interrupts to a higher privilege level within a task. Timings for interrupts through task gates are not shown.
Examples
iret
CPU 88/86 286 386 486
Clock Cycles 32 (88=44) 17+m,pm=(31,55)+m 22,pm=38,82 15,pm=20,36
Jcondition Jump Conditionally

Transfers execution to the specified label if the flags condition is true. The condition is tested by checking the flags shown in the table on the following page. If condition is false, no jump is taken and program execution continues at the next instruction. On the 808680286 processors, the label given as the operand must be short (between 128 and +127 bytes from the instruction following the jump).* The 8038680486 processors allow near jumps (32,768 to +32,767 bytes). On the 8038680486, the assembler generates the shortest jump possible, unless the jump size is explicitly specified. When the 8038680486 processors are in FLAT memory model, short jumps range from 128 to +127 bytes and near jumps range from 2 to +2 gigabytes. There are no far jumps. Flags No change
96
Jcondition
Jump Conditionally
Encoding
0111cond
Syntax
disp (1)
Examples
jg jo jpe bigger SHORT too_big p_even
CPU 88/86 286 386 486
Clock Cycles 16,noj=4 7+m,noj=3 7+m,noj=3 3,noj=1
Jcondition label
Encoding
00001111
Syntax
1000cond
disp (2)
CPU 88/86 286 386 486 Clock Cycles 7+m,noj=3 3,noj=1
Examples
je next jnae lesser js negative
Jcondition label
* If a source file for an 808680286 program contains a conditional jump outside the range of 128 to +127 bytes, the assembler emits a level 3 warning and generates two instructions (including an unconditional jump) that are the equivalent of the desired instruction. This behavior can be enabled and disabled with the OPTION LJMP and OPTION NOLJMP directives. Near labels are only available on the 8038680486. They are the default.
Jump Conditions
Opcode* size 0010 size 0011 size 0110 size 0111 size 0100 size 0101 size 1100 size 1101 size 1110 size 1111 size 1000 size 1001
Mnemonic JB/JNAE JAE/JNB JBE/JNA JA/JNBE JE/JZ JNE/JNZ JL/JNGE JGE/JNL JLE/JNG JG/JNLE JS JNS
Flags Checked CF=1 CF=0 CF=1 or ZF=1 CF=0 and ZF=0 ZF=1 ZF=0 SF_OF SF=OF ZF=1 or SF_OF ZF=0 and SF=OF SF=1 SF=0
Description Jump if below/not above or equal (unsigned comparisons) Jump if above or equal/not below (unsigned comparisons) Jump if below or equal/not above (unsigned comparisons) Jump if above/not below or equal (unsigned comparisons) Jump if equal (zero) Jump if not equal (not zero) Jump if less/not greater or equal (signed comparisons) Jump if greater or equal/not less (signed comparisons) Jump if less or equal/not greater (signed comparisons) Jump if greater/not less or equal (signed comparisons) Jump if sign Jump if not sign
JMP Opcode* size 0010 size 0011 size 0000 size 0001 size 1010 size 1011 Mnemonic JC JNC JO JNO JP/JPE JNP/JPO Flags Checked CF=1 CF=0 OF=1 OF=0 PF=1 PF=0
Jump Unconditionally
97
Description Jump if carry Jump if not carry Jump if overflow Jump if not overflow Jump if parity/parity even Jump if no parity/parity odd
* The size bits are 0111 for short jumps or 1000 for 8038680486 near jumps.
JCXZ/JECXZ Jump if CX is Zero

Transfers program execution to the specified label if CX is 0. On the 80386 80486, JECXZ can be used to jump if ECX is 0. If the count register is not 0, execution continues at the next instruction. The label given as the operand must be short (between 128 and +127 bytes from the instruction following the jump). Flags Encoding No change 11100011
Syntax JCXZ label JECXZ label*
disp (1)
Examples
jcxz not found
CPU 88/86 286 386 486
Clock Cycles 18,noj=6 8+m,noj=4 9+m,noj=5 8,noj=5
* 8038680486 only.
JMP Jump Unconditionally

Transfers program execution to the address specified by the destination operand. Jumps are near (between 32,768 and +32,767 bytes from the instruction following the jump), or short (between 128 and +127 bytes), or far (in a different code segment). Unless a distance is explicitly specified, the assembler selects the shortest possible jump. With near and short jumps, the operand specifies a new IP address. With far jumps, the operand specifies new IP and CS addresses.
98
JMP
Jump Unconditionally
When the 8038680486 processors are in FLAT memory model, short jumps range from 128 to +127 bytes and near jumps range from 2 to +2 gigabytes. Flags Encoding No change 11101011
Syntax JMP label
disp (1)
Examples
jmp SHORT exit
CPU 88/86 286 386 486
Clock Cycles 15 7+m 7+m 3
Encoding
11101001
Syntax JMP label
disp (2*)
Examples
jmp jmp close NEAR PTR distant
CPU 88/86 286 386 486
Clock Cycles 15 7+m 7+m 3
Encoding
11101010
Syntax JMP label
disp (4*)
Examples
jmp jmp FAR PTR close distant
CPU 88/86 286 386 486
Clock Cycles 15 11+m,pm=23+m 12+m,pm=27+m 17,pm=19
Encoding
11111111
Syntax
mod,100,r/m
disp (0 or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 11 7+m 7+m 5 18+EA 11+m 10+m 5
Examples
jmp ax
JMP reg16 JMP mem32
JMP mem16 JMP mem32
jmp jmp jmp
WORD PTR [bx] table[di] DWORD PTR [si]
LAR Load Access Rights
99
Encoding
11111111
Syntax
mod,101,r/m
disp (4*)
CPU 88/86 286 386 486 Clock Cycles 24+EA 15+m,pm=26+m 12+m,pm=27+m 13,pm=18
Examples
jmp jmp jmp fpointer[si] DWORD PTR [bx] FWORD PTR [di]
JMP mem32 JMP mem48
* On the 8038680486, the displacement can be 4 bytes for near jumps or 6 bytes for far jumps. Timings for jumps through call or task gates are not shown, since they are normally used only in operating systems. 8038680486 only. You can use DWORD PTR to specify near register-indirect jumps or FWORD PTR to specify far register-indirect jumps.
LAHF Load Flags into AH Register

Transfers bits 0 to 7 of the flags register to AH. This includes the carry, parity, auxiliary carry, zero, and sign flags, but not the trap, interrupt, direction, or overflow flags. Flags Encoding No change 10011111
Syntax LAHF Examples
lahf
CPU 88/86 286 386 486
LAR Load Access Rights

80286-80486 Protected Only Loads the access rights of a selector into a specified register. The source operand must be a register or memory operand containing a selector. The destination operand must be a register that will receive the access rights if the selector is valid and visible at the current privilege level. The zero flag is set if the access rights are transferred, or cleared if they are not. See Intel documentation for details on selectors, access rights, and other privileged-mode concepts.
100
LDS/LES/LFS/LGS/LSS
Load Far Pointer
Flags Encoding
O D I
T S Z A P C 00000010 mod, reg, r/m

Examples
lar ax,bx
00001111
Syntax
disp (0, 1, 2, or 4)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 14 15 11 16 16 11
LAR reg16,reg16 LAR reg32,reg32*
LAR reg16,mem16 LAR reg32,mem32*
lar
cx,selector
* 8038680486 only.
LDS/LES/LFS/LGS/LSS Load Far Pointer

Reads and stores the far pointer specified by the source memory operand. The instruction moves the pointers segment value into DS, ES, FS, GS, or SS (depending on the instruction). Then it moves the pointers offset value into the destination operand. The LDS and LES instructions are available on all processors. The LFS, LGS, and LSS instructions are available only on the 8038680486. Flags Encoding No change 11000101
Syntax LDS reg,mem
mod, reg, r/m
disp (2)
CPU 88/86 286 386 486 Clock Cycles 16+EA (88=24+EA) 7,pm=21 7,pm=22 6,pm=12
Examples
lds si,fpointer
Encoding
11000100
Syntax
mod, reg, r/m
disp (2)
CPU 88/86 286 386 486 Clock Cycles 16+EA (88=24+EA) 7,pm=21 7,pm=22 6,pm=12
Examples
les di,fpointer
LES reg,mem
LEA Load Effective Address
101
Encoding
00001111
Syntax LFS reg,mem
10110100
mod, reg, r/m
disp (2 or 4)
CPU 88/86 286 386 486 Clock Cycles 7,pm=25 6,pm=12
Examples
lfs edi,fpointer
Encoding
00001111
Syntax
10110101
mod, reg, r/m
disp (2 or 4)
Examples
lgs bx,fpointer
LGS reg,mem
Encoding
00001111
Syntax LSS reg,mem
10110010
mod, reg, r/m
disp (2 or 4)
Examples
lss bp,fpointer
LEA Load Effective Address

Calculates the effective address (offset) of the source memory operand and stores the result in the destination register. If the source operand is a direct memory address, the assembler encodes the instruction in the more efficient MOV reg,immediate form (equivalent to MOV reg, OFFSET mem). Flags Encoding No change 10001101
Syntax LEA reg16,mem LEA reg32,mem*
mod, reg, r/m
disp (2)
CPU 88/86 286 386 486 Clock Cycles 2+EA 3 2 1
Examples
lea bx,npointer
* 8038680486 only. 2 if index register used.
102
LEAVE High Level Procedure Exit
LEAVE High Level Procedure Exit

Terminates the stack frame of a procedure. LEAVE reverses the action of a previous ENTER instruction by restoring SP and BP to the values they had before the procedure stack frame was initialized. LEAVE is equivalent to mov sp,bp, followed by pop bp. Flags Encoding No change 11001001
Syntax LEAVE Examples
leave
CPU 88/86 286 386 486
Clock Cycles 5 4 5
LES/LFS/LGS Load Far Pointer to Extra Segment

See LDS.
LGDT/LIDT/LLDT Load Descriptor Table

Loads a value from an operand into a descriptor table register. LGDT loads into the Global Descriptor Table, LIDT into the Interrupt Vector Table, and LLDT into the Local Descriptor Table. These instructions are available only in privileged mode. See Intel documentation for details on descriptor tables and other protected-mode concepts. Flags Encoding No change 00001111
Syntax LGDT mem48
00000001
mod, 010,r/m
disp (2)
CPU 88/86 286 386 486 Clock Cycles 11 11 11
Examples
lgdt descriptor
LMSW Load Machine Status Word
103
Encoding
00001111
Syntax
00000001
mod, 011,r/m
disp (2)
CPU 88/86 286 386 486 Clock Cycles 12 11 11
Examples
lidt descriptor
LIDT mem48
Encoding
00001111
Syntax LLDT reg16
00000000
mod, 010,r/m
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 17 20 11 19 24 11
Examples
lldt ax
LLDT mem16
lldt
selector
LMSW Load Machine Status Word

80286-80486 Privileged Only Loads a value from a memory operand into the Machine Status Word (MSW). This instruction is available only in privileged mode. See Intel documentation for details on the MSW and other protectedmode concepts. Flags Encoding No change 00001111
Syntax LMSW reg16
00000001
mod, 110,r/m
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 3 10 13 6 13 13
Examples
lmsw ax
LMSW mem16
lmsw
machine
104
LOCK Lock the Bus
LOCK Lock the Bus

Locks out other processors during execution of the next instruction. This instruction is a prefix. It must precede an instruction that accesses a memory location that another processor might attempt to access at the same time. See Intel documentation for details on multiprocessor environments. Flags Encoding No change 11110000
Syntax LOCK instruction Examples
lock xchg ax,sem
CPU 88/86 286 386 486
LODS/LODSB/LODSW/LODSD Load Accumulator from String LODS/LODSB/LODSW/LODSD Load Accumulator from String Loads the accumulator register with an element from a string in memory. DS:SI
must point to the source element, even if an operand is given. For each source element loaded, SI is adjusted according to the size of the operand and the status of the direction flag. SI is incremented if the direction flag has been cleared with CLD or decremented if the direction flag has been set with STD. If the LODS form of the instruction is used, an operand must be provided to indicate the size of the data elements to be processed. A segment override can be given. If LODSB (bytes), LODSW (words), or LODSD (doublewords on the 8038680486 only) is used, the instruction determines the size of the data elements to be processed and whether the element will be loaded to AL, AX, or EAX. LODS and its variations are not used with repeat prefixes, since there is no reason to repeatedly load memory values to a register. Flags No change
LOOPcondition/LOOPconditionW/LOOPconditionD Loop Conditionally
105
Encoding
1010110w
Syntax LODS [ [segreg:] ]src LODSB [ [segreg:] ] [[ ]src] LODSW[ [segreg:] ] [[ ]src] LODSD [ [segreg:] ] [[ ]src] Examples
lods es:source lodsw
CPU 88/86 286 386 486
Clock Cycles 12 (W88=16) 5 5 5
LOOP/LOOPW/LOOPD Loop
Loops repeatedly to a specified label. LOOP decrements CX (without changing any flags) and, if the result is not 0, transfers execution to the address specified by the operand. On the 8038680486, LOOP uses the 16-bit CX in 16-bit mode and the 32-bit ECX in 32-bit mode. The default can be overridden with LOOPW (CX) or LOOPD (ECX). If CX is 0 after being decremented, execution continues at the next instruction. The operand must specify a short label (between 128 and +127 bytes from the instruction following the LOOP instruction). Flags Encoding No change 11100010
Syntax LOOP label LOOPW label* LOOPD label*
* 8038680486 only.
disp (1)
Examples
loop wend
CPU 88/86 286 386 486
Clock Cycles 17,noj=5 8+m,noj=4 11+m 7,noj=6
LOOPcondition/LOOPconditionW/LOOPconditionD Loop Conditionally

Loops repeatedly to a specified label if condition is met and if CX is not 0. On the 8038680486, these instructions use the 16-bit CX in 16-bit mode and the 32-bit ECX in 32-bit mode. This default can be overridden with the W (CX) or D (ECX) forms of the instruction. The instruction decrements CX (without changing any flags) and tests whether the zero flag was set by a previous instruction (such as CMP). With LOOPE and LOOPZ (they are synonyms),
106
LSL
Load Segment Limit
execution is transferred to the label if the zero flag is set and CX is not 0. With LOOPNE and LOOPNZ (they are synonyms), execution is transferred to the label if the zero flag is cleared and CX is not 0. Execution continues at the next instruction if the condition is not met. Before entering the loop, CX should be set to the maximum number of repetitions desired. Flags Encoding No change 11100001
Syntax LOOPE label LOOPEW label* LOOPED label* LOOPZ label LOOPZW label* LOOPZD label*
disp (1)
Examples
loopz again
CPU 88/86 286 386 486
Clock Cycles 18,noj=6 8+m,noj=4 11+m 9,noj=6
Encoding
11100000
Syntax
disp (1)
Examples
loopnz for_next
CPU 88/86 286 386 486
Clock Cycles 19,noj=5 8,noj=4 11+m 9,noj=6
LOOPNE label LOOPNEW label* LOOPNED label* LOOPNZ label LOOPNZW label* LOOPNZD label*
* 8038680486 only.
LSL Load Segment Limit

80286-80486 Protected Only Loads the segment limit of a selector into a specified register. The source operand must be a register or memory operand containing a selector. The destination operand must be a register that will receive the segment limit if the selector is valid and visible at the current privilege level. The zero flag is set if the segment limit is transferred, or cleared if it is not. See Intel documentation for details on selectors, segment limits, and other protectedmode concepts. Flags O D I T S Z A P C
LTR Load Task Register
107
Encoding
00001111
Syntax
00000011
mod, reg, r/m

Examples
lsl ax,bx
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 14 20,25 10 16 21,26 10
LSL reg16,reg16 LSL reg32,reg32*
LSL reg16,mem16 LSL reg32,mem32*
lsl
cx,seg_lim
* 8038680486 only. The first value is for byte granular; the second is for page granular.
LSS Load Far Pointer to Stack Segment

See LDS.
LTR Load Task Register

80286-80486 Protected Only Loads a value from the specified operand to the current task register. LTR is available only in privileged mode. See Intel documentation for details on task registers and other protected-mode concepts. Flags Encoding No change 00001111
Syntax LTR reg16
00000000
mod, 011,r/m
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 17 23 20 19 27 20
Examples
ltr ax
LTR mem16
ltr
task
108
MOV Move Data
MOV Move Data

Moves the value in the source operand to the destination operand. If the destination operand is SS, interrupts are disabled until the next instruction is executed (except on early versions of the 8088 and 8086). Flags Encoding No change 100010dw
Syntax MOV reg,reg
mod, reg, r/m
disp (0, 1, or 2)
Examples
mov mov mov mov mov dh,bh dx,cx bp,sp array[di],bx count,cx
MOV mem,reg
MOV reg,mem
mov mov
bx,pointer dx,matrix[bx+di]
Encoding
1100011w
Syntax
mod, 000,r/m
disp (0, 1, or 2)
data (1 or 2)
CPU 88/86 286 386 486 Clock Cycles 10+EA (W88=14+EA) 3 2 1
Examples
mov mov [bx],15 color,7
MOV mem,immed
Encoding
1011w reg
Syntax
data (1 or 2)
Examples
mov mov cx,256 dx,OFFSET string
CPU 88/86 286 386 486
MOV reg,immed
MOV Move to/from Special Registers
109
Encoding
101000aw
Syntax
disp (2)
Examples
mov total,ax
CPU 88/86 286 386 486 88/86 286 386 486
Clock Cycles 10 (W88=14) 3 2 1 10 (W88=14) 5 4 1
MOV mem,accum
MOV accum,mem
mov
al,string
Encoding
100011d0
Syntax
mod,sreg, r/m
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486 Clock Cycles 2 2,pm=17 2,pm=18 3,pm=9 8+EA (88=12+EA) 5,pm=19 5,pm=19 3,pm=9 2 2 2 3 9+EA (88=13+EA) 3 2 3
Examples
mov ds,ax
MOV segreg,reg16
MOV segreg,mem16
mov
es,psp
MOV reg16,segreg
mov
ax,ds
MOV mem16,segreg
mov
stack_save,ss

8038680486 Only Moves a value from a special register to or from a 32-bit general-purpose register. The special registers include the control registers CR0, CR2, and CR3; the debug registers DR0, DR1, DR2, DR3, DR6, and DR7; and the test registers TR6 and TR7. On the 80486, the test registers TR3, TR4, and TR5 are also available. See Intel documentation for details on special registers. Flags O D I ? T S Z A P C ? ? ? ? ?
110
Encoding
00001111
Syntax
001000d0
11, reg*, r/m

Examples
mov eax,cr2
CPU 88/86 286 386 486 88/86 286 386 486
Clock Cycles 6 4 CR0=10,CR2=4,CR3= 5 4,CR0=16
MOV reg32, controlreg
MOV controlreg,reg32
mov
cr0,ebx
Encoding
00001111
Syntax
001000d1
11, reg*, r/m

Examples
mov edx,dr3
CPU 88/86 286 386 486 88/86 286 386 486
Clock Cycles DR03=22,DR67=14 10 DR03=22,DR67=16 11
MOV reg32,debugreg
MOV debugreg,reg32
mov
dr0,ecx
Encoding
00001111
Syntax
001001d0
11,reg*, r/m
Examples
mov edx,tr6
CPU 88/86 286 386 486 88/86 286 386 486
Clock Cycles 12 4,TR3=3 12 4,TR3=6
MOV reg32,testreg
MOV testreg, reg32
mov
tr7,eax
* The reg field contains the register number of the special register (for example, 000 for CR0, 011 for DR7, or 111 for TR7).
MOVSX Move with Sign-Extend
111
MOVS/MOVSB/MOVSW/MOVSD Move String Data

Moves a string from one area of memory to another. DS:SI must point to the source string and ES:DI to the destination address, even if operands are given. For each element moved, DI and SI are adjusted according to the size of the operands and the status of the direction flag. They are increased if the direction flag has been cleared with CLD, or decreased if the direction flag has been set with STD. If the MOVS form of the instruction is used, operands must be provided to indicate the size of the data elements to be processed. A segment override can be given for the source operand (but not for the destination). If MOVSB (bytes), MOVSW (words), or MOVSD (doublewords on the 8038680486 only) is used, the instruction determines the size of the data elements to be processed. MOVS and its variations are normally used with the REP prefix. Flags Encoding
Syntax MOVS [ [ES:] ]dest,[ [segreg:] ]src MOVSB [ [ES:] [[ ]dest,[ [segreg:] ] ]src] MOVSW [ [ES:] [[ ]dest,[ [segreg:] ] ]src] MOVSD [ [ES:] [[ ]dest,[ [segreg:] ] ]src]
No change 1010010w
Examples
rep movs movsb dest,es:source
CPU 88/86 286 386 486
MOVSX Move with Sign-Extend

8038680486 Only Moves and sign-extends the value of the source operand to the destination register. MOVSX is used to copy a signed 8-bit or 16-bit source operand to a larger 16-bit or 32-bit destination register. Flags Encoding No change 00001111
Syntax MOVSX reg,reg
1011111w
mod, reg, r/m
disp (0, 1, 2, or 4)
CPU 88/86 286 386 486 Clock Cycles 3 3
Examples
movsx movsx movsx eax,bx ecx,bl bx,al
112
MOVZX Move with Zero-Extend Syntax MOVSX reg,mem Examples

movsx movsx movsx cx,bsign edx,wsign eax,bsign
CPU 88/86 286 386 486
Clock Cycles 6 3
MOVZX Move with Zero-Extend

8038680486 Only Moves and zero-extends the value of the source operand to the destination register. MOVZX is used to copy an unsigned 8-bit or 16-bit source operand to a larger 16-bit or 32-bit destination register. Flags Encoding No change 00001111
Syntax MOVZX reg,reg
1011011w
mod, reg, r/m
disp (0, 1, 2, or 4)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 3 3 6 3
Examples
movzx movzx movzx movzx movzx movzx eax,bx ecx,bl bx,al cx,bunsign edx,wunsign eax,bunsign
MOVZX reg,mem
MUL Unsigned Multiply

Multiplies an implied destination operand by a specified source operand. Both operands are treated as unsigned numbers. If a single 16-bit operand is given, the implied destination is AX and the product goes into the DX:AX register pair. If a single 8-bit operand is given, the implied destination is AL and the product goes into AX. On the 8038680486, if the operand is EAX, the product goes into the EDX:EAX register pair. The carry and overflow flags are set if DX is not 0 for 16-bit operands or if AH is not 0 for 8-bit operands. Flags O D I T S Z A P C ? ? ? ?
NEG Twos Complement Negation
113
Encoding
1111011w
Syntax MUL reg
mod, 100, r/m

Examples
mul mul bx dl
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles b=7077,w=118133 b=13,w=21 b=914,w=922,d=938* b=1318,w=1326,d=1342 (b=7683,w=124139)+EA b=16,w=24 b=1217,w=1225,d=1241* b=1318,w=1326,d=1342
MUL mem
mul mul
factor WORD PTR [bx]
* The 8038680486 processors have an early-out multiplication algorithm. Therefore, multiplying an 8-bit or 16-bit value in EAX takes the same time as multiplying the value in AL or AX. Word memory operands on the 8088 take (128143)+EA clocks.
NEG Twos Complement Negation

Replaces the operand with its twos complement. NEG does this by subtracting the operand from 0. If the operand is 0, the carry flag is cleared. Otherwise, the carry flag is set. If the operand contains the maximum possible negative value ( 128 for 8-bit operands or 32,768 for 16-bit operands), the value does not change, but the overflow and carry flags are set. Flags Encoding O D I T S Z A P C mod, 011, r/m
Examples
neg ax
1111011w
Syntax NEG reg
disp (0, 1, or 2)
NEG mem
neg
balance
114
NOP No Operation
NOP No Operation
Performs no operation. NOP can be used for timing delays or alignment. Flags Encoding No change 10010000*
Syntax NOP Examples
nop
CPU 88/86 286 386 486
* The encoding is the same as XCHG AX,AX.
NOT Ones Complement Negation

Toggles each bit of the operand by clearing set bits and setting cleared bits. Flags Encoding No change 1111011w
Syntax NOT reg
mod, 010, r/m

Examples
not ax
disp (0,1,or2)
NOT mem
not
masker
OR Inclusive OR
115
OR Inclusive OR
Performs a bitwise OR operation on the source and destination operands and stores the result to the destination operand. For each bit position in the operands, if either or both bits are set, the corresponding bit of the result is set. Otherwise, the corresponding bit of the result is cleared. Flags Encoding O D I 0 T S Z A P C ? 0 mod, reg, r/m disp (0, 1, or 2)
000010dw
Syntax OR reg,reg
Examples
or ax,dx
OR mem,reg
or or
bits,dx [bp+6],cx
OR reg,mem
or or
bx,masker dx,color[di]
Encoding
100000sw
Syntax
mod,001, r/m
disp (0, 1, or 2)
data (1 or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 4 3 2 1 (b=17,w=25)+EA 7 7 3
Examples
or dx,110110b
OR reg,immed
OR mem,immed
or
flag_rec,8
Encoding
0000110w
Syntax
data (1 or 2)
Examples
or ax,40h
CPU 88/86 286 386 486
OR accum,immed
116
OUT Output to Port
OUT Output to Port

Transfers a byte or word (or a doubleword on the 8038680486) to a port from the accumulator register. The port address is specified by the destination operand, which can be DX or an 8-bit constant. In protected mode, a generalprotection fault occurs if OUT is used when the current privilege level is greater than the value of the IOPL flag. Flags Encoding No change 1110011w
Syntax OUT immed8,accum
data (1)
Examples
out 60h,al
CPU 88/86 286 386 486
Clock Cycles 10 (88=14) 3 10,pm=4,24* 16,pm=11,31*
Encoding
1110111w
Syntax OUT DX,accum Examples
out out dx,ax dx,al
CPU 88/86 286 386 486
Clock Cycles 8 (88=12) 3 11,pm=5,25* 16,pm=10,30*
* First protected-mode timing: CPL < IOPL. Second timing: CPL > IOPL.
OUTS/OUTSB/OUTSW/OUTSD Output String to Port

8018680486 Only Sends a string to a port. The string is considered the source and must be pointed to by DS:SI (even if an operand is given). The output port is specified in DX. For each element sent, SI is adjusted according to the size of the operand and the status of the direction flag. SI is increased if the direction flag has been cleared with CLD, or decreased if the direction flag has been set with STD. If the OUTS form of the instruction is used, an operand must be provided to indicate the size of data elements to be sent. A segment override can be given. If OUTSB (bytes), OUTSW (words), or OUTSD (doublewords on the 80386 80486 only) is used, the instruction determines the size of the data elements to be sent.
POP
Pop
117
OUTS and its variations are normally used with the REP prefix. Before the instruction is executed, CX should contain the number of elements to send. In protected mode, a general-protection fault occurs if OUTS is used when the current privilege level is greater than the value of the IOPL flag. Flags Encoding No change 0110111w
Syntax OUTS DX, [ [segreg:] src ] OUTSB [ [DX, [ [segreg:] src] ] ] OUTSW [ [DX, [ [segreg:] src] ] ] OUTSD [ [DX, [ [segreg:] src] ] ] Examples
rep outs dx,buffer outsb rep outsw
CPU 88/86 286 386 486
Clock Cycles 5 14,pm=8,28* 17,pm=10,32*
* First protected-mode timing: CPL < IOPL. Second timing: CPL > IOPL.
POP Pop
Pops the top of the stack into the destination operand. The value at SS:SP is copied to the destination operand and SP is increased by 2. The destination operand can be a memory location, a general-purpose 16-bit register, or any segment register except CS. Use RET to pop CS. On the 8038680486, 32-bit values can be popped by giving a 32-bit operand. ESP is increased by 4 for 32bit pops. Flags Encoding No change 01011 reg
Syntax POP reg16 POP reg32* Examples
pop cx
CPU 88/86 286 386 486
Clock Cycles 8 (88=12) 5 4 1
Encoding
10001111
Syntax
mod,000,r/m
disp (2)
CPU 88/86 286 386 486 Clock Cycles 17+EA (88=25+EA) 5 5 6
Examples
pop param
POP mem16 POP mem32*
118
POPA/POPAD Pop All
Encoding
000,sreg,111
Syntax POP segreg Examples
pop pop pop es ds ss
CPU 88/86 286 386 486
Clock Cycles 8 (88=12) 5,pm=20 7,pm=21 3,pm=9
Encoding
00001111
Syntax POP segreg*
10,sreg,001
Examples
pop pop fs gs
CPU 88/86 286 386 486
Clock Cycles 7,pm=21 3,pm=9
* 8038680486 only.
POPA/POPAD Pop All

80186-80486 Only Pops the top 16 bytes on the stack into the eight generalpurpose registers. The registers are popped in the following order: DI, SI, BP, SP, BX, DX, CX, AX. The value for the SP register is actually discarded rather than copied to SP. POPA always pops into 16-bit registers. On the 80386 80486, use POPAD to pop into 32-bit registers. Flags Encoding No change 01100001
Syntax POPA POPAD* Examples
popa
CPU 88/86 286 386 486
Clock Cycles 19 24 9
* 8038680486 only.
PUSH/PUSHW/PUSHD Push
119
POPF/POPFD Pop Flags

Pops the value on the top of the stack into the flags register. POPF always pops into the 16-bit flags register. On the 8038680486, use POPFD to pop into the 32-bit flags register. Flags Encoding O D I T S Z A P C 10011101
Syntax POPF POPFD* Examples
popf
CPU 88/86 286 386 486
Clock Cycles 8 (88=12) 5 5 9,pm=6
* 8038680486 only.
PUSH/PUSHW/PUSHD Push
Pushes the source operand onto the stack. SP is decreased by 2 and the source value is copied to SS:SP. The operand can be a memory location, a generalpurpose 16-bit register, or a segment register. On the 8018680486 processors, the operand can also be a constant. On the 8038680486, 32-bit values can be pushed by specifying a 32-bit operand. ESP is decreased by 4 for 32-bit pushes. On the 8088 and 8086, PUSH SP saves the value of SP after the push. On the 8018680486 processors, PUSH SP saves the value of SP before the push. The PUSHW and PUSHD instructions push a word (2 bytes) and a doubleword (4 bytes), respectively. Flags Encoding No change 01010 reg
Syntax PUSH reg16 PUSH reg32* PUSHW reg16 PUSHD reg32* Examples
push dx
CPU 88/86 286 386 486
Clock Cycles 11 (88=15) 3 2 1
120
PUSHA/PUSHAD Push All
Encoding
11111111
Syntax
mod, 110,r/m
disp (2)
CPU 88/86 286 386 486 Clock Cycles 16+EA (88=24+EA) 5 5 4
Examples
push push [di] fcount
PUSH mem16 PUSH mem32*
Encoding
00,sreg,110
Syntax PUSH segreg PUSHW segreg PUSHD segreg* Examples
push push push es ss cs
CPU 88/86 286 386 486
Clock Cycles 10 (88=14) 3 2 3
Encoding
00001111
Syntax
10,sreg,000
Examples
push push fs gs
CPU 88/86 286 386 486
Clock Cycles 2 3
PUSH segreg PUSHW segreg PUSHD segreg*
Encoding
011010s0
Syntax
data (1 or 2)
Examples
push push 'a' 15000
CPU 88/86 286 386 486
Clock Cycles 3 2 1
PUSH immed PUSHW immed PUSHD immed*
* 8038680486 only.
PUSHA/PUSHAD Push All

8018680486 Only Pushes the eight general-purpose registers onto the stack. The registers are pushed in the following order: AX, CX, DX, BX, SP, BP, SI, DI. The value pushed for SP is the value before the instruction. PUSHA always pushes 16-bit registers. On the 8038680486, use PUSHAD to push 32-bit registers. Flags No change
RCL/RCR/ROL/ROR Rotate
121
Encoding
01100000
Syntax PUSHA PUSHAD* Examples
pusha
CPU 88/86 286 386 486
* 8038680486 only.
PUSHF/PUSHFD Push Flags

Pushes the flags register onto the stack. PUSHF always pushes the 16-bit flags register. On the 8038680486, use PUSHFD to push the 32-bit flags register. Flags Encoding No change 10011100
Syntax PUSHF PUSHFD* Examples
pushf
CPU 88/86 286 386 486
Clock Cycles 10(88=14) 3 4 4,pm=3
* 8038680486 only.
Rotates the bits in the destination operand the number of times specified in the source operand. RCL and ROL rotate the bits left; RCR and ROR rotate right. ROL and ROR rotate the number of bits in the operand. For each rotation, the leftmost or rightmost bit is copied to the carry flag as well as rotated. RCL and RCR rotate through the carry flag. The carry flag becomes an extension of the operand so that a 9-bit rotation is done for 8-bit operands, or a 17-bit rotation for 16-bit operands. On the 8088 and 8086, the source operand can be either CL or 1. On the 8018680486, the source operand can be CL or an 8-bit constant. On the 8018680486, rotate counts larger than 31 are masked off, but on the 8088 and 8086, larger rotate counts are performed despite the inefficiency involved. The
122
overflow flag is modified only by single-bit variations of the instruction; for multiple-bit variations, the overflow flag is undefined. Flags Encoding O D I T S Z A P C mod, TTT*,r/m
Examples
ror rol ax,1 dl,1
1101000w
Syntax ROL reg,1 ROR reg,1
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486 Clock Cycles 2 2 3 3 2 2 9 3 15+EA (W88=23+EA) 7 7 4 15+EA (W88=23+EA 7 10 4
RCL reg,1 RCR reg,1
rcl rcr
dx,1 bl,1
ROL mem,1 ROR mem,1
ror rol
bits,1 WORD PTR [bx],1
RCL mem,1 RCR mem,1
rcl rcr
WORD PTR [si],1 WORD PTR m32[0],1
Encoding
1101001w
Syntax ROL reg,CL ROR reg,CL
mod, TTT*,r/m
Examples
ror rol
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486 Clock Cycles 8+4n 5+n 3 3 8+4n 5+n 9 830 20+EA+4n (W88=28+EA+4n) 8+n 7 4
ax,cl dx,cl
RCL reg,CL RCR reg,CL
rcl rcr
dx,cl bl,cl
ROL mem,CL ROR mem,CL
ror rol
color,cl WORD PTR [bp+6],cl
REP Repeat String Syntax RCL mem,CL RCR mem,CL Examples

rcr rcl WORD PTR [bx+di],cl masker
123
CPU 88/86 286 386 486
Clock Cycles 20+EA+4n (W88=28+EA+4n) 8+n 10 931
Encoding
1100000w
Syntax
mod,TTT*,r/m
Examples
rol ror
disp (0, 1, or 2)
data (1)
CPU 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486 Clock Cycles 5+n 3 2 5+n 9 830 8+n 7 4 8+n 10 931
ROL reg,immed8 ROR reg,immed8
ax,13 bl,3 286
RCL reg,immed8 RCR reg,immed8
rcl rcr
bx,5 si,9
ROL mem,immed8 ROR mem,immed8
rol ror
BYTE PTR [bx],10 bits,6
RCL mem,immed8 RCR mem,immed8
rcl rcr
WORD PTR [bp+8], masker,3
* TTT represents one of the following bit codes: 000 for ROL, 001 for ROR, 010 for RCL, or 011 for RCR.
REP Repeat String

Repeats a string instruction the number of times indicated by CX. First, CX is compared to 0; if it equals 0, execution proceeds to the next instruction. Otherwise, CX is decremented, the string instruction is performed, and the loop continues. REP is used with MOVS and STOS. REP also can be used with INS and OUTS on the 8018680486 processors. On all processors except the 8038680486, combining a repeat prefix with a segment override can cause errors if an interrupt occurs. Flags No change
124
REP Repeat String
Encoding
11110011
Syntax
1010010w
Examples
rep rep movs source,dest movsw
CPU 88/86 286 386 486
Clock Cycles 9+17n (W88=9+25n) 5+4n 7+4n 12+3n#
REP MOVS dest,src REP MOVSB [ [dest,src] ] REP MOVSW [ [dest,src] ] REP MOVSD [ [dest,src] ]*
Encoding
11110011
Syntax
1010101w
Examples
rep rep stosb stos dest
CPU 88/86 286 386 486
Clock Cycles 9+10n (W88=9+14n) 4+3n 5+5n 7+4n
REP STOS dest REP STOSB [ [dest] ] REP STOSW [ [dest] ] REP STOSD [ [dest] ]*
Encoding
11110011
Syntax
1010101w
Examples
rep rep lodsb lods dest
CPU 88/86 286 386 486
Clock Cycles 7+4n
REP LODS dest REP LODSB [ [dest] ] REP LODSW [ [dest] ] REP LODSD [ [dest] ]*
Encoding
11110011
Syntax
0110110w
Examples
rep rep insb ins dest,dx
CPU 88/86 286 386 486
Clock Cycles 5+4n 13+6n,pm=(7,27)+6n 16+8n,pm=(10,30)+8n
REP INS dest,DX REP INSB [ [dest,DX] ] REP INSW [ [dest,DX] ] REP INSD [ [dest,DX] ]*
Encoding
11110011
Syntax
0110111w
Examples
rep rep outs dx,source outsw
CPU 88/86 286 386 486
Clock Cycles 5+4n 12+5n,pm=(6,26)+5n 17+5n,pm=(11,31)+5n
REP OUTS DX,src REP OUTSB [ ] [src] REP OUTSW [ ] [src] REP OUTSD [ ]* [src]
* 8038680486 only. # 5 if n = 0, 13 if n = 1. 5 if n = 0.
First protected-mode timing: CPL IOPL. Second timing: CPL > IOPL.
REPcondition Repeat String Conditionally
125
REPcondition Repeat String Conditionally

Repeats a string instruction as long as condition is true and the maximum count has not been reached. REPE and REPZ (they are synonyms) repeat while the zero flag is set. REPNE and REPNZ (they are synonyms) repeat while the zero flag is cleared. The conditional-repeat prefixes should only be used with SCAS and CMPS, since these are the only string instructions that modify the zero flag. Before executing the instruction, CX should be set to the maximum allowable number of repetitions. First, CX is compared to 0; if it equals 0, execution proceeds to the next instruction. Otherwise, CX is decremented, the string instruction is performed, and the loop continues. On all processors except the 8038680486, combining a repeat prefix with a segment override may cause errors if an interrupt occurs during a string operation. Flags Encoding O D I 11110011
Syntax REPE CMPS src,dest REPE CMPSB [ [src,dest] ] REPE CMPSW [ [src,dest] ] REPE CMPSD [ [src,dest] ]*
T S Z A P C 1010011w
Examples
repz cmpsb repe cmps src,dest
CPU 88/86 286 386 486
Encoding
11110011
Syntax
1010111w
Examples
repe repz scas dest scasw
CPU 88/86 286 386 486
REPE SCAS dest REPE SCASB [ [dest] ] REPE SCASW [ [dest] ] REPE SCASD [ [dest] ]*
Encoding
11110010
Syntax
1010011w
Examples
repne cmpsw repnz cmps src,dest
CPU 88/86 286 386 486
REPNE CMPS src,dest REPNE CMPSB [ [src,dest] ] REPNE CMPSW [ [src,dest] ] REPNE CMPSD [ [src,dest] ]*
126
RET/RETN/RETF Return from Procedure
Encoding
11110010
Syntax
1010111w
Examples
repne scas dest repnz scasb
CPU 88/86 286 386 486
Clock Cycles 9+15n (W88=9+19n) 5+8n 5+8n 7+5n*
REPNE SCAS des REPNE SCASB [ [dest] ] REPNE SCASW [ [dest] ] REPNE SCASD [ [dest] ]*
* 8038680486 only. # 5 if n=0.
RET/RETN/RETF Return from Procedure

Returns from a procedure by transferring control to an address popped from the top of the stack. A constant operand can be given indicating the number of additional bytes to release. The constant is normally used to adjust the stack for arguments pushed before the procedure was called. The size of a return (near or far) is the size of the procedure in which the RET is defined with the PROC directive. RETN can be used to specify a near return; RETF can specify a far return. A near return pops a word into IP. A far return pops a word into IP and then pops a word into CS. After the return, the number of bytes given in the operand (if any) is added to SP. Flags Encoding No change 11000011
Syntax RET RETN Examples
ret retn
CPU 88/86 286 386 486
Clock Cycles 16 (88=20) 11+m 10+m 5
Encoding
11000010
Syntax
data (2)
Examples
ret retn 2 8
CPU 88/86 286 386 486
Clock Cycles 20 (88=24) 11+m 10+m 5
RET immed16 RETN immed16
SAHF Store AH into Flags
127
Encoding
11001011
Syntax RET RETF Examples
ret retf
CPU 88/86 286 386 486
Clock Cycles 26 (88=34) 15+m,pm=25+m,55* 18+m,pm=32+m,62* 13,pm=18,33*
Encoding
11001010
Syntax
data (2)
Examples
ret retf 8 32
CPU 88/86 286 386 486
Clock Cycles 25 (88=33) 15+m,pm=25+m,55* 18+m,pm=32+m,68* 14,pm=17,33*
RET immed16 RETF immed16
* The first protected-mode timing is for a return to the same privilege level; the second is for a return to a lesser privilege level.
ROL/ROR Rotate
See RCL/RCR.
SAHF Store AH into Flags

Transfers AH into bits 0 to 7 of the flags register. This includes the carry, parity, auxiliary carry, zero, and sign flags, but not the trap, interrupt, direction, or overflow flags. Flags Encoding O D I T S Z A P C
10011110
Syntax SAHF Examples
sahf
CPU 88/86 286 386 486
128
SAL/SAR Shift
SAL/SAR Shift
See SHL/SHR/SAL/SAR.
SBB Subtract with Borrow

Adds the carry flag to the second operand, then subtracts that value from the first operand. The result is assigned to the first operand. SBB is used to subtract the least significant portions of numbers that must be processed in multiple registers. Flags Encoding O D I T S Z A P C mod, reg, r/m disp (0, 1, or 2)
000110dw
Syntax SBB reg,reg
Examples
sbb dx,cx
SBB mem,reg
sbb
WORD PTR m32[2],dx
SBB reg,mem
sbb
dx,WORD PTR m32[2]
Encoding
100000sw
Syntax
mod,011, r/m
disp (0, 1, or 2)
data (1 or 2)
Examples
sbb dx,45
SBB reg,immed
SBB mem,immed
sbb
WORD PTR m32[2],40
SCAS/SCASB/SCASW/SCASD Scan String Flags
129
Encoding
0001110w
Syntax
data (1 or 2)
Examples
sbb ax,320 88/86
CPU 4 86 386 486
Clock Cycles 3 2 1
SBB accum,immed
SCAS/SCASB/SCASW/SCASD Scan String Flags

Scans a string to find a value specified in the accumulator register. The string to be scanned is considered the destination. ES:DI must point to that string, even if an operand is specified. For each element, the destination element is subtracted from the accumulator value and the flags are updated to reflect the result (although the result is not stored). DI is adjusted according to the size of the operands and the status of the direction flag. DI is increased if the direction flag has been cleared with CLD, or decreased if the direction flag has been set with STD. If the SCAS form of the instruction is used, an operand must be provided to indicate the size of the data elements to be processed. No segment override is allowed. If SCASB (bytes), SCASW (words), or SCASD (doublewords on the 8038680486 only) is used, the instruction determines the size of the data elements to be processed and whether the element scanned for is in AL, AX, or EAX. SCAS and its variations are normally used with repeat prefixes. REPNE (or REPNZ) is used to find the first element in a string that matches the value in the accumulator register. REPE (or REPZ) is used to find the first mismatch. Before the scan, CX should contain the maximum number of elements to scan. After a REPNE SCAS, the zero flag is clear if the string does not contain the accumulator value. After a REPE SCAS, the zero flag is set if the string contains nothing but the accumulator value. When the instruction finishes, ES:DI points to the element that follows (if the direction flag is clear) or precedes (if the direction flag is set) the match or mismatch. If CX decrements to 0, ES:DI points to the element that follows or precedes the last comparison. The zero flag is set or clear according to the result of the last comparison, not according to the value of CX. Flags O D I T S Z A P C
130
SETcondition
Set Conditionally
Encoding
1010111w
Syntax SCAS [ [ES:] dest ] SCASB [ [ES:] dest] [[ ] ] SCASW [ [ES:] dest] [[ ] ] SCASD [ [ES:] dest] [[ ] ]*
* 8038680486 only
Examples
repne repe scas scasw scasb es:destin
CPU 88/86 286 386 486
SETcondition Set Conditionally

8038680486 Only Sets the byte specified in the operand to 1 if condition is true or to 0 if condition is false. The condition is tested by checking the flags shown in the table on the following page. The instruction is used to set Boolean flags conditionally. Flags Encoding No change 00001111
Syntax SETcondition reg8
1001cond
mod,000,r/m
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 4 true=4, false=3 5 true=3, false=4
Examples
setc setz setae seto setle sete dh al bl BTYE PTR [ebx] flag Booleans[di]
SETcondition mem8
Set Conditions
Opcode 10010010 10010011 10010110 10010111 10010100 10010101 Opcode
Mnemonic SETB/SETNAE SETAE/SETNB SETBE/SETNA SETA/SETNBE SETE/SETZ SETNE/SETNZ Mnemonic
Flags Checked CF=1 CF=0 CF=1 or ZF=1 CF=0 and ZF=0 ZF=1 ZF=0 Flags Checked
Description Set if below/not above or equal (unsigned comparisons) Set if above or equal/not below (unsigned comparisons) Set if below or equal/not above (unsigned comparisons) Set if above/not below or equal (unsigned comparisons) Set if equal/zero Set if not equal/not zero Description
SGDT/SIDT/SLDT Store Descriptor Table 10011100 10011101 10011110 10011111 10011000 10011001 10010010 10010011 10010000 10010001 10011010 10011011 SETL/SETNGE SETGE/SETNL SETLE/SETNG SETG/SETNLE SETS SETNS SETC SETNC SETO SETNO SETP/SETPE SETNP/SETPO SF_OF SF=OF ZF=1 or SF_OF ZF=0 and SF=OF SF=1 SF=0 F=1 CF=0 OF=1 OF=0 PF=1 PF=0 Set if less/not greater or equal (signed comparisons) Set if greater or equal/not less (signed comparisons)
131
Set if less or equal/not greater or equal (signed comparisons) Set if greater/not less or equal (signed comparisons) Set if sign Set if not sign Set if carry Set if not carry Set if overflow Set if not overflow Set if parity/parity even Set if no parity/parity odd
SGDT/SIDT/SLDT Store Descriptor Table

80286-80486 Only Stores a descriptor table register into a specified operand. SGDT stores the Global Descriptor Table; SIDT, the Interrupt Vector Table; and SLDT, the Local Descriptor Table. These instructions are generally useful only in privileged mode. See Intel documentation for details on descriptor tables and other protected-mode concepts. Flags Encoding No change 00001111
Syntax SGDT mem48
00000001
mod,000,r/m
disp (2)
CPU 88/86 286 386 486 Clock Cycles 11 9 10
Examples
sgdt descriptor
132
SHL/SHR/SAL/SAR Shift
Encoding
00001111
Syntax SIDT mem48
00000001
mod,001,r/m
disp (2)
CPU 88/86 286 386 486 Clock Cycles 12 9 10
Examples
sidt descriptor
Encoding
00001111
Syntax SLDT reg16
00000000
mod, 000,r/m
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 2 2 2 3 2 3
Examples
sldt ax
SLDT mem16
sldt
selector
Shifts the bits in the destination operand the number of times specified by the source operand. SAL and SHL shift the bits left; SAR and SHR shift right. With SHL, SAL, and SHR, the bit shifted off the end of the operand is copied into the carry flag, and the leftmost or rightmost bit opened by the shift is set to 0. With SAR, the bit shifted off the end of the operand is copied into the carry flag, and the leftmost bit opened by the shift retains its previous value (thus preserving the sign of the operand). SAL and SHL are synonyms. On the 8088 and 8086, the source operand can be either CL or 1. On the 8018680486 processors, the source operand can be CL or an 8-bit constant. On the 8018680486 processors, shift counts larger than 31 are masked off, but on the 8088 and 8086, larger shift counts are performed despite the inefficiency. Only single-bit variations of the instruction modify the overflow flag; for multiple-bit variations, the overflow flag is undefined. Flags O D I T S Z A P C ?
133
Encoding
1101000w
Syntax SAR reg,1
mod,TTT*,r/m
Examples
sar sar
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486 Clock Cycles 2 2 3 3 2 2 3 3 15+EA (W88=23+EA) 7 7 4 15+EA (W88=23+EA) 7 7 4
di,1 cl,1
SAL SHL SHR SAR
reg,1 reg,1 reg,1 mem,1
shr shl sal sar
dh,1 si,1 bx,1 count,1
SAL mem,1 SHL mem,1 SHR mem,1
sal shl shr
WORD PTR m32[0],1 index,1 unsign[di],1
88/86 286 386 486
Encoding
1101001w
Syntax SAR reg,CL
mod,TTT*,r/m
Examples
sar sar
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486 Clock Cycles 8+4n 5+n 3 3 8+4n 5+n 3 3 20+EA+4n (W88=28+EA+4n) 8+n 7 4 20+EA+4n (W88=28+EA+4n) 8+n 7 4
bx,cl dx,cl
SAL reg,CL SHL reg,CL SHR reg,CL SAR mem,CL
shr shl sal sar sar
dx,cl di,cl ah,cl sign,cl WORD PTR [bp+8],cl
SAL mem,CL SHL mem,CL SHR mem,CL
shr sal shl
WORD PTR m32[2],cl BYTE PTR [di],cl index,cl
134
SHLD/SHRD Double Precision Shift
Encoding
1100000w
Syntax
mod,TTT*,r/m
Examples
sar sar
disp (0, 1, or 2)
data (1)
CPU 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486 88/86 286 386 486 Clock Cycles 5+n 3 2 5+n 3 2 8+n 7 4 8+n 7 4
SAR reg,immed8
bx,5 cl,5
SAL reg,immed8 SHL reg,immed8 SHR reg,immed8 SAR mem,immed8
sal shl shr sar sar
cx,6 di,2 bx,8 sign_count,3 WORD PTR [bx],5
SAL reg,immed8 SHL reg,immed8 SHR reg,immed8
shr shl sal
mem16,11 unsign,4 array[bx+di],14
* TTT represents one of the following bit codes: 100 for SHL or SAL, 101 for SHR, or 111 for SAR.

8038680486 Only Shifts the bits of the second operand into the first operand. The number of bits shifted is specified by the third operand. SHLD shifts the first operand to the left by the number of positions specified in the count. The positions opened by the shift are filled by the most significant bits of the second operand. SHRD shifts the first operand to the right by the number of positions specified in the count. The positions opened by the shift are filled by the least significant bits of the second operand. The count operand can be either CL or an 8-bit constant. If a shift count larger than 31 is given, it is adjusted by using the remainder (modulo) of a division by 32. Flags O D I ? T S Z A P C ?
135
Encoding
00001111
Syntax
10100100
mod,reg,r/m
Examples
shld
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486
data (1)
SHLD reg16,reg16,immed8 SHLD reg32,reg32,immed8
ax,dx,10
SHLD mem16,reg16,immed8 SHLD mem32,reg32,immed8
shld
bits,cx,5
Encoding
00001111
Syntax
10101100
mod,reg,r/m
Examples
shrd
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486
data (1)
SHRD reg16,reg16,immed8 SHRD reg32,reg32,immed8
cx,si,3
SHRD mem16,reg16,immed8 SHRD mem32,reg32,immed8
shrd
[di],dx,13
Encoding
00001111
Syntax
10100101
mod,reg,r/m
Examples
shld
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 3 3 7 4
SHLD reg16,reg16,CL SHLD reg32,reg32,CL
ax,dx,cl
SHLD mem16,reg16,CL SHLD mem32,reg32,CL
shld masker,ax,cl
136
SMSW Store Machine Status Word
Encoding
00001111
Syntax
10101101
mod,reg,r/m
Examples
shrd
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 3 3 7 4
SHRD reg16,reg16,CL SHRD reg32,reg32,CL
bx,dx,cl
SHRD mem16,reg16,CL SHRD mem32,reg32,CL
shrd
[bx],dx,cl
SMSW Store Machine Status Word

80286-80486 Only Stores the Machine Status Word (MSW) into a specified memory operand. SMSW is generally useful only in protected mode. See Intel documentation for details on the MSW and other protected-mode concepts. Flags Encoding No change 00001111
Syntax SMSW reg16
00000001
mod,100,r/m
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 2 2 2 3 3 3
Examples
smsw ax
SMSW mem16
smsw
machine
STI Set Interrupt Flag
137
STC Set Carry Flag

Sets the carry flag. Flags Encoding O D I 11111001
Syntax STC Examples
stc
T S Z A P C 1
CPU 88/86 286 386 486
STD Set Direction Flag

Sets the direction flag. All subsequent string instructions will process down (from high addresses to low addresses). Flags Encoding O D I 1 T S Z A P C
11111101
Syntax STD Examples
std
CPU 88/86 286 386 486
STI Set Interrupt Flag

Sets the interrupt flag. When the interrupt flag is set, maskable interrupts are recognized. If interrupts were disabled by a previous CLI instruction, pending interrupts will not be executed immediately; they will be executed after the instruction following STI. Flags O D I T S Z A P C 1
138
STOS/STOSB/STOSW/STOSD Store String Data
Encoding
11111011
Syntax STI Examples
sti
CPU 88/86 286 386 486
STOS/STOSB/STOSW/STOSD Store String Data

Stores the value of the accumulator in a string. The string is the destination and must be pointed to by ES:DI, even if an operand is given. For each source element loaded, DI is adjusted according to the size of the operand and the status of the direction flag. DI is incremented if the direction flag has been cleared with CLD or decremented if the direction flag has been set with STD. If the STOS form of the instruction is used, an operand must be provided to indicate the size of the data elements to be processed. No segment override is allowed. If STOSB (bytes), STOSW (words), or STOSD (doublewords on the 8038680486 only) is used, the instruction determines the size of the data elements to be processed and whether the element comes from AL, AX, or EAX. STOS and its variations are often used with the REP prefix to fill a string with a repeated value. Before the repeated instruction is executed, CX should contain the number of elements to store. Flags Encoding No change 1010101w
Syntax STOS [ [ES:] dest ] STOSB [ [ES:] dest] [[ ] ] STOSW [ [ES:] dest] [[ ] ] STOSD [ [ES:] dest] [[ ] ]*
* 8038680486 only
Examples
stos es:dstring rep stosw rep stosb
CPU 88/86 286 386 486
SUB Subtract
139
STR Store Task Register

80286-80486 Only Stores the current task register to the specified operand. This instruction is generally useful only in privileged mode. See Intel documentation for details on task registers and other protected-mode concepts. Flags Encoding No change 00001111
Syntax STR reg16
00000000
mod, 001, reg
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 2 2 2 3 2 3
Examples
str cx
STR mem16
str
taskreg
SUB Subtract
Subtracts the source operand from the destination operand and stores the result in the destination operand. Flags Encoding O D I T S Z A P C mod, reg, r/m disp (0, 1, or 2)
001010dw
Syntax SUB reg,reg
Examples
sub sub ax,bx bh,dh
SUB mem,reg
sub sub
tally,bx array[di],bl
140
TEST
Logical Compare Syntax SUB reg,mem Examples

sub sub cx,discard al,[bx]
CPU 88/86 286 386 486
Clock Cycles 9+EA (W88=13+EA) 7 7 2
Encoding
100000sw
Syntax
mod,101,r/m
disp (0, 1, or 2)
data (1 or 2)
Examples
sub sub dx,45 bl,7
SUB reg,immed
SUB mem,immed
sub sub
total,4000 BYTE PTR [bx+di],2
Encoding
0010110w
Syntax
data (1 or 2)
Examples
sub ax,32000
CPU 88/86 286 386 486
SUB accum,immed
TEST Logical Compare

Tests specified bits of an operand and sets the flags for a subsequent conditional jump or set instruction. One of the operands contains the value to be tested. The other contains a bit mask indicating the bits to be tested. TEST works by doing a bitwise AND operation on the source and destination operands. The flags are modified according to the result, but the destination operand is not changed. This instruction is the same as the AND instruction, except the result is not stored. Flags O D I 0 T S Z A P C ? 0
VERR/VERW Verify Read or Write
141
Encoding
1000010w
Syntax TEST reg,reg
mod, reg, r/m
disp (0, 1, or 2)
Examples
test test dx,bx bl,ch
TEST mem,reg TEST reg,mem*
test test
dx,flags bl,bitarray[bx]
Encoding
1111011w
Syntax
mod,000,r/m
disp (0, 1, or 2)
data (1 or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 5 3 2 1 11+EA 6 5 2
Examples
test test cx,30h cl,1011b
TEST reg,immed
TEST mem,immed
test test
masker,1 BYTE PTR [bx],03h
Encoding
1010100w
Syntax TEST accum,immed
data (1 or 2)
Examples
test ax,90h
CPU 88/86 286 386 486
* MASM transposes TEST reg,mem; that is, it is encoded as TEST mem,reg.
VERR/VERW Verify Read or Write

80286-80486 Protected Only Verifies that a specified segment selector is valid and can be read or written to at the current privilege level. VERR verifies that the selector is readable. VERW verifies that the selector can be written to. If the segment is verified, the zero flag is set. Otherwise, the zero flag is cleared. Flags O D I T S Z A P C
142
WAIT Wait
Encoding
00001111
Syntax VERR reg16
00000000
mod, 100,r/m
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 14 10 11 16 11 11
Examples
verr ax
VERR mem16
verr
selector
Encoding
00001111
Syntax
00000000
mod, 101,r/m
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 14 15 11 16 16 11
Examples
verw cx
VERW reg16
VERW mem16
verw
selector
WAIT Wait
Suspends processor execution until the processor receives a signal that a coprocessor has finished a simultaneous operation. It should be used to prevent a coprocessor instruction from modifying a memory location that is being modified simultaneously by a processor instruction. WAIT is the same as the coprocessor FWAIT instruction. Flags Encoding No change 10011011
Syntax WAIT Examples
wait
CPU 88/86 286 386 486
XADD Exchange and Add
143
WBINVD Write Back and Invalidate Data Cache

80486 Only Empties the contents of the current data cache after writing changes to memory. Proper use of this instruction requires knowledge of how contents are placed in the cache. WBINVD is intended primarily for system programming. See Intel documentation for details. Flags Encoding No change 00001111
Syntax WBINVD
00001001
Examples
wbinvd
CPU 88/86 286 386 486
Clock Cycles 5
XADD Exchange and Add

80486 Only Adds the source and destination operands and stores the sum in the destination; simultaneously, the original value of the destination is moved to the source. The instruction sets flags according to the result of the addition. Flags Encoding O D I T S Z A P C 1100000b mod, reg, r/m
Examples
xadd xadd warr[bx],ax string,bl
00001111
Syntax
disp (0, 1, or 2)
CPU 88/86 286 386 486 88/86 286 386 486 Clock Cycles 4 3
XADD mem,reg
XADD reg,reg
xadd xadd
dl,al bx,dx
144
XCHG Exchange
XCHG Exchange
Exchanges the values of the source and destination operands. Flags Encoding No change 1000011w
Syntax XCHG reg,reg
mod,reg,r/m
disp (0, 1, or 2)
Examples
xchg xchg xchg xchg xchg cx,dx bl,dh al,ah [bx],ax bx,pointer
XCHG reg,mem XCHG mem,reg
Encoding
10010 reg
Syntax XCHG accum,reg16* XCHG reg16,accum* Examples
xchg xchg ax,cx cx,ax
CPU 88/86 286 386 486
* On the 8038680486, the accumulator may also be exchanged with a 32-bit register.
XLAT/XLATB Translate
Translates a value from one coding system to another by looking up the value to be translated in a table stored in memory. Before the instruction is executed, BX should point to a table in memory and AL should contain the unsigned position of the value to be translated from the table. After the instruction, AL contains the table value at the specified position. No operand is required, but one can be given to specify a segment override. DS is assumed unless a segment override is given. XLATB is a synonym for XLAT. Either version allows an operand, but neither requires one.
XOR Exclusive OR
145
Flags Encoding
No change 11010111
Syntax XLAT [ [segreg:] mem] [[ ] ] XLATB [ [segreg:] mem] [[ ] ] Examples
xlat xlatb es:table
CPU 88/86 286 386 486
XOR Exclusive OR
Performs a bitwise exclusive OR operation on the source and destination operands and stores the result in the destination. For each bit position in the operands, if both bits are set or if both bits are cleared, the corresponding bit of the result is cleared. Otherwise, the corresponding bit of the result is set. Flags Encoding O D I 0 T S Z A P C ? 0 mod, reg, r/m
Examples
xor xor cx,bx ah,al
001100dw
Syntax XOR reg,reg
disp (0, 1, or 2)
XOR mem,reg
xor xor
[bp+10],cx masked,bx
XOR reg,mem
xor xor
cx,flags bl,bitarray[di]
146
XOR Exclusive OR
Encoding
100000sw
Syntax
mod,110,r/m
disp (0, 1, or 2)
data (1 or 2)
Examples
xor xor bx,10h bl,1
XOR reg,immed
XOR mem,immed
xor xor
Boolean,1 switches[bx],101b
Encoding
0011010w
Syntax
data (1 or 2)
Examples
xor ax,01010101b
CPU 88/86 286 386 486
XOR accum,immed
XOR Exclusive OR
147
145
C H A P T E R
Coprocessor
Topical Cross-reference for Coprocessor Instructions . Interpreting Coprocessor Instructions. . . . . . . . . . . . . Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Size . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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146 148 148 148 148 148 149
146
Reference
Topical Cross-reference for Coprocessor Instructions

Arithmetic
FABS FCHS FDIVR/FIDIVR FMULP FRNDINT FSUB/FISUB FSUBRP FADD/FIADD FDIV/FIDIV FDIVRP FPREM FSCALE FSUBP FXTRACT FADDP FDIVP FMUL/FIMUL FPREM1 FSQRT FSUBR/FISUBR
Compare
FCOM/FICOM FSTSW/FNSTSW FUCOMP FCOMP/FICOMP FTST FUCOMPP FCOMPP FUCOM FXAM
Load
FLD/FILD/FBLD FRSTOR FLDCW FXCH FLDENV
Load Constant
FLD1 FLDLG2 FLDZ FLDL2E FLDLN2 FLDL2T FLDPI
Processor Control
FCLEX/FNCLEX FENI/FNENI* FINIT/FNINIT FRSTOR FSTCW/FNSTCW FWAIT FDECSTP FFREE FLDCW FSAVE/FNSAVE FSTENV/FNSTENV FDISI/FNDISI* FINCSTP FNOP FSETPM_ FSTSW/FNSTSW
Store Data
FSAVE/FNSAVE FSTENV/FNSTENV FST/FIST FSTP/FISTP/FBSTP FSTCW/FNSTCW FSTSW/FNSTSW
Coprocessor
147
Transcendental
F2XM1 FPREM FSIN
FCOS FPREM1

FPATAN FPTAN FYL2P1
FSINCOS
FYL2X
* 8087 only 80287 only. 8038780486 only.
148
Reference
Interpreting Coprocessor Instructions

This section provides an alphabetical reference to instructions of the 8087, 80287, and 80387 coprocessors. The format is the same as the processor instructions except that encodings are not provided. Differences are noted in the following. The 80486 has the coprocessor built in. This one chip executes all the instructions listed in the previous section and this section.
Syntax
Syntaxes in Column 1 use the following abbreviations for operand types:
Syntax reg memreal memint membcd Operand A coprocessor stack register A direct or indirect memory operand storing a real number A direct or indirect memory operand storing a binary integer A direct or indirect memory operand storing a BCD number
Examples
The position of the examples in Column 2 is not related to the clock speeds in Column 3.
Clock Speeds
Column 3 shows the clock speeds for each processor. Sometimes an instruction may have more than one possible clock speed. The following abbreviations are used to specify variations:
Abbreviation EA Description Effective address. This applies only to the 8087. See the Processor Section, Timings on the 8088 and 8086 Processors, for an explanation of effective address timings. Short real, long real, and 10-byte temporary real. Word, doubleword, and quadword binary integer. To or from stack top. On the 80387 and 80486, the to clocks represent timings when ST is the destination. The fr clocks represent timings when ST is the source.
s,l,t w,d,q to, fr
Instruction Size
The instruction size is always 2 bytes for instructions that do not access memory. For instructions that do access memory, the size is 4 bytes on the 8087 and 80287. On the 80387 and 80486, the size for instructions that access memory is 4 bytes in 16-bit mode, or 6 bytes in 32-bit mode.
Coprocessor
149
On the 8087, each instruction must be preceded by the WAIT (also called FWAIT) instruction, thereby increasing the instructions size by 1 byte. The assembler inserts WAIT automatically by default, or with the .8087 directive.
Architecture
The 8087, 80287, and 80387 coprocessors, along with the 80486, have several common elements of architecture. All have a register stack made up of eight 80bit data registers. These can contain floating-point numbers in the temporary real format. The coprocessors also have 14 bytes of control registers. Figure 5.1 shows the format of registers.
Fig. 5.1
Coprocessor Registers
150
F2XM1 2X1
The most important control registers are the control word and the status word. Figure 5.2 shows the format of these registers.
Fig. 5.2
Control Word and Status Word
F2XM1 2X1
Calculates Y = 2X 1. X is taken from ST. The result, Y, is returned in ST. X must be in the range 0 X 0.5 on the 8087/287, or in the range 1.0 X +1.0 on the 8038780486.
Syntax F2XM1 Examples
f2xm1
CPU 87 287 387 486
Clock Cycles 310630 310630 211476 140279
FABS Absolute Value

Converts the element in ST to its absolute value.
Syntax FABS Examples
fabs
CPU 87 287 387 486
FBSTP Store BCD and Pop
151
FADD/FADDP/FIADD Add
Adds the source to the destination and returns the sum in the destination. If two register operands are specified, one must be ST. If a memory operand is specified, the sum replaces the value in ST. Memory operands can be 32- or 64bit real numbers or 16- or 32-bit integers. If no operand is specified, ST is added to ST(1) and the stack is popped, returning the sum in ST. For FADDP, the source must be ST; the sum is returned in the destination and ST is popped.
Syntax FADD [ [reg,reg] ] Examples
fadd st,st(2) fadd st(5),st fadd faddp st(6),st
CPU 87 287 387 486 87 287 387 486 87 287 387 486
Clock Cycles 70100 70100 to=2331, fr=2634 820 75105 75105 2331 820 (s=90120,s=95 125)+EA s=90120,l=95125 s=2432,l=2937 820 (w=102137,d=108 143)+EA w=102137,d=108 143 w=7185,d=5772 w=2035,d=1932
FADDP reg,ST
FADD memreal
fadd QWORD PTR [bx] fadd shortreal
FIADD memint
fiadd int16 fiadd warray[di] fiadd double
87 287 387 486
FBLD Load BCD

See FLD.
FBSTP Store BCD and Pop

See FST.
152
FCHS Change Sign
FCHS Change Sign

Reverses the sign of the value in ST.
Syntax FCHS Examples
fchs
CPU 87 287 387 486
Clock Cycles 1017 1017 2425 6
FCLEX/FNCLEX Clear Exceptions

Clears all exception flags, the busy flag, and bit 7 in the status word. Bit 7 is the interrupt-request flag on the 8087, and the error-status flag on the 80287, 80387, and 80486. The instruction has wait and no-wait versions.
Syntax FCLEX FNCLEX Examples
fclex
CPU 87 287 387 486
Clock Cycles* 28 28 11 7
* These timings reflect the no-wait version of the instruction. The wait version may take additional clock cycles.
FCOM/FCOMP/FCOMPP/FICOM/FICOMP Compare
Compares the specified source operand to ST and sets the condition codes of the status word according to the result. The instruction subtracts the source operand from ST without changing either operand. Memory operands can be 32- or 64-bit real numbers or 16- or 32-bit integers. If no operand is specified or if two pops are specified, ST is compared to ST(1) and the stack is popped. If one pop is specified with an operand, the operand is compared to ST. If one of the operands is a NAN, an invalid-operation exception occurs (see FUCOM for an alternative method of comparing on the 8038780486).
FCOM/FCOMP/FCOMPP/FICOM/FICOMP Compare Syntax FCOM [ [reg] ] Examples

fcom fcom st(2)
153
CPU 87 287 387 486 87 287 387 486 87 287 387 486
Clock Cycles 4050 4050 24 4 4252 4252 26 4 4555 4555 26 5 (s=6070,l=6575)+EA s=6070,l=6575 s=26,l=31 4 (s=6373,l=6777)+EA s=6373,l=6777 s=26,l=31 4 (w=7286,d=7891)+EA w=7286,d=7891 w=7175,d=5663 w=1620,d=1517 (w=7488,d=8093)+EA w=7488,d=8093 w=7175,d=5663 w=1620,d=1517
FCOMP [ [reg] ]
fcomp fcomp
st(7)
FCOMPP
fcompp
FCOM memreal
fcom fcom
shortreals[di] longreal
87 287 387 486 87 287 387 486 87 287 387 486
FCOMP memreal
fcomp fcomp
longreal shorts[di]
FICOM memint
ficom ficom
double warray[di]
FICOMP memint
ficomp [bp+6] ficomp
WORD PTR darray[di]
87 287 387 486
Condition Codes for FCOM C3 0 0 1 1 C2 0 0 0 1 C1 ? ? ? ? C0 0 1 0 1 Meaning ST > source ST < source ST = source ST is not comparable to source
154
FCOS Cosine
FCOS Cosine
8038780486 Only Replaces a value in radians in ST with its cosine. If |ST | < 263, the C2 bit of the status word is cleared and the cosine is calculated. Otherwise, C2 is set and no calculation is performed. ST can be reduced to the required range with FPREM or FPREM1.
Syntax FCOS Examples
fcos
CPU 87 287 387 486
Clock Cycles 123772* 257354
* For operands with an absolute value greater than /4, up to 76 additional clocks may be required. For operands with an absolute value greater than /4, add n clocks where n = operand/(/4).
FDECSTP Decrement Stack Pointer

Decrements the stack-top pointer in the status word. No tags or registers are changed, and no data is transferred. If the stack pointer is 0, FDECSTP changes it to 7.
Syntax FDECSTP Examples
fdecstp
CPU 87 287 387 486
FDISI/FNDISI Disable Interrupts

8087 Only Disables interrupts by setting the interrupt-enable mask in the control word. This instruction has wait and no-wait versions. Since the 80287, 80387, and 80486 do not have an interrupt-enable mask, the instruction is recognized but ignored on these coprocessors.
Syntax FDISI FNDISI Examples
fdisi
CPU 87 287 387 486
FDIV/FDIVP/FIDIV
Divide
155
FDIV/FDIVP/FIDIV Divide
Divides the destination by the source and returns the quotient in the destination. If two register operands are specified, one must be ST. If a memory operand is specified, the quotient replaces the value in ST. Memory operands can be 32- or 64-bit real numbers or 16- or 32-bit integers. If no operand is specified, ST(1) is divided by ST and the stack is popped, returning the result in ST. For FDIVP, the source must be ST; the quotient is returned in the destination register and ST is popped.
Syntax FDIV [ [reg,reg] ] Examples
fdiv fdiv st,st(2) st(5),st
CPU 87 287 387 486 87 287 387 486 87 287 387 486 87 287 387 486
Clock Cycles 193203 193203 to=88, fr=91 73 197207 197207 91 73 (s=215225,l=220 230)+EA s=215225,l=220230 s=89,l=94 73 (w=224238,d=230 243)+EA w=224238,d=230 243 w=136140,d=120 127 w=8589,d=8486
FDIVP reg,ST
fdivp
st(6),st
FDIV memreal
fdiv fdiv fdiv
DWORD PTR [bx] shortreal[di] longreal
FIDIV memint
fidiv fidiv fidiv
int16 warray[di] double
156
FDIVR/FDIVRP/FIDIVR Divide Reversed
FDIVR/FDIVRP/FIDIVR Divide Reversed

Divides the source by the destination and returns the quotient in the destination. If two register operands are specified, one must be ST. If a memory operand is specified, the quotient replaces the value in ST. Memory operands can be 32- or 64-bit real numbers or 16- or 32-bit integers. If no operand is specified, ST is divided by ST(1) and the stack is popped, returning the result in ST. For FDIVRP, the source must be ST; the quotient is returned in the destination register and ST is popped.
Syntax FDIVR [ [reg,reg] ] Examples
fdivr fdivr fdivr fdivrp st,st(2) st(5),st
CPU 87 287 387 486 87 287 387 486 87 287 387 486
Clock Cycles 194204 194204 to=88, fr=91 73 198208 198208 91 73 (s=216226,l=221 231)+EA s=216226,l=221231 s=89,l=94 73 (w=225239,d=231 245)+EA w=225239,d=231 245 w=135141,d=121128 w=8589,d=8486
FDIVRP reg,ST
st(6),st
FDIVR memreal
fdivr fdivr
longreal shortreal[di]
FIDIVR memint
fidivr fidivr
double warray[di]
87 287 387 486
FENI/FNENI Enable Interrupts

8087 Only Enables interrupts by clearing the interrupt-enable mask in the control word. This instruction has wait and no-wait versions. Since the 80287, 80387, and 80486 do not have interrupt-enable masks, the instruction is recognized but ignored on these coprocessors.
FILD Load Integer Syntax FENI FNENI Examples

feni
157
CPU 87 287 387 486
FFREE Free Register

Changes the specified registers tag to empty without changing the contents of the register.
Syntax FFREE ST(i) Examples
ffree st(3)
CPU 87 287 387 486
FIADD/FISUB/FISUBR/ FIMUL/FIDIV/FIDIVR Integer Arithmetic

See FADD, FSUB, FSUBR, FMUL, FDIV, and FDIVR.
FICOM/FICOMP Compare Integer

See FCOM.
FILD Load Integer

See FLD.
158
FINCSTP Increment Stack Pointer
FINCSTP Increment Stack Pointer

Increments the stack-top pointer in the status word. No tags or registers are changed, and no data is transferred. If the stack pointer is 7, FINCSTP changes it to 0.
Syntax FINCSTP Examples
fincstp
CPU 87 287 387 486
FINIT/FNINIT Initialize Coprocessor

Initializes the coprocessor and resets all the registers and flags to their default values. The instruction has wait and no-wait versions. On the 8038780486, the condition codes of the status word are cleared. On the 8087/287, they are unchanged.
Syntax FINIT FNINIT Examples
finit
CPU 87 287 387 486
FIST/FISTP Store Integer

See FST.
FLD1/FLDZ/FLDPI/FLDL2E/FLDL2T/FLDLG2/FLDLN2 Load Constant
159
FLD/FILD/FBLD Load
Pushes the specified operand onto the stack. All memory operands are automatically converted to temporary-real numbers before being loaded. Memory operands can be 32-, 64-, or 80-bit real numbers or 16-, 32-, or 64-bit integers.
Syntax FLD reg Examples
fld st(3)
CPU 87 287 387 486 87 287
Clock Cycles 1722 1722 14 4 (s=3856,l=4060,t= 5365)+EA s=3856,l=4060,t= 5365 s=20,1=25,t=44 s=3,l=3,t=6 (w=4654,d=52 60,q=6068)+EA w=46-54,d=52-60,q= 60-68 w=6165,d=45 52,q=5667 w=1316,d=912,q= 1018 (290310)+EA 290310 266275 70103
FLD memreal
fld fld fld
longreal shortarray[bx+di] tempreal
387 486 FILD memint

fild fild fild mem16 DWORD PTR [bx] quads[si]
87 287 387 486
FBLD membcd
fbld
packbcd
87 287 387 486
FLD1/FLDZ/FLDPI/FLDL2E/ FLDL2T/FLDLG2/FLDLN2 Load Constant FLD1/FLDZ/FLDPI/FLDL2E/FLDL2T/FLDLG2/FLDLN2 Load Constant a constant onto the stack. The following constants can be loaded: Pushes
Instruction FLD1 FLDZ FLDPI Constant +1.0 +0.0
160
FLD1/FLDZ/FLDPI/FLDL2E/FLDL2T/FLDLG2/FLDLN2 Load Constant Instruction FLDL2E FLDL2T FLDLG2 FLDLN2 Syntax FLD1 Constant Log2(e) Log2(10) Log10(2) Loge(2) Examples
fld1
CPU 87 287 387 486 87 287 387 486 87 287 387 486 87 287 387 486 87 287 387 486 87 287 387 486 87 287 387 486
Clock Cycles 1521 1521 24 4 1117 1117 20 4 1622 1622 40 8 1521 1521 40 8 1622 1622 40 8 1824 1824 41 8 1723 1723 41 8
FLDZ
fldz
FLDPI
fldpi
FLDL2E
fldl2e
FLDL2T
fldl2t
FLDLG2
fldlg2
FLDLN2
fldln2
FMUL/FMULP/FIMUL
Multiply
161
FLDCW Load Control Word

Loads the specified word into the coprocessor control word. The format of the control word is shown in the Interpreting Coprocessor Instructions section.
Syntax FLDCW mem16 Examples
fldcw ctrlword
CPU 87 287 387 486
Clock Cycles (714)+EA 714 19 4
FLDENV/FLDENVW/FLDENVD Load Environment State

Loads the 14-byte coprocessor environment state from a specified memory location. The environment includes the control word, status word, tag word, instruction pointer, and operand pointer. On the 8038780486 in 32-bit mode, the environment state is 28 bytes.
Syntax FLDENV mem FLDENVW mem* FLDENVD mem* Examples
fldenv [bp+10]
CPU 87 287 387 486
Clock Cycles (3545)+EA 3545 71 44,pm=34
* 8038780486 only.
FMUL/FMULP/FIMUL Multiply
Multiplies the source by the destination and returns the product in the destination. If two register operands are specified, one must be ST. If a memory operand is specified, the product replaces the value in ST. Memory operands can be 32- or 64-bit real numbers or 16- or 32-bit integers. If no operand is specified, ST(1) is multiplied by ST and the stack is popped, returning the product in ST. For FMULP, the source must be ST; the product is returned in the destination register and ST is popped.
162
FNinstruction No-Wait Instructions Syntax FMUL [ [reg,reg] ] Examples

fmul fmul fmul st,st(2) st(5),st
CPU 87 287 387 486
Clock Cycles 130145 (90105)* 130145 (90105)* to=4654 (49), fr= 2957 (52) 16 134148 (94108)* 134148 (94108)* 2957 (52) 16 (s=110125,l=154 168)+EA s=110125,l=154 168 s=2735,l=3257 s=11,l=14 (w=124138,d=130 144)+EA w=124138,d=130 144 w=7687,d=6182 w=2327,d=2224
FMULP reg,ST
fmulp
st(6),st
87 287 387 486 87 287 387 486
FMUL memreal
fmul fmul fmul
DWORD PTR [bx] shortreal[di+3] longreal
FIMUL memint
fimul fimul fimul
int16 warray[di] double
87 287 387 486
* The clocks in parentheses show times for short valuesthose with 40 trailing zeros in their fraction because they were loaded from a short-real memory operand. The clocks in parentheses show typical speeds. If the register operand is a short valuehaving 40 trailing zeros in its fraction because it was loaded from a short-real memory operandthen the timing is (112126)+EA on the 8087 or 112126 on the 80287.
FNinstruction No-Wait Instructions

Instructions that have no-wait versions include FCLEX, FDISI, FENI, FINIT, FSAVE, FSTCW, FSTENV, and FSTSW. Wait versions of instructions check for unmasked numeric errors; no-wait versions do not. When the .8087 directive is used, the assembler puts a WAIT instruction before the wait versions and a NOP instruction before the no-wait versions.
FPREM Partial Remainder
163
FNOP No Operation
Performs no operation. FNOP can be used for timing delays or alignment.
Syntax FNOP Examples
fnop
CPU 87 287 387 486
FPATAN Partial Arctangent

Finds the partial tangent by calculating Z = ARCTAN(Y / X). X is taken from ST and Y from ST(1). On the 8087/287, Y and X must be in the range 0 Y < X < . On the 8038780486, there is no restriction on X and Y. X is popped from the stack and Z replaces Y in ST.
Syntax FPATAN Examples
fpatan
CPU 87 287 387 486
Clock Cycles 250800 250800 314487 218303
FPREM Partial Remainder

Calculates the remainder of ST divided by ST(1), returning the result in ST. The remainder retains the same sign as the original dividend. The calculation uses the following formula:
remainder = ST ST(1) * quotient
The quotient is the exact value obtained by chopping ST / ST(1) toward 0. The instruction is normally used in a loop that repeats until the reduction is complete, as indicated by the condition codes of the status word.
Syntax FPREM Examples
fprem
CPU 87 287 387 486
Clock Cycles 15190 15190 74155 70138
164
FPREM1 Partial Remainder (IEEE Compatible)
Condition Codes for FPREM and FPREM1 C3 ? 0 0 0 0 1 1 1 1 C2 1 0 0 0 0 0 0 0 0 C1 ? 0 0 1 1 0 0 1 1 C0 ? 0 1 0 1 0 1 0 1 Meaning Incomplete reduction quotient MOD 8 = 0 quotient MOD 8 = 4 quotient MOD 8 = 1 quotient MOD 8 = 5 quotient MOD 8 = 2 quotient MOD 8 = 6 quotient MOD 8 = 3 quotient MOD 8 = 7
FPREM1 Partial Remainder (IEEE Compatible)

8038780486 Only Calculates the remainder of ST divided by ST(1), returning the result in ST. The remainder retains the same sign as the original dividend. The calculation uses the following formula:
remainder = ST ST(1) * quotient
The quotient is the integer nearest to the exact value of ST / ST(1). When two integers are equally close to the given value, the even integer is used. The instruction is normally used in a loop that repeats until the reduction is complete, as indicated by the condition codes of the status word. See FPREM for the possible condition codes.
Syntax FPREM1 Examples
fprem1
CPU 87 287 387 486
Clock Cycles 95185 72167
FRNDINT Round to Integer
165
FPTAN Partial Tangent

Finds the partial tangent by calculating Y / X = TAN(Z). Z is taken from ST. Z must be in the range 0 Z / 4 on the 8087/287. On the 8038780486, |Z| must be less than 263. The result is the ratio Y / X. Y replaces Z, and X is pushed into ST. Thus, Y is returned in ST(1) and X in ST.
Syntax FPTAN Examples
fptan
CPU 87 287 387 486
Clock Cycles 30540 30540 191497* 200273
FRNDINT Round to Integer

Rounds ST from a real number to an integer. The rounding control (RC) field of the control word specifies the rounding method, as shown in the introduction to this section.
Syntax FRNDINT Examples
frndint
CPU 87 287 387 486
Clock Cycles 1650 1650 6680 2130
166
FRSTOR/FRSTORW/FRSTORD Restore Saved State
FRSTOR/FRSTORW/FRSTORD Restore Saved State

Restores the 94-byte coprocessor state to the coprocessor from the specified memory location. In 32-bit mode on the 8038780486, the environment state takes 108 bytes.
Syntax FRSTOR mem FRSTORW mem* FRSTORD mem* Examples
frstor [bp94]
CPU 87 287 387 486
Clock Cycles (197207)+EA 308 131,pm=120
* 8038780486 only. Clock counts are not meaningful in determining overall execution time of this instruction. Timing is determined by operand transfers.
FSAVE/FSAVEW/FSAVED/FNSAVE/ FNSAVEW/FNSAVED Save Coprocessor State

Stores the 94-byte coprocessor state to the specified memory location. In 32-bit mode on the 8038780486, the environment state takes 108 bytes. This instruction has wait and no-wait versions. After the save, the coprocessor is initialized as if FINIT had been executed.
Syntax FSAVE mem FSAVEW mem* FSAVED mem* FNSAVE mem FNSAVEW mem* FNSAVED mem*
* 8038780486 only. Clock counts are not meaningful in determining overall execution time of this instruction. Timing is determined by operand transfers. These timings reflect the no-wait version of the instruction. The wait version may take additional clock cycles.
Examples
fsave [bp94] fsave cobuffer
CPU 87 287 387 486
Clock Cycles (197207)+EA 375376 154,pm=143
FSETPM Set Protected Mode
167
FSCALE Scale
Scales by powers of 2 by calculating the function Y = Y * 2X. X is the scaling factor taken from ST(1), and Y is the value to be scaled from ST. The scaled result replaces the value in ST. The scaling factor remains in ST(1). If the scaling factor is not an integer, it will be truncated toward zero before the scaling. On the 8087/287, if X is not in the range 215 X < 215 or if X is in the range 0 < X < 1, the result will be undefined. The 8038780486 have no restrictions on the range of operands.
Syntax FSCALE Examples
fscale
CPU 87 287 387 486
Clock Cycles 3238 3238 6786 3032
FSETPM Set Protected Mode

80287 Only Sets the 80287 to protected mode. The instruction and operand pointers are in the protected-mode format after this instruction. On the 80387 80486, FSETPM is recognized but interpreted as FNOP, since the 80386/486 processors handle addressing identically in real and protected mode.
Syntax FSETPM Examples
fsetpm
CPU 87 287 387 486
168
FSIN
Sine
FSIN Sine
8038780486 Only Replaces a value in radians in ST with its sine. If |ST | < 263, the C2 bit of the status word is cleared and the sine is calculated. Otherwise, C2 is set and no calculation is performed. ST can be reduced to the required range with FPREM or FPREM1.
Syntax FSIN Examples
fsin
CPU 87 287 387 486
FSINCOS Sine and Cosine

8038780486 Only Computes the sine and cosine of a radian value in ST. The sine replaces the value in ST, and then the cosine is pushed onto the stack. If |ST | < 263, the C2 bit of the status word is cleared and the sine and cosine are calculated. Otherwise, C2 is set and no calculation is performed. ST can be reduced to the required range with FPREM or FPREM1.
Syntax FSINCOS Examples
fsincos
CPU 87 287 387 486
FST/FSTP/FIST/FISTP/FBSTP
Store
169
FSQRT Square Root

Replaces the value of ST with its square root. (The square root of 0 is 0.)
Syntax FSQRT Examples
fsqrt
CPU 87 287 387 486
Clock Cycles 180186 180186 122129 8387
FST/FSTP/FIST/FISTP/FBSTP Store
Stores the value in ST to the specified memory location or register. Temporaryreal values in registers are converted to the appropriate integer, BCD, or floating-point format as they are stored. With FSTP, FISTP, and FBSTP, the ST register value is popped off the stack. Memory operands can be 32-, 64-, or 80-bit real numbers for FSTP or 16-, 32-, or 64-bit integers for FISTP.
Syntax FST reg Examples
fst fst st(6) st
CPU 87 287 387 486 87 287 387 486 87 287 387 486
Clock Cycles 1522 1522 11 3 1724 1724 12 3 (s=8490,l=96 104)+EA s=8490,l=96104 s=44,l=45 s=7,l=8 (s=8692,l=98106, t=5258)+EA s=8692,l=98106, t=5258 s=44,l=45,t=53 s=7,l=8,t=6
FSTP reg
fstp fstp
st st(3)
FST memreal
fst fst
shortreal longs[bx]
FSTP memreal
fstp fstp
longreal tempreals[bx]
87 287 387 486
170
FSTCW/FNSTCW Store Control Word Syntax FIST memint Examples

fist fist int16 doubles[8]
CPU 87 287 387 486
Clock Cycles (w=8090,d=82 92)+EA w=8090,d=8292 w=82-95,d=79-93 w=2934,d=2834 (w=8292,d=8494, q=94105)+EA w=8292,d=8494, q=94105 w=8295,d=7993, q=8097 2934 (520540)+EA 520540 512534 172176
FISTP memint
fistp fistp
longint doubles[bx]
87 287 387 486
FBSTP membcd
fbstp
bcds[bx]
87 287 387 486
FSTCW/FNSTCW Store Control Word

Stores the control word to a specified 16-bit memory operand. This instruction has wait and no-wait versions.
Syntax FSTCW mem16 FNSTCW mem16 Examples
fstcw ctrlword
CPU 87 287 387 486
Clock Cycles* 1218 1218 15 3
FSTENV/FSTENVW/FSTENVD/FNSTENV/FNSTENVW/ FNSTENVD Store Environment State

Stores the 14-byte coprocessor environment state to a specified memory location. The environment state includes the control word, status word, tag word, instruction pointer, and operand pointer. On the 8038780486 in 32-bit mode, the environment state is 28 bytes.
FSUB/FSUBP/FISUB Subtract Syntax FSTENV mem FSTENVW mem* FSTENVD mem* FNSTENV mem FNSTENVW mem* FNSTENVD mem*
* 8038780486 only. These timings reflect the no-wait version of the instruction. The wait version may take additional clock cycles.
171
Examples
fstenv [bp14]
CPU 87 287 387 486
Clock Cycles (4050)+EA 4050 103104 67,pm=56
FSTSW/FNSTSW Store Status Word

Stores the status word to a specified 16-bit memory operand. On the 80287, 80387, and 80486, the status word can also be stored to the processors AX register. This instruction has wait and no-wait versions.
Syntax FSTSW mem16 FNSTSW mem16 Examples
fstsw statword
CPU 87 287 387 486 87 287 387 486
Clock Cycles* 1218 1218 15 3 1016 13 3
FSTSW AX FNSTSW AX
fstsw
ax
FSUB/FSUBP/FISUB Subtract
Subtracts the source operand from the destination operand and returns the difference in the destination operand. If two register operands are specified, one must be ST. If a memory operand is specified, the result replaces the value in ST. Memory operands can be 32- or 64-bit real numbers or 16- or 32-bit integers. If no operand is specified, ST is subtracted from ST(1) and the stack is popped, returning the difference in ST. For FSUBP, the source must be ST; the difference (destination minus source) is returned in the destination register and ST is popped.
172
FSUBR/FSUBRP/FISUBR Subtract Reversed Syntax FSUB [ [reg,reg] ] Examples

fsub fsub fsub fsubp st,st(2) st(5),st
CPU 87 287 387 486 87 287 387 486 87 287 387 486
Clock Cycles 70100 70100 to=2937, fr=2634 820 75105 75105 2634 820 (s=90120,s=95 125)+EA s=90120,l=95125 s=2432,l=2836 820 (w=102137,d=108143)+EA w=102137,d=108 143 w=7183,d=5782 w=2035,d=1932
FSUBP reg,ST
st(6),st
FSUB memreal
fsub fsub
longreal shortreals[di]
FISUB memint
fisub double fisub warray[di]
87 287 387 486
FSUBR/FSUBRP/FISUBR Subtract Reversed

Subtracts the destination operand from the source operand and returns the result in the destination operand. If two register operands are specified, one must be ST. If a memory operand is specified, the result replaces the value in ST. Memory operands can be 32- or 64-bit real numbers or 16- or 32-bit integers. If no operand is specified, ST(1) is subtracted from ST and the stack is popped, returning the difference in ST. For FSUBRP, the source must be ST; the difference (source minus destination) is returned in the destination register and ST is popped.
Syntax FSUBR [ [reg,reg] ] Examples
fsubr fsubr fsubr st,st(2) st(5),st
CPU 87 287 387 486 87 287 387 486
Clock Cycles 70100 70100 to=2937, fr=2634 820 75105 75105 2634 820
FSUBRP reg,ST
fsubrp st(6),st
FUCOM/FUCOMP/FUCOMPP Unordered Compare Syntax FSUBR memreal Examples

fsubr fsubr fsubr QWORD PTR [bx] shortreal[di] longreal
173
CPU 87 287 387 486 87 287 387 486
Clock Cycles (s=90120,s=95 125)+EA s=90120,l=95125 s=2533,l=2937 820 (w=103139,d=109 144)+EA w=103139,d=109 144 w=7284,d=5883 w=2055,d=1932
FISUBR memint
fisubr int16 fisubr warray[di] fisubr double
FTST Test for Zero

Compares ST with +0.0 and sets the condition of the status word according to the result.
Syntax FTST Examples
ftst
CPU 87 287 387 486
Condition Codes for FTST C3 0 0 1 1 C2 0 0 0 1 C1 ? ? ? ? C0 0 1 0 1 Meaning ST is positive ST is negative ST is 0 ST is not comparable (NAN or projective infinity)
FUCOM/FUCOMP/FUCOMPP Unordered Compare

8038780486 Only Compares the specified source to ST and sets the condition codes of the status word according to the result. The instruction subtracts the source operand from ST without changing either operand. Memory operands are not allowed. If no operand is specified or if two pops are specified, ST is compared to ST(1). If one pop is specified with an operand, the given register is compared to ST.
174
FWAIT Wait
Unlike FCOM, FUCOM does not cause an invalid-operation exception if one of the operands is NAN. Instead, the condition codes are set to unordered.
Syntax FUCOM [ [reg] ] Examples
fucom fucom st(2)
CPU 87 287 387 486 87 287 387 486 87 287 387 486
Clock Cycles 24 4 26 4 26 5
FUCOMP [ [reg] ]
fucomp fucomp
st(7)
FUCOMPP
fucompp
Condition Codes for FUCOM C3 0 0 1 1 C2 0 0 0 1 C1 ? ? ? ? C0 0 1 0 1 Meaning ST > source ST < source ST = source Unordered
FWAIT Wait
Suspends execution of the processor until the coprocessor is finished executing. This is an alternate mnemonic for the processor WAIT instruction.
Syntax FWAIT Examples
fwait
CPU 87 287 387 486
FXAM Examine
175
FXAM Examine
Reports the contents of ST in the condition flags of the status word.
Syntax FXAM Examples
fxam
CPU 87 287 387 486
Clock Cycles 1223 1223 3038 8
Condition Codes for FXAM C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Meaning + Unnormal* + NAN Unnormal* NAN + Normal + Infinity Normal Infinity +0 Empty 0 Empty + Denormal Empty* Denormal Empty*
* Not used on the 8038780486. Unnormals are not supported by the 8038780486. Also, the 80387 80486 use two codes instead of four to identify empty registers.
176
FXCH Exchange Registers
FXCH Exchange Registers

Exchanges the specified (destination) register and ST. If no operand is specified, ST and ST(1) are exchanged.
Syntax FXCH [ [reg] ] Examples
fxch fxch st(3)
CPU 87 287 387 486
FXTRACT Extract Exponent and Significand

Extracts the exponent and significand (mantissa) fields of ST. The exponent replaces the value in ST, and then the significand is pushed onto the stack.
Syntax FXTRACT Examples
fxtract
CPU 87 287 387 486
Clock Cycles 2755 2755 7076 1620
FYL2X Y log2(X)
Calculates Z = Y log2(X). X is taken from ST and Y from ST(1). The stack is popped, and the result, Z, replaces Y in ST. X must be in the range 0 < X < and Y in the range < Y < .
Syntax FYL2X Examples
fyl2x
CPU 87 287 387 486
Clock Cycles 9001100 9001100 120538 196329
FYL2XP1 Y log2(X+1)
177
FYL2XP1 Y log2(X+1)
Calculates Z = Y log2(X + 1). X is taken from ST and Y from ST(1). The stack is popped once, and the result, Z, replaces Y in ST. X must be in the range 0 < |X| < (1 (2 / 2)). Y must be in the range < Y < .
Syntax FYL2XP1 Examples
fyl2xp1
CPU 87 287 387 486
Clock Cycles 7001000 7001000 257547 171326
178
FYL2XP1 Y log2(X+1)
179
C H A P T E R
Macros
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIOS.INC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMACROS.INC, CMACROS.NEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MS-DOS.INC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MACROS.INC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROLOGUE.INC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WIN.INC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
180 180 180 183 184 185 185
Filename: LMARFC06.DOC Project: MASM Reference Template: MSGRIDA1.DOT Author: a.c. birdsong Last Saved By: Launi Lockard Revision #: 26 Page: 179 of 1 Printe d: 10/02/00 04:16 PM
180
Reference
Introduction
Each of the INCLUDE files is listed with the names of the macros it contains. Macros listed take the form:
<macroname>MACRO[[ <variables[[:=<default value>]], ..>]]
Some variables are listed as name:req. In these cases, req indicates that macroname cannot be called without the variable name supplied. For specific information on the macros themselves, see the contents of the commented *.INC file.
BIOS.INC
@Cls MACRO pagenum @GetCharAtr MACRO pagenum @GetCsr MACRO pagenum @GetMode MACRO @PutChar MACRO chr, atrib, pagenum, loops @PutCharAtr MACRO chr, atrib, pagenum, loops @Scroll MACRO distance:REQ, atrib:=<07h>, upcol, uprow, dncol, dnrow @SetColor MACRO color @SetCsrPos MACRO column, row, pagenum @SetCsrSize MACRO first, last @SetMode MACRO mode @SetPage MACRO pagenum @SetPalette MACRO color
CMACROS.INC, CMACROS.NEW
These two include files contain the same macros. Use CMACROS.NEW for programs written in MASM 6.0 and later. Use CMACROS.INC for programs written in MASM 5.1 or earlier, or if you have problems with CMACROS.NEW. @reverse MACRO list arg MACRO args assumes MACRO s,ln
Filename: LMARFC06.DOC Project: MASM Reference Template: MSGRIDA1.DOT Author: a.c. birdsong Last Saved By: Launi Lockard Revision #: 26 Page: 180 of 2 Printed: 10/02/00 04:16 PM
Macros
181
callcrt MACRO funcname cBegin MACRO pname cEnd MACRO pname cEpilog MACRO procname, flags, cbParms, cbLocals, reglist, userparms cProc MACRO pname:REQ, attribs, autoSave cPrologue MACRO procname, flags, cbParms, cbLocals, reglist, userparms createSeg MACRO segName, logName, aalign, combine, class, grp cRet MACRO defGrp MACRO foo:vararg errn$ MACRO l,x errnz MACRO x externA MACRO names:req, langtype externB MACRO names:req, langtype externCP MACRO n,c externD MACRO names:req, langtype externDP MACRO n,c externFP MACRO names:req, langtype externNP MACRO names:req, langtype externP MACRO n,c externQ MACRO names:req, langtype externT MACRO names:req, langtype externW MACRO names:req, langtype farPtr MACRO n,s,o globalB MACRO name:req, initVal:=<?>, repCount, langType globalCP MACRO n,i,s,c globalD MACRO name:req, initVal:=<?>, repCount, langType globalDP MACRO n,i,s,c globalQ MACRO name:req, initVal:=<?>, repCount, langType globalT MACRO name:req, initVal:=<?>, repCount, langType globalW MACRO name:req, initVal:=<?>, repCount, langType labelB MACRO names:req,langType labelCP MACRO n,c
182
Reference
labelD MACRO names:req,langType labelDP MACRO n,c labelFP MACRO names:req,langType labelNP MACRO names:req,langType labelP MACRO n,c labelQ MACRO names:req,langType labelT MACRO names:req,langType labelW MACRO names:req,langType lbl MACRO names:req localB MACRO name localCP MACRO n localD MACRO name localDP MACRO n localQ MACRO name localT MACRO name localV MACRO name,a localW MACRO name logName&_assumes MACRO s logName&_sbegin MACRO n MACRO outif MACRO name:req, defval:=<0>, onmsg, offmsg parmB MACRO names:req parmCP MACRO n parmD MACRO names:req parmDP MACRO n parmQ MACRO names:req parmR MACRO n,r,r2 parmT MACRO names:req parmW MACRO names:req regPtr MACRO n,s,o save MACRO r sBegin MACRO name:req
Macros
183
sEnd MACRO name setDefLangType MACRO overLangType staticB MACRO name:req, initVal:=<?>, repCount staticCP MACRO name:req, i, s staticD MACRO name:req, initVal:=<?>, repCount staticDP MACRO name:req, i, s staticI MACRO name:req, initVal:=<?>, repCount staticQ MACRO name:req, initVal:=<?>, repCount staticT MACRO name:req, initVal:=<?>, repCount staticW MACRO name:req, initVal:=<?>, repCount
MS-DOS.INC
NPVOID TYPEDEF NEAR PTR FPVOID TYPEDEF FAR PTR FILE_INFO STRUCT @ChDir MACRO path:REQ, segmnt @ChkDrv MACRO drive @CloseFile MACRO handle:REQ @DelFile MACRO path:REQ, segmnt @Exit MACRO return @FreeBlock MACRO segmnt @GetBlock MACRO graphs:REQ, retry:=<0> @GetChar MACRO ech:=<1>, cc:=<1>, clear:=<0> @GetDate MACRO @GetDir MACRO buffer:REQ, drive, segmnt @GetDrv MACRO @GetDTA MACRO @GetFileSize MACRO handle:REQ @GetFirst MACRO path:REQ, atrib, segmnt @GetInt MACRO interrupt:REQ @GetNext MACRO
184
Reference
@GetStr MACRO ofset:REQ, terminator, limit, segmnt @GetTime MACRO @GetVer MACRO @MakeFile MACRO path:REQ, atrib:=<0>, segmnt, kind @MkDir MACRO path:REQ, segmnt @ModBlock MACRO graphs:REQ, segmnt @MoveFile MACRO old:REQ, new:REQ, segold, segnew @MovePtrAbs MACRO handle:REQ, distance @MovePtrRel MACRO handle:REQ, distance @OpenFile MACRO path:REQ, access:=<0>, segmnt @PrtChar MACRO chr:VARARG @Read MACRO ofset:REQ, bytes:REQ, handle:=<0>, segmnt @RmDir MACRO path:REQ, segmnt @SetDate MACRO month:REQ, day:REQ, year:REQ @SetDrv MACRO drive:REQ @SetDTA MACRO buffer:REQ, segmnt @SetInt MACRO interrupt:REQ, vector:REQ, segmnt @SetTime MACRO hour:REQ, minutes:REQ, seconds:REQ, hundredths:REQ @ShowChar MACRO chr:VARARG @ShowStr MACRO ofset:REQ, segmnt @TSR MACRO paragraphs:REQ, return @Write MACRO ofset:REQ, bytes:REQ, handle:=<1>, segmnt
MACROS.INC
@ArgCount MACRO arglist:VARARG @ArgI MACRO index:REQ, arglist:VARARG @ArgRev MACRO arglist @PopAll MACRO @PushAll MACRO @RestoreRegs MACRO @SaveRegs MACRO regs:VARARG echof MACRO format:REQ, args:VARARG pushc MACRO op
Macros
185
PROLOGUE.INC
cEpilogue MACRO szProcName, flags, cbParams, cbLocals, rgRegs, rgUserParams cPrologue MACRO szProcName, flags, cbParams, cbLocals, rgRegs, rgUserParams
WIN.INC
The include file WIN.INC is WINDOWS.H processed by H2INC, and slightly modified to reduce unnecessary warnings.
186
Reference
187
C H A P T E R
Tables
ASCII Chart . . . . . . . . . . . . . . . . . . . . . Key Codes . . . . . . . . . . . . . . . . . . . . . . MS-DOS Program Segment Prefix (PSP) Color Display Attributes . . . . . . . . . . . . . Hexadecimal-Binary-Decimal Conversion
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188 190 192 193 194
188
Reference
ASCII Codes
Tables
189
190
Reference
Key Codes
Tables
191
192
Reference
MS-DOS Program Segment Prefix (PSP)
1 Opcode for INT 20h instruction (CDh 20h) 2 Segment of first allocatable address following the program (used for memory allocation) 3 Reserved or used by MS-DOS 4 Opcode for far call to MS-DOS function dispatcher 5 Vector for terminate routine 6 Vector for CTRL+C handler routine 7 Vector for error handler routine 8 Segment address of programs environment block 9 Opcode for MS-DOS INT 21h and far return (you can do a far call to this address to execute MS-DOS calls) 10 First command-line argument (formatted as uppercase 11-character filename) 11 Second command-line argument (formatted as uppercase 11-character filename) 12 Number of bytes in command-line argument 13 Unformatted command line and/or default Disk Transfer Area (DTA)
Tables
193
Color Display Attributes

Background Bits F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 A B C D E F Black Blue Green Cyan Red Magenta Brown White Black blink Blue blink Green blink Cyan blink Red blink Brown blink White blink
I
Foreground Num Color Bits* I 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 R 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 A B C D E F Black Blue Green Cyan Red Magenta Brown White Dark gray Light Blue Light green Light cyan Light red Light Magenta Yellow Bright White Num Color
Magenta blink 1
F Flashing bit R Red bit
G Green bit B Blue bit
Intensity bit
* On monochrome monitors, the blue bit is set and the red and green bits are cleared (001) for underline; all color bits are set (111) for normal text.
194
Reference
Hexadecimal-Binary-Decimal Conversion
Hex Number 0 1 2 3 4 5 6 7 8 9 A B C D E F Binary Number 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Decimal Digit 000X 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Decimal Digit 00X0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 Decimal Digit 0X00 0 256 512 768 1,024 1,280 1,536 1,792 2,048 2,304 2,560 2,816 3,072 3,328 3,584 3,840 Decimal Digit X000 0 4,096 8,192 12,288 16,384 20,480 24,576 28,672 32,768 36,864 40,960 45,056 49,152 53,248 57,344 61,440

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CSCI 240 - Assembly Language Programming - MASM & Intel Docs

Microsoft MASM 6.1 Reference Guide

file:///D|/Kip/AsmBookRelated/MASM_Manuals_PDF/ReferenceGuide.htm [9/8/2002 11:24:03 AM]

Document No. DB35749-1292 Printed in the United States of America.

Chapter 5 Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Topical Cross-reference for Coprocessor Instructions . . . . . . . . . . . . . . . . . . . . . 146

Filename: LMARFINT.DOC Template: MSGRIDA1.DOT Revision #: 16 Page: 9 of 2

The following document conventions are used throughout this book:

[ [optional items] ] {choice1 | choice2}

Microsoft CodeView Debugger

Variable HELPFILES INIT

Error! Style not defined.

/DU /E[ ] [n]

/L /NOLOGO /Ooutfile /Sn

/HELP /Ht /Mn /Ni /Zn string

Variable CL H2INC INCLUDE

Error! Style not defined.

/NOL Option /P:number

Operator +name name +name *name *name

/NOF /NOI /NOL

/NOP /PACKC[ [:number] ]

Error! Style not defined.

Variable INCLUDE MASM TMP

/Bl filename /c /Cp /Cu /Cx /Dsymbol[ [=value] ]

For compatibility with QuickAssembler makefiles, ML recognizes these options:

/Cl /Ez /P1 /P2 /s /Sq

Variable INCLUDE ML TMP

Error! Style not defined.

PWB (Programmers WorkBench)

PWB (Programmers WorkBench)

/m mark /P[ [init] ]

Error! Style not defined. Option [ ] file... [/t] Action

Variable HELPFILES INIT TMP

/HELP /Iu /n /o filename /v /?

Variable HELPFILES QH TMP

Topical Cross-reference for Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Topical Cross-reference for Directives

Conditional Control Flow

Structure and Record

Symbols and Operators

Topical Cross-reference for Symbols

Symbols and Operators

Topical Cross-reference for Operators

Logical and Shift

Symbols and Operators

Symbols and Operators

Symbols and Operators

Symbols and Operators

Topical Cross-reference for Processor Instructions

SETAE/SETNB SETC SETGE/SETNL SETNC SETNP/SETPO SETP/SETPE

SETB/SETNAE SETE/SETZ SETL/SETNGE SETNE/SETNZ SETNS SETS

CLTS LMSW SGDT/SIDT/SLDT VERR INVD#

LAR LSL SMSW VERW INVLPG#

Interpreting Processor Instructions

Timings on the 8088 and 8086 Processors

Timings on the 8028680486 Processors

Sign bit. If set, sign-extend 8-bit immediate data to 16 bits.

Register. This 3-bit field specifies one of the general-purpose registers:

Segment register. This field specifies one of the segment registers:

Interpreting 8038680486 Encoding Extensions

Encoding Differences for 32-Bit Operations

Scaled Index Base Byte

AAA ASCII Adjust After Addition

AAD ASCII Adjust Before Division

CPU 88/86 286 386 486

AAD ASCII Adjust Before Division

CPU 88/86 286 386 486

AAM ASCII Adjust After Multiply

AAM ASCII Adjust After Multiply

CPU 88/86 286 386 486

AAS ASCII Adjust After Subtraction

CPU 88/86 286 386 486

ADC Add with Carry

ADC Add with Carry

WORD PTR m32[2],dx

dx,WORD PTR m32[2]

WORD PTR m32[2],16

Operator +name name +name name name