Module-2

Combinational Logic &

Sequential Logic
 Syllabus
• Introduction, Combinational Circuits,
• Design Procedure,
• Binary Adder- Subtractor,
• Decoders,
• Encoders,
• Multiplexers,
• HDL Models of Combinational Circuits – Adder, Multiplexer,
Encoder.
• Introduction, Sequential Circuits,
• Storage Elements: Latches, Flip-Flops.
 Introduction
• A combinational circuit consists of logic gates whose outputs
at any time are determined from only the present combination
of inputs.
• A combinational circuit performs an operation that can be
specified logically by a set of Boolean functions.

• In contrast, sequential circuits employ storage elements in

addition to logic gates. Their outputs are a function of the
inputs and the state of the storage elements.
• Because the state of the storage elements is a function of
previous inputs, the outputs of a sequential circuit depend not
only on present values of inputs, but also on past inputs, and
the circuit behavior must be specified by a time sequence of
inputs and internal states.
 COMBINATIONAL CIRCUITS
• A combinational circuit consists of an interconnection of
logic gates.

• The n input binary variables come from an external

source; the m output variables are produced by the internal
combinational logic circuit and go to an external
destination.
• Each input and output variable exists physically as an
analog signal whose values are interpreted to be a binary
signal that represents logic 1 and logic 0.
 COMBINATIONAL CIRCUITS
• For n input variables, there are 2n possible combinations of the
binary inputs.
• A combinational circuit can be specified with a truth table that
lists the output values for each combination of input variables.
• Here we formulate systematic analysis and design procedures
for combinational circuits.
• We’ll address three tasks: (1) Analyze the behavior of a given
logic circuit, (2) synthesize a circuit that will have a given
behavior, and (3) write hardware description language (HDL)
models for some common circuits.
• There are several combinational circuits that are employed
extensively in the design of digital systems. These circuits are
available in IC and are classified as standard components.
They perform specific digital functions commonly needed in
the design of digital systems.
 DESIGN PROCEDURE

The procedure involves the following steps:

1. From the specifications of the circuit, determine the
required number of inputs and outputs and assign a
symbol to each.
2. Derive the truth table that defines the required
relationship between inputs and outputs.
3. Obtain the simplified Boolean functions for each output
as a function of the input variables.
4. Draw the logic diagram and verify the correctness of the
design (manually/simulation).
 DESIGN PROCEDURE
• Truth table, Combinational circuit
• The output functions specified in the truth table give the exact
definition of the combinational circuit. It is important that the verbal
specifications be interpreted correctly in the truth table.
• The output binary functions listed in the truth table are simplified by
any available method, such as algebraic manipulation, the map
method, or a computer-based simplification program. Frequently,
there is a variety of simplified expressions from which to choose.
• In a particular application, certain criteria will serve as a guide in the
process of choosing an implementation.
• A practical design must consider such constraints as the number of
gates, number of inputs to a gate, propagation time of the signal
through the gates, number of interconnections, limitations of the
driving capability of each gate, and various other criteria that must be
taken into consideration when designing integrated circuits.
 Code Conversion Example
• The large variety of codes for the same discrete elements of
information results in the use of different codes by different digital
systems.
• It is sometimes necessary to use the output of one system as the
input to another.
• A conversion circuit must be inserted between the two systems if
each uses different codes for the same information.
• Thus, a code converter is a circuit that makes the two systems
compatible even though each uses a different binary code.
• A combinational circuit performs this transformation by means of
logic gates.
• The design procedure will be illustrated by an example, that
converts binary coded decimal (BCD) to the excess-3 code for the
decimal digits.
• The bit combinations assigned to the BCD and excess-3 codes are
listed in Table.
• Note that four binary variables may have 16 bit combinations, but only 10
are listed in the truth table. The six bit combinations not listed for the input
variables are don’t-care combinations.
• These values have no meaning in BCD and we assume that they will never
occur in actual operation of the circuit. Therefore, we are at liberty to assign
to the output variables either a 1 or a 0, whichever gives a simpler circuit.
y = CD + (C + D)’
x = B’(C + D) + BC’D’ w = A + BC + BD = A + B(C + D)
= B’(C + D) + B(C + D)’
 BINARY ADDER–SUBTRACTOR
• A binary adder–subtractor is a combinational circuit that
performs the arithmetic operations of addition and
subtraction with binary numbers.
• When the augend and addend numbers contain more
significant digits, the carry obtained from the addition of
two bits is added to the next higher order pair of significant
bits.
• A combinational circuit that performs the addition of two
bits is called a half adder.
• One that performs the addition of three bits (two significant
bits and a previous carry) is a full adder.
• The names of the circuits stem from the fact that two half
adders can be employed to implement a full adder.
 Half Adder
• The input variables designate the augend and addend bits; the output
variables produce the sum and carry. We are assigning symbols x and y to
the two inputs and S (sum) and C (carry) to the outputs.
• The simplified sum-of-products expressions are S = x’y + xy’ and C = xy.
 Full Adder
• Addition of n-bit binary numbers requires the use of a full adder, and the process of
addition proceeds on a bit-by-bit basis, right to left, beginning with the least
significant bit. After the least significant bit, addition at each position adds not only
the respective bits of the words, but must also consider a possible carry bit from
addition at the previous position.
• A full adder is a combinational circuit that forms the arithmetic sum of three bits. It
consists of three inputs and two outputs. Two of the input variables, denoted by x and
y, represent the two significant bits to be added. The third input, z , represents the
carry from the previous lower significant position. The two outputs are designated by
the symbols S for sum and C for carry.
• The simplified expressions are
S = x’y’z + x’yz’ + xy’z’ + xyz
C = xy + xz + yz
ഥB
Sum = A ഥ BCത + AB
ഥC + A ഥCത + ABC ഥ BC + AB
Carry = A ഥC + ABCത + ABC ഥ 𝐁 + 𝐀𝑩
[= C(𝑨 ഥ ) + 𝐀𝐁 = C(𝐀 ⊕ 𝐁)+AB]

ഥB
Sum = A ഥ BCത + AB
ഥC + ABC + A ഥCത ഥ BC + AB
Carry = A ഥC + ABCത + ABC + ABC + ABC

ഥB
Sum = C(A ഥ + AB) + Cത (A
ഥB + AB
ഥ) ഥ BC + ABC + AB
Carry = A ഥC + ABC + ABCത + ABC

Sum = C(A ⊕ B) + Cത (A ⊕ B) ഥ + A + AC B
Carry = BC A ഥ + B + AB(Cത + C)

Sum = 𝐀 ⊕ 𝐁 ⊕ 𝐂 Carry = 𝐀𝐁 + 𝐁𝐂 + 𝐀𝐂
Implementation of full adder with two half
adders and an OR gate
 MULTIPLEXERS(MUX)
• A multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single
output line. The selection of a particular input line is controlled by a
set of selection lines.
• Normally, there are 2n input lines and n selection lines whose bit
combinations determine which input is selected.
• A two-to-one-line multiplexer connects one of two 1-bit sources to a
common destination, as shown in Fig.

2:1 Mux

[2n:1Mux, with n select line]

• The circuit has two data input lines, one output line, and
one selection line S. When S = 0, the upper AND gate is
enabled and I0 has a path to the output. When S = 1, the
lower AND gate is enabled and I1 has a path to the output.
• The multiplexer acts like an electronic switch that selects
one of two sources.
• The block diagram of a multiplexer is depicted by a wedge-
shaped symbol.
• A multiplexer is also called a data selector, since it selects
one of many inputs and steers the binary information to the
output line.
 • Each of the four inputs, I0
through I3, is applied to one
input of an AND gate.
• Selection lines S1 and S0 are
decoded to select a particular
AND gate.
• The outputs of the AND gates
are applied to a single OR
gate that provides the one-line
output.
• The function table lists the
input that is passed to the
output for each combination
of the binary selection values.

4:1 Mux
 Quadruple 2-to-1-line multiplexer
• The AND gates and inverters in the multiplexer resemble a decoder circuit, and
indeed, they decode the selection input lines.
• The outputs of the AND gates are applied to a single OR gate. The size of a
multiplexer is specified by the number 2n of its data input lines and the single
output line. The n selection lines are implied from the 2n data lines.
• As in decoders, multiplexers may have an enable input to control the operation of
the unit.
• When the enable input is in the inactive state, the outputs are disabled, and when it
is in the active state, the circuit functions as a normal multiplexer.
• Multiplexer circuits can be combined with common selection inputs to provide
multiple-bit selection logic.
• The circuit has four multiplexers, each capable of selecting one of two input lines.
Output Y0 can be selected to come from either input A0 or input B0. Similarly,
output Y1 may have the value of A1 or B1, and so on.
• Input selection line S selects one of the lines in each of the four multiplexers. The
enable input E must be active for normal operation.
• As shown in the function table, the unit is enabled when E = 0. Then, if S = 0, the
four A inputs have a path to the four outputs. If, by contrast, S = 1, the four B inputs
are applied to the outputs. The outputs have all 0’s when E = 1, regardless of the
value of S .
Quadruple 2-to-1-line multiplexer
Boolean Function Implementation in MUX
• The minterms of a function are generated in a
multiplexer by the circuit associated with the selection
inputs.
• The individual minterms can be selected by the data
inputs. Boolean function of n variables with a
multiplexer that has n - 1 selection inputs.
• The first n - 1 variables of the function are connected to
the selection inputs of the multiplexer.
• The remaining single variable of the function is used for
the data inputs. If the single variable is denoted by z,
each data input of the multiplexer will be z, z’, 1, or 0.
Consider the Boolean function, F (x, y, z) = Σm(1, 2, 6, 7)
Implement the function(F) using 4:1 mux with x,y as select lines.
• The two variables x and y are applied to the selection lines as x
is connected to the S1 input and y to the S0 input. The values for
the data input lines are determined from the truth table of the
function.
• When xy = 00, output F is equal to z because F = 0 when z = 0
and F = 1 when z = 1. This requires that variable z be applied to
data input 0.
• In a similar fashion, we can determine the required input to data
lines 1, 2, and 3 from the value of F when xy = 01, 10, and 11,
respectively.
• Procedure: The general procedure for implementing any
Boolean function of n variables with a multiplexer with n - 1
selection inputs and 2n-1 data inputs. To begin with, Boolean
function is listed in a truth table. Then first n - 1 variables in the
table are applied to the selection inputs of the multiplexer. For
each combination of the selection variables, we evaluate the
output as a function of the last variable. This function can be 0,
1, the variable, or the complement of the variable. These values
are then applied to the data inputs in the proper order.
Consider the implementation of the Boolean function,
F (A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)
using 8:1 mux with A,B,C as select lines.
 Three-State Gates
• A multiplexer can be constructed with three-state gates—digital
circuits that exhibit three states.
• Two of the states are signals equivalent to logic 1 and logic 0 as in a
conventional gate. The third state is a high-impedance state in which
(1) the logic behaves like an open circuit, (2) the circuit has no logic
significance, and (3) the circuit connected to the output of the
three-state gate is not affected by the inputs to the gate.
• Three-state gates may perform any conventional logic, such as AND
or NAND. However, the one most commonly used is the buffer gate.
• A normal buffer is having an input control line entering the bottom
of the symbol.
• When the control input is equal to 1, the output is enabled and the
gate behaves like a conventional buffer, with the output equal to the
normal input. When the control input is 0, the output is disabled.
• When a output is disabled, gate goes to a high-impedance state.
The high-impedance state of a three-state gate outputs can be
connected with wires to form a common line without
endangering loading effects.
• For the construction of a two-to-one-line multiplexer with 2
three-state buffers and an inverter.
• The two outputs are connected together to form a single output
line. (Note that this type of connection cannot be made with
gates that do not have three-state outputs.)
• When the select input is 0, the upper buffer is enabled by its
control input and the lower buffer
is disabled. Output Y is then equal
to input A. When the select input
is 1, the lower buffer is enabled
and Y is equal to B.
• The outputs of 4 three-state buffers are connected together to form a single
output line.
• The control inputs to the buffers determine which one of the four normal inputs
I0 through I3 will be connected to the output line.
• The connected buffers must be
controlled so that only 1 three state
buffer has access to the output while
all other buffers are maintained in a
high impedance state.
• One way to ensure that no more than
one control input is active at any
given time is to use a decoder.
• When the enable input of the
decoder is 0, all of its four
outputs are 0 and the bus line is
in a high-impedance state.
When the enable input is active,
one of the three state buffers
will be active, depending on the
binary value in the select inputs
of the decoder.
 HDL MODELS OF COMBINATIONAL CIRCUITS
• The module is the basic building block for modeling hardware with the Verilog HDL.

• The logic of a module can be described in any one of the following modeling styles:

1) Gate-level modeling using instantiations of predefined and user-defined primitive gates.

2) Dataflow modeling using continuous assignment statements with the keyword assign.

3) Behavioral modeling using procedural assignment statements with the keyword always.

• Gate-level (structural) modeling describes a circuit by specifying its gates and how
they are connected with each other. Dataflow modeling is used mostly for describing
the Boolean equations of combinational logic. Behavioral modeling that is used to
describe combinational and sequential circuits at a higher level of abstraction.

• Combinational logic can be designed with truth tables, Boolean equations, and
schematics; Verilog has a construct corresponding to each of these “classical”
approaches to design: user-defined primitives, continuous assignments, and primitives.
 Gate-Level Modeling
• In a gate-level modeling, a circuit is specified by its logic gates and
their interconnections. Gate level modeling provides a textual
description of a schematic diagram.
• The Verilog HDL includes 12 basic gates as predefined primitives.
Four of these primitive gates are of the three-state type.
• They are all declared with the lowercase keywords and, nand, or, nor,
xor, xnor, not, and buf.
• When the gates are simulated, the simulator assigns one value to the
output of each gate at any instant. In addition to the two logic values of
0 and 1, there are two other values: unknown(x) and high
impedance(z).
• A high-impedance condition occurs at the output of three-state gates
that are not enabled.
The four-valued logic truth tables for the and, or, xor, and not
primitives are shown.
• When a primitive gate is listed in a module, we say that it is instantiated in
the module.
• A module that uses a gate in its description is said to instantiate the gate. In a
gate-level modeling, used identifiers having multiple bit widths, called
vectors.
• The syntax specifying a vector includes within square brackets two numbers
separated with a colon. The following Verilog statements specify two
vectors:
output [0: 3] D;
wire [7: 0] SUM;
• Remember that the output is always listed first in the port list of a primitive ,
followed by the inputs.
• Note that the keywords not and nand are written only once and do not have
to be repeated for each gate, but commas must be inserted at the end of each
of the gates in the series, except for the last statement, which must be
terminated with a semicolon.
This decoder has two data inputs A and B and an enable input E .
The four outputs are specified with the vector D. The wire
declaration is for internal connections. Three not gates produce
the complement of the inputs, and four nand gates provide the
outputs for D.
module decoder_2x4_gates (D, A, B, enable);
output [0: 3] D;
input A, B;
input enable;
wire A_not,B_not, enable_not;
not
G1 (A_not, A),
G2 (B_not, B),
G3 (enable_not, enable);
nand
G4 (D[0], A_not, B_not, enable_not),
G5 (D[1], A_not, B, enable_not),
G6 (D[2], A, B_not, enable_not),
G7 (D[3], A, B, enable_not);
endmodule
• Two or more modules can be combined to build a
hierarchical description of a design.
• There are two basic types of design methodologies:
top down and bottom up.
• In a top-down design, the top-level block is defined
and then the subblocks necessary to build the top-
level block are identified.
• In a bottom-up design, the building blocks are first
identified and then combined to build the top-level
block.
• Note that the first character of an identifier cannot
be a number, but can be an underscore.
 Dataflow Modeling
• Dataflow modeling of combinational logic uses a number of operators
that act on binary operands to produce a binary result.
• Verilog HDL provides about 30 different operators. It is necessary to
distinguish between arithmetic and logic operations, so different
symbols are used for each.
• The plus symbol 1+2 indicates the arithmetic operation of addition;
the bitwise logic AND operation (conjunction) uses the symbol &.
• There are special symbols for bitwise logical OR (disjunction), NOT,
and XOR.
• The equality symbol uses two equals signs (without spaces between
them) to distinguish it from the equals sign used with the assign
statement.
• The bitwise operators operate bit by bit on a pair of vector operands to
produce a vector result.
• The concatenation operator provides a mechanism for appending
multiple operands.
• The conditional operator acts like a multiplexer.
• It should be noted that a bitwise operator (e.g., ~) and its
corresponding logical operator (e.g., !) may produce
different results, depending on their operand. For example,
~(1010) is (0101), and !(1010) is 0.
• If the operands are scalar the results will be identical; if the
operands are vectors the result will not necessarily match.
• In general, use the bitwise operators to describe arithmetic
operations and the logical operators to describe logical
operations.
• Dataflow modeling uses continuous assignments and the
keyword assign. A continuous assignment is a statement
that assigns a value to a net.
• The data type family net is used in Verilog HDL to
represent a physical connection between circuit elements.
• A net is declared explicitly by a net keyword (e.g., wire ) or
by declaring an identifier to be an input port.
• If the net is connected to an output of a gate, the net is said to
be driven by the gate, and the logic value of the net is
determined by the logic values of the inputs to the gate and
the truth table of the gate.
• As an example, assuming that the variables were declared, a
2-to-1-line multiplexer with scalar data inputs A and B, select
input S, and output Y is described with the continuous
assignment;
assign Y == (A && S) || (B && S)
• The relationship between Y, A, B, and S is declared by the
keyword assign, followed by the target output Y and an
equals sign.
• The circuit is defined with four continuous assignment
statements using Boolean expressions, one for each
output.
• The addition logic is described by a single statement
using the operators of addition and concatenation.

// Dataflow description of two-to-four-line decoder with active-

low output enable and inverted output
module decoder_2x4_df (output [0: 3] D, input A, B,
enable);
assign D[0] = !((!A) && (!B) && (!enable)),
D[1] = !(!A) && B && (!enable)),
D[2] = !(A && (!B) && (!enable)),
D[3] = !(A && B && (!enable));
endmodule
• The plus symbol (+) specifies the binary addition of the four
bits of A with the four bits of B and the one bit of C in.
• The target output is the concatenation of the output carry Cout
and the four bits of Sum. Concatenation of operands is
expressed within braces and a comma separating the operands.
• Thus, {C_out, Sum} represents the five-bit result of the addition
operation.

// Dataflow description of four-bit adder

module binary_adder (output [3: 0] Sum, output C_out, input [3: 0] A,
B, input C_in);
assign {C_out, Sum} = A + B + C_in;
endmodule
• Dataflow HDL models describe combinational circuits by their
function rather than by their gate structure.
• The module specifies two, 4-bit inputs A and B and three
outputs. One output (A_lt_B) is logic 1 if A is less than B, a 2nd
output (A_gt_B) is logic 1 if A is greater than B, and a 3rd output
(A_eq_B) is logic 1 if A is equal to B.
• A Verilog HDL synthesis compiler can accept this module
description as input, execute synthesis algorithms, and provide
an output netlist and a schematic of a circuit equivalent without
manual intervention. The designer need not draw the schematic.

// Dataflow description of a four-bit comparator

module mag_compare(output A_lt_B, A_eq_B, A_gt_B, input [3: 0] A,
B);
assign A_lt_B = (A < B);
assign A_gt_B = (A > B);
assign A_eq_B = (A = = B);
endmodule
• The next example uses the conditional operator (? :). This operator
takes three operands:
condition ? true-expression : false-expression;
• The condition is evaluated. If the result is logic 1, the true expression
is evaluated and used to assign a value to the left-hand side of an
assignment statement. If the result is logic 0, the false expression is
evaluated.
• The two conditions together are equivalent to an if–else condition.
• The continuous assignment,
assign OUT = select ? A : B;
• specifies the condition that OUT A if select 1, else OUT B if select 0.

// Dataflow description of two-to-one-line multiplexer

module mux_2x1_df(m_out, A, B, select);
output m_out;
input A, B;
input select;
assign m_out = (select)? A : B;
endmodule
 Behavioral Modeling
• Behavioral modeling represents digital circuits at a
functional and algorithmic level. It is used mostly to
describe sequential circuits, but can also be used to describe
combinational circuits.
• Behavioral descriptions use the keyword always, followed
by an optional event control expression and a list of
procedural assignment statements. The event control
expression specifies when the statements will execute.
• The target output of a procedural assignment statement must
be of the reg data type. Contrary to the wire data type,
whereby the target output of an assignment may be
continuously updated, a reg data type retains its value until a
new value is assigned.
• Since variable m_out is a target output, it must be declared as reg. The
procedural assignment statements inside the always block are executed every
time there is a change in any of the variables listed after the @ symbol. (Note
that there is no semicolon (;) at the end of the always statement.)
• In this case, these variables are the input variables A, B, and select. The
statements execute if A, B, or select changes value. Note that the keyword or,
instead of the bitwise logical OR operator “|”, is used between variables. The
conditional statement if–else provides a decision based upon the value of the
select input. The if statement can be written without the equality symbol:
if (select) OUT = A;
• The statement implies that select is checked for logic 1.

// Behavioral description of two-to-one-line multiplexer

module mux_2x1_beh (m_out, A, B, select);
output m_out;
input A, B, select;
reg m_out;
always @(A or B or select)
if (select == 1) m_out = A;
else m_out = B;
endmodule
• The select input is defined as a two-bit vector, and output y is declared to have type
reg.
• The always statement, in this example, has a sequential block enclosed between the
keywords case and endcase. The case statement is a multiway conditional branch
construct. The block is executed whenever any of the inputs listed after the @ symbol
changes in value.
• Whenever in_0, in_1, in_2, in_3 or select change, the case expression (select) is
evaluated and its value compared, from top to bottom, with the values in the list of
statements that follow, the so-called case items.
• The statement associated with the first case item that matches the case expression is
executed. In the absence of a match, no statement is executed.
• Since select is a two-bit number, it can be equal to 00, 01, 10, or 11. The case items
have an implied priority because the list is evaluated from top to bottom.

// Behavioral description of four-to-one line multiplexer

module mux_4x1_b(output reg m_out,input in_0, in_1, in_2, in_3, input [1: 0] select);
always @ (in_0, in_1, in_2, in_3, select)
case (select)
2’b00: m_out = in_0;
2’b01: m_out = in_1;
2’b10: m_out = in_2;
2’b11: m_out = in_3;
endcase
endmodule
• The list is called a sensitivity list and is equivalent to the event control
expression formed by “ORing” the signals.
• Combinational logic is reactive-when an input changes an output may
change.
• Binary numbers in Verilog are specified and interpreted with the letter b
preceded by a prime. The size of the number is written first and then its
value. Thus, 2’b01 specifies a two-bit binary number whose value is 01.
• Numbers are stored as a bit pattern in memory, but they can be
referenced in decimal, octal, or hexadecimal formats with the letters d, o
and h, respectively.
• For ex., 4’HA = 4’d10 = 4’b1010 and have the same representation in a
simulator.
• If the base of the number is not specified, its interpretation defaults to
decimal. If the size of the number is not specified, the system assumes
that the size of the number is at least 32 bits;
• The integer data type (keyword integer) is stored in a 32-bit
representation.
• The case construct has two important variations: casex
and casez.
• The casex will treat as don’t-cares any bits of the case
expression or the case item that have logic value x or z.
• The casez construct treats as don’t-cares only the logic
value z, for the purpose of detecting a match between
the case expression and a case item.
• The list of case items need not be complete. If the list
of case items does not include all possible bit patterns
of the case expression, no match can be detected.
• Unlisted case items, i.e., bit patterns that are not
explicitly decoded can be treated by using the default
keyword as the last item in the list of case items.
 Introduction to Sequential circuits
• Hand-held devices, cell phones, navigation receivers, personal
computers, digital cameras, personal media players, and
virtually all electronic consumer products have the ability to
send, receive, store, retrieve, and process information
represented in a binary format.
• The technology enabling and supporting these devices is
critically dependent on electronic components that can store
information, i.e., have memory.
• The digital circuits considered thus far have been
combinational--their output depends only and immediately on
their input--they have no memory,
• Sequential circuits, however, act as storage elements and have
memory. They can store, retain, and then retrieve information
when needed at a later time.
 SEQUENTIAL CIRCUITS
• The sequential circuit consists of a combinational circuit to which storage
elements are connected to form a feedback path. The storage elements are devices
capable of storing binary information. The binary information stored in these
elements at any given time defines the state of the sequential circuit at that time.
• The sequential circuit receives binary information from external inputs that,
together with the present state of the storage elements, determine the binary value
of the outputs.
• These external inputs also determine the condition for changing the state in the
storage elements.
• The block diagram demonstrates that the outputs in a sequential circuit are a
function not only of the inputs, but also of the present state of the storage
elements. The next state of the storage elements is also a function of external
inputs and the present state.
• Thus, a sequential circuit is specified by a time sequence of inputs, outputs,
and internal states.
 Types of sequential circuits
• There are two main types of sequential circuits, and their
classification is a function of the timing of their signals.
• A synchronous sequential circuit is a system whose behavior can be
defined from the knowledge of its signals at discrete instants of time.
• The behavior of an asynchronous sequential circuit depends upon the
input signals at any instant of time and the order in which the inputs
change.
• The storage elements commonly used in asynchronous sequential
circuits are time-delay devices. The storage capability of a time-delay
device varies with the time it takes for the signal to propagate through
the device.
• In gate-type asynchronous systems, the storage elements consist of
logic gates whose propagation delay provides the required storage.
• Thus, an asynchronous sequential circuit may be regarded as a
combinational circuit with feedback. Because of the feedback among
logic gates, an asynchronous sequential circuit may become unstable
at times.
 • A synchronous sequential circuit employs signals that affect the storage
elements at only discrete instants of time.
• Synchronization is achieved by a timing device called a clock
generator, which provides a clock signal having the form of a periodic
train of clock pulses. The clock signal is commonly denoted by the
identifiers clock and clk.
• The clock pulses are distributed throughout the system in such a way
that storage elements are affected only with the arrival of each pulse.
• Synchronous sequential circuits that use clock pulses to control storage
elements are called clocked sequential circuits.
• The design of synchronous circuits is feasible.

Synchronous clocked
sequential circuit
• The storage elements (memory) used in clocked sequential circuits
are called flipflops. A flip-flop is a binary storage device capable of
storing one bit of information. In a stable state, the output of a flip-
flop is either 0 or 1. A sequential circuit may use many flip-flops to
store as many bits as necessary.
• The combinational logic must respond to a change in the state of the
flip-flop in time to be updated before the next pulse arrives.
• Propagation delays play an important role in determining the
minimum interval between clock pulses that will allow the circuit to
operate correctly.
• A change in state of the flip-flops is initiated only by a clock pulse
Transition-for example, when the value of the clock signals changes
from 0 to 1.
• The transition from one state to the next occurs only at
predetermined intervals dictated by the clock pulses.
 STORAGE ELEMENTS: LATCHES
• A storage element in a digital circuit can maintain a binary state
indefinitely until directed by an input signal to switch states.
• The major differences among various types of storage elements
are in the number of inputs they possess and in the manner in
which the inputs affect the binary state.
• Storage elements that operate with signal levels are referred to
as latches ; those controlled by a clock transition are flip-flops.
• Latches are said to be level sensitive devices; flip-flops are
edge-sensitive devices.
• The two types of storage elements are related because latches
are the basic circuits from which all flip-flops are constructed.
• Although latches are useful for storing binary information and
for the design of asynchronous sequential circuits, they are not
practical for use as storage elements in synchronous sequential
circuits. Because they are the building blocks of flip-flops.
 SR Latch
• The SR latch is a circuit with two cross-coupled NOR gates or two cross-
coupled NAND gates, and two inputs labeled S for set and R for reset.
• The latch has two useful states. When output Q = 1 and Q’ = 0, the latch is
said to be in the set state. When Q = 0 and Q’ = 1, it is in the reset state.
• Outputs Q and Q’ are normally the complement of each other.
• However, when both inputs are equal to 1 at the same time, a condition in
which both outputs are equal to 0 occurs. If both inputs are then switched to 0
simultaneously, the device will enter an unpredictable or undefined state or a
metastable state.
• In normal operation, this condition is avoided by making sure that 1’s are not
applied to both inputs simultaneously.
• The SR latch with two cross-coupled NAND gates is shown
in Fig.
• In comparing the NAND with the NOR latch, note that the
input signals for the NAND require the complement of
those values used for the NOR latch.
• Because the NAND latch requires a 0 signal to change its
state, it is sometimes referred to as an SR latch.
• The operation of the basic SR latch can be modified by providing an additional
input signal that determines (controls) when the state of the latch can be changed
by determining whether S and R (or S and R ) can affect the circuit.
• It consists of the basic SR latch and two additional NAND gates. The control
input En acts as an enable signal for the other two inputs.
• The outputs of the NAND gates stay at the logic-1 level as long as the enable
signal remains at 0. This is the quiescent condition for the SR latch. When the
enable input goes to 1, information from the S or R input is allowed to affect the
latch.
• An indeterminate condition occurs when all three inputs are equal to 1. This
indeterminate condition makes this circuit difficult to manage.
• The SR latch is an important circuit because other useful latches and flip-flops are
constructed from it.
 D Latch (Transparent Latch)
• One way to eliminate the undesirable condition of the indeterminate state in
the SR latch is to ensure that inputs S and R are never equal to 1 at the same
time. This is done in the D latch.
• This latch has only two inputs: D (data) and En (enable). The D input goes
directly to the S input, and its complement is applied to the R input.
• As long as the enable input is at 0, the cross-coupled SR latch has both inputs
at the 1 level and the circuit cannot change state regardless of the value of D.
• The D input is sampled when En = 1. If D = 1, the Q output goes to 1, placing
the circuit in the set state. If D = 0, output Q goes to 0, placing the circuit in
the reset state.
• The D latch receives that designation from its ability to hold data in its
internal storage.
• The binary information present at the data input of the D latch is transferred to
the Q output when the enable input is asserted.
• The output follows changes in the data input as long as the enable input is
asserted. This situation provides a path from input D to the output, and for this
reason, the circuit is often called a transparent latch.
• When the enable input signal is de-asserted, the binary information that was
present at the data input at the time the transition occurred is retained at the Q
output until the enable input is asserted again.
• The graphic symbols for the various latches are shown in Fig.
• The graphic symbol for the SR latch has inputs S and R indicated inside the
block. In the case of a NAND gate latch, bubbles are added to the inputs to
indicate that setting and resetting occur with a logic-0 signal.