Sir Syed CASE Institute of Technology, Islamabad

EE2401 Digital Logic Design

Lab No. 6

Name of Student: Roll No. :

Date of Experiment: Report submitted on:

Marks obtained: Instructor’s Signature:

Instructor: Engr. Safdar Munir

Objectives

1. Introduction to data flow level modeling

2. Operators for data flow level modeling
3. Arithmetic operators
4. Bitwise arithmetic operators
5. Logical operators
6. Conditional operator
7. Concatenation operator
8. Replication operator
9. Task

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Introduction to Gate Level Modeling
LAB TASKS
1. Implement XOR with gate level modeling.

2. Implement the following circuit using gate level modeling.

Sample Output:
A B C Q
1 0 1 0
0 0 1 1
1 1 1 1
3. Implement the following circuit using gate level modeling.

Sample Output:
A B C D O

0 0 0 0 0

0 0 0 1 1

1 0 1 0 0

Display Values in Verilog

Before moving to the verilog syntax and methodology for data flow modelling, it is
important to first understand the functionality of display statement.

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$display task prints output using format similar to C and creates a new line for
further printing.
e.g. $display (“A=%d, B=%o, C=%h, D=%b”, A, B, C, D);

These statements display the values of A, B, C, and D in decimal, octal, hex and
binary number representation respectively. The directives %d, %o, %h, and %b are
sued to print values in decimal, octal, hexadecimal, and binary format respectively.

Variable Declaration and Width Specification

In almost all software programming languages, only variables with fixed sized can
be declared, like C/C++ a variable can be of type char, short, or int. Unlike these
languages a Verilog variable can take any width. The following syntax is used for
declaring a wire

The range is specified as

[Most Significant bit (MSb): Least Significant bit (LSb)].

It is read as MSb down to LSb. If not specified the default value of range is taken as
one bit wide. A Similar syntax is used for declaring a variable of type register.
reg [MSB:LSB] r;

A Similar syntax is used for declaring a inputs or inputs of width more than 1 bit.
input [MSB:LSB] in;

Examples
The Verilog code in this example declares a 1 bit wide variable of type reg r, and
two 1bit wide variables of type wire w1, and w2, an 8 bit wide variable of type reg
vreg, and an 8-bite wide and 1Kbyte deep memory mem in Verilog.
Following are the declarations, a double forward slanted bar ‘//’ in Verilog is used
for comments:

reg r; // 1-bit reg variable r

wire w1, w2; // 2 1-bit wire variables w1 and w2
reg [7:0] vreg; // 8-bit reg variable vreg

A Variable of type reg can also be initialized at declaration as shown here.

reg r = 1’b0; // 1-bit reg variable r initialize to 0 at declaration

Constants
Like variables, a constant in Verilog can be of any size and it can be written in
decimal, binary, octal or hexadecimal format. The decimal is the default format. As
the constant can be of any size, its size is usually written with a ‘ and d, b, o, or h to
specify decimal, binary, octal, or hexadecimal format respectively. A number 13
can be written in different format as shown in Table 2-2:
Table 2-2: Formats to represent constants
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Digital Logic Design Lab (EE-2401) 5
Introduction to Data Flow Modeling
This level of abstraction is higher than the gate level. Expressions, operands and
Operators characterize this level. Most of the operators used in Data Flow
modeling are common to software programmers but there are few more which
are very specific to HW design. In this level every expression starts with keyword
assign. Here is a simple example where two signals a and b are added to produce
c.
assign c = a + b;
-----------------------------------------------------------------------------------------------------
Operator for dataflow level modeling
Dataflow modeling is all about expressions and operators. List of operators for
dataflow modeling is as follows,
------------------------------------------------------------------------------------------------------
1. Arithmetic:
 Binary: +, -, *, /, % (the modulus operator)
 Unary: +, - (This is used to specify the sign)
 Integer division truncates any fractional part
 The result of a modulus operation takes the sign of the first operand
 If any operand bit value is the unknown value x, then the entire result value
is x

Example
Code:
module arithmetic_operators;
initial begin
$display (" 5 + 10 = %d", 5 + 10);
$display (" 5 - 10 = %d", 5 - 10);
$display (" 10 - 5 = %d", 10 - 5);

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 $display (" 10 * 5 = %d", 10 * 5);
$display (" 10 / 5 = %d", 10 / 5);
$display (" 10 / -5 = %d", 10 / -5);
$display (" 10 %s 3 = %d","%", 10 % 3);
$display (" +5 = %d", +5);
$display (" -5 = %d", -5);
$display(“5 power 2=%d”,5**2);
end
endmodule

Output:
5 + 10 = 15
5 - 10 = -5
10 - 5 = 5
10 * 5 = 50
10 / 5 = 2
10 / -5 = -2
10 % 3 = 1
+5 = 5
-5 = -5
5 power 2 =25
-------------------------------------------------------------------------------------------------------
2. Bitwise Arithmetic Operators:
Bitwise operators perform a bit wise operation on two operands. They take
each bit in one operand and perform the operation with the corresponding
bit in the other operand. If one operand is shorter than the other, it will be
extended on the left side with zeroes to match the length of the longer
operand.
 Computations include unknown bits, in the following way:
~x = x
0&x = 0
1&x = x&x = x
1|x = 1
0|x = x|x = x
0^x = 1^x = x^x = x
0^~x = 1^~x = x^~x = x
 When operands are of unequal bit length, the shorter operand is zero-filled
in the most significant bit positions.

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Example:
CODE:
module bitwise_operators;

initial begin
// Bit Wise Negation
$display (" ~4'b0001 = %b", (~4'b0001));
$display (" ~4'bx001 = %b", (~4'bx001));

// Bit Wise AND

$display (" 4'b0001 & 4'b1001 = %b", (4'b0001 & 4'b1001));
$display (" 4'b1001 & 4'bx001 = %b", (4'b1001 & 4'bx001));

// Bit Wise OR
$display (" 4'b0001 | 4'b1001 = %b", (4'b0001 | 4'b1001));
$display (" 4'b0001 | 4'bx001 = %b", (4'b0001 | 4'bx001));
// Bit Wise XOR
$display (" 4'b0001 ^ 4'b1001 = %b", (4'b0001 ^ 4'b1001));
$display (" 4'b0001 ^ 4'bx001 = %b", (4'b0001 ^ 4'bx001));

// Bit Wise XNOR

$display (" 4'b0001 ~^ 4'b1001 = %b", (4'b0001 ~^ 4'b1001));
$display (" 4'b0001 ~^ 4'bx001 = %b", (4'b0001 ~^ 4'bx001));
end
endmodule

OUTPUT:
~4'b0001 = 1110
~4'bx001 = x110
4'b0001 & 4'b1001 = 0001
4'b1001 & 4'bx001 = x001
4'b0001 | 4'b1001 = 1001
4'b0001 | 4'bx001 = x001
4'b0001 ^ 4'b1001 = 1000
4'b0001 ^ 4'bx001 = x000
4'b0001 ~^ 4'b1001 = 0111
4'b0001 ~^ 4'bx001 = x111
--------------------------------------------------------------------------------------------------------
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 3. Logical Operators
 Expressions connected by && and || are evaluated from left to right
 Evaluation stops as soon as the result is known
 The result is a scalar value:
o 0 if the relation is false
o 1 if the relation is true
o x if any of the operands has x (unknown) bits

Example
CODE:
module logical_operators();

initial begin
// Logical AND
$display ("1'b1 && 1'b1 = %b", (1'b1 && 1'b1));
$display ("1'b1 && 1'b0 = %b", (1'b1 && 1'b0));
$display ("1'b1 && 1'bx = %b", (1'b1 && 1'bx));
// Logical OR
$display ("1'b1 || 1'b0 = %b", (1'b1 || 1'b0));
$display ("1'b0 || 1'b0 = %b", (1'b0 || 1'b0));
$display ("1'b0 || 1'bx = %b", (1'b0 || 1'bx));
// Logical Negation
$display ("! 1'b1 = %b", (! 1'b1));
$display ("! 1'b0 = %b", (! 1'b0));
end

endmodule

OUTPUT:
1'b1 && 1'b1 = 1
1'b1 && 1'b0 = 0
1'b1 && 1'bx = x
1'b1 || 1'b0 = 1
1'b0 || 1'b0 = 0
1'b0 || 1'bx = x
! 1'b1 = 0
! 1'b0 = 1
--------------------------------------------------------------------------------------------------------

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 4. Condition Operator
c =( cond) ? a : b;
Same as C/C++ code of
if (cond)
c = a;
else
c=b;

Example
CODE:
module condition_operator;
reg enable,data1,data2;
wire out;
assign out=(enable)? data1:data2;
initial
begin
enable=1;
data1=1;
data2=0;
#20 enable=0;
data1=1;
data2=0;
#20 enable=1;
data1=0;
data2=1;
#20 enable=0;
data1=1;
data2=0;
end
endmodule

OUTPUT:
---------------------------------------------------------------------------------------------------------

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 5. Concatenation Operator:
 Concatenations are expressed using the brace characters { and }, with
commas separating the expressions within.
o Example: + {a, b[3:0], c, 4'b1001} // if a and c are 8-bit numbers, the
results has 24 bits
 Unsized constant numbers are not allowed in concatenations.
Example
CODE:
module concatenation_operator();
initial
begin
$display (" {4'b1001,4'b10x1} = %b", {4'b1001,4'b10x1});
end
endmodule

OUTPUT:
{4'b1001,4'b10x1} = 100110x1
-----------------------------------------------------------------------------------------------------

6. Replication Operator
Replication operator is used to replicate a group of bits n times. Say you have a 4
bit variable and you want to replicate it 4 times to get a 16 bit variable: then we
can use the replication operator.

Operator Description
{n{m}} Replicate value m, n times

 Repetition multipliers (must be constants) can be used:

o {3{a}} // this is equivalent to {a, a, a}
 Nested concatenations and replication operator are possible:
o {b, {3{c, d}}} // this is equivalent to {b, c, d, c, d, c, d}
Example
CODE:
module replication_operator();
initial begin

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$display (" {4{4'b1001}} = %b", {4{4'b1001}});
end
endmodule
OUTPUT:
{4{4'b1001} = 1001100110011001
----------------------------------------------------------------------------------------------------------
Examples
%--------------MAIN
MODULE--------------------------
module my_HA_assign(x,y,s,c);
input x,y;
output s,c;
assign s=x^y;
assign c=x&y;
endmodule

%--------------------------- STIMULUS ------------------------------------------------

module stim_HA_assign;
reg x,y;
wire s,c;
my_HA_assign aa(x,y,s,c);
initial
begin
x=0;
y=0;
#20 x=0;
y=1;
#20 x=1;
y=0;
#20 x=1;
y=1;
end
endmodule
-----------------------------------------------------------------------------------
Problems
1. Implement the following through Data flow continuous assignments. Where in1, in2 and
sel are one bit inputs.

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 2. Implement the following using continous assignments and the operators of data flow
modeling.

3. Prove that a + b = b + a using bitwise or logical operators. a and b are two 4 bit
numbers.
4. Make a two input calculator having functionalities of Addition, Subtraction,
Multiplication and division, using two conditional operators. The inputs are 8 bit decimal
values. Also take a select line as an input. Follow the following rules for the operations
of the calculator.
Selection Operation
0 (00) Addition
1 (01) Subtraction
2 (10) Multiplication
3 (11) Division.

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