Development Guide of T5L ASIC

Development Guide of DWIN T5L ASIC Ver1.
1
Catalog
1. Summary ...........................................................................................................................................................................- 2 -
2. Hardware Description........................................................................................................................................................- 4 -
2.1 PIN Definition .........................................................................................................................................................- 4 -
2.2 Packaging Dimension ..............................................................................................................................................- 9 -
2.3 Basic performance parameters.................................................................................................................................- 9 -
2.4 Notices for Hardware Design ................................................................................................................................- 10 -
3. OS CPU Description........................................................................................................................................................- 11 -
3.1 Initial Configuration ..............................................................................................................................................- 11 -
3.2 Memory .................................................................................................................................................................- 12 -
3.2.1 Code memory(64KBytes)...........................................................................................................................- 12 -
3.2.2 DGUS Variable Memory(256KBytes)........................................................................................................- 13 -
3.2.3 Data Memory(32KBytes) ...........................................................................................................................- 15 -
3.2.4 Extended SFR register ................................................................................................................................- 16 -
3.3 Mathematical operating unit(MDU) ......................................................................................................................- 17 -
3.4 Timer .....................................................................................................................................................................- 18 -
3.5 Watchdog Timer(WDT).........................................................................................................................................- 20 -
3.6 IO...........................................................................................................................................................................- 20 -
3.7 UART communication interface............................................................................................................................- 22 -
3.7.1 UART2 interface.........................................................................................................................................- 22 -
3.7.2 UART3 interface.........................................................................................................................................- 22 -
3.7.3 UART4 interface.........................................................................................................................................- 23 -
3.7.4 UART5 interface.........................................................................................................................................- 24 -
3.8 CAN communication interface ..............................................................................................................................- 24 -
3.9 Interrupt system .....................................................................................................................................................- 27 -
3.9.1 Interrupt control SFR..................................................................................................................................- 27 -
3.9.2 Interrupt priority .........................................................................................................................................- 27 -
3.10 8051 Instruction set of T5L ASIC........................................................................................................................- 29 -
4. Simulation Debug............................................................................................................................................................- 31 -
5. EK043 Evaluation Board.................................................................................................................................................- 33 -
Appendix 1 ..........................................................................................................................................................................- 34 -
Beijing DWIN Technology Co., Ltd. - 1 -- www.dwin.com.cn 400 018 9008 dwinhmi@dwin.com.cn
Development Guide of DWIN T5L ASIC Ver1.1
(4) Summary
The T5L series ASIC is a single-chip and dual-core ASIC IC designed by DWIN technology co., ltd for
AIOT applications with low power consumption, high cost performance, GUI and highly integrated
application, including T5L1(low resolution) and T5L2(high resolution). Its main features are as follow:
(2) Using 8051 core which is the most widely used, mature and stable, the maximum operating frequency of
T5L is up to 250MHZ, 1T(single instruction cycle)high speed operation.
(3) Separated GUI CPU Core running DGUS II System:
(1) High-speed display memory, 2.4 GB/S bandwidth, 24bit color display resolution supporting to
800*600(T5L1) or 1366*768(T5L2).
(2) 2D hardware acceleration, the decompression speed of JPEG is up to 200fps@1280*800, the UI

interface with animation and icons as its main feature is extremely cool and smooth.
(3) JPEG stores images and icons in compressed mode, external memory greatly reduced to low-cost
16Mbytes SPI Flash.
(4) With maximum 400 Hz touch point speed, touch screen supports resistance or capacitance, and its
sensitivity can be adjusted.
(5) High-quality speech compression storage and playback.
(6) 128Kbytes variable storage space, exchanging data with OS CPU Core using memory interface,
extremely simple to apply.
(7) 2-way 10bit, 800KHz, DC/DC controller, simplify LED backlight, analog power supply design and save
cost and space.
(8) 1-way 15bit32Ksps PWM digital power amplifier driver loudspeaker, save power amplifier cost and
achieve high signal-to-noise ratio and sound quality restoration.
(9) Supporting PC configuration development and simulation,supporting background remote upgrade.

(4) Separated CPU (OS CPU) core runs user 8051 code or DWIN OS system, user CPU is omitted in
practical application.
(10)Standard 8051 architecture and instruction set, 64Kbytes code space, 32Kbytes on-chip RAM.
(11)64 bit integer mathematical operation unit(MDU), including 64 bit MAC and 64 bit divider.
(12)Built-in software WDT, three 16 bit Timers, 12 interrupt signals with the highest four interrupt nesting.
(13)22 IO, 4-channel UARTS,1-channel CAN interface, up to 8-channel 12-bit A/D, 1-channle16-bit
resolution adjustable PWM.
(14)Support IAP on-line simulation and debugging, unlimited number of breakpoints.

(15)Upgrade code online through DGUS system.
(5) 1Mbytes on-chip Flash with DWIN patent encryption technology ensure code and data security,
eliminate copycat and cloning.
(6) Reduces crystal requirements and PCB design challenges for a variety of inexpensive wide-range tuned
impedance crystal oscillators and PLLs.
(7) 3.3V IO voltage, can adapt to 1.8/2.5/3.3 various levels.
(8) Supporting SD interface or UART1 download and configuration, supporting SD card file reading and
rewriting.
(9) Supporting DWIN WiFi module to access to DWIN cloud directly, and easily developing various cloud
platform applications.
(10) Working temperature ranges from - 40℃ to +85℃ (Customizable IC for -55℃ to 105℃
operating temperature range )

(11)With low power consumption and strong anti-interference ability, it can work steadily on the
double-sided PCB design, and easy to pass EMC/EMI test.
(12) Using 0.4mm ELQFP128 packaging, low manufacturing difficulty and low cost.
(13)Providing T5L IC + LCD + touch screen + design support for industry customers with cost-effective
matching program sales and comprehensive technical service support.
(5) Hardware Description
• PIN Definition
T5L ASIC is packaged in ELQFP128 (16*16*1.5mm), pins arrangement are shown in Fig 2-1.
Fig.2-1 The arrangement of T5L pin
Definition
C PI
P N# Functio Instructions Function Instructions Function Instructions
O 1 n 1TX4 UART4 data 2 3
S
O 11 RX4 transmition
UART4 data reception
S
O 21 TX5 UART5 data
S
O 21 RX5 transmition
UART5 data reception
S
O 21 P0.0 I/O port
S
O 21 P0.1 I/O port
S
O 21 P0.2 I/O port CAN_T CAN interface data transmition
S
O 21 P0.3 I/O port X
CAN_R CAN interface data reception
S
O 21 P0.4 I/O port X TX2 UART2 data transmition
S
O 21 P0.5 I/O port RX2 UART2 data reception
S
O 21 P0.6 I/O port TX3 UART3 data transmition
S
O 2 P0.7 I/O port RX3 UART3 data reception
S T5L1=1.25V
O 3 VDD
S T5L2=1.2V
O 4 VIO 3.3V
S
O 5 P1.0 I/O port
S
O 6 P1.1 I/O port
S
O 7 P1.2 I/O port
S
O 8 P1.3 I/O port
S
O 9 P1.4 I/O port
S
O 1 P1.5 I/O port
S
O 01 P1.6 I/O port
S
O 11 P1.7 I/O port
S 2 T5L1=1.25V
O 1 VDD
S 3 T5L2=1.2V
O 1 VIO 3.3V
S
O 41 P2.0 I/O port
S
O 51 P2.1 I/O port
S
O 61 P2.2 I/O port
S
O 71 P2.3 I/O port
S
O 81 P2.4 I/O port
S
O 92 P2.5 I/O port
S
O 02 P2.6 I/O port
S
O 12 P2.7 I/O port
S 2 T5L1=1.25V
O 2 VDD
S 3 T5L2=1.2V
O 2 VIO 3.3V
S
O 42 P3.0 I/O port EX0 External interrupt 0 input
S
O 52 P3.1 I/O port EX1 External interrupt 1 input
S
O 62 P3.2 I/O port
S
O 72 P3.3 I/O port
S 82 GND
93 GND
03 GND
1 0:GUI JTAG, 1=OS
3 OS/G
2 UI JTAG
3 /RST System reset input
33 JTAG PIN35#-PIN38# Select: 0=JTAG, 1=I/O port
4 S LCD screen
G 3 P0.0 I/O port TMS JTAG interface TCON_C
U 5 S TCON
interface
LCD screen
G 3 P0.1 I/O port TCK JTAG interface TCON_CL
U 6 K TCON
TCON_DA interface
LCD screen
G 3 P0.2 I/O port TDI JTAG interface T
U 7 TCON
G 3 P0.3 I/O port TDO JTAG interface A
TCON_RS interface
LCD screen
U 8
Beijing DWIN Technology Co., Ltd. - 5 -- www.dwin.com.cn 400 018 9008 T dwinhmi@dwin.com.cn
TCON
G 3 P0.4 I/O port TX1 UART1 data transmition interface
U
G 94 P0.5 I/O port RX1 UART1 data reception
U
G 04 P0.6 I/O port FSK_T FSK transceiver data
U
G 14 P0.7 I/O port X
FSK_R transmition
FSK transceiver data reception
U 2 X 4-wire resistance touch screen
G 4 ADC AD input RTP_X
U 3 0 0 interface
4-wire resistance touch screen
G 4 ADC AD input RTP_Y
U 4 1 0 interface
G 4 ADC AD input RTP_X
U 5 2 1 interface
G 4 ADC AD input RTP_Y
U 6 3 1 interface
G 4 ADC AD input IF_0.4 DC/DC 0.4V voltage feedback
U
G 74 4ADC AD input VF_1.2 DC/DC 1.25V voltage feedback
U
G 84 5ADC AD input 5IF_0.4
U
G 95 6ADC AD input VF_1.2
U
G 05 7
AGN AD GND 5
U 1 D AD power supply,3.3V, please as close as possible to the AVDD pin to connect the 470pJ(COG
G 5 AVD materal)
U 2 D
in
ADparallel withpower
reference 105 for capacitor
supply, filtering
please as close as possible to the VREF pin to connect the 470pJ(COG
G 5 VRE
U 3 F materal) in parallel with 105 for capacitor filtering
T5L1=1.25V T5L2=1.2V,please as close as possible to the VDDPLL pin to connect the
G 5 VDDP 470pJ(COG
U 4 LL
G 5 XIN materal) in parallel with 105
Crystal,10MHz- for capacitor
CLK_I 3.3Vfiltering
clock input
U
G 55 XOU 12MHZ
Crystal N
U
G 65 TVDD 1.1V
U
G 75 VIO 3.3V
U
G 85 P1.0 I/O port PWM 16bit PWM output
U 9 0 LCD screen
G 6 P1.1 I/O port PWM 16bit PWM output PWM_V
U 0 1 AVDD
DC/DC
LCD
G 6 P1.2 I/O port PWM 16bit PWM output PWM_I backlight
U 1 2
DC/DC
Buzzer/speake
G 6 P1.3 I/O port PWM 16bit PWM output BUZZ&SP r
U 2 3 K
drive
SPI Flash
G 6 P1.4 I/O port SDD0 SD card interface:data SPI_D0
U 3 interface:data
SPI Flash
U 4 interface:data
SPI Flash
U 5 interface:data
SPI Flash
U 6 interface:data
G 6 VDD T5L1=1.25V
U 7
T5L2=1.2V
G 6 VIO 3.3V
U 8 Amplifier
G 6 P2.0 I/O port SDCK SD card interface:clock PA_EN power switch
U 9 for voice
I
G 7 P2.1 I/O port SDCK SD card interface:instructions
U
G 07 P2.2 I/O port SPI_C SPI Flash interface:chip
U
G 17 P2.3 I/O port S
SPI_CL selection
SPI Flash interface:clock
U 2 K Capacitan
4-wire resistance touch
G 7 P2.4 I/O port RTP_Y CTP_SD ce touch
U 3 1 screen interface A screen
I
Capacitan
G 7 P2.5 I/O port RTP_X CTP_IN ce touch
U 4 1 screen interface T screen
I
Capacitan
G 7 P2.6 I/O port RTP_Y CTP_SC ce touch
U 5 0 screen interface L screen
I
Capacitan
G 7 P2.7 I/O port RTP_X CTP_RS ce touch
U 6 0 screen interface T screen
I
T5L1=1.25V
G 7 VDD
U 7 T5L2=1.2V
G 7 VIO 3.3V
U 8 System clock frequency
G 7 P3.0 I/O port CLK_O division
U 9 UT
output
T/R switching signal
G 8 P3.1 I/O port FSK_T for half-duplex use of
U 0 R SFK
I
G 8 P3.2 I/O port
U
G 18 P3.3 I/O port
U 2 LCD_PC
G 8 P3.4 I/O port L LCD interface
U 3
G 8 P3.5 I/O port K
LCD_D LCD interface
U
G 48 P3.6 I/O port E
LCD_H LCD interface
U
G 58 P3.7 I/O port S
LCD_V LCD interface
U 6 T5L1=1.25V S
G 8 VDD
U 7 T5L2=1.2V
G 8 VIO 3.3V
U
G 88 P4.0 I/O port LCD_B LCD interface
U
G 99 P4.1 I/O port 0LCD_B LCD interface
U
U
U
U
U 4 5
G 9 P4.6 I/O port LCD_B LCD interface
U
U 6 T5L1=1.25V 7
G 9 VDD
U 7 T5L2=1.2V
G 9 VIO 3.3V
U
G 89 P5.0 I/O port LCD_G LCD interface
U
G 19 P5.1 I/O port 0LCD_G LCD interface
U
U
U
U
U
U
U 0 T5L1=1.25V 7
G 1 VDD
U 0 T5L2=1.2V
G 1 VIO 3.3V
U
G 01 P6.0 I/O port LCD_R LCD interface
U
G 01 P6.1 I/O port 0LCD_R LCD interface
U
U
U
U
U
U
U 1 T5L1=1.25V 7
G 1 VDD
U 1 T5L2=1.2V
G 1 VIO 3.3V
U 1
Note that the pad on the bottom of the IC must be grounded reliably, otherwise the performance of the IC
will be affected.
• Packaging Dimension
For PCB design, please use the device packaging and reference design provided by DWIN Technology.
• Basic performance parameters

Parameter U Minimum Typical Maximum Instructions
nit
V value1.10 value
1.20 value1.30 T5L2
CPU core voltage
V 1.20 1.25 1.35 T5L1
Dual-core 200MHz full
CPU core current m 100 speed
A
operation
5V TTL/CMOS level
IO voltage (VIO) V 1.8 3.3 3.6 input requires voltage
divider or
AD operating voltage(VADD) V 1.8 3.3 3.6
AD reference voltage (Vref) V VADD+0.3
AD input voltage V Vref+0.3
IO high level output VIO=3.3V,IO load current
V 3.0
amplitude(VOH) 8mA
IO low level 1utput VIO=3.3V,IO load current
V 0.3
amplitude(Vol) 8mA
IO high level output current m -10 VIO=3.3V,VOH=3V
IO low level output current A
m 10 VIO=3.3V,VOL=0.3V
A
IO port turnover speed M 100
IO high level recognition Hz
V 1.6
voltage(VIH)
IO low level recognition
V 0.6
voltage(VIL)
External crystal frequency M 10.0 11.0592 12.0
Hz Corresponding to
11.0592MHz crystal, CPU
CPU main
M 206.4384 main frequency = crystal
frequency Hz frequency* 56/3.
(CPU_CLK)
350MHz version of the code
Working temperature ℃ -40 +85 can be customized.
Storage temperature ℃ -55 +105
ESD protection capability K 2 HBM
V
• Notices for Hardware Design
(1) The core power voltage must be stable, otherwise it will lead to abnormal CPU operation.
(2) Reset is recommended to use low-level reset IC processing such as SGM809S instead of simple RC reset
circuit. Each T5L CPU core has a built-in watchdog(WDT) , doesn’t need external WDT IC.
(3) Four layer PCB application design is recommended to achieve excellent EMC characteristics. When
designing in a dual panel application, please as close as possible to the IC power supply pin to connect the
470pF in parallel with 104 (or 105) for capacitor filtering and reduce noise emissions.
(4) When IO input signal is over 0.3V of VIO voltage, IO must be protected by voltage divider or clamp,
otherwise it may cause abnormal signal or damage IC.
(5) All IO ports are floating input when they are configured as input mode, without internal pull-up or
pull-down. All IO ports are in the input state during the reset process. If they are output, they can be pulled
down or pulled up externally to ensure that the reset process has a definite level.
(6) The 4-bit bus speed of T5L and external SPI Flash is 100MHz, thus the wiring should be as close as
possible, and capacitor filtering of 470pF parallel 105 must be arranged on the power pin of SPI Flash.
Beijing DWIN Technology Co., Ltd. - 10 - www.dwin.com.cn 400 018 9008 dwinhmi@dwin.com.cn
(6) OS CPU Description

The T5L OS CPU adopt the 8051 kernel, which is the most widely used in industry and has the longest time
in mass production. On the basis of keeping 8051 real-time, fast IO speed, stability and reliability, DWIN
has greatly improved 8051 memory access and calculation capability by optimizing code processing,
expanding SFR bus and adding hardware mathematical processor.
Users can also let OS CPU run DWIN OS platform for secondary application development on DWIN OS
platform. For specific development methods, please refer to "DWIN OS program development guide based
on T5L CPU".
• Initial Configuration
When the 8051 kernel is powered on, the special function register (SFR) in the following table must be
initialized correctly.
Initial
SFR name Addre configurati Instructions
ss on values
CKON 0X8 0X00 CPU runs in 1T mode
E
Configure extended interrupt system, configure timer T2 to run in
T2CON 0XC 0X70 Autoload
8
mode
After the operation of MOVX instruction, how DPTR's changed. It must
DPC 0X9 0X00 or 0x01 be configured as 0x00 when process is developed in C51.
3 0x00:unchanged.
0x01:DPTR=DPTR+1. 0X03:DPTR=DPTR-1.
PAGESEL 0X9 0X01 64KB code space
D_PAGESEL 40X9 0X02 32KB RAM space accessed by MOVX, address 0x8000-0xFFFF
5 Peripheral multiplexing selection:
.7 1 = CAN interface leads to P0.2, P0.3, 0 = CAN interface does not
lead out, it is IO interface;
0x60 or
.6 1 = UART2 interface leads to P0.4, P0.5, 0 = UART2 interface does
configuration
MUX_SEL 0XC not lead out, it is IO interface;
9 according to
.5 1 = UART3 interface leads to P 0.6, P 0.7, 0 = UART3 interface does
application
not lead out, it is IO interface;
needs
.4-.2 retain;
.1 WDT control 1=open 0=close;
.0 WDT feed dog, 1=feed the dog one time(The WDT count becomes zero,
and the watchdog's overflowing time is one second. );
0x01 or
configuration Driver capability configuration of IO port output
PORTDRV 0XF
9 according to mode,0x00=4mA 0X01=8mA 0X02=16mA 0X03=32mA
application
RAMMODE 0XF needs
0X00 DGUS variable memory access interface control
8
• Memory
The 8051 kernel of OS can access seven different kinds of memory, which are shown in the table below.
Memory type Size Address space Access mode
It can only be read by MOVC instruction, which is same as
Code memory 64KByt 0x0000-0xFFFF
es standard 8051.
Data register 256KBy 0x00-0xFF The same as standard 8051
tes The same as standard 8051, DWIN can provide user SFR
SFR register 128KBy 0X80-0XFF
tes definition files( .INC or .H header file).
Access with the SFR register interface defined by EXADR
Extended SFR 64KByt 0x00-0x3F and
register es
EXDATA.
Using MOVX instruction to access. When DPC is configured
Data memory 32KByt 0x8000-0xFFFF
es as 0x00, it is same as standard 8051.
DGUS variable 256KBy 0x00:0000- Access using DGUS variable memory interface.
memory
CAN Communication tes 0x00:FFFF
48KByt 0xFF:0060- Access using DGUS variable memory interface.
interface es 0xFF:006B
• Code memory(64KBytes)
Functional partitioning and definition of the code memory space are shown in the following table.
Addre Definition Instructions
ss
0x00 Reset_PC After reset, the program starts running address .
00
0x00 EX0_ISR_PC External interrupt 0 program interface
03
0x00 T0_ISR_PC Timer0 interrupt program interface
0B
0x00 EX1_ISR_PC External interrupt 1 program interface
13
1B
0x00 UART2_ISR_PC UART2 TX/RX interrupt program interface
23
2B
0x00 CAN_ISR_PC CAN interface interrupt program interface
4B
0x00 UART4_TX_ISR_PC UART4 TX interrupt program interface
53
0x00 UART4_RX_ISR_PC UART4 RX interrupt program interface
5B
0x00 UART5_TX_ISR_PC UART5 TX interrupt program interface
63
0x00 UART5_RX_ISR_PC UART5 RX interrupt program interface
6B
0x00 UART3_ISR_PC UART3 TX/RX interrupt program interface
83 0xFFFF will allow connection to JTAG interface for simulation debugging,
0x00 JTAG interface enabled
F8 and other values will be prohibited.
0x00 "DWINT5" Code identification, illegal values will cause OS 8051 to stop running.
FA
0x01 Application code start Maximum 63.75KB
00
The OS 8051 code is stored in the 0x01:0000-0x01:FFFF position of the 1Mbytes on chip Flash. After
power-on reset, the system loads and runs in RAM.Code can only be written to on-chip Flash through SD
interface or UART1 interface (or WIFI network interface).
• DGUS Variable Memory(256KBytes)
The bit width of DGUS variable memory is 32 bits, and each address corresponds to 4Bytes data, in which:
(1)Address from 0x00:0000 to 0x00:7FFF , corresponding to 128Kbytes variable memory space, are
currently used by DGUSII system.
For example, 0x1000 and 0x1001 DGUSII variable memory correspond to 0x800 address of OS 8051
DGUS variable memory. D3 corresponds to 0x1000 variable high byte, D2 corresponds to 0x1000 variable
low byte, D1 corresponds to 0x1001 variable high byte, D0 corresponds to 0x1001 variable low byte.
(2)Address from 0x00:8000to 0x00:0800 are not currently in use. Users can define themselves as variable
memory to use.
(3)Address from 0xFF:0060 to 0XFF:006B address, are CAN communication interface configuration and
transceiver buffer.
Accessing DGUS variable memory uses the SFR register interface of the table below.
SFR Addre Instruction

name ss The interface control of DGUS variable memory access, which is Bit Addressable.
.7 Write 1 to occupy DGUS variable memory for reading and writing, and must be cleared
when not occupied;
.6 APP_EN Write 1 to start reading and writing once, and it is cleared after hardware execution;
RAMMO 0xF8 .5 APP_RW 1= read variable memory 0= write variable memory;
DE .4 APP_ACK hardware pair 8051 occupies the variable memory request, 1 = OK, 0 = BUSY,
need to continue to wait;
.3-.0 Corresponding Data3:DATA0 Writing Enables 1=corresponding Byte is written
0=corresponding Byte is not written;
ADR_H 0XF DGUS variable memory high 8-bit address,A23:A16.
ADR_M 10XF DGUS variable memory middle 8-bit address,A15:A8.
2
ADR_L 0XF DGUS variable memory low 8-bit address,A7:A0.
3 The increment of address automatically increases after reading and writing of DGUS variable
ADR_IN 0xF4 memory, that is after reading and writing ADR_H:M:L=before reading and
C writing ADR_H:M:L+ADR_INC.
DATA3 0xF DGUS variable data interface,write selection corresponds to RAMMODE.3.
DATA2 A
0XF DGUS variable data interface,write selection corresponds to RAMMODE.2.
DATA1 B
DATA0 C
D
DGUS variable memory must be read and written according to the following process(If you want to use
interrupt in the application, the interrupt must be closed when the main application reads and writes DGUS
variable data, not nested.)
(2) Configured address and address increment;

(3) Set RAMMODE as 0x8F (write) or 0xAF (read), check if RAMMODE. 4=1 confirms access to read and
write control.
(4) Read and write data, set RAMMODE as 0X00 after reading and writing.
Examples of application:Read and write two double words in 0x0800 address (corresponding to DGUSII
variable memory address 0x1000).
MOV ADR_H,#00H ;Configure DGUS variable memory address
MOV ADR_M,#08H
MOV ADR_L,#00H
MOV ADR_INC,#01H ;Configuration address increment
MOV RAMMODE,#0AFH ;Start read mode
JNB APP_ACK,$ ;Waiting for confirmation
MOV R0,#TEST_BUF ;Demonstration reading
MOV R1,#2
RDVP: SETB APP_EN ;Start reading data once
JB APP_EN,$
MOV @R0,DATA3
INC R0
MOV @R0,DATA2
INC R0
MOV @R0,DATA1
INC R0
MOV @R0,DATA0
INC R0
DJNZ R1,RDVP
CLR APP_RW ;Writing mode, demo writing
MOV ADR_L,#00H ;Adjust the address to 0x08:0000
MOV R0,#TEST_BUF
MOV R1,#2
WRVP: MOV
DATA3,@R0 INCR0
MOV DATA2,@R0
INC R0
MOV DATA1,@R0
INC R0
MOV DATA0,@R0
SETB APP_EN ;Start writing data once
JNB APP_EN,$
INC R0
DJNZ R1,WRVP
MOV RAMMODE, #00H ;Variable memory read and write ends
• Data Memory(32KBytes)
OS 8051 CPU Of T5L has 32KBytes RAM as data storage, corresponding address from 0x8000 to 0xFFFF,
related interface SFR are as follows.
SFR Address Instruction

name After using DPTP MOVX instruction operation, DPTR change mode:
DPC=0X00:DPTR remains unchanged after operation of MOVX instructions. If
DPC 0x93 developed using C51, DPTR must be configured as 0x00
DPC=0X01 After MOVX instruction operation,DPTR=DPTR+1
DPC=0X03 After MOVX instruction operation,DPTR=DPTR-1
DPH 0X83
DPTR data pointer
DPL 0X82
The address space from 0x0000 to 0x7FFF prohibit using MOVX instructions to read and write, which may
cause code to run abnormally.
T5L MOVX instruction takes three instruction cycles (14.5nS in 3T, 11.0592MHz crystal), and DPC can
configure DPTR automatic incremental (or decrement) mode, which makes T5L read-write data memory
much faster than standard 8051, especially for reverse storage read-write applications.
Examples of application :
MOV DPC,#01H ;DPTR++
MOV DPTR,#8000
H
MOV A,@DPTR ;A=@8000
X
MOV A,@DPTR ;A=@8001,After
X readingDPTR=8002
• Extended SFR register
Extended SFR registers use EXADR, EXDDATA register to read and write.
SFR Addre Instruction
name
EXAD ss0xFE Extend the SFR address and automatically add 1 to the next SFR after each reading and writing.
R
EXDA 0xFF Expanding SFR data interface
TA
The extended SFR register defines the register interface of the Mathematical Operating Unit (MDU) and
provides 48 additional data storage for users. The following table is defined:
EXADR Definition Instruction

0x00 MDU_A7 Maximum bit of MDU A register(64bit)
......
0x07 MDU_A0 Minimum bit of MDU A register(64bit)
0x08 MDU_B7 Maximum bit of MDU B register(64bit)
......
0x0F MDU_B0 Minimum bit of MDU B register(64bit)
0x10 MDU_C7 Maximum bit of MDU C register(64bit)
......
0x17 MDU_C0 Minimum bit of MDU C register(64bit)
0x18 EXR0 First extended data register.
0x19 EXR1 Second extended data register
0x3F EXR39 Fortieth extended data register
If read-write extension SFR is needed in interrupt application, the main program must shutdown interrupt
when read-write extension SFR, and can not be nested.
3.8 Mathematical operating unit(MDU)
Due to the limited computing power of 8051, the hardware mathematic unit (MDU) is extended in T5L to
improve computing power. OS 8051 applications can access hardware MAC and hardware divider. The
related SFR definitions are as follows:
SFR name Addr Instruction

ess The MAC hardware multiplier-adder control register is defined as follows:
.7 MAC enabled, write 1 to perform a calculation, becomes zero after hardware treatment;
.6 MAC mode, 1 is multiplier-adder mode: C=A*B+C,0 is multiplier mode:C=A*B;
.5 Write 0;
MAC_CN 0xE5 .4 1=64bit MAC 0=32bit MAC(A3:0/B3:0/C7:0,note that C is still 64bit );
.3 1 = Signed number, 0 = Unsigned number;
.2-.0 Write 0;
The A、B、C register group is the MDU_A, MDU_B, MDU_C register group of extended
SFR registers.
DIV hardware divider control register (division C/A, quotient A, remainder B) is defined as follows:
.7 DIV enabled write 1 to perform a calculation and the hardware to perform zero clearance;
.6 DIV mode 1: Rounded 0: Not rounded;
.5-.4 Undefined, write 0;
DIV_CN 0XE6
.3 1 = Signed number 0 = unsigned number;
.2-.0 Write 0;
The A、B、C register group is the MDU_A, MDU_B, MDU_C register group of extended
SFR registers.
Examples of application: 32bit MAC calculate 0x1234*0x5678-0x2000

MOV EXADR,#04H ;write A3:A0=0x 00 00 12
34
MOV EXDATA,#00
H
MOV EXDATA,#00
H
MOV EXDATA,#12
H
MOV EXADR,#34H ;write B3:B0=0x 00 00 56
78
MOV EXDATA,#00
H
MOV EXDATA,#00
H
MOV EXDATA,#56
H
MOV EXDATA,#78H
MOV EXADR,#10H ;write C7:C0=0xFF FF FF FF FF FF E0 00 (-0x2000)
MOV EXDATA,#0FFH
MOV EXDATA,#0FFH
MOV EXDATA,#0FFH
MOV EXDATA,#0FFH
MOV EXDATA,#0FFH
MOV EXDATA,#0FFH
MOV EXDATA,#0E0H
MOV EXDATA,#00H
MOV MAC_CN,#0C8H ;32bit integer MAC
WTMAC: MOV A,MAC_CN
JB ACC,7,WTMAC
MOV EXADR,#10H ;read results00 00 00 00 06 25 E0 60
MOV R7,EXDATA
MOV R6,EXDATA
MOV R5,EXDATA
MOV R4,EXDATA
MOV R3,EXDATA
MOV R2,EXDATA
MOV R1,EXDATA
MOV R0,EXDATA
3.9 Timer
T5L OS 8051 has three timers T0/T1/T2, of which T0/T1 is consistent with standard 8051, and T2 can only
work in 16 bit Autoload mode. The clocks of T0 and T1 are 1/12 of the CPU main frequency. The clocks of
T2 can be configured as 1/12 or 1/24 of the CPU main frequency.
Relevant SFR are shown in the table below.
SFR Address Instructions
name T0, T1 control registers, same as standard 8051, can be addressable by bit
.7=TF1 .6=TR1 .5=TF0 .4=TR0 .3=IE1 .1=IEO .0=ITO
TCON 0x88
IT1 and IT0 are external interrupt trigger mode selection: 0 = low level trigger
1 = down-jump edge trigger.
TMOD 0x89 T0, T1 mode selection, same as standard 8051.
TH0 0x8C
TL0 0x8A
TH1 0x8D
TL1 0x8B
The T2 control register can be addressable by bit.
.7:Clock frequency division selection,0=CPU Main frequency /12, 1=CPU Main frequency
/24;
T2CON 0xC8
.6-.4:must write 1;
.3-.1:must write 0;
.0:TR2,1=T2 run 0=T2 close;
TH2 0xCD T2 running value, automatically loaded every time counting overflow
TL2 0xCC TH2=CRCH TL2=CRCL.
The reload value of T2 = 65536-T2 timer interval (uS)*T2 clock frequency (MHz).
TRL2H 0xCB
CPU main frequency = crystal frequency * 56/3, corresponding CPU main frequency /
12 = crystal frequency * 14/9, CPU main frequency / 24 = crystal frequency * 7/9.
TRL2L 0xCA For example, the CPU main frequency is 206.438 MHz, T2 chooses 1/12 frequency
division,
and the setting value of 1 mS timer interval is 48333 (0xBCCD).
The relevant settings of timer interrupt are as follows:

Interrupt
Interrupt Program entry Trigger enabling Remarks
type address marker
T0 0x000B TF0(TCON. control
IEN0.1 Automatic clearing of TF0 in interrupt
interruption
T1 0x001B 5)
TF1(TCON. IEN0.3 response
Automatic clearing of TF0 in interrupt
interruption 7) response
After interrupt response, TF2 needs to be
T2 0x002B TF2(TCON. IEN0.5 cleared by software, otherwise interrupt will
interruption 6) be
Examples of application: In 11.0592 MHz crystal (corresponding to the main frequency of CPU 206.4384
MHz), T2 1mS interruption is set to output 500 Hz square wave at P 1.0.
ORG 002BH ;T2 interrupt program
entry
LJM T21NT
P
T21NT: CLR TF2 ;T2 interrupt

program CPL P1.0
RETI
;initialization of T2-related SFR
MOV CRCH,#HIGH(48333) ;1mS timer
MO CRCL,#LOW(48333)
V
MO T2CON,#71H ;TR2=1
V
OR IEN0,#20H ;ET2=1 turn on T2
L interrupt
3.10Watchdog Timer(WDT)
In order to monitor the operation of the software and ensure that the system automatically returns to normal
when operation becomes abnormal, T5L OS 8051 is equipped with a software watchdog (WDT) timer
whose counting reset time is set to 1 second (corresponding to 11.0592 MHz crystal).Once the WDT is
turned on, the software needs to feed the dog in the counting reset time, otherwise a system reset will occur.
Reset has no effect on the contents of 32KB data memory and 0x008000-0x00FFFF space 128KB DGUS
variable memory.
The relevant reference codes for WDT operations are as follows：
ORL MUX_SEL,#02H ;open WDT
ANL MUX_SEL,#0FDH ;close WDT
ORL MUX_SEL,#01H ;WDT reset (feeding
dog)
3.11IO
T5L OS 8051 has three 8 bit parallel ports(P0-P2) and a 4 bit parallel port(P3.0-P3.3), a total of 28 IO ports.
P0-P0.7 of P0 port is multiplexed with UART and CAN interface, and multiplexing function or IO function
can be selected through MUX_SEL register.
The input of all IO ports is always open, the input is floating, and there is no internal pull-up or pull-down.
When IO port is used as output, it is necessary to open the output control, and the output driving ability can
also be configured.
Because the IO interface of power-on reset process is input mode, when used as output, it must be pulled up
or pulled down externally to ensure that the reliable output of power-on process is ensured, and will not
malfunction due to IO floating.
P3.0 is external interrupt 0, and P3.1 is external interrupt 1 input. It can be configured as low level trigger (0)
or jump down edge trigger (1) through IT0 and IT1.
In addition to the need to control the output switch, output strength and peripheral multiplexing power-on
initialization configuration, the subsequent use of IO is consistent with the standard 8051.
IO-related SFR are shown in the following table:
SFR Address Instructions
name
P0 0x80 Addressable by bit, same as standard 8051
P1 0x90 Addressable by bit, same as standard 8051
P2 0xA0 Addressable by bit, same as standard 8051
P3 0xB0 It can be addressable by bit, the same as standard 8051, only P3.0-P3.3 is valid.
P0 Interface Output Configuration:
.7 0=P0.7Output shutdown 1=P0.7Output Open (push-pull output);
.6 0=P0.6Output shutdown 1=P0.6Output Open (push-pull output );
.5 0=P0.5Output shutdown 1=P0.5Output Open (push-pull output );
POMDO 0xB7 .4 0=P0.4Output shutdown 1=P0.4Output Open (push-pull output);
UT .3 0=P0.3Output shutdown 1=P0.3Output Open (push-pull output);
P1MDO 0xBC P1 interface output configuration
UT
P2MDO 0xBD P2 interface output configuration
UT
P3MDO 0xBE P3 interface output configuration
UT Selection of peripheral reuse:
.7 1 = CAN interface leads to P 0.2 and P 0.3,0 = CAN interface is not introduced, it is
IO interface.
.6 1 = UART2 interface leads to P 0.4 and P 0.5,0 = UART2 interface is not introduced, it is
IO interface;
MUX_SE 0xC9 .5 1 = UART3 interface leads to P 0.6 and P 0.7,0 = UART3 interface is not introduced, it is
L IO interface;
.4-.2 Retain;
.1 WDT control, 1=open 0=close;
.0 WDT feed dog, 1=feed the dog one time(The WDT count becomes zero, and the
watchdog's overflowing time is one second. );
Driver capability configuration of IO port output mode, 0x00 = 4mA
PORTDR 0xF9 0x01=8mA(recommended
V
values) 0x02=16mA 0x03=32mA
The relevant settings of external interrupt of IO port are as follows:

Interrupt Program Trigger Interrupt enabling
Remarks
type entry marker control
address
IE0 is cleared automatically when interrupt
EX0 response, corresponding to P3.0.
0x0003 IE0(TCON IEN0.0
interrupt .1) IT0 (TCON.0) = 0 low level trigger interrupt, IT0 = 1 jump
down edge trigger interrupt.
IE1 is cleared automatically when interrupt
EX1 response, corresponding to P3.1.
0x0013 IE1(TCON IEN0.2
interrupt .3) IT1 (TCON.2) = low level trigger interrupt, IT1 = 1 jump
down
edge trigger interrupt.
3.12 UART communication interface
3.12.1 UART2 interface
UART2 related SFR are shown in the following table.

SFR Addre Instructions
name ss .6 1 = UART2 interface leads to P 0.4 and P 0.5, 0 = UART02 interface does not lead out, it is IO
MUX_S 0xC
EL 9 port .
UART2 control interface, the same as standard 8051, can be addressable by bit.
SCON 0x98 .7=SM0 .6=SM1 .5=SM2(multiprocessor communication bit)
O .4=REN0 .3=TB80 .2=RB80 .1=TI0 .0=RI0.
SBUF 0x99 UART2 transceiver data interface
0
ADCO 0xD Baud rate generator selection, 0x00 = T1 timer (standard 8051), 0x80 = SRELOH: L.
N 8 .7 = SMOD baud rate frequency doubling selection, 0 = no frequency doubling, 1 = frequency
PCON 0x87
doubling.
SRELO 0xB When ADCON = 0x80, SRELOH:L is used to set the baud rate without taking up
H A T1. SMOD=0 SREOH:L=1024-CPU main frequency/(64*baud rate )
SMOD=1 SREOH:L=1024-CPU main frequency/(32*baud rate )
SRELO 0xA
L A CPU main frequency = crystal frequency * 56/3, 11.0592 MHz crystal corresponds to 206.4384
MHz main frequency.
The relevant settings for UART2 interruption are as follows:

Interrupt Program entry Interrupt enabling
Trigger Remarks
type address marker control
UART RIO(SCON0. After interruption processing, software needs to
2 0x0023 0) IEN0.4 clear
interru TIO(SCON0. the interruption trigger mark.

SFR Addre Instructions
name ss
MUX_S 0xC .5 1 = UART3 interface leads to P 0.6, P 0.7, 0 = UART3 interface does not lead out, it is IO port.
EL 9 UART3 control interface, it is not addressable by bit.
.7 0=9bit UART, 1=8bit UART;
.6 Undefined;
.5=SM2(multiprocessor communication bit )
SCON 0x9
1 B .4=REN .3=TB8 .2=RB8 .1=TI .0=RI.
Clearing the SCON1 bit tag requires two consecutive writings, such
as ANL SCON1,#0FEH
ANL SCON1,#0FEH
SBUF 0x9 UART3 transceiver data interface
1
SREL1 C
0xB UART3 baud rate setting (CPU main frequency = crystal frequency * 56/3, 11.0592
H B crystal corresponding to 206.4384 MHz main frequency):
SREL1 0x9
L D SRE1H:L=1024-CPU main frequency/(32*baud rate)
The relevant settings for UART3 interruption are as follows:

Interrupt Program entry Trigger Interrupt enabling
Remarks
UART3 SCON1.0, After interruption processing, software needs to clear
0x0083 IEN2.0
interrup SC the interruption trigger mark.
t
SFR name Addr Instructions

ess UART4 transmition control:
.7 UART4 sending enables,0=close,1=open;
.6 0=8bit Mode,1=9bit Mode;
SCON2T 0x9
6 .5 TB8, 9th bit sent in 9bit mode;
.4-.1 Write0;
.0 TI, send flag, the position at which the stop bit is sent.
UART4 receive control:
.6 Write0;
SCON2R 0x9
7 .5 TB8, 9th bit sent in 9bit mode;
.4-.1 Write0;
.0 R RI, receive tag, set when the stop bit is received when a valid stop bit is received.
SBUF2_T 0x9 UART4 sending data interface
X
SBUF3_R E
0x9 UART4 receiving data interface
X
BODE2_DIV F
0X UART4 baud rate setting
_H
BODE2_DIV D9
0X BODE2_DIV_H:L=CPU main frequency/(8*baud rate)
_L D7
The relevant settings of UART4 interruption are as follows:
Program entry Trigge Interrupt
Interrupt r enabling Remarks
type address
UART4 send marker control After interruption processing, software needs to clear
0x0053 SCON2 IEN1.2 the
interrupt T.0
UART4 interruption triggerprocessing,
After interruption mark. software needs to clear
receive 0x005B SCON2 IEN1.3 the
R.0
Interruption interruption trigger mark.
The relevant settings of UART5 are as follows:

SFR name Addres Instructions
s UART5 transmition control:
.6 0=8bit Mode,1=9bit Mode;
SCON3T 0xA7
.5 TB8, 9th bit sent in 9bit mode;
.4-.1 Write0;
.0 TI, send flag, set when the stop bit is received when a valid stop bit is received.
UART5 receive control:

.6 Write0;
SCON3R 0xAB
.5 TB8, 9th bit sent in 9bit mode;
.4-.1 Write0;
.0 R RI, receive tag, set when the stop bit is received when a valid stop bit is
received.
SBUF3_TX 0xAC UART5 sending data interface
SBUF4_RX 0xAD UART5 receiving data interface
BODE3_DIV_H 0xAE UART5 baud rate setting
BODE3_DIV_L 0xAF BODE3_DIV_H:L=CPU main frequency/(8*baud rate)
The relevant settings of UART5 interruption are as follows:

Program entry Trigge Interrupt
Interrupt r enabling Remarks
type address
UART5 send marker control After interruption processing, software needs to clear
0x0063 SCON3 IEN1.4 the
interrupt T.0
UART5 interruption triggerprocessing,
After interruption mark. software needs to clear
receive 0x006B SCON3 IEN1.5 the
R.0
Interruption interruption trigger mark.
3.3 CAN communication interface
The SFR associated with the CAN interface are shown in the following table :
SFR Addr Instrctions

name
MUX_S ess
0xC .7 1 = CAN interface leads to P 0.4 and P 0.5,0 = CAN interface does not lead out, it is IO port .
EL 9 CAN Interface Control Register:
.7 CAN interface enabled,1=open 0=close;
.6 CAN interface mode，1=software reset 0=working normally;
.5 Write 1 to configure the configuration data of CAN interface once (0xFF:0060-0xFF:0062),
and cleaned up after hardware processing;
CAN_C 0x8
R F .4 Set speed mode, 1 = 1 Sampling 0 = 3 Sampling;
.3 Setting filter mode,1=double 0=single;
.2 Write 1 starts sending once, and the hardware processing (sending success, arbitration failure,
EI (CAN_IR.3) occurred, software reset) clears up;
.1-0 Undefined,write 0.
CAN Interface Interrupt Status Register
.7 RF_IF, remote frame receiving interrupt flag, hardware configuration, software
clearance is required;
.6 CAN_RX_IF, CAN receives interrupt markers, hardware placement, software clearance is
required. During the placement period, the hardware can no longer update the data;
.5 CAN_RX_IF, CAN sends a successful interrupt marker, hardware placement, software
CAN_I 0x9
R 1 clearance is required;
.4 OI, receiving overflow markers, hardware blanking, software clearance is required;
.3 EI, error marker, CAN_ET [4:0] has an error when the bit is raised and software
clearance is required;
.2 JI, send arbitration mark, 1 = send arbitration failure, 0 = send arbitration success;
.1-.0 Undefined.
CAN interface error type register, hardware blanking, need software zeroing. Addressable by bit.
.7 Node suspension identifcation;
.6 Active error identification;
.5 Passive error identification;
CAN_E 0xE .4 CRC Check error identification;
T 8 .3 Response error identification;
.2 Format error identification;
.1 Bit filling error identification;
.0 Bit error identification.
The CAN communication interface is defined in terms of DGUS variable space. The related variables are
defined in the following table:
Addres Positi Leng Definiti Instructions
s onD3 th1 on BRP
BRP: Baud rate frequency divider register
D2 1 BTR0
BTR0: [7:5] is the synchronous jump width sjw, [3:0] prop propagation time
0xFF:00 D1 1 BTR1
60 T0. [7:4] is phase buffer segment 1, T1, [3:0] is phase buffer segment 2, T2.
Undefine
D0 1 T0+T1+T2=CPU main frequency/(baud rate*(BRP*2+1))-4
d,
0xFF:00 D3: 4 write
ACR3: 0 Acceptance code register
61 D0 0
0xFF:00 D3: 4 AMR3: Acceptance code register
62 D0D3 1 0RXER Receiving error count register
0xFF:00 D2 1 R
TXER Sending error count register
63 D1: 2 R
Undefin Write 0
D0 ed
CAN_T
D3 1 X_ [7]IDE,[6]RTR,[3:0]—DLC, frame data length
0xFF:00
64 D2: 3 BUFFE
Undefin
D0 ed ID ID, 29bit is valid when expanding frames, 11bit is valid for standard frames.
D3 1 ID, first byte, standard frame and extended frame.
ID, the second byte, [7:5] is 3bit of the standard frame, and the second byte of
0xFF:00 D2 1 the
65
D1 1 extended frame.
ID, third byte, invalid standard frame, third byte of extended frame.
D0 1 ID, fourth byte, invalid standard frame, [7:3] extended frame height 5 bit.
0xFF:00 D3: 4 Data Send data,DATA1-DATA4
66
0xFF:00 D0
D3: 4 Data Send data,DATA5-DATA8
67 D0 CAN_R
D3 1 X_ [7]IDE,[6]RTR,[3:0]—DLC, frame data length
0xFF:00
68 D2: 3 BUFFE
Undefin
D0 ed ID ID, 29bit is valid when expanding frames, 11bit is valid for standard frames.
D3 1 ID, first byte, standard frame and extended frame.
0xFF:00 ID, the second byte, [7:5] standard frame height 3 bit, and the second byte of the
69 D2 1
extended frame.
D1 1 ID, third byte, invalid standard frame, third byte of extended frame.
D0 1 ID, fourth byte, invalid standard frame, [7:3] extended frame height 5 bit.
0xFF:00
6 D3: 4 Data Receive data,DATA1-DATA4
D0
A
0xFF:00
6 D3: 4 Data Receive data,DATA5-DATA8
D0
B
The relevant settings of CAN interface interruption are as follows:
Program entry Trigger Interrupt enabling

Interrupt Remarks
interface After interruption processing, software needs to
0x004B CAN_I IEN1.1
interruption R clear the interruption trigger mark.
3.4 Interrupt system
3.4.1 Interrupt control SFR
T5L OS CPU has 12 interrupts. The related control SFR list is as follows:
SF
R Addr Instructions
ess
nam The interrupt enable controller 0 can be addressed by bit.
.7 Interrupt master control bit;0=all interrupts closed 1=Whether an interrupt is opened is controlled by
the control bit of each interrupt;
.6 Must write 0;
.5 ET2 T2 timer interrupt enable control bit;
IEN 0xA
0 8 .4 ES0 USRT2 interrupt enable control bit;
.2 EX1 external interrupt 1 (P3.1 pin) interrupt enabling control bit;
.0 EX0 external interrupt 1 (P3.0 pin) interrupt enabling control bit.
The interrupt enable controller 1 can be addressed by bit.
.7-.6 Must write 0;
.5 ES3R UART5 receiving interrupt enabled control bit;
.4 ES3T UART5 receiving interrupt enabled control bit;
IEN 0xB
1 8 .3 ES2R UART4 receiving interrupt enabled control bit;
.2 ES2R UART4 receiving interrupt enabled control bit;
.1 ECAN CAN communication interrupt enabling control bit;
.0 Must write 0.
Interrupt enabling controller 2
IEN 0x9 .7-.1 Must write 0
2 A .0 ESI USRT3 interrupt enabling control bit
IEN 0xD Interrupt enabling controller 3, must write 0x00
3IP0 1
0xA Interrupt priority controller 0
IP1 90xB Interrupt priority controller 1
9
3.4.2 Interrupt priority
The interrupt priority of T5L OS CPU is handled according to the following rules:
(1) Twelve interrupts are divided into six groups with two interrupts in each group. The priority in the same
group is fixed. For example, the priority of interrupt 0 is higher than that of UART3, as shown in the table
below.
Groupin IP0 IP1 Interrupt correspondence
g correspondence correspondence
High priority Low priority
G0 .0 .0 External interrupt UART3 interruption
0 CAN communication
G1 .1 .1 T0 timer interrupt
interruption
G2 .2 .2 External interrupt UART4 send interrupt
G3 .3 .3 1
T1 timer interrupt UART4 receiving interruption
G4 .4 .4 UART2 interrupt UART5 send interrupt
G5 .5 .5 T2 timer interrupt UART5 receiving interruption
(1)There are four levels of priority among the six groups, which can be configured by the corresponding bits
of IP0 and IP1 according to the table below.
Inter group priority IP1 counterpart IP0 counterpart
3(highest) 1 1
2 1 0
1 0 1
0(minimum) 0 0
For example, to set the G2 group's T2 timer interrupt and UART5 receive interrupt priority to the highest,
you can set 1P1=0x20, 1P0=0x20.
(2)If the configurations have the same priority (IP1 = 0x00 IP0 = 0x00), the G0 group has the highest
priority and the G5 group has the lowest priority. The interrupt priority weights with the same configuration
are as follows:
Weig 11 10 9 8 7 6 5 4 3 2 1 0
ht
Priori Maxim Minimu
ty
Interr umEX0 UAR E CA EX UART4- ET UART4- UAR UART5- ET m
UART5-
upt T3 T0 N 1 TX 1 RX T2 TX 2 RX
(3)High priority interrupts can be nested in low priority interrupts (i.e. interrupts with small weights can be
interrupted by interrupts with large weights), and at most four levels can be nested.
Special Notice:
T5L OS CPU is fast (1 uS can execute 130-150 instructions on average). Interrupt execution time is short
and real-time is very high. It is not recommended that users use interrupt nesting to cause complex program
architecture. Interrupt is closed directly at the execution of each interrupt service program (EA = 0), and
interrupt is opened again at exit of program (EA = 1).
3.10 8051 Instruction set of T5LASIC
Instructi Instructio Instructio Instructi

Instruction format on n Instruction format n on
ADD/ADDDC A,Rn length
1 cycle
1 MOV @Ri,direct length
2 cycle
2
ADD/ADDDC A,direct 2 2 MOV @Ri,#data 2 2
ADD/ADDDC A,@Ri 1 2 MOV 3 3
ADD/ADDDC A,@data 2 2 DPTR,#data16
MOVC 1 3
SUBB A,Rn 1 1 A,@A+DPTR
MOVC A,@A+PC 1 3
SUBB A,direct 2 2 MOVX A,@Ri 1 3
SUBB A,@Ri 1 2 MOVX 1 3
SUBB A,#data 2 2 A,@DPTR
MOVX A,@Ri,A 1 3
INC/DEC A 1 1 MOVX 1 3
INC/DEC Rn 1 1 @DPTR,A
PUSH/POP 1 2
INC/DEC direct 2 2 XCH A,Rn 1 1
INC/DEC @Ri 1 2 XCH A,direct 2 2
INC DPTP 1 1 XCH A,@Ri 1 2
MUL AB 1 4 XCHD A,@Ri 1 2
DIV AB 1 4 ACALL addr11 2 2
DA A 1 1 LCALL addr16 3 3
ANL/ORL/XRL A,Rn 1 1 RET/RETI 1 4
ANL/ORL/XRL A,direct 2 2 AJMP addr11 2 2
ANL/ORL/XRL A,@Ri 1 2 LJMP addr16 3 3
ANL/ORL/XRL A,#data 2 2 SJMP rel 2 2
ANL/ORL/XRL direct,A 2 2 JMP @A+DPTR 1 3
ANL/0RL/XRL 3 3 JZ/JNZ/JC/JNC rel 2 3
direct,#data
CLR A 1 1 JB/JNB/JBC 3 4
CPL A 1 1 CJNE A,direct,rel 3 4
RL/RR A 1 1 CJNE A,#data,rel 3 4
RLC/RRC A 1 1 CJNE Rn,#data,rel 3 4
SWAP A 1 1 CJNE 3 5
MOV A,Rn 1 1 @Ri,#data,rel
DJNZ Rn,rel 2 3
MOV A,direct 2 2 DJNZ direct,rel 3 4
MOV A,@Ri 1 2 NOP 1 1
MOV A,#data 2 2 CLR/SETB C 1 1
MOV Rn,A 1 1 CLR/SETB bit 2 2
MOV Rn,direct 2 2 CPL C 1 2
MOV Rn,#data 2 2 CPL bit 2 2
MOV direct,A 2 2 ANL C,bit 2 2
MOV direct,Rn 2 2 ANL C,/bit 2 2
MOV direct1,direct2 3 3 ORL C,bit 2 2
MOV direct,@Ri 2 2 ORL C,/bit 2 2
MOV direct,#data 3 3 MOV C,bit 2 2
MOV @Ri,A 1 1 MOV bit,C 2 2
CPU main frequency = crystal frequency * 56/3, 11.0592MHz crystal corresponds to 206.438MHz main
frequency, corresponding to an instruction cycle (1T) of 4.844nS.
Such as:
Under 11.0592 MHz crystal, the following code will output 206.4384/((2+2)*2)=25.8048 MHz square wave
on the P3.3 IO interface.
OUTTEST:CPL P3.3 ;2T
AJMP OUTTEST ;2T
(7) Simulation Debug

With the help of HME05 simulator (need to install the corresponding USB driver), users can connect T5L
JTAG interface and debug code IAP and run simulation under Keil development environment.
The following points should be paid attention in simulation debugging:
(1)JTAG interface must be selected to OS CPU, and must be JTAG mode, that is, OS/GUI (PIN#32) = 0
JTAGS (PIN#34) = 1 .When the 4.3 inch evaluation board is used for simulation, the jumper pad on the
JTAG interface side is disconnected.
(2)The AGDI driver is installed to enable Keil to support T5 and HME05 simulators. Afterinstallation,
select and configure according to the following figure. After installation, copy the header file of T5LOS
CPU (*. INC or *. h) to KEIL/C51/INC/DWIN directory.
(3)Before setting the breakpoint to read the content of data storage (XDATA), DPC = 0x00 must be ensured,
otherwise the data will be misaligned.
(4)Before simulation, it is necessary to ensure that the OS CPU code address 0x00F8 of T5L Flash starts
with 0xFF FF 4457 494E 5435, otherwise the JTAG interface of OS CPU is prohibited and HME05
emulator cannot be connected.
(5)Users for standard C or other 8051 platform code migration, please pay attention to SFR header file
loading at compile time to select T5L corresponding. INC or. H file. If the SFR definition and T5L definition
in customer code are different, you can modify the code or T5L SFR header file to be consistent.
(6)HME05 realizes hardware simulation by downloading code to Code RAM of T5L OS CPU. The code is
not burned to Flash in the chip.To burn code into the chip, it is necessary to use SD card interface or UART1
debugging interface. When SD interface is burned, T5L underlying software will automatically change the
location of OS code 0x00F8 to 0x0000 (JTAG interface is forbidden) 44 57 49 4E 54 35.
T5L OS CPU adopts the standard 8051 architecture. Except for the slight difference between SFR and
extended peripheral access, the instruction set is identical. When the user has the original 8051 code, pay
attention to the following aspects and you can complete it quickly:
➢ According to the hardware design, after reset, the startup.A51 (C51 startup code) or initcpu () program
provided by DWIN is used to simply modify and configure T5L-specific SFR and parameter settings.
Typical differences are IO, main frequency of timer, baud rate, interrupt, WDT and so on.
➢ T5L IO output mode is controllable. When switching between input and output modes, PxMDOUT
registers should be configured accordingly, otherwise errors will occur.
➢ Turn off interrupt nesting, EA = 0 for each interrupt service program and set 1when exiting.
➢ When using Out-of-chip RAM (XRAM) as data storage in the code, it should be noted that the starting
address of T5L 32KB data RAM starts at 0x8000.
➢ Code 0x00F8 position plus 0xFFFF (or 0x0000 forbid JTAG interface) 44 57 49 4E 54 35.
(6)Accelerate the algorithm of optimizing original code with MDU hardware operation: Move UI and
Internet (such as access to DWIN cloud through DWIN WiFi module) function to DGUSII platform, user
code is processed by simple read-write DGUS variable space, greatly improve product performance and the
efficiency of research and development.
(8) EK043 Evaluation Board

EK043 evaluation board uses T5L1 to drive 4.3 inch 480*272 TFT screen, and matches capacitor touch
screen. Its main features include:
(1)11.0592 MHz crystal, 206.4384 MHz main frequency operation, support HME05 simulator.
(1) External 16MB SPI Flash, run standard DGUS II UI;
(2) Power supply and debugging use USB interface;
1. The OS CPU 8051 program can be downloaded through the USB interface and automatically reset
by hardware;
2. It can read and write DGUS variable memory and download pictures and word libraries through
USB interface to facilitate DGUS debugging;
3. The assembly location of DWIN WiFi module is reserved for easy access to DWIN cloud (both
WiFi module and USB occupy UART1 interface, with a baud rate of 921600 bps);
4. All interfaces of T5L OS CPU are drawn out with 2.54mm spacing through-hole bonding pad
and marked.
5. Six AD, ADC0-ADC3, ADC6-ADC7 which can be used by users are drawn out and marked with
2.54mm spacing through-hole bonding pad.
Appendix 1
Date Revision Document version
2019.03.15 First released V1.0
2019.09.27 Modify some errors in the document. V1.1
If you have any questions or want to know more about the latest information of DWIN products during the
use of this document or DWIN products, please contact us in time:
400 toll-free telephone：400 018 9008
Enterprise QQ and wechat: 400 018 9008
Enterprise mail:dwinhmi@dwin.com.cn
Thank you for your support for DWIN. Your support is the driving force of our progress.
Thank you all.

Development Guide of T5L ASIC

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Development Guide of T5L ASIC

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Development Guide of DWIN T5L ASIC Ver1.

(2) 2D hardware acceleration, the decompression speed of JPEG is up to 200fps@1280*800, the UI

(9) Supporting PC configuration development and simulation,supporting background remote upgrade.

(14)Support IAP on-line simulation and debugging, unlimited number of breakpoints.

operating temperature range )

(5) Hardware Description

Fig.2-1 The arrangement of T5L pin

• Basic performance parameters

• Notices for Hardware Design

(6) OS CPU Description

• DGUS Variable Memory(256KBytes)

SFR Addre Instruction

(2) Configured address and address increment;

SFR Address Instruction

• Extended SFR register

EXADR Definition Instruction

3.8 Mathematical operating unit(MDU)

SFR name Addr Instruction

Examples of application: 32bit MAC calculate 0x1234*0x5678-0x2000

Relevant SFR are shown in the table below.

The relevant settings of timer interrupt are as follows:

T21NT: CLR TF2 ;T2 interrupt

The relevant settings of external interrupt of IO port are as follows:

3.12 UART communication interface

3.12.1 UART2 interface

UART2 related SFR are shown in the following table.

The relevant settings for UART2 interruption are as follows:

3.12.2 UART3 interface

UART3 related SFR are shown in the following table.

The relevant settings for UART3 interruption are as follows:

3.12.3 UART4 interface

UART4 related SFR are shown in the following table.

SFR name Addr Instructions

3.12.4 UART5 interface

The relevant settings of UART5 are as follows:

UART5 receive control:

The relevant settings of UART5 interruption are as follows:

3.3 CAN communication interface

SFR Addr Instrctions

The relevant settings of CAN interface interruption are as follows:

Program entry Trigger Interrupt enabling

3.4 Interrupt system

3.4.1 Interrupt control SFR

3.4.2 Interrupt priority

3.10 8051 Instruction set of T5LASIC

Instructi Instructio Instructio Instructi

(7) Simulation Debug

(8) EK043 Evaluation Board

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