ISSN: 0974-5823 Vol. 6 No.

3 October-December, 2021

International Journal of Mechanical Engineering

Single Cycle 32-bit RISC-V ISA Implementation

and Verification
Hyogeun An
Department of Information and Communication Engineering, Hanbat National University, Daejeon, 34158, South Korea
ahnhyogean@gmail.com

Sudong Kang
Department of Information and Communication Engineering, Hanbat National University, Daejeon, 34158, South Korea
sudongkang@gmail.com

Dennis A. N. Gookyi
Department of Information and Communication Engineering, Hanbat National University, Daejeon, 34158, South Korea
dennisgookyi@gmail.com

Guard Kanda
Department of Information and Communication Engineering, Hanbat National University, Daejeon, 34158, South Korea
guardkanda@gmail.com

Kwangki Ryoo*
Department of Information and Communication Engineering, Hanbat National University, Daejeon, 34158, South Korea
kkryoo@gmail.com

Abstract designers in the computer architecture field to

understand the architecture of the ISA. This paper
Background/Objectives: This paper provides an insight outlines the steps in implementing a single cycle 32-bit
into the internal verification of a 32-bit single cycle RISC-V ISA using Verilog HDL. The uniqueness of this
processor that implements the Reduced Instruction Set work is in the verification of each instruction in the ISA.
Computer Five Instruction Set Architecture. The verification is achieved using an FPGA device with
Methods/Statistical analysis: This paper accesses the peripherals such as seven-segment display, text LCD, dot
internal operation and information of a RISC-V 32-bit matrix, keypad, and LEDs. These peripherals are used to
single cycle processor using a Field Programmable Gate display contents from the RISC-V processor core such as
Array board. The internal components such as the the register file, PC, instruction memory, and data
register file, the Program Counter, the instruction memory. This work is vital because it enables researchers
memory, and the data memory are displayed on who are new to the RISC-V ISA quickly understand the
peripherals such seven-segment display, text LCD, dot internal operation of a processor core during real world
matrix, and LEDs. The hardware structures were realized operation on an FPGA board.
using Verilog Hardware Description Language and Improvements/Applications: The synthesis report of the
synthesized using Xilinx Integrated Synthesis RISC-V single cycle processor core with the various
Environment 14.3 that incorporates ISE Simulator for peripheral modules utilized 6834 Look-up-Tables at a
simulation purposes. maximum frequency of 64 MHz. This indicates that the
Findings: With the recent trend of increasing demand and core is suitable for low-cost IoT SoC devices and can serve
scope in the market for Internet of Things ubiquitous as tutorial material for the computer architecture course.
platforms, low-cost System-on-Chip devices are currently
been deployed as sensors. Processor cores that implement Keywords: RISC-V ISA, Single Cycle Processor, FPGA,
the RISC-V ISA are suitable for low-cost SoCs due to IoT, SoC, Hardware Verification.
their use of minimal hardware resources. The RISC-V
ISA is fairly new but is taking over the open-source
market and it is therefore important for hardware

Copyrights @Kalahari Journals Vol. 6 No. 3 (October-December, 2021)

International Journal of Mechanical Engineering

855
1. Introduction file, PC, instruction memory, and data memory.
 A verification platform is built and loaded onto an
The Central Processing Unit (CPU) is an electronic circuit FPGA board for inputting instruction and observing the data
designed specifically to execute instructions called programs. in the internal architecture of the processor
The CPU executes many forms of instructions such as The rest of this paper is organized as follows: Section 2
arithmetic and logic instructions as well as memory access discusses some related works, Section 3 gives an introduction
instructions. These instructions which are specific to each to the RISC-V ISA, Section 4 illustrates the design and
CPU vendor are collectively known as the ISA. The ISA implementation of the 32-bit single cycle RISC-V ISA,
describes a specific instruction set that can be compiled by Section 5 describe the verification module for testing the
dedicated compilers and translated into machine codes. There processor core, Section 6 present the hardware resource
are many systems in today's society that require very large utilized by the processor core together with the peripheral
computations such as deep learning and image-based modules while the conclusion of the paper is discussed in
processing. Therefore, the demand for embedded systems Section 7.
requiring low power, low cost, and high performance is also
increasing. The paper in [1] gives an example of a system that 2. Related Work
efficiently recognizes vehicle license plate using an
embedded systems and AI. In addition, the usability of IoT is Since the introduction of the RISC-V ISA in the last decade,
gaining popularity and increasing user convenience based on several processor cores have been proposed and implemented
its applicability in real life. Using the Lora module, paper [2] for different reasons. Most the processor cores are meant for
designed a system that broadcasts kindergarten school bus academic use while a few others are commercial. The
location notifications to users on SMS or apps on mobile academic processor cores are designed with interfaces for
devices. Among them, processors are indispensable easy integration into an SoC. This is good for advances
components. But the commercially available ISAs belong to hardware engineers to quickly assemble an SoC but very
companies such as Intel and AMD which include the x86 difficult for beginners to understand the working of the
family of ISAs [3], [4]. These ISAs are patented and cannot processor core. This section therefore explores RISC-V
be used without license that cost a lot of money and thereby processor cores with input/output peripherals that enable a
preventing researchers in academia and hobbyist from using designer to gain understanding of the internal operation of the
them. Moreover, the licenses prevent designers from processor cores.
implementing the ISAs but instead limits them to use the The authors of [11] implemented the RISC-V ISA with
processor cores provided by the companies. This prevents instruction which include environment call, break, status
competition, innovation, and sometimes trust issues as registers, control, branch, memory, and arithmetic logic. A
companies could imbed malicious circuitry in the processor total of 38 instructions were simulated using ModelSim and
for spying [5]. Quartus-II simulators. This work only resulted to functional
The licensing issue associated with commercial processor is simulation without real hardware implementation on an
solved by the design of a new ISA known as RISC-V [6], [7] FPGA board. This makes it difficult to know if the processor
by the computer architecture group in University of will work in the real world.
California, Berkeley. The RISC-V ISA is an open-source ISA The authors of [12] proposed an Integrated Machine Code
available for implementation under the free Berkeley open- Monitor (iMCM) and implemented together with a RISC-V
source license. The RISC-V project started in 2010 and has processor on an FPGA. The iMCM monitors functions
rapidly grown with their board of directors that come from according to the verification method of the RISC-V
companies such as NVIDIA and Google. There are a number processor. A total of 27 compressed RISC-V ISA instructions
of open-source processors that implement the RISC-V ISA were monitored through simulations and FPGA evaluation.
which include Rocket [8], Berkeley Out of Order Machine The verification of the processor instruction is through a
(BOOM) [8], PICORV32 [9] and many more. These terminal to displays only the memory related commands and
processors are complex with pipelined structures that achieve the results of the program trace in hexadecimal values. This
high throughput with low hardware footprint [10]. These makes it difficult to understand the actual internal operations
processors are therefore difficult to understand by researchers of the processor under evaluation.
seeking information about the RISC-V ISA architecture. This The work that comes close to this paper is proposed by [13].
paper therefore implements a 32-bit single cycle RISC-V ISA The author of [13] proposed and implemented a fully
core with peripherals to monitor the internal operations of the synthesizable RISC-V processor core on an FPGA device to
processor. text LCD display port. A user inputs Assembly code which is
The objectives of this paper are as follows converted to machine code and executed by the processor
 The paper illustrates design and implementation of with the results displayed on the text LCD. The text LCD
the control and datapath for a 32-bit single cycle RISC-V ISA shown only current PC value and the results of executed
core using Verilog HDL RISC-V instruction. The work of [13] is extended with
 Hardware controllers for peripherals such as seven- peripherals such as seven-segment display, LEDs, dot matrix,
segment display, text LCD, dot matrix, LEDs, and keypad are and keypad to form the basis of this paper. The displays show
added to monitor the internal activities of the processor core. the internal content of the processor which include the PC,
This is done to provide an easy way to input instruction and register file, instruction memory, and the data memory. These
observe the internal data of components such as the register displayed values are shown for each RISC-V instruction

Copyrights @Kalahari Journals Vol. 6 No. 3 (October-December, 2021)

International Journal of Mechanical Engineering

856
which makes it easy to understand the internal operation of a RV32/64/128M Extension for Integer Multiplication
typical RISC-V processor core. and Division Instructions
RV32/64/128A Extension for Atomic Instructions
3. RISC-V ISA Technical Specification RV32/64/128F Extension for Single-Precision
Floating-Point Instructions
The RISC-V ISA is a load-store ISA based on the principles RV32/64/128D Extension for Double-Precision
of RISC. The load-store ISA format typically divide Floating-Point Instructions
instructions into two groups which include memory access
(where only store and load instructions have access to There are a total of 32 registers used by the RISC-V ISA out
memory) and ALU operations (where the operands are in of which 31 are general purposed registers (register x1 to x31)
registers). The simplicity of the RISC-V ISA design makes it while one register (register x0) is hardware wired to a
possible execute instructions in just one clock cycle. constant 0. In addition to the 32 registers, a special register is
RISC-V has a base ISA which is referred to as RISC-V 32- used to store the address of the current instruction known as
bit Integer (RV32I) which is compulsory for any the PC register. The width of the registers could be 32-bit, 64-
implementation. The RV32I instructions which include loads, bit, or 128-bit depending on the implementation.
stores, control flow, and integer computations. The RV32I The RISC-V ISA consists of six main instruction formats
instructions can be extended to include multiplication and which include, R-type (register-register instructions), I-type
division (RV32IM), atomic operations (RV32IA), single (loads and jump-and-link instructions), S-type (store
precision floating point (RV32IF), and double precision instructions), B-type (branch instructions), U-type (load-
floating point (RV32ID). These extensions are optional to upper-immediate instructions), and J-type (jump
implement. It must be noted that the RISC-V ISA also allows instructions). Figure 1 illustrates the various instruction
for data widths of 64-bit and 128-bit as shown in Table 1 but format [14], [15] where funct stands for function, opcode
this paper implements a data width of 32-bit. stands for operation code, imm stands for immediate, rd
Table 1: Summary of RISC-V ISAs stands for destination registers, rs1 stands for source register
ISA Description 1, and rs2 stands for source register 2.
RV32/64/128I Base Integer Instruction Set

Figure 1. RISC-V 32-bit Instruction Format

of the 39 instructions which are illustrated in Figure 2.
The RISC-V RV32I which is implemented in this paper
consist of a total of 39 instructions. This paper implements 37

Copyrights @Kalahari Journals Vol. 6 No. 3 (October-December, 2021)

International Journal of Mechanical Engineering

857
 Figure 2. RISC-V RV32I Base Instruction Set
4. RV32I ISA Single Cycle Processor Hardware of this work is to help researchers understand the inner
Architecture workers of the RISC-V processor, the implementation of the
RV32I ISA is simplified. The hardware architecture of the
The hardware architecture for the RV32I ISA was designed RV32I ISA implementation is shown in Figure 3. The
by expanding on an architecture implemented in the RISC-V architecture is a single cycle design which means it is capable
book [15]. The authors of [15] implemented a basic RISC-V of fetching, decoding, and executing the 37 RISC-V
hardware architecture capable of executing a total of seven instructions in just a single cycle using components such as
instructions which include load doubleword (ld), store double the PC, ALU, register file, instruction memory, data memory,
word (sd), add, sub, and, or, and branch if equal (beq). This and some basic logic gates. This section examines each
architecture was expanded to execute a total of 37 instructions component of Figure 3.
and formed the basis of this work. Since the main objective

Copyrights @Kalahari Journals Vol. 6 No. 3 (October-December, 2021)

International Journal of Mechanical Engineering

858
 Figure 3. The Hardware Architecture of the RV32I ISA Design
by a factor of 1 to fetch all 32-bit instruction in the instruction
4.1. Program Counter Register memory. When executing B-type (branch), U-type (load-
The PC is a special register inside the processor that stores upper-immediate), and J-type (jump), the PC register stores
the address of the next processor instruction. The PC register the calculated value of the jump addresses. The output of the
in the RV32I ISA is has a data width of 32-bit. The instruction PC register is assigned to the instruction memory, register
is the machine code which is in the instruction memory. file, or the ALU depending on the type of instruction
Generally, in the design of a CPU, the PC is usually increased performed. Figure 4 shows a diagram of the PC register
by 4 during the normal instruction execution. The increased input/output signals.
by a factor 4 is because most CPUs are byte addressable. For
simplicity of the memory design, this work increases the PC

Figure 4. PC Register Input/Output Signals

4.2. ALU Architecture the register). A multiplexer is used to route the signals to the
The ALU is responsible for performing arithmetic and logical input of the ALU. The internal circuitry of the ALU can
operations. The ALU is a fundamental basic block of every perform 10 operations which include AND, OR, ADD, SLL,
processor. The ALU cannot store data on its own, it must go XOR, SUB, SLT, SRL, SRA, and NOR. The output signal is
through a register. The built-in ALU designed in this work assigned to the PC register, the data memory, and the Data
has three 32-bit inputs and one 32-bit output. The inputs Modification Module depending on the instruction type.
consist of a data from the PC (JAL instruction execution) and Figure 5 shows the architecture of the ALU.
data from the instruction memory (R-type instruction from

Copyrights @Kalahari Journals Vol. 6 No. 3 (October-December, 2021)

International Journal of Mechanical Engineering

859
 Figure 5. ALU Architecture
Two multiplexors with select signals from the instruction are
4.3. Register File Architecture used to route data to selected registers. The internal
The RV32I ISA consist of a total of 32 32-bit registers for architecture of the register file is made up 32x32 memory.
holding data. A register is a memory device that temporarily The value of ina, inb determines the address of the 32-bit
remembers the data that the processor needs to process the output ports outa, outb. The output signals are assigned to the
instruction. The registers are few but are directly connected Data Modification Module which in goes to the PC register
to the ALU which makes the computation and storage of depending on the type of instruction. Figure 6 shows the
intermediate data very fast. The register file implemented in input/output logic of the register file implemented in this
the work consist of five inputs and two outputs. The input work.
labeled ina, inb, and ind each of 5-bit width select the register
to write to or read from depending on the instruction type.

Figure 6. Register File Architecture

4.4. Data Modification Module internal circuitry of the Data Modification Module consists of
The Data Modification Module is responsible for the division logic that converts 32-bit data into the signed format and logic
of data into bytes, handling of signed and unsigned numbers, that divides 32-bit data into 8-bit, 16-bit, and 24-bits. The
and some computation of values. Data Modification Module output signals labeled otherouta and otheroutb are assigned to
consist of seven inputs and three outputs. The three input the ALU while the output signal labeled otherreg is assigned
labeled othercon, opcode, and imm serve as control signals to the register file. Figure 7 shows the architecture of the Data
for activating the Data Modification Module. The signal Modification Module.
labeled otherina and otherinb are data from the register file
and the signal labeled memdata is from data memory. The

Copyrights @Kalahari Journals Vol. 6 No. 3 (October-December, 2021)

International Journal of Mechanical Engineering

860
 Figure 7. Data Modification Module Architecture
be read from the instruction memory. The 32-bit instruction
4.5. Instruction Memory from the output of the instruction memory is assigned to
The instruction memory is responsible for storing 32-bit modules such as the PC, register file, ALU, data memory, and
machine code (instructions). The instruction memory Data Modification Module. The 32-bit output serve as control
implemented in this work is made up of 32-bit data width with signal for activating the values modules depending on the
a depth of 512. This memory is read only and therefore only type of instruction to execute. Figure 8 illustrates the
needs an address port to get access to a particular instruction. input/output signal of the instruction memory.
The PC output port provides the address of an instruction to

Figure 8. Instruction Memory Input/Output

and written. RISC-V is little endian which means that when
4.6. Data Memory storing data in memory, the Least Significant Byte (LSB) is
The data memory is responsible for storing data that is not stored first. The data memory consists of four inputs and one
instruction or machine code. This data is usually generated output. The 32-bit output of the instruction memory is
when the processor operational. This memory is a type of assigned to the Data Modification. Figure 9 shows the
Random-Access Memory (RAM) in which data can be read input/output signals of the data memory.

Copyrights @Kalahari Journals Vol. 6 No. 3 (October-December, 2021)

International Journal of Mechanical Engineering

861
 Figure 9. Data Memory Input/Output
Execution
4.7. General Flow of RISC-V ISA
The typical operation of the RISC-V processor consists of 5. Hardware Verification Module of RISC-V Processor
five steps which include instruction fetch, decode, execute, A verification module is proposed to observe the
memory access, and writeback. Figure 10 shows the flow of functionality of the RISC-V RV32I processor core. This
a typical RISC-V processor operation. In the information module is important because it enables observers to easily
fetch stage, the PC output the address to the instruction understand the RISC-V ISA by observing real internal values
memory which make available the 32-bit instruction or when an instruction is operating. To observe the internal
machine code. The decode stage group the instruction code operation of the processor core, various peripherals are used
and sent to the various modules as control signals. In the to access real-time values from components such as registers,
execute stage, the various modules which the ALU, register PC registers, data memory, and instruction memory during
file, and Data Modification Module are used to perform the normal operation of the processor. Figure 11 shows the
instruction. In the memory access stage, data is read or stored various peripheral used to observe the internal operation of
in the data memory depending on the type of instruction. The the RISC-V processor. The peripherals and with their
writeback stage stores value in the register file depending on functionalities are shown in Table 1.
the type of instruction.

Figure 10. General Flow of RISC-V Instruction Figure 11. RISC-V Processor Verification Peripherals
Table 1: Functionalities of RISC-V Processor Verification Peripherals
Peripheral Functionality
USER SW1 button is used to increment of the PC by 1 while USER SW2 button is used
(a) Push Button
to increment the address of the instruction memory.
First row 2-4 displays status. First row 8-15 display user value entered. The second row
(b) Text LCD 2-5 display the current instruction. Second row 7-14 displays the current value in the
instruction memory.
(c) LEDs Eight LEDs are used to display the current PC value.
(d) 7-Segment Display The last two segments display the address of the instruction memory
The Dot matrix is used to display data stored in the instruction memory, data memory
(e) Dot Matrix
and register file.
The del button is used to delete an entered value. The ins button is used to insert an
(f) Keypad
entered value. Button 1 to 9 are used for entering the machine code.
(g) Dip Switch The first five are used to set the register and data memory address.

dot matrix, keypad, and dip switch. Controller modules were

5.1. Processor Verification on an FPGA Board designed for each of the peripherals. Figure 12 shows the
The RV32I single cycle processor was verified on an FPGA connections of the peripheral to the FPGA device. From the
board designed by HANBACK Electronics. The test board is figure, the Test_module consist of the various peripheral
equipped with Virtex-4 XC4VLX80 FPGA device. The controllers which are also connected to the processor.
peripherals for observing the operation of the processor
include, push buttons, text LCD, LEDs, 7-segment display,

Copyrights @Kalahari Journals Vol. 6 No. 3 (October-December, 2021)

International Journal of Mechanical Engineering

862
 Figure 12. Connections of Peripheral to the FPGA Device
instruction code. By entering all the values of the instruction
Figure 13 shows the flow chart for checking RISC-V code, it is stored in FPGA instruction memory at the address
processor instructions on the FPGA board. When the FPGA previously specified. The USER SW1 button is used to
is powered up, all registers and memory locations are manually increase the value of the PC which is shown on the
initialized to zero. The user uses the keypad to insert a LED. The dip switch is used to display values from the
instruction that starts with the Operation Code (OPCODE). register file, instruction memory, and data memory on the dot
The USER SW2 button is used to set the instruction address matrix. Figure 14 illustrates the output of ADD UPPER
shown in seven segments before entering the instruction data. IMMEDIATE TO PC (AUIPC) instruction on the FPGA
The desired number of buttons are used to insert the board.

Figure 13. RISC-V Processor Verification Flow Chart

Copyrights @Kalahari Journals Vol. 6 No. 3 (October-December, 2021)

International Journal of Mechanical Engineering

863
 Figure 14. Display of AUIPC RISC-V Instruction of an
FPGA Board

5.2. Hardware Synthesis Results of RISC-V Verification

Module
The processor core together with the peripheral controllers
was synthesized using Xilinx Virtex4 FPGA device which
resulted in 6834 LUTs at a maximum frequency of 64 MHz
as shown in Table 2. Don et al. [13] designed a RISC-V
processor with Text LCD peripheral for verification. When
this work is compared to that of [13], this work consumed
more LUTs because of the use of several peripheral
controllers for the processor internal state verification than
that of reference [13] but achieved twice the frequency of
reference [13].

Table 2: Synthesis Results and Comparison

Design Processor Type and Peripherals Area (LUTs) Frequency (MHz)
[13] RV32I Processor, Text LCD 5578 32

RV32I Processor, Text LCD, LEDs, Dip Switch, Push

This Work 6834 64
Buttons, 7-Segment, Dot Matrix, Keypad

6. Andrew W, Yunsup L, David P, Krste A. The RISC-

5. Hardware Verification Module of RISC-V Processor V Instruction Set Manual, Volume I: Base User-Level ISA.
Technical Report UCB/EECS-2011-62, EECS Department,
This work provides an insight into the internal operation of a University of California, Berkeley, May 2011.
RISC-V RV32I processor using an FPGA device and 7. Nari L. "SiFive to showcase RISC-V based PC in
input/output peripherals. This work can serve as teaching October," [Online], Retrieved 26 February, 2021.
material for the computer architecture course that will enable http://www.thelec.net/news/articleView.html?idxno=1584.
students to understand the internal operation of a RISC-V
processor core. In the future, a user-friendly desktop/web
8. Krste A, Rimas A, Jonathan B, Scott B, David B,
Christopher C, Henry C, Daniel D, John H, Adam I, Sagar K,
application will be designed to serve as an interface to the
Ben K, Donggyu K, John K. The Rocket chip generator.
FPGA and display the internal values of the RISC-V
Technical Report UCB/EECS-2016-17, EECS Department,
processor core.
University of California, Berkeley, Apr 2016.
9. Clifford W. "PICORV32 – A size-optimized RISC-
7. Reference V CPU," [Online], Retrieved 26 February, 2021.
https://github.com/cliffordwolf/picorv32.
1. Ryu JW, Lee JH, An Efficient Vehicle License Plate 10. Dennis ANG, Kwangki R. Selecting a synthesizable
Recognition System Based on Embedded Systems, Journal of RISC-V processor core for low-cost hardware devices,
Next-generation Convergence Technology Association. 2021 Journal of Information Processing Systems. 2019
Feb. 5(1) 22-27. Dec. 15(6), 1406-1421.
2. Ryu HG, Ryu KK, Kindergarten school bus 11. Lee JB, Simulation and synthesis of RISC-V
notification service using IoT network, Journal of Next- processors, The Journal of the Institute of Internet,
generation Convergence Technology Association. 2019 Mar. Broadcasting and Communication. 2019 Feb. 19(1), 239-245.
3(1) 21-28. 12. Hiroaki K, Akinori K. An integrated machine code
3. Daniel D. Open hardware: Initial experience with monitor for a RISC-V processor on an FPGA, Artificial Life
synthesizable open cores [dissertation]. [Uppsala]: Uppsala Robotics. 2020 Mar. 25, 427–433.
Universitet; 2019. 13. Don KD, Ayushi P, Virk SS, Sajal A, Tanuj S, Arit
4. Kim WY. "The Linux 'RISC-V' singularity in the M, Kailash CR, Single cycle RISC-V micro architecture
CPU world has begun to break through," [Online], Retrieved processor and its FPGA prototype, Proceedings of 7th
25 January, 2021. International Symposium on Embedded Computing and
https://zdnet.co.kr/view/?no=20201201123035. System Design. 2017 Dec. India.
5. Swarup B, Michael SH, Mainak B, Seetharam N. 14. Bucknell University Computer Science Department.
Hardware trojans attacks: Threat analysis and "RISC-V instruction reference (green sheet)," [Online],
countermeasures, Proceedings of the IEEE. 2014 Aug; 102(8): Retrieved 26 February, 2021.
1229-1247. http://csci206sp2020.courses.bucknell.edu/files/2020/01/risc
v-card.pdf

Copyrights @Kalahari Journals Vol. 6 No. 3 (October-December, 2021)

International Journal of Mechanical Engineering

864
15. David AP, John LH. Computer organization and
design: The hardware/software interface, RISC-V 5th edn,
Elsevier, 2017.

Copyrights @Kalahari Journals Vol. 6 No. 3 (October-December, 2021)

International Journal of Mechanical Engineering

865