Received September 2, 2021, accepted October 18, 2021, date of publication October 22, 2021, date of current version

November 2, 2021.
Digital Object Identifier 10.1109/ACCESS.2021.3122238

Fractional-Order and Power-Law Shelving Filters:

Analysis and Design Examples
STAVROULA KAPOULEA 1 , (Student Member, IEEE), ABDULLAH YESIL 2, (Member, IEEE),
COSTAS PSYCHALINOS 1 , (Senior Member, IEEE),
SHAHRAM MINAEI3 , (Senior Member, IEEE),
AHMED S. ELWAKIL 4,5,6 , (Senior Member, IEEE),
AND PANAGIOTIS BERTSIAS 1
1 ElectronicsLaboratory, Department of Physics, University of Patras, 26504 Rio Patras, Greece
2 Department of Electrical and Electronics Engineering, Bandirma Onyedi Eylül University, 10200 Balikesir, Turkey
3 Department of Electrical and Electronics Engineering, Dogus University, 34775 Umraniye, Istanbul, Turkey
4 Department of Electrical and Computer Engineering, University of Sharjah, Sharjah, United Arab Emirates
5 Department of Electrical and Software Engineering, University of Calgary, Calgary, AB T2N 1N4, Canada
6 Nanoelectronics Integrated Systems Center (NISC), Nile University, Giza 12588, Egypt

Corresponding author: Costas Psychalinos ([email protected])

This work was supported in part by the Greece and the European Union (European Social Fund—ESF) through the Operational
Program ‘‘Human Resources Development, Education and Lifelong Learning’’ in the context of the project ‘‘Strengthening Human
Resources Research Potential via Doctorate Research-2nd Cycle’’ implemented by the State Scholarships Foundation (IKY) under
Grant MIS-5000432, and in part by the Istanbul Technical University VLSI Laboratories for the Cadence Design Environment.

ABSTRACT Low-pass and high-pass non-integer order shelving filter designs, which are suitable for
acoustic applications, are presented in this work. A first design is based on a standard fractional-order bilinear
transfer function, while a second one is based on the transposition of the integer-order transfer function into
its power-law counterpart. Both transfer functions are approximated using the Oustaloup approximation
tool, while the implementation in the case of the power-law filters is performed through the employment
of the concept of driving-point impedance synthesis. An attractive benefit is the extra degree of freedom,
resulting from the variable order of both fractional-order and power-law filters, which allows improved
design flexibility compared to the case of integer-order filters. From the implementation point of view, only
one building block is required to realize both filter types, thanks to the employment of the Voltage Conveyor.

INDEX TERMS Fractional-order filters, power-law filters, shelving filters, acoustic filters, fractional-order
impedance, Oustaloup approximation, voltage conveyor.

I. INTRODUCTION experience, based on the equal-loudness-level contours

The most important characteristic of shelving filters is (ELLC) provided by the ISO226:2003 standard [10], where it
that, instead of completely removing the out-of-band fre- was mentioned that the slope of the gradient in the transition
quencies as low/high-pass filters perform, they attenuate between the two bands must be less than 20 dB/dec. The
them by a predefined factor. Shelving filters are very analysis of fractional-order filters is based on the funda-
mental relationship L 0 Dαt f (t) = sα F(s), which describes
 
important building blocks for implementing home Hi-Fi
equipment, car stereos, in mixers, etc. [1], [2]. Among the Laplace transform of the derivative, for zero initial con-
the main categories of shelving filers are the following: ditions. The transition slope offered by a fractional filter,
a) low-pass or ‘‘low-shelf’’ filters, which boost or attenuate of order 0 < α < 1, is equal to 20 · α dB/dec, making it
the low end of the frequency spectrum, and b) high-pass an attractive solution for fulfilling the aforementioned spec-
or ‘‘high-shelf’’ filters, which boost or attenuate the high ifications [11]–[17]. An implementation of fractional-order
end of the frequency spectrum [3]–[8]. Shelving filters have shelving filters has been presented in [18], where the ratio-
been employed in [9] in order to improve the listening nal integer-order function, derived through the approxima-
tion of the fractional Laplacian operator, was implemented
The associate editor coordinating the review of this manuscript and using Operational Transconductance Amplifiers (OTAs) as
approving it for publication was Venkata Rajesh Pamula . active elements in a multi-feedback filter configuration.

This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
VOLUME 9, 2021 145977
 S. Kapoulea et al.: Fractional-Order and Power-Law Shelving Filters: Analysis and Design Examples

Setting sα = ωα · cos( απ απ
 
Although this scheme offers electronic tunability and versatil- 2 ) + j sin( 2 ) in (1), the derived
ity, as both low-pass and high-pass filters are implementable expressions for the magnitude and phase responses are
by the same core, it suffers from the large active component
count. | HFO (ω) |
p
In the present work, two different methods are followed for = GL GH
the implementation of non-integer shelving filter functions. √ #1/2
(ωτ0 )2α + 2 G (ωτ0 )α cos απ
"

2 +G
The first one is based on the substitution of the capaci- · √ , (3)
G (ωτ0 )2α + 2 G (ωτ0 )α cos απ


tors in the conventional (i.e., integer-order) shelving filter 2 +1
structures by fractional-order ones and their approximation 6 HFO (ω)

(ωτ0 )α sin απ
" #
by suitable RC networks. The second one is related to the


−1 2
implementation of power-law shelving filters and is based on = tan √
G + (ωτ0 )α cos απ


the approximation of a transfer function formed as a ratio of 2
" √
G (ωτ0 )α sin απ

#
a power-law impedance and an integer-order impedance. The
− tan −1
√ 2

. (4)
overall power-law impedance is approximated and this is the 1 + G (ωτ0 )α cos απ 2
main difference compared to fractional-order filters, where
√
only the impedance of the corresponding fractional-order The gain at the frequency ω0 is equal to GL GH and is
capacitor is approximated. This leads to the reduction of the the (geometric) mean of the characteristic gains of the filter.
circuit complexity in terms of passive component count. The Considering (2), it is derived that the pole and zero loca-
performed comparison shows that the power-law shelving tions are adjustable through the order of the filter. This
filter function is the most advantageous solution with regards is not the √ case for integer-order filters (α = 1), where
√
to the spread of the values of passive elements, without ωP = ω0 / G, ωZ = ω0 G, and the position of the pole
losing the extra degree of freedom, which is offered by the and zero is fixed through G and ω0 . Owing to the fact that the
variable order of the filter. Another important point is that pole and zero locations determine the location of the low (ωL )
the implementation of both filters is performed using only and high (ωH ) cutoff frequencies (they are not the same in
one active element, which is the Voltage Conveyor (VCII) the case of fractional-order filters), the slope of the transition
[19]–[22]. between the two bands can be adjusted through the order of
The paper is organized as follows: the effect of the order on the filter, assuming that the shelving gain (G) and the center
the frequency characteristics of both types of filters is studied frequency (ω0 ) are predefined. The slope of the gain through
in Section II, where the findings are supported by MAT- the transition from the passband to the stopband is calculated
LAB results. The proposed fractional-order and power-law through the following expression
filters implementations are introduced in Section III, and the
verification of their behavior is performed using the TSMC 20 log(G)
slope = (dB/dec). (5)
log ωωHL
 
0.18 µm CMOS process technology file in Section IV.

II. NON-INTEGER SHELVING FILTERS In order to have a better sense of the effect of the pole
A. FRACTIONAL-ORDER SHELVING FILTERS and zero location on the cutoff frequencies and, consequently,
The transfer function of a fractional-order (0 < α < 1) on the slope, let us consider the case of a filter with a given
shelving filter, is given by (1) set of {ω0 , G, GL(H ) } and with pole and zero frequencies far
√ apart from each other. As a result, the low and high cutoff
p (τ0 s)α + G frequencies will be determined according to the following
HFO (s) = GL GH · √ , (1)
G (τ0 s)α + 1 expressions [11]
 απ   απ  1/α
where the shelving gain G is defined as G ≡ GL /GH , with
r
ωL,FO = ωP · 1 + cos 2 − cos ,
GL and GH being the asymptotic low and high frequency 2 2
gains, respectively [18]. In the case that GL > GH , the filter r  απ   απ  1/α
performs as low-pass filter, while for GL < GH it behaves ωH ,FO = ωZ · 1 + cos2 + cos ,
as a high-pass filter. The time constant is τ0 = 1/ω0 , and the 2 2
pole and zero frequencies are equally spaced (in logarithmic (6)
scale) around the characteristic frequency ω0 according to (2) or, using (2)
1 1
ωP = ω0 G− 2α , ωZ = ω0 G 2α . (2) 1
r  απ   απ  1/α
ωL,FO = ω0 G − 2α
· 1 + cos 2 − cos ,
2 2
Therefore, the characteristic frequency will be the r  απ   απ  1/α
(geometric) mean of the pole and zero frequencies, i.e., ω0 = ωH ,FO = ω0 G 2α
1
· 1 + cos2 + cos .
√
ωP · ωZ , and it will be referred to as center frequency 2 2
hereinafter. (7)

145978 VOLUME 9, 2021

S. Kapoulea et al.: Fractional-Order and Power-Law Shelving Filters: Analysis and Design Examples

It is readily obtained from (7) that the cutoff frequencies

are, also, symmetrically located (in logarithmic scale) around
the center frequency ω0 and they can be shifted through the
change of the order. The slope is calculated as
20α log(G)
slopeFO = √ (dB/dec).
2 )−cos( 2 )
1+cos2 ( απ απ
log √ απ − log(G)
1+cos2 ( απ
2 )+cos( 2 )
(8)
In the case of an integer-order filter, changing the slope is
not possible, because the pole and zero frequencies are equal
to the corresponding cutoff frequencies, i.e.,√ωL = ωP and
FIGURE 1. Bode plots of integer-order (black line), fractional-order
ωH√= ωZ and, consequently, ωL = ω0 / G and ωH = (red line) and
 power-law(blue line) types of low-pass filter with
ω0 G. Setting α = 1 in (8), the well-known −20dB/dec α = 0.7 and GL , GH = 10, 1 .
slope of the integer-order filter is obtained.

B. POWER-LAW SHELVING FILTERS

An alternative transfer function, which describes a power-law
shelving filter, is that given in (9)
1
!α
p τ0 s + G 2a
HPL (s) = GL GH · 1
. (9)
G 2a τ0 s + 1
The location of the pole and zero is still described by (2),
being the same as in the corresponding fractional-order
filter [23]. Setting s = jω, the magnitude and phase responses
are given by (10) and (11)
" 1
# α2
p (ωτ0 )2 + G α
| HPL (ω) | = GL GH · 1
, (10)
G α (ωτ0 )2 + 1
ωτ0
    1 
6 HPL (ω) = α · tan−1 − tan−1
G ωτ0 .
2α
1
G 2α
(11)
The√gain at the center frequency is still given by the for-
mula GL GH . Under the same assumptions as in the case of
a fractional-order filter, the low and high cutoff frequencies
are
1 p
ωL,PL = ω0 G− 2α · 21/α − 1, FIGURE 2. Frequency responses of fractional-order shelving
low/high-pass filters with f0 = 1 kHz for α = 0.7, 0.8, 0.9 .

1
ω0 G 2α
ωH ,PL = √ . (12)
21/α − 1 It must be mentioned at this point that the accurate location
Using (12), the expression of the slope is of the cutoff frequencies must be calculated using (3) or (10).
20α log(G) Let us consider the case of non-integer low-pass/high-pass
slopePL = (dB/dec), (13) filters with {GL , GH } equal to {10,1} (low-pass) or {1,10}
α · log 21/α − 1 − log(G)


(high-pass) and f0 = 1 kHz. The corresponding gain and
and, consequently, the same derivations as in the case of phase plots for orders α = {0.7, 0.8, 0.9}, in the case
fractional-order filters are valid. The only difference is the of a fractional-order filter, are depicted in Fig. 2, along
scaling factors, by which the zero and pole frequencies are with the corresponding plots of the integer-order filter. The
multiplied. Resulting in different slopes of the transition most important performance characteristics are summarized
between the passband and the stopband. To make this more in Table 1, while the corresponding ones of the power-law
evident, let us consider a power-law low-pass shelving filter counterparts in Table 2.
with order α = 0.7 and {GL , GH } = {10, 1}. The obtained From these results, it is concluded that the fractional-order
bode plots of the integer-order (black line), fractional-order filter shifts the cutoff frequencies of the filter further away
(red line) and power-law (blue line) types of filters are from the center frequency, with regards to its power-law
demonstrated in Fig. 1, where this claim is confirmed. and integer-order counterparts. This reflects a less steep

VOLUME 9, 2021 145979

 S. Kapoulea et al.: Fractional-Order and Power-Law Shelving Filters: Analysis and Design Examples

TABLE
 1. Frequency response characteristics of fractional-order filters for
α = 0.7, 0.8, 0.9 and their integer-order counterpart.

TABLE
 2. Frequency response characteristics of power-law filters for
α = 0.7, 0.8, 0.9 and their integer-order counterpart.

transition from the passband to the stopband. The power-law

filter offers an intermediate slope between the integer and FIGURE 3. Frequency responses  of power-law shelving low/high-pass
fractional orders, due to the location of the cutoff frequencies, filters with f0 = 1 kHz for α = 0.393, 0.506, 0.678 .
being between the corresponding ones of the integer-order
and fractional-order filters.
Another important finding is that the equivalent order (αeq )
of a power-law filter offers the same cutoff frequencies with
those of a fractional-order filter. The values of the power-law
filters, which correspond to 0.7, 0.8, 0.9 fractional-order
filters, are 0.393, 0.506 and 0.678, respectively. This is ver-
ified through the plots demonstrated in Fig. 3, where the
obtained frequency characteristics are the same with those of
the fractional-order filters of Table 1.
FIGURE 4. CCII-based implementation of low-pass fractional-order
III. PROPOSED SHELVING FILTER IMPLEMENTATIONS shelving filters.
A. IMPLEMENTATION OF FRACTIONAL-ORDER SHELVING
FILTERS
Fractional-order shelving filters, described by (1), can be A problem, that occurs in the topologies of Figs. 4-5, is that
realized, using second-generation current conveyors (CCIIs) they suffer from the effect of loading and, therefore, an extra
as active elements, by the topologies in Figs. 4-5. The topol- output buffer is required in the case of cascade connection of
ogy in Fig. 4 corresponds to a low-pass and the one in Fig. 5 to filter stages.
a high-pass filter. Taking into account that the impedance of a A promising active element for avoiding such problems is
fractional-order capacitor of order α and pseudo-capacitance the VCII, with its symbol depicted in Fig. 6. This element is
Cα is given by the formula Z (s) = 1/Cα sα , the associated constructed from a current follower, which establishes that
design equations are respectively iY = iX , and from a voltage follower, which conveys the
R2 R1 //R2 R2 voltage at the terminal X into that at the terminal Z, estab-
GL = , GH = , G= , lishing that υX = υZ . An enhanced low-frequency model
R3 R3 R1 //R2
i1 of the VCII, with the associated parasitic resistors of each
α terminal included, is given in Fig. 7 (ideally, rY , rZ → 0, and
hp
τ0 = R1 (R1 + R2 )C1α , (14)
rX → ∞).
R3 R3 R1 //R2
GL = GH = G= , The proposed topologies of VCII-based shelving filters
R2 R1 //R2 R2 are demonstrated in Figs. 8–9. Assuming that the VCII is
i1 ideal, then, by performing a routine analysis, it is easily
α
hp
τ0 = R1 (R1 + R2 )C1α . (15)
verified that the design equations in (14)–(15) are also valid.
145980 VOLUME 9, 2021
S. Kapoulea et al.: Fractional-Order and Power-Law Shelving Filters: Analysis and Design Examples

FIGURE 5. CCII-based implementation of high-pass fractional-order

shelving filters. FIGURE 9. Fractional-order high-pass filter using VCII as active element.

FIGURE 6. Voltage conveyor (VCII) symbol of ideal element.

FIGURE 10. Foster type-I network for approximating the fractional-order

capacitor in Figs. 8–9.

FIGURE 7. Voltage conveyor (VCII) low-frequency model including

parasitic resistors.

FIGURE 11. Power-law shelving low-pass filter using VCII as active

element.

The approximation of the fractional-order capacitors

in Figs. 8–9 can be performed through the utilization of
Foster or Cauer types of networks; for demonstration pur-
poses, a Foster type-I network, whose configuration is given
in Fig. 10, is used. Utilizing an nth -order approximation,
FIGURE 8. Fractional-order low-pass filter using VCII as active element.
the rational integer-order transfer function, that approaches
the impedance of the capacitor C1α , will have the form of

Considering the model in Fig. 7, the design equations become Bn sn + Bn−1 sn−1 + . . . + B1 s + B0
Z (s) = , (18)
R2 //rX R1 //R2 //rX An sn + An−1 sn−1 + . . . + A1 s + A0
GL = , GH = ,
R3 + rY R3 + rY with Ai and Bi (i = 0 . . . n) being positive and real coeffi-
R2 //rX cients. The required number of capacitors and resistors is
G= , equal to n and n + 4, respectively. The design equations of
1 + R1 //R2 //rX
i1 the Foster type-I network in Fig. 10 are summarized in (19)
α
hp
τ0 = R1 [R1 + (R2 //rX )]C1α , (16)
ri 1
R3 //rX R3 //rX R0 = k, Ri = , Ci = (i = 1, 2 . . . n), (19)
GL = , GH = , |pi | ri
R2 + rY (R1 //R2 ) + rY
(R1 //R2 ) + rY where ri , pi , k are the residues, poles and gain of (18) [24].
G= ,
R2 + rY
i1 B. IMPLEMENTATION OF POWER-LAW SHELVING FILTERS
α
hp
τ0 = R1 [R1 + (R2 + rY )]C1α . (17) The implementation of the power-law shelving filters will
be performed by the topologies in Figs. 11–12, where
Therefore, the parasitics affect both the shelving gain, as Zeq is considered as a driving-point impedance [25], given
well as the characteristic frequency of the filter. by (20)–(21), in the case of low-pass and high-pass

VOLUME 9, 2021 145981

 S. Kapoulea et al.: Fractional-Order and Power-Law Shelving Filters: Analysis and Design Examples

TABLE 3. Values of the elements of the type-I foster RC network in Fig. 10

for approximating the fractional-order capacitor in Figs. 8–9.

FIGURE 12. Power-law shelving high-pass filter using VCII as active

element.

filters, respectively.
1
!α
p τ0 s + G 2a
Zeq,PL−LP (s) = R3 GL GH · 1
, (20)
G 2a τ0 s + 1
1
!α
R3 G 2a τ0 s + 1
Zeq,PL−HP (s) = √ · 1
. (21)
GL GH τ0 s + G 2a the Foster type-I network in Fig. 10, calculated using the
The approximation of the impedances in Figs. 11–12 can expressions in (19) and rounded to the standard electronic
be performed using the Oustaloup approximation [26], with component values conforming to the E96 series defined in
the resulting rational polynomial transfer function having the IEC 60063, are summarized in Table 3.
form of (18) and, consequently, being implementable by the MOS transistors provided by the TSMC 0.18 µm CMOS
RC network in Fig. 10 using the design equations of (19). process are used in the simulations of the VCII topology
The required number of capacitors is the same as in the case shown in Fig. 13 [27]. Considering that VDD = −VSS =
of fractional-order filters, but the number of resistors is now 0.9 V and IB1 = IB2 = 30 µA, the nMOS transistors’ aspect
reduced by three, becoming equal to n + 1. ratio is chosen as 13.5 µm / 0.54 µm, while for the pMOS
Considering the effect of parasitic resistances of the VCII transistors as 40 µm / 0.54 µm. The bulk terminals of the
in both types of filters in Figs. 11–12, the derived transfer pMOS transistors are connected to the source terminals of
functions are modified to (22)–(23) the relevant transistors, while the bulk terminals of the nMOS
transistors are connected to the negative DC supply voltage.
1 The parasitic resistances of Y, X, and Z terminal of VCII were
HPL−LP (s) =   · HPL (s), (22)
calculated as 49.3 Ω, 16.33 M Ω and 52.76 Ω, respectively.
 
rY Zeq
1+ R3 · 1+ rX
It should be noted that the parasitic output resistance of the
1 X terminal has been increased thanks to the cascode stage.
HPL−HP (s) =     · HPL (s), (23)
1 + RrX3 · 1 + rY
Zeq
The dimensions of the derived layout design of VCII, given
in Fig. 13, are 40.78 µm × 37.55 µm, while the total power
with HPL (s) being the transfer function in (9). consumption is equal to 380.6 µW .
According to (9) and (22)–(23), the presence of parasitics The obtained post-layout magnitude and phase responses
affects only the gain of the realized transfer function. of the fractional-order filters in the acoustic band
(20 Hz − 20 kHz) are depicted in Fig. 14 (solid lines),
IV. SIMULATION RESULTS along with the corresponding ones derived by the Oustaloup
A. FRACTIONAL-ORDER FILTERS approximation of the transfer functions, marked by dashes.
The performance of the proposed shelving filter topologies The most important characteristics of their frequency behav-
in Figs. 8–9 and 11–12 will be evaluated considering fil- ior are summarized in Table 4, where the values that cor-
ter functions with {GL , GH } equal to {10,1} (low-pass) or respond to the Oustaloup approximation are given between
{1,10} (high-pass) and center frequency f0 = 1 kHz. Assum- parentheses.
ing that R3 = 20 k, in the case of low-pass fractional-order The sensitivity of the filter, with regards to the effects of
filter functions, the values of R1 , R2 , calculated from (14) MOS transistor mismatching and process parameters varia-
or (15), are 22.1 k and 200 k, respectively, while the tions as well as of passive elements’ values variations, has
values of the pseudo-capacitance C1α for orders 0.7, 0.8, been evaluated through the utilization of the Monte-Carlo
0.9 are 31.319 nF/s0.3 , 13.061 nF/s0.2 and 5.47 nF/s0.1 . analysis tool offered by the Analog Design Environment for
Accordingly, in the case of high-pass filters, R1 = 2.21 k, N = 100 runs. The obtained statistical plots of the gain and
R2 = 20 k and the pseudo-capacitances are 31.319 nF/s0.3 , phase at the center frequency of a high-pass shelving filter
13.061 nF/s0.2 and 54.47 nF/s0.1 . Considering a 5th -order with α = 0.8 are demonstrated in Figs. 15–16, where the
Oustaloup approximation, the values of passive elements of values of the standard deviation were 0.133 dB and 0.085◦

145982 VOLUME 9, 2021

S. Kapoulea et al.: Fractional-Order and Power-Law Shelving Filters: Analysis and Design Examples

FIGURE 13. Modified VCII topology and the corresponding layout design employed in simulations [27].

FIGURE 15. Monte-Carlo analysis results of the gain at the center

frequency f0 = 1 kHz of a high-pass fractional-order shelving filter
(α = 0.8) filter.

FIGURE 14. Post-layout simulated frequency responses (solid lines) of

the low/high-pass fractional-order shelving filters (f0 = 1kHz) (a) gain,
and (b) phase for α = 0.7, 0.8, 0.9 , along with the corresponding

Oustaloup approximated responses (dashed lines).

for the gain and phase, respectively. As the nominal values

are 10 dB and −35.3◦ , the derived results confirm that the
topology has reasonable sensitivity characteristics.
The time-domain behavior of this filter is evaluated
through its stimulation by a 10 mV , 1 kHz sinusoidal input
signal and the obtained input and output waveforms are plot-
ted in Fig. 17 confirming stability. The values of the gain and FIGURE 16. Monte-Carlo analysis results of the phase at the center
frequency f0 = 1 kHz of a high-pass fractional-order shelving filter
phase are 9.6 dB and −39.6◦ , close to the theoretical values (α = 0.8) filter.
of 10 dB and −35.3◦ , respectively.

B. POWER-LAW FILTERS fractional-order filters will be used. Therefore, the implemen-

In order to achieve fair comparison, the same condi- tation of power-law shelving filters with exactly the same
tions employed for evaluating the performance of the characteristics as those of their fractional-order counterparts

VOLUME 9, 2021 145983

 S. Kapoulea et al.: Fractional-Order and Power-Law Shelving Filters: Analysis and Design Examples

FIGURE 17. Input and output waveforms of a high-pass fractional-order

shelving filter (α = 0.8), for a 10 mV , 1 kHz input signal.

TABLE 4. Simulated frequency response characteristics of the

low/high-pass fractional-order filters with α = 0.7, 8, 0.9


(the values between parentheses are those derived through the

Oustaloup approximation of the transfer function).

FIGURE 18. Post-layout simulated frequency responses (solid lines) of

the low/high-passpower-law shelving filters (f0 = 1kHz) (a) gain and
(b) phase for α = 0.393, 0.506, 0.678 , along with the corresponding
Oustaloup approximated responses (dashed lines).

TABLE 6. Simulated frequency response characteristics of the low/

high-pass power-law shelving filters, with α = 0.393, 0.506, 0.678

(the values between parentheses are those derived through the
Oustaloup approximation of the transfer function).

TABLE 5. Values of the elements of the type-I foster RC network in Fig. 10

for approximating the impedance Zeq in Figs. 11–12.

are given in Table 5, where it is evident that there is a signif-

icant reduction in the spread of the passive elements’ values,
compared to the corresponding values of the fractional-order
type, given in Table 3 [28].
The obtained results showing the frequency behavior of the
power-law filters, which are given in Fig. 18 and Table 6,
confirm their performance in terms of accuracy.
The sensitivity of a high-pass shelving filter with
is performed. As it was mentioned in Section II, the corre- α = 0.506 has been evaluated from the statistical plots
sponding orders of the power-law filter for achieving the same in Figs. 19–20, where the corresponding values of the stan-
cutoff frequencies are 0.393, 0.506 and 0.678, respectively. dard deviation of the gain and phase at the center frequency
Using again the Oustaloup approximation, the values of pas- were 0.132 dB and 0.082◦ . The time-domain behavior of the
sive elements, required for approximating the impedance Zeq , filter is demonstrated in Fig. 21 and the measured values of

145984 VOLUME 9, 2021

S. Kapoulea et al.: Fractional-Order and Power-Law Shelving Filters: Analysis and Design Examples

V. CONCLUSION
Two types of shelving filters, a conventional fractional-order
one and a power-law one, both derived from an integer-order
based function, were designed in this work. It was partic-
ularly shown that, for fulfilling the design specifications,
the required order of the power-law filter is smaller than that
of the corresponding fractional-order filter and this stems
from the fact that the location of the cutoff frequencies is
different for filters of the same order. Both filters are real-
ized using appropriately configured RC networks intended
to approximate the fractional-order capacitor, in the case
of fractional-order filters, and the driving-point impedance,
in the case of power-law filters. The design procedure is
straightforward and the resulting structures are constructed
FIGURE 19. Monte-Carlo analysis results of the gain at the center from just one active element. This is not the case in the topolo-
frequency f0 = 1 kHz of a high-pass power-law (α = 0.506) shelving
filter.
gies presented in [18], where OTAs have been used as active
elements and the increased circuit complexity and compli-
cated design procedure were the price paid for the offered
design flexibility and versatility. The realized filter functions
have been obtained using a 5th -order Oustaloup approxima-
tion and the provided post-layout simulation results of the
designed acoustic filter functions verify the behavior of the
presented structures in terms of accuracy and robustness.
It must be mentioned at this point that the approximation of
the power-law shelving filters can be also performed using
curve-fitting-based tools, as in [23], [29], but in this work the
Oustaloup approximation tool has been utilized in order to
perform a fair comparison between the presented structures.
The proposed concept can be also applied in the area of
control systems, because shelving filters are the equivalents
of the lead-lag compensators and this exploitation is a subject
of ongoing research [30]–[33].
FIGURE 20. Monte-Carlo analysis results of the phase at the center
frequency f0 = 1 kHz of a high-pass power-law (α = 0.506) shelving filter. ACKNOWLEDGMENT
The publication of this article has been financed by the
Research Committee of the University of Patras.

REFERENCES
[1] J. Corey, Audio Production and Critical Listening: Technical Ear Training.
London, U.K.: Taylor & Francis, 2016.
[2] R. Izhaki, Mixing Audio: Concepts, Practices, and Tools. Evanston, IL,
USA: Routledge, 2017.
[3] F. Fontana and M. Karjalainen, ‘‘Magnitude-complementary filters for
dynamic equalization,’’ in Proc. Conf. Digit. Audio Effects (DAFX),
Limerick, Ireland, 2001, pp. 160–164.
[4] F. Keiler and U. Zolzer, ‘‘Parametric second- and fourth-order shelving
filters for audio applications,’’ in Proc. IEEE 6th Workshop Multimedia
Signal Process., Sep. 2004, pp. 231–234.
[5] M. Holters and U. Zölzer, ‘‘Parametric higher-order shelving filters,’’ in
Proc. 14th Eur. Signal Process. Conf., 2006, pp. 1–4.
[6] A. Fernandez-Vazquez, R. Rosas-Romero, and J. Rodriguez-Asomoza,
‘‘A new method for designing flat shelving and peaking filters based
on allpass filters,’’ in Proc. 17th Int. Conf. Electron., Commun. Comput.
(CONIELECOMP), Feb. 2007, p. 10.
[7] S. Sarkka and A. Huovilainen, ‘‘Accurate discretization of analog audio
FIGURE 21. Input and output waveforms of a high-pass filter power-law filters with application to parametric equalizer design,’’ IEEE Trans. Audio,
shelving filter (α = 0.506), for a 10 mV , 1 kHz input signal. Speech, Langauge Process., vol. 19, no. 8, pp. 2486–2493, Nov. 2011.
[8] V. Välimäki and J. Reiss, ‘‘All about audio equalization: Solutions and
frontiers,’’ Appl. Sci., vol. 6, no. 5, p. 129, May 2016.
the gain and phase were 9.6 dB and 39.6◦ , confirming also its [9] L. Fierro, J. Rämö, and V. Välimäki, ‘‘Adaptive loudness compensation in
accuracy in the time domain. music listening,’’ in Proc. Sound Music Comput. Conf., 2019, pp. 135–142.

VOLUME 9, 2021 145985

 S. Kapoulea et al.: Fractional-Order and Power-Law Shelving Filters: Analysis and Design Examples

[10] Acoustics–Normal Equal-Loudness Level Contours, Standard I. 226:2003, [32] A. A. Dastjerdi, N. Saikumar, and S. H. HosseinNia, ‘‘Tuning guide-
International Standards Organization (ISO), 1987. lines for fractional order PID controllers: Rules of thumb,’’ Mechatronics,
[11] G. Tsirimokou, C. Psychalinos, and A. Elwakil, Design of CMOS Analog vol. 56, pp. 26–36, Dec. 2018.
Integrated Fractional-Order Circuits: Applications in Medicine and Biol- [33] S. H. HosseinNia and N. Saikumar, ‘‘Fractional-order precision motion
ogy. Cham, Switzerland: Springer, 2017. control for mechatronic applications,’’ in Handbook of Fractional Calculus
[12] G. A. Haidar, R. A. Z. Daou, and X. Moreau, ‘‘Synthesis of a fractional With Applications, vol. 6. Berlin, Germany: Walter de Gruyter GmbH,
order audio boost filter,’’ in Proc. 29th Int. Conf. Microelectron. (ICM), 2019, pp. 339–356.
Dec. 2017, pp. 1–5.
[13] G. Tsirimokou, C. Psychalinos, A. S. Elwakil, and K. N. Salama, ‘‘Elec-
tronically tunable fully integrated fractional-order resonator,’’ IEEE Trans.
Circuits Syst. II, Exp. Briefs, vol. 65, no. 2, pp. 166–170, Feb. 2017.
[14] F. Schultz, N. Hahn, and S. Spors, ‘‘Shelving filter cascade with adjustable
STAVROULA KAPOULEA (Student Member,
transition slope and bandwidth,’’ in Audio Engineering Society Convention,
IEEE) received the B.Sc. degree in physics and
vol. 148. New York, NY, USA: Audio Engineering Society, 2020.
the M.Sc. degree in electronics from the University
[15] A. S. Mohapatra and K. Biswas, ‘‘A fractional order notch filter to com-
pensate the attenuation-loss due to change in order of the circuit,’’ IEEE
of Patras, Greece, in 2016 and 2018, respectively.
Trans. Circuits Syst. I, Reg. Papers, vol. 68, no. 2, pp. 655–666, Feb. 2020. She is currently pursuing the Ph.D. degree with
[16] O. Sladok, J. Koton, D. Kubanek, J. Dvorak, and C. Psychalinos, ‘‘Pseudo- the Analog Integrated Circuits Design Research
differential (2 + α)-order Butterworth frequency filter,’’ IEEE Access, Group, Electronics Laboratory, Department of
vol. 9, pp. 92178–92188, 2021. Physics, University of Patras, Greece. Her main
[17] D. Lin, X. Liao, L. Dong, R. Yang, S. S. Yu, H. Ho-Ching Iu, T. Fernando, research interests include the design and applica-
and Z. Li, ‘‘Experimental study of fractional-order RC circuit model using tions of fractional-order circuits.
the caputo and caputo-fabrizio derivatives,’’ IEEE Trans. Circuits Syst. I,
Reg. Papers, vol. 68, no. 3, pp. 1034–1044, Mar. 2021.
[18] S. Kapoulea, C. Psychalinos, and A. S. Elwakil, ‘‘Fractional-order shelving
filter designs for acoustic applications,’’ in Proc. IEEE Int. Symp. Circuits
Syst. (ISCAS), Oct. 2020, pp. 1–5. ABDULLAH YESIL (Member, IEEE) received
[19] L. Safari, G. Barile, V. Stornelli, and G. Ferri, ‘‘An overview on the second the B.Sc., M.Sc., and Ph.D. degrees in elec-
generation voltage conveyor: Features, design and applications,’’ IEEE trical and electronics engineering from Istanbul
Trans. Circuits Syst. II, Exp. Briefs, vol. 66, no. 4, pp. 547–551, Apr. 2018. University, in 2009, 2011, and 2016, respec-
[20] G. Barile, V. Stornelli, G. Ferri, L. Safari, and E. D’Amico, ‘‘A new rail- tively. He is currently an Associate Professor
to-rail second generation voltage conveyor,’’ Electronics, vol. 8, no. 11,
with the Department of Electrical and Electronics
p. 1292, Nov. 2019.
Engineering, Bandirma Onyedi Eylül University,
[21] L. Safari, G. Barile, G. Ferri, and V. Stornelli, ‘‘Traditional op-amp and new
Balikesir, Turkey. He has more than 60 publica-
VCII: A comparison on analog circuits applications,’’ AEU-Int. J. Electron.
tions in scientific journals, book chapters, or con-
Commun., vol. 110, Oct. 2019, Art. no. 152845.
ference proceedings. His main research interests
[22] A. Yesil and S. Minaei, ‘‘New simple transistor realizations of second-
include active network synthesis, current-mode circuit designs, low-noise
generation voltage conveyor,’’ Int. J. Circuit Theory Appl., vol. 48, no. 11,
pp. 2023–2038, Nov. 2020. implementation of continuous time filters, MOS-only filter designs, mem-
[23] S. Kapoulea, C. Psychalinos, and A. S. Elwakil, ‘‘Power law filters: A new
ristor emulators, and electronic circuits for computer-aided design.
class of fractional-order filters without a fractional-order Laplacian opera-
tor,’’ AEU-Int. J. Electron. Commun., vol. 129, Feb. 2021, Art. no. 153537.
[24] G. Tsirimokou, ‘‘A systematic procedure for deriving RC networks of
fractional-order elements emulators using Matlab,’’ AEU-Int. J. Electron.
Commun., vol. 78, pp. 7–14, Aug. 2017. COSTAS PSYCHALINOS (Senior Member, IEEE)
[25] S. Kapoulea, C. Psychalinos, and A. S. Elwakil, ‘‘Simple implementations received the B.Sc. and Ph.D. degrees in physics
of fractional-order driving-point impedances: Application to biological and electronics from the University of Patras,
tissue models,’’ AEU-Int. J. Electron. Commun., vol. 137, Jul. 2021, Greece, in 1986 and 1991, respectively. From
Art. no. 153784. 1993 to 1995, he worked as a Postdoctoral
[26] A. Oustaloup, F. Levron, B. Mathieu, and F. M. Nanot, ‘‘Frequency-band Researcher with the VLSI Design Laboratory, Uni-
complex noninteger differentiator: Characterization and synthesis,’’ IEEE versity of Patras. From 1996 to 2000, he was an
Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 47, no. 1, pp. 25–39, Adjunct Lecturer at the Department of Computer
Jan. 2000. Engineering and Informatics, University of Patras.
[27] L. Safari, E. Yuce, S. Minaei, G. Ferri, and V. Stornelli, ‘‘A second- From 2000 to 2004, he worked as an Assistant
generation voltage conveyor (VCII)–based simulated grounded inductor,’’ Professor at the Electronics Laboratory, Department of Physics, Aristotle
Int. J. Circuit Theory Appl., vol. 48, no. 7, pp. 1180–1193, Jul. 2020.
University of Thessaloniki, Greece. Since 2004, he has been a Faculty
[28] S. Kapoulea, C. Psychalinos, and A. S. Elwakil, ‘‘Minimization of spread Member at the Electronics Laboratory, Department of Physics, University of
of time-constants and scaling factors in fractional-order differentiator and
Patras, and currently, he is a Full Professor. His research interests include the
integrator realizations,’’ Circuits, Syst., Signal Process., vol. 37, no. 12,
development of CMOS analog integrated circuits, including fractional-order
pp. 5647–5663, Dec. 2018.
circuits and systems, continuous and discrete-time analog filters, amplifiers,
[29] S. Kapoulea, G. Tsirimokou, C. Psychalinos, and A. S. Elwakil, ‘‘Employ-
ment of the Padé approximation for implementing fractional-order lead/lag
and low voltage/low power building blocks for analog signal processing.
compensators,’’ AEU-Int. J. Electron. Commun., vol. 120, Jun. 2020, He is a member of the Nonlinear Circuits and Systems Technical Committee
Art. no. 153203. of the IEEE CAS Society. He serves as the Editor-in-Chief for the Circuit and
[30] M. S. Tavazoei and M. Tavakoli-Kakhki, ‘‘Compensation by fractional- Signal Processing Section of the Electronics journal (MDPI). He serves as an
order phase-lead/lag compensators,’’ IET Control Theory Appl., vol. 8, Area Editor for the International Journal of Electronics and Communications
no. 5, pp. 319–329, Mar. 2014. (AEUE) journal and an Editor for the International Journal of Circuit Theory
[31] C. Muñiz-Montero, L. A. Sánchez-Gaspariano, C. Sánchez-López, and Applications. He is an Associate Editor of the Circuits, Systems, and
V. R. González-Díaz, and E. Tlelo-Cuautle, ‘‘On the electronic realiza- Signal Processing Journal and the Journal of Advanced Research. He is
tions of fractional-order phase-lead-lag compensators with OpAmps and a member of the Editorial Board of the Microelectronics Journal, Analog
FPAAs,’’ in Fractional Order Control and Synchronization of Chaotic Integrated Circuits and Signal Processing journal, Fractal and Fractional
Systems. Cham, Switzerland: Springer, 2017, pp. 131–164. journal, and Journal of Low Power Electronics and Applications.

145986 VOLUME 9, 2021

S. Kapoulea et al.: Fractional-Order and Power-Law Shelving Filters: Analysis and Design Examples

SHAHRAM MINAEI (Senior Member, IEEE) linear dynamics, chaos theory, and fractional-order circuits and systems with
received the B.Sc. degree in electrical and elec- diverse applications ranging from the modeling of oscillatory networks and
tronics engineering from the Iran University of nonlinear behavior in electronic circuits and plasma physics to modeling
Science and Technology (IUST), Tehran, Iran, of energy storage devices, bio-materials, and biological tissues. He has
in 1993, and the M.Sc. and Ph.D. degrees in been a member of the IEEE Technical Committee on Nonlinear Circuits
electronics and communication engineering from and Systems, since 2000. He was a recipient of the Egyptian Government
Istanbul Technical University (ITU), Istanbul, First Class Medal for achievements in engineering sciences, in 2015, and
Turkey, in 1997 and 2001, respectively. He is cur- the UAE President Award (Khalifa Award), in 2020. He is an International
rently a Professor with the Department of Elec- Observer in the European Cooperation in Science and Technology (COST)
tronics and Communications Engineering, Dogus action on fractional-order system analysis synthesis and their importance
University, Istanbul. He has more than 130 publications in scientific for future design (CA15225) and an Expert with the United Nations Devel-
SCI-indexed journals. His published works have received more than opment Program (UNDP). He was on the Editorial Board of the IEEE
4500 citations and his H-index is 38 in Google Scholar. His research JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS and an
interests include current-mode circuits and analog signal processing. He is Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—
the Editor-in-Chief of the AEÜ-International Journal of Electronics and I: REGULAR PAPERS. He serves as the Editor-in-Chief for the International
Communications. Journal of Circuit Theory and Applications (Wiley) and an Associate Edi-
tor for the International Journal of Electronics and Telecommunications
(AEUE, Elsevier).

AHMED S. ELWAKIL (Senior Member, IEEE)

was born in Cairo, Egypt. He received the B.Sc.
and M.Sc. degrees in electronics and commu-
nications from Cairo University, Egypt, and the
Ph.D. degree in electrical and electronic engineer-
ing from the National University of Ireland, Uni- PANAGIOTIS BERTSIAS received the B.Sc.
versity College Dublin. He held visiting positions degree in physics and the M.Sc. and Ph.D. degrees
at Istanbul Technical University, Turkey; Queen’s in electronics from the University of Patras,
University, Belfast, U.K.; the Technical Univer- Greece, in 2016, 2018, and 2021, respectively.
sity of Denmark, Lyngby, Denmark; and the King He is currently a Postdoctoral Researcher work-
Abdullah University of Science and Technology, Saudi Arabia. He is cur- ing with the Analog Integrated Circuits Design
rently a Full Professor with the University of Sharjah, United Arab Emirates; Research Group, Electronics Laboratory, Depart-
also with the University of Calgary, AB, Canada; and also with the Nanoelec- ment of Physics, University of Patras, Greece.
tronics Integrated Systems Center (NISC) Research Center, Nile University, His main research interests include the design and
Cairo. He has authored or coauthored more than 350 publications in these applications of fractional-order circuits.
areas (current H-index 45). His research interests include circuit theory, non-

VOLUME 9, 2021 145987