Verilog Tips & Rules

Introduction I t d ti
Purpose of HDL: 1. 1 Describe the circuit in algorithmic level (like c) and in gate-level (e.g. And gate) 2. 2 Simulation 3. Synthesis 4. Words are better than pictures

The best way to describe a circuit?

If both inputs are 1, change both outputs. If one input is 1 change an output as follows: If the previous outputs are equal change the output with input 0; If the previous outputs are unequal change the output with input 1. If both inputs are 0, change nothing.

Lexicography L i h
Comments:
Two Types: yp
// Comment

/* These comments extend

over multiple lines. Good for commenting out code */

Character Set:
0123456789ABCD..YZabcd...yz_$ Cannot start with a number or $

Data Types D t T
Data Values:
0,1,x,z module sample (a,b,c,d); input a,b; output c,d; wire [7:0] b; reg c,d; integer k;

Wire
-

Synthesizes into wires Used in structural code

Reg g
-

May synthesize into latches, flip-flops or wires Used in procedural code

Integer
32-bit integer used as indexes

Input, Output, inout

Defines ports of a module (wire by default)

Data V l D t Values
Numbers:
Numbers are defined by number of bits
Value of 23: 5b10111 5d23 5h17

Parameters:
parameter n=4; wire [n-1:0] t, d;
`define Reset state = 0, state B =1, define Reset_state state_B 1, Run_state =2, finish_state = 3; if(state==`Run_state)

Constants:
wire [3:0] t d; t,d; assign t = 23; assign d= 4b0111;

Operators O t
Arithmetic:
*,+,-, /,%

Relational
<,<=,>,>=,==, !=

reg [3:0] a, b, c, d; i [7 0] wire[7:0] x,y,z; parameter n =4; c = a + b; ; d = a *n; If(x==y) d = 1; else d =0; d = a ~^ b; if ((x>=y) && (z)) a=1; else a = !x;

Bit-wise Operators

Not: ~ XOR: ^ And A d:& 5b11001 & 5b01101 ==> 5b01001 OR: | XNOR: ~^ or ^~

Logical Operators
Returns 1or 0, treats all nonzero as 1

! : Not && : AND || : OR

27 && -3 ==> 1

Operators O t
Reduction Operators: p
Unary operations returns single-bit values & : and | :or ~& : nand ~| : nor ^ : xor ~^ :xnor module sample (a, b, c, d); input [2:0] a b; a, output [2;0] c, d; wire z,y; assign z = ~| a; c = a * b; If(a==b) d = 1; else d =0; d = a ~^ b; if ((a>=b) && (z)) y=1; else y = !x; assign d << 2; //shift left twice assign {carry, d} = a + b; assign c = {2{carry},2{1b0}}; // c = {carry,carry,0,0} {carry carry 0 0} assign c= (inc==2)? a+1:a-1;

Shift Operators
Shift Left: << Shift right: >>

Concatenation Operator
{ } (concatenation) { n{item} } (n fold replication of an item)

Conditional Operator Implements if-then-else statement

(cond) ? (result if cond true) : (result if cond false)

Verilog Structure V il St t
All code are contained in modules Can invoke other modules Modules cannot be contained in another module d l

Verilog Structure (cont..) (cont )

module gate(Z,A,B,C); input A,B,C; output Z; assign Z = A|(B&C); Endmodule

module two_gates(Z2,A2,B2,C2) input A2,B2,C2; output Z2; gate gate_1(G2,A2,B2,C2); t t 1(G2 A2 B2 C2) gate gate_2(Z2,G2,A2,B2); endmodule

Structural V P St t l Vs Procedural d l
Structural textual d t t l description of i ti f circuit order does not matter Starts with assign statements Harder to code Need to work out logic
wire c, d; assign c =a & b; assign d = c |b;

Procedural Think lik Thi k like C code d Order of statements are important Starts with initial or always statement Easy to code Can use case if for case, if,
reg c, d; y @ (a ) g always@ ( or b or c) begin assign c =a & b; assign d = c |b; end

Structural V P St t l Vs Procedural d l
Procedural
reg [3:0] Q; wire [1:0] y; always@(y) begin Q=4b0000; case(y) begin 2b00: Q[0]=1; 2b01: Q[1]=1; 2b10: Q[2]=1; 2b11: Q[3]=1; Q[ ] ; endcase end

Structural
wire [3:0]Q; wire [1:0]y; assign Q[0]=(~y[1])&(~y[0]), Q[1]=(~y[1])&y[0], Q[2]=y[1]&(~y[0]), Q[3]=y[1]&y[0];

Q[0]

Q[1]

Q[2] y[ ] y[0] y[1]

Q[3]

Blocking Vs Non-Blocking
Blocking <variable> = <statement> i bl t t t Similar to C code The next assignment a s until the p ese e present waits u one is finished Used for combinational logic Non-blocking <variable> <= <statement> The inputs are stored once the th procedure i t i d is triggered d Statements are executed in parallel ll l Used for flip-flops, latches p p , and registers

Do not mix both assignments in one procedure

Blocking Vs Non-Blocking Bl ki V N Bl ki
Initial begin g #1 e=2; #1 b=1; b 1; #1 b<=0; e<=b; // grabbed the old b f=e; // used old e=2, did not wait e<=b

Behavior Modeling

If Statements St t t
Syntax if (expression) begin g ...statements... end else if (expression) ( p ) begin ...statements... end ...more else if blocks else begin ...statements... end

Case St t C Statements t
Syntax case (expression) case_choice1: begin ...statements... end case_choice2: begin ...statements... end ...more case choices blocks... more blocks default: begin ...statements... end d endcase

For l F loops
Syntax integer j; for (count= value1; count</<=/>/>= value2; count=count+/- step) t t+/ t ) begin ...statements... statements end for(j=0;j<=7;j=j+1) begin c[j] = a[j] + b[j]; end

Component Inference

Flip-Flops Fli Fl
always@(posedge clk) begin a<=b; a<=b&c; end

D Flip-Flop with Asynchronous Flip Flop Reset

always@(posedge clk or negedge rst) begin b i if (!rst) a<=0; else a<=b; end

D Flip-flop with Synchronous reset Flip flop and Enable

always@(posedge clk) begin if (rst) a<=0; else if (enable) a<=b; end d

Shift R i t Registers
reg[3:0] Q; always@(posedge clk or posedge rset ) begin if (rset) Q<=0; else begin Q <=Q << 1; Q[0]<=Q[3]; end

Multiplexers M lti l
Method 1 assign a = (select ? b : c); Method 2 always@(select or b or c) begin if(select) a=b; else a=c; end Method 2b case(select) ( l t) 1b1: a=b; 1b0: a=c; endcase

Counters C t
reg [7:0] count; wire enable; always@(posedge clk or negedge rst) begin if (rst) count<=0; else if (enable) count<=count+1; end

Avoiding Unwanted Latches

Latches are BAD

Rule R l #1
If the procedure has several paths paths, every path must evaluate all outputs
Method1: Set all outputs to some value at the start of the procedure. procedure Later on different values can overwrite those values. always @(... begin x=0;y=0;z=0; if (a) x=2; elseif (b) y=3; else z=4; End Method2: Be sure every branch of every if and case generate every output always @(... begin if (a) begin x=2; y=0; z=0; end elseif (b) begin x=0; y=3; z=0; end else begin x=0; y=0; z=4; end end

Rule R l #2
All inputs used in the procedure must appear in the trigger list
Right-hand side variables: Except variables both calculated and used in the procedure. always @(a or b or c or x or y) begin x=a; y=b; z=c; w=x+y; end Branch controlling variables: Be sure every branch of every if and case generate every output always @(a or b) begin if (a) begin x=2; y=0; z=0; end elseif (b) begin x=0; y=3; z=0; end else begin x=0; y=0; z=4; end end

Rule R l #3
All possible inputs used control statements must be covered End a case state e ts with t e de au t case whether d all statements t the default et e you need it or not. case(state) ... default: next_state = reset; endcase Do not forget the self loops in your state graph o r if(a|b&c) next_state=S1; elseif(c&d) next_state=S2; else next_state=reset;

Finite State Machines

Standard Form for a Verilog FSM St d d F f V il

// state flip-flops reg [2:0] state, nxt_st; // state definitions parameter reset=0,S1=1,S2=2,S3=3,..

// REGISTER DEFINITION always@(posedge clk) begin g state<=next_state; end // OUTPUT CALCULATIONS output= f(state, inputs)

// NEXT STATE CALCULATIONS always@(state or inputs or ...) begin next_state= ... end d

Example E l
module myFSM (clk, x, z) y ( , , ) input clk, x; output z; // state flip-flops reg [ ] state, nxt_st; g [2:0] , ; // state definition parameter S0=0,S1=1,S2=2,S3=3,S7=7 // REGISTER DEFINITION always @(posedge clk) begin state<=nxt_st; end // OUTPUTCALCULATIONS assign z = (state==S7); // NEXT STATE CALCULATIONS always @(state or x) begin case (state) S0: if(x) nxt_st=S1; nxt st=S1; else nxt_st=S0; S1: if(x) nxt_st=S3; else nxt_st=S2; S2: if(x) nxt_st=S0; nxt st=S0; else nxt_st=S7; S3: if(x) nxt_st=S2; else nxt_st=S7; S7: nxt_st=S0; nxt st=S0; default: nxt_st = S0; endcase end endmodule

Test Benches

System tasks S t t k
Used to generate input and output during simulation. Start with $ sign. Display Selected Variables:
$display (format_string,par_1,par_2,...); $monitor(format_string,par_1,par_2,...); Example: $display(Output z: %b, z); $display( Output %b

Writing to a File:
$fopen, $fdisplay, $fmonitor and $fwrite

Random number generator: $random (seed) Query current simulation time: $time

Test B T t Benches h
Overview 1. 1 Invoke the verilog under design 2. 2 Simulate input vectors
3. 1. 1 2.

Approach Initialize all inputs Set the clk signal Send test vectors Specify when to end the simulation.

3. Implement the system tasks to view the results

4.

Example E l
timescale1 ns /100 ps // ti timeunit =1ns; precision=1/10ns; it 1 i i 1/10 module my_fsm_tb; reg clk, rst, x; wire z; /**** DESIGN TO SIMULATE (my_fsm) INSTANTIATION ****/ myfsm dut1(clk, rst, x, z); / /****RESET AND CLOCK SECTION****/ RESET SECTION / Initial begin clk=0; rst=0; #1rst=1; /*The delay i #1 t 1 /*Th d l gives rst a posedge f t d for sure.*/ #200 rst=0; //Deactivate reset after two clock cycles +1ns*/ end always #50 lk l #50clk=~clk; /* 10MHz clock (50*1ns*2) lk 10MH l k (50*1 *2) with 50% duty-cycle */ /****SPECIFY THE INPUT WAVEFORM x ****/ Initial begin #1 x=0; #400 x=1;
$display(Output z: %b, z); p y( p , );

#100 x=0; @(posedge clk) x=1; #1000 $finish; //stop simulation //without this, it will not stop this end endmodule

0111 S Sequence D t t Detector