UNIT-3 INTERRUPTS IN 8085

 Overview of Interrupt:

Interrupts are the signals generated by the external devices to request the microprocessor to perform a
task. For transferring data between the peripheral and the microprocessor, interrupts are mainly used.

An interrupt is considered to be an emergency signal that may be serviced. The Microprocessor may
respond to it as soon as possible.

• What happens when MP is interrupted?

When the Microprocessor receives an interrupt signal, it suspends the currently executing program and
jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt. Each interrupt will most
probably have its own ISR.

If an interrupt occurs, it accepts the interrupt and sends the INTR’ signal to the peripheral. The
microprocessor executes an interrupt service routine (ISR) stored in memory. It returns to the main
program by RET instruction, after the ISR is executed. The interrupt process is shown in figure.

Interrupt process
Microprocessor & Interfacing techniques Unit 3 Notes

 Types of Interrupts:

There are six types of Interrupts in 8085.

1. Hardware interrupts
2. Software interrupts
3. Maskable interrupts
4. Non-Maskable interrupts
5. Vectored interrupts
6. Non-vectored interrupts

1. Hardware interrupts: These interrupts are given by the peripheral devices to the interrupt pin
(hardware) of the microprocessor. Hardware interrupts are also called external interrupts.
2. Software interrupts: These interrupts are internally generated within the microprocessor using
software instructions. Software interrupts are also called internal interrupts.
3. Maskable interrupts (Can be delayed or rejected): These external interrupts can be delayed or
rejected by the microprocessor.
4. Non-maskable interrupts (Cannot be delayed or rejected): These external
interrupts cannot be delayed or rejected by the microprocessor. Non-maskable
interrupts are used for handling emergency situations.
5. Vectored interrupts: When the address of the Interrupt Service Routine (ISR) is fixed within the
microprocessor itself, then the interrupt is called Vectored interrupt.
6. Non-vectored interrupts: When the address of the Interrupt Service Routine (ISR) is supplied by
the peripheral device, then the interrupt is called Non-vectored interrupt.

 8085 Hardware interrupts:

In 8085 microprocessor, there are 5 hardware interrupts as shown in figure.

1. TRAP
2. RST 5.5
3. RST 6.5
4. RST 7.5
5. INTR
Microprocessor & Interfacing techniques Unit 3 Notes

In additional to these hardware interrupts, 8085 microprocessor has eight software interrupts.

 8085 Software Interrupt:

 The software interrupts are program instructions. These instructions are inserted at desired locations in
a program. While running a program, if software interrupt instruction is encountered, then the processor
executes an interrupt service routine (ISR).
 When the instruction is executed, the processor executes an interrupt service routine stored in the vector
address of the software interrupt instruction. The software interrupts of 8085 are RST 0, RST1, RST 2,
RST 3, RST 4, RST 5, RST6 and RST 7.
 All software interrupts of 8085 is vectored interrupts. The software interrupts cannot be masked and
they cannot be disabled.

 Maskable Interrupts:
 Maskable interrupts are those interrupts which can be enabled or disabled. Enabling and disabling is
done by software instructions. The interrupts can be masked by moving an appropriate data to
accumulator and then executing SIM instruction. (SIM - Set Interrupt Mask). The status of maskable
interrupts can be read into accumulator by executing RIM instruction (RIM - Read Interrupt Mask).
List of Maskable Interrupts: RST 7.5, RST 6.5 ,RST 5.5 ,INTR

 Non-Maskable Interrupts:
 The interrupts which are always in enabled mode are called non maskable interrupts. These interrupts
can never be disabled by any software instruction. TRAP is a non-maskable interrupt.
Microprocessor & Interfacing techniques Unit 3 Notes

 Vectored Interrupts:
 The interrupts which have fixed memory location for transfer of control from normal execution.
List of vectored interrupts:
1. RST 7.5
2. RST 6.5
3. RST 5.5
4. TRAP
The addresses to which program control goes for vectored interrupts:
Name Vectored Address

RST 7.5 003C H (7.5 x 0008 H)

RST 6.5 0034 H (6.5 x 0008 H)

RST 5.5 002C H (5.5 x 0008 H)

TRAP 0024 H (4.5 x 0008 H)

 Non-Vectored Interrupts:
 The interrupts which don't have fixed memory location for transfer of control from normal execution
is called Non-Vectored Interrupts. The address of the memory location is sent along with the interrupt.
INTR is a non-vectored interrupt.

 Interrupt priority:
 The microprocessor can respond to only one interrupt at one time. When multiple (more than one)
interrupts occur simultaneously, the microprocessor will service the interrupts in their fixed priority
order. Interrupt having the highest priority level will be serviced first.
In 8085, TRAP interrupt has the highest priority and INTR has the lowest priority.

 TRAP
 This interrupt can be considered as a non-maskable interrupt. Any mask or interrupt enable cannot
affect this.
 It is a vectored interrupt. The interrupt vector address is 0024H.
 TRAP has the highest priority level.
Microprocessor & Interfacing techniques Unit 3 Notes

 We can say that TRAP interrupt is level and edge triggered. This means that till the
acknowledgement, the TRAP must go high and remain high.
 In emergency situations like sudden power failure, it executes an ISR and sends the data from main
memory to backup memory.
 RST 7.5
 The RST 7.5 can be considered as a maskable interrupt.
 It is a vectored interrupt. The interrupt vector address is 003CH.
 It has second highest priority.
 It is edge triggered. ie. Input attains at high and no need to retain the high state until it is recognized
and acknowledged.
 RST 6.5
 The RST 6.5 interrupt is a maskable interrupt.
 It is a vectored interrupt. The interrupt vector address is 0034H.
 It has the third highest priority.
 It is level triggered. ie. Input goes to high and stays high until it is recognized and acknowledged.
 RST 5.5
 The RST 5.5 interrupt is a maskable interrupt.
 It is a vectored interrupt. The interrupt vector address is 002CH.
 It has the fourth highest priority.
 It is level triggered. ie. Input goes to high and stays high until it is recognized and acknowledged.
 INTR
 • INTR is a maskable interrupt.
 It is a non- vectored interrupt.
 It has the lowest priority.
 It is a level triggered. ie. Input goes to high and it is necessary to maintain high state until it is
recognized and acknowledged.

 Instructions for Interrupts handling in 8085 microprocessor:

There are four instructions available for interrupts handling. They are,
1. DI (Disable Interrupt)
2. EI (Enable Interrupt)
3. SIM (Set Interrupt Mask)
4. RIM (Read Interrupt Mask)
Microprocessor & Interfacing techniques Unit 3 Notes

 DI (Disable Interrupt)
This instruction resets the Interrupt Enable Flip-flop inside the microprocessor. All the interrupts
except the TRAP are disabled.
 EI (Enable Interrupt)
Inside the microprocessor, this instruction sets the Interrupt Enable Flip-flop also all the interrupts
are enabled.
 SIM (Set Interrupt Mask)
This instruction is used to selectively mask (disable) and unmask (enable) RST 7.5, RST 6.5 and RST
5.5 interrupts. For serial data output, we can use this instruction. The SIM the instruction uses the
accumulator contents for masking and unmasking the interrupts.
 RIM (Read Interrupt Mask)
This instruction is used to read the status of RST 7.5, RST 6.5 and RST 5.5 interrupts like pending
and enable / disable details. This instruction is also used for reading the serial data. When the RIM
instruction is given, the microprocessor loads the details into the accumulator.

 Process of INTR interrupt:

1. With the use of the EI instruction, the interrupt process should be enabled.
2. Whenever an instruction is executed, the 8085 checks for an interrupt signal.
3. If INTR is high, the microprocessor completes current instruction, disables the interrupt and sends
INTR’ signal to the peripheral device.
4. INTR' allows the peripheral device to send an RST instruction through data bus.
5. Upon receiving the INTR’ signal, the microprocessor saves the memory location of the next
instruction on the stack and the program is transferred to ‘call’ location (ISR Call) specified by the
RST instruction.
6. Microprocessor executes the ISR.
7. Within the program, In order to enable the further interrupt, ISR must include the ‘EI’ instruction.
8. The RET instruction at the end of the ISR retrieves the return address from the stack and the program
is transferred back to main program which was interrupted.

 Interrupt Vector And The Vector Table:

An interrupt vector is a pointer to where the ISR is stored in memory. All interrupts (vectored or
otherwise) are mapped onto a memory area called the Interrupt Vector Table (IVT). The IVT is usually
located in memory page 00 (0000H - 00FFH). The purpose of the IVT is to hold the vectors that redirect
the microprocessor to the right place when an interrupt arrives.
Example: Let , a device interrupts the Microprocessor using the RST 7.5 interrupt line.
Microprocessor & Interfacing techniques Unit 3 Notes

Because the RST 7.5 interrupt is vectored, Microprocessor knows , in which memory location it has to go
using a call instruction to get the ISR address.

RST7.5 is known as Call 003Ch to Microprocessor. Microprocessor goes to 003C location and will get a
JMP instruction to the actual ISR address. The Microprocessor will then, jump to the ISR location.

 The 8085 Non-Vectored Interrupt Process:

1. The interrupt process should be enabled using the EI instruction.
2. The 8085 checks for an interrupt during the execution of every instruction.
3. If INTR is high, MP completes current instruction, disables the interrupt and sends INTA
(Interrupt acknowledge)signal to the device that interrupted
4. INTA allows the I/O device to send a RST instruction through data bus.
5. Upon receiving the INTA signal, MP saves the memory location of the next instruction on the stack
and the program is transferred to ‘call’ location (ISR Call) specified by the RST instruction
6. Microprocessor Performs the ISR.
7. ISR must include the ‘EI’ instruction to enablethe further interrupt within the program.
8. RET instruction at the end of the ISR allows the MP to retrieve the return address from the stack
and the program is transferred back to where the program was interrupted.

 Summary of 8085 interrupts:

Interrupt Vector address Priority Type
Hardware interrupt
1(highest Vectored interrupt
TRAP 0024H priority) Non-maskable interrupt
Hardware interrupt
Vectored interrupt
RST 7.5 003CH 2 Maskable interrupt
Hardware interrupt
Vectored interrupt
RST 6.5 0034H 3 Maskable interrupt
Hardware interrupt
Vectored interrupt
RST 5.5 002CH 4 Maskable interrupt
Hardware interrupt
5(lowest Non - Vectored interrupt
INTR - priority) Maskable interrupt
Microprocessor & Interfacing techniques Unit 3 Notes

RST 0 – 0000H
RST 1 – 0008H
RST 2 – 0010H
RST 3 – 0018H
RST 4 – 0020H
RST 5 - 0028H Software interrupt
RST 6 – 0030H Vectored interrupt
RST instruction RST 7 – 0038H - Maskable interrupt