Microprocessor - 8085 Architecture

8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit

microprocessor designed by Intel in 1977 using NMOS technology.
It has the following configuration −

 8-bit data bus

 16-bit address bus, which can address upto 64KB
 A 16-bit program counter
 A 16-bit stack pointer
 Six 8-bit registers arranged in pairs: BC, DE, HL
 Requires +5V supply to operate at 3.2 MHZ single phase clock
It is used in washing machines, microwave ovens, mobile phones, etc.

8085 Microprocessor – Functional Units

8085 consists of the following functional units −

Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE
operations. It is connected to internal data bus & ALU.

Arithmetic and logic unit

As the name suggests, it performs arithmetic and logical operations like Addition,
Subtraction, AND, OR, etc. on 8-bit data.

General purpose register

There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L.
Each register can hold 8-bit data.
These registers can work in pair to hold 16-bit data and their pairing combination
is like B-C, D-E & H-L.

Program counter
It is a 16-bit register used to store the memory address location of the next
instruction to be executed. Microprocessor increments the program whenever an
instruction is being executed, so that the program counter points to the memory
address of the next instruction that is going to be executed.

Stack pointer
It is also a 16-bit register works like stack, which is always
incremented/decremented by 2 during push & pop operations.

Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical
operations.
 Flag register
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1
depending upon the result stored in the accumulator.
These are the set of 5 flip-flops −

 Sign (S)
 Zero (Z)
 Auxiliary Carry (AC)
 Parity (P)
 Carry (C)
Its bit position is shown in the following table −

D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY

Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored
in the Instruction register. Instruction decoder decodes the information present in
the Instruction register.

Timing and control unit

It provides timing and control signal to the microprocessor to perform operations.
Following are the timing and control signals, which control external and internal
circuits −

 Control Signals: READY, RD’, WR’, ALE

 Status Signals: S0, S1, IO/M’
 DMA Signals: HOLD, HLDA
 RESET Signals: RESET IN, RESET OUT

Interrupt control
As the name suggests it controls the interrupts during a process. When a
microprocessor is executing a main program and whenever an interrupt occurs,
the microprocessor shifts the control from the main program to process the
incoming request. After the request is completed, the control goes back to the
main program.
There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST
5.5, TRAP.

Serial Input/output control

It controls the serial data communication by using these two instructions: SID
(Serial input data) and SOD (Serial output data).
 Address buffer and address
address-data buffer
The content stored in the stack pointer and program counter is loaded into the
address buffer and address--data
data buffer to communicate with the CPU. The memory
and I/O chips are connected to these buses; the CPU can exchange the desired
data with the memory and I/O chips.

Address bus and data bus

Data bus carries the data to be stored
stored.. It is bidirectional, whereas address bus
carries the location to where it should be stored and it is unidirectional. It is used
to transfer the data & Address I/O devices.

8085 Architecture
We have tried to depict the architecture of 8085 with this following image −
 Microprocessor - 8085 Pin Configuration

The following image depicts the pin diagram of 8085 Microprocessor −

The pins of a 8085 microprocessor can be classified into seven groups −

Address bus
A15-A8, it carries the most significant 8
8-bits of memory/IO address.

Data bus
AD7-AD0,
AD0, it carries the least significant 8
8-bit address and data bus.

Control and status signals

These signals are used to identify the nature of operation. There are 3 control
signal and 3 status signals.
Three control signals are RD, WR & ALE.
 RD − This signal indicates that the selected IO or memory device is to be
read and is ready for accepting data available on the data bus.
  WR − This signal indicates that the data on the data bus is to be written into
a selected memory or IO location.
 ALE − It is a positive going pulse generated when a new operation is started
by the microprocessor. When the pulse goes high, it indicates address.
When the pulse goes down it indicates data.
Three status signals are IO/M, S0 & S1.

IO/M
This signal is used to differentiate between IO and Memory operations, i.e. when it
is high indicates IO operation and when it is low then it indicates memory
operation.

S1 & S0
These signals are used to identify the type of current operation.

Power supply
There are 2 power supply signals − VCC & VSS. VCC indicates +5v power supply
and VSS indicates ground signal.

Clock signals
There are 3 clock signals, i.e. X1, X2, CLK OUT.
 X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used
to set frequency of the internal clock generator. This frequency is internally
divided by 2.
 CLK OUT − This signal is used as the system clock for devices connected
with the microprocessor.

Interrupts & externally initiated signals

Interrupts are the signals generated by external devices to request the
microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST
7.5, RST 6.5, RST 5.5, and INTR. We will discuss interrupts in detail in interrupts
section.
 INTA − It is an interrupt acknowledgment signal.
 RESET IN − This signal is used to reset the microprocessor by setting the
program counter to zero.
 RESET OUT − This signal is used to reset all the connected devices when
the microprocessor is reset.
 READY − This signal indicates that the device is ready to send or receive
data. If READY is low, then the CPU has to wait for READY to go high.
 HOLD − This signal indicates that another master is requesting the use of
the address and data buses.
  HLDA (HOLD Acknowledge) − It indicates that the CPU has received the
HOLD request and it will relinquish the bus in the next clock cycle. HLDA is
set to low after the HOLD signal is removed.

Serial I/O signals

There are 2 serial signals, i.e. SID and SOD and these signals are used for serial
communication.
 SOD (Serial output data line) − The output SOD is set/reset as specified by
the SIM instruction.
 SID (Serial input data line) − The data on this line is loaded into
accumulator whenever a RIM instruction is executed.

8085 Addressing Modes & Interrupts

Now let us discuss the addressing modes in 8085 Microprocessor.

Addressing Modes in 8085

These are the instructions used to transfer the data from one register to another
register, from the memory to the register, and from the register to the memory
without any alteration in the content. Addressing modes in 8085 is classified into 5
groups −

Immediate addressing mode

In this mode, the 8/16-bit data is specified in the instruction itself as one of its
operand. For example: MVI K, 20F: means 20F is copied into register K.

Register addressing mode

In this mode, the data is copied from one register to another. For example: MOV
K, B: means data in register B is copied to register K.

Direct addressing mode

In this mode, the data is directly copied from the given address to the
register. For example: LDB 5000K: means the data at address 5000K is copied to
register B.

Indirect addressing mode

In this mode, the data is transferred from one register to another by using the
address pointed by the register. For example: MOV K, B: means data is
transferred from the memory address pointed by the register to the register K.

Implied addressing mode

This mode doesn’t require any operand; the data is specified by the opcode
itself. For example: CMP.
 Interrupts in 8085
Interrupts are the signals generated by the external devices to request the
microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST
7.5, RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter −
 Vector interrupt − In this type of interrupt, the interrupt address is known
to the processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
 Non-Vector interrupt − In this type of interrupt, the interrupt address is
not known to the processor so, the interrupt address needs to be sent
externally by the device to perform interrupts. For example: INTR.
 Maskable interrupt − In this type of interrupt, we can disable the interrupt
by writing some instructions into the program. For example: RST7.5,
RST6.5, RST5.5.
 Non-Maskable interrupt − In this type of interrupt, we cannot disable the
interrupt by writing some instructions into the program. For
example: TRAP.
 Software interrupt − In this type of interrupt, the programmer has to add
the instructions into the program to execute the interrupt. There are 8
software interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5,
RST6, and RST7.
 Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware
interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA.
Note − NTA is not an interrupt, it is used by the microprocessor for sending
acknowledgement. TRAP has the highest priority, then RST7.5 and so on.

Interrupt Service Routine (ISR)

A small program or a routine that when executed, services the corresponding
interrupting source is called an ISR.

TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts.
Bydefault, it is enabled until it gets acknowledged. In case of failure, it executes as
ISR and sends the data to backup memory. This interrupt transfers the control to
the location 0024H.

RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register
into the stack and branches to 003CH address.
 RST 6.5
It is a maskable interrupt, having the third highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register
into the stack and branches to 0034H address.

RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor saves the
content of the PC register into the stack and branches to 002CH address.

INTR
It is a maskable interrupt, having the lowest priority among all interrupts. It can
be disabled by resetting the microprocessor.
When INTR signal goes high, the following events can occur −
 The microprocessor checks the status of INTR signal during the execution of
each instruction.
 When the INTR signal is high, then the microprocessor completes its current
instruction and sends active low interrupt acknowledge signal.
 When instructions are received, then the microprocessor saves the address
of the next instruction on stack and executes the received instruction.

Microprocessor - 8085 Instruction Sets

Let us take a look at the programming of 8085 Microprocessor.
Instruction sets are instruction codes to perform some task. It is classified into five
categories.

S.No. Instruction & Description

Control Instructions
1 Following is the table showing the list of Control instructions
with their meanings.

Logical Instructions
2 Following is the table showing the list of Logical instructions
with their meanings.

Branching Instructions
3 Following is the table showing the list of Branching instructions
with their meanings.

Arithmetic Instructions
4
Following is the table showing the list of Arithmetic instructions
 with their meanings.

Data Transfer Instructions

5 Following is the table showing the list of Data-transfer
instructions with their meanings.

Microprocessor - 8085 Control Instructions

Opcode Operand Meaning Explanation

No No operation is performed, i.e., the instruction is

NOP None
operation fetched and decoded.

Halt and The CPU finishes executing the current instruction

enter and stops further execution. An interrupt or reset is
HLT None
wait necessary to exit from the halt state.
state

Disable The interrupt enable flip-flop is reset and all the

DI None
interrupts interrupts are disabled except TRAP.

Enable The interrupt enable flip-flop is set and all the

EI None
interrupts interrupts are enabled.

Read This instruction is used to read the status of

RIM None interrupt interrupts 7.5, 6.5, 5.5 and read serial data input
mask bit.

Set
This instruction is used to implement the interrupts
SIM None interrupt
7.5, 6.5, 5.5, and serial data output.
mask

Microprocessor - 8085 Logical Instructions

Opcode Operand Meaning Explanation

Compare the
R The contents of the operand (register or memory)
CMP register or memory
are M compared with the contents of the
M with the
accumulator.
accumulator
Compare
The second byte data is compared with the
CPI 8-bit data immediate with the
contents of the accumulator.
accumulator
Logical AND
R The contents of the accumulator are logically AND
register or memory
ANA with M the contents of the register or memory,
M with the
and the result is placed in the accumulator.
accumulator
Logical AND The contents of the accumulator are logically AND
ANI 8-bit data
immediate with the with the 8-bit data and the result is placed in the
 accumulator accumulator.
Exclusive OR
R The contents of the accumulator are Exclusive OR
register or memory
XRA with M the contents of the register or memory,
M with the
and the result is placed in the accumulator.
accumulator
Exclusive OR The contents of the accumulator are Exclusive OR
XRI 8-bit data immediate with the with the 8-bit data and the result is placed in the
accumulator accumulator.

R Logical OR register The contents of the accumulator are logically OR

ORA or memory with with M the contents of the register or memory,
M the accumulator and result is placed in the accumulator.

Logical OR The contents of the accumulator are logically OR

ORI 8-bit data immediate with the with the 8-bit data and the result is placed in the
accumulator accumulator.
Each binary bit of the accumulator is rotated left
Rotate the by one position. Bit D7 is placed in the position of
RLC None
accumulator left D0 as well as in the Carry flag. CY is modified
according to bit D7.
Each binary bit of the accumulator is rotated right
Rotate the by one position. Bit D0 is placed in the position of
RRC None
accumulator right D7 as well as in the Carry flag. CY is modified
according to bit D0.
Each binary bit of the accumulator is rotated left
Rotate the by one position through the Carry flag. Bit D7 is
RAL None accumulator left placed in the Carry flag, and the Carry flag is
through carry placed in the least significant position D0. CY is
modified according to bit D7.
Each binary bit of the accumulator is rotated right
Rotate the by one position through the Carry flag. Bit D0 is
RAR None accumulator right placed in the Carry flag, and the Carry flag is
through carry placed in the most significant position D7. CY is
modified according to bit D0.
Complement The contents of the accumulator are
CMA None
accumulator complemented. No flags are affected.
Complement carry The Carry flag is complemented. No other flags
CMC None
are affected.
STC None Set Carry Set Carry

Microprocessor - 8085 Branching Instructions

Opcode Operand Meaning Explanation

The program sequence is

16-bit Jump
JMP transferred to the memory address
address unconditionally
given in the operand.

Opcode Description Flag

The program sequence is
Status
16-bit Jump transferred to the memory address
address conditionally given in the operand based on the
Jump on
JC CY=1 specified flag of the PSW.
Carry
 Jump on
JNC CY=0
no Carry

Jump on
JP S=0
positive

Jump on
JM S=1
minus

Jump on
JZ Z=1
zero

Jump on
JNZ Z=0
no zero

Jump on
JPE parity P=1
even

Jump on
JPO P=0
parity odd

Opcode Description Flag

Status

Call on
CC CY=1
Carry

Call on no
CNC CY=0
Carry

Call on
CP S=0
positive
The program sequence is
transferred to the memory address
Call on
CM S=1 16-bit Unconditional given in the operand. Before
minus
address subroutine call transferring, the address of the next
instruction after CALL is pushed
Call on onto the stack.
CZ Z=1
zero

Call on no
CNZ Z=0
zero

Call on
CPE parity P=1
even

Call on
CPO P=0
parity odd

Return from The program sequence is

RET None subroutine transferred from the subroutine to
unconditionally the calling program.
Opcode Description Flag
Status

Return on
RC CY=1
Carry

Return on
RNC CY=0
no Carry

Return on
RP S=0
positive
The program sequence is
transferred from the subroutine to
Return on Return from
RM S=1 the calling program based on the
minus None subroutine
specified flag of the PSW and the
conditionally
program execution begins at the
Return on new address.
RZ Z=1
zero

Return on
RNZ Z=0
no zero

Return on
RPE parity P=1
even

Return on
RPO P=0
parity odd

The contents of registers H & L are

Load the
copied into the program counter.
program
PCHL None The contents of H are placed as the
counter with
high-order byte and the contents of
HL contents
L as the loworder byte.

The RST instruction is used as

software instructions in a program
to transfer the program execution to
one of the following eight locations.

Instruction Restart
Address

RST 0 0000H

RST 0-7 Restart RST 1 0008H

RST 2 0010H

RST 3 0018H

RST 4 0020H

RST 5 0028H

RST 6 0030H
 RST 7 0038H

The 8085 has additionally 4

interrupts, which can generate RST
instructions internally and doesn’t
require any external hardware.
Following are those instructions and
their Restart addresses −

Interrupt Restart
Address

TRAP 0024H

RST 5.5 002CH

RST 6.5 0034H

RST 7.5 003CH

8085 Arithmetic Instructions

Opcode Operand Meaning Explanation

Add register The contents of the register or memory are

R or memory, added to the contents of the accumulator and
ADD the result is stored in the accumulator.
M to the
accumulator Example − ADD K.

The contents of the register or memory & M

Add register the Carry flag are added to the contents of
R to the
ADC the accumulator and the result is stored in
M accumulator the accumulator.
with carry
Example − ADC K

Add the The 8-bit data is added to the contents of the

immediate accumulator and the result is stored in the
ADI 8-bit data accumulator.
to the
accumulator Example − ADI 55K

Add the The 8-bit data and the Carry flag are added
immediate to the contents of the accumulator and the
ACI 8-bit data to the result is stored in the accumulator.
accumulator
with carry Example − ACI 55K

Reg. pair, 16bit Load the The instruction stores 16-bit data into the
LXI
data register pair register pair designated in the operand.
 immediate Example − LXI K, 3025M

Add the The 16-bit data of the specified register pair

register pair are added to the contents of the HL register.
DAD Reg. pair
to H and L
registers Example − DAD K

Subtract The contents of the register or the memory

the register are subtracted from the contents of the
R or the accumulator, and the result is stored in the
SUB
M memory accumulator.
from the
accumulator Example − SUB K

Subtract The contents of the register or the memory &

the source M the Borrow flag are subtracted from the
R
SBB and borrow contents of the accumulator and the result is
M from the placed in the accumulator.
accumulator Example − SBB K

Subtract The 8-bit data is subtracted from the contents

the of the accumulator & the result is stored in
SUI 8-bit data immediate the accumulator.
from the
accumulator Example − SUI 55K

The contents of register H are exchanged with

Exchange H the contents of register D, and the contents
XCHG None and L with of register L are exchanged with the contents
D and E of register E.
Example − XCHG

Increment The contents of the designated register or the

R the register memory are incremented by 1 and their
INR or the result is stored at the same place.
M memory by
Example − INR K
1

The contents of the designated register pair

Increment are incremented by 1 and their result is
INX R register pair stored at the same place.
by 1
Example − INX K

R Decrement The contents of the designated register or

DCR the register memory are decremented by 1 and their
M result is stored at the same place.
or the
 memory by Example − DCR K
1

The contents of the designated register pair

Decrement are decremented by 1 and their result is
DCX R the register stored at the same place.
pair by 1
Example − DCX K

The contents of the accumulator are changed

from a binary value to two 4-bit BCD digits.
If the value of the low-order 4-bits in the
accumulator is greater than 9 or if AC flag is
Decimal set, the instruction adds 6 to the low-order
DAA None adjust four bits.
accumulator If the value of the high-order 4-bits in the
accumulator is greater than 9 or if the Carry
flag is set, the instruction adds 6 to the high-
order four bits.
Example − DAA

8085 Data-transfer Instructions

Opcode Operand Meaning Explanation

Rd, Sc Copy from the This instruction copies the contents of

source (Sc) to the source register into the destination
MOV M, Sc
the register without any alteration.
Dt, M destination(Dt) Example − MOV K, L

Move The 8-bit data is stored in the

Rd, data
MVI immediate 8- destination register or memory.
M, data bit Example − MVI K, 55L

The contents of a memory location,

Load the specified by a 16-bit address in the
LDA 16-bit address operand, are copied to the accumulator.
accumulator
Example − LDA 2034K

The contents of the designated register

Load the
pair point to a memory location. This
LDAX B/D Reg. pair accumulator
instruction copies the contents of that
indirect
memory location into the accumulator.
 Example − LDAX K

The instruction loads 16-bit data in the

Load the register pair designated in the register or
Reg. pair, 16-bit
LXI register pair the memory.
data
immediate
Example − LXI K, 3225L

The instruction copies the contents of

the memory location pointed out by the
Load H and L address into register L and copies the
LHLD 16-bit address contents of the next memory location
registers direct
into register H.
Example − LHLD 3225K

The contents of the accumulator are

copied into the memory location
specified by the operand.
This is a 3-byte instruction, the second
STA 16-bit address 16-bit address
byte specifies the low-order address and
the third byte specifies the high-order
address.
Example − STA 325K

The contents of the accumulator are

Store the copied into the memory location
STAX 16-bit address accumulator specified by the contents of the operand.
indirect
Example − STAX K

The contents of register L are stored in

the memory location specified by the 16-
bit address in the operand and the
contents of H register are stored into the
next memory location by incrementing
Store H and L the operand.
SHLD 16-bit address
registers direct
This is a 3-byte instruction, the second
byte specifies the low-order address and
the third byte specifies the high-order
address.
Example − SHLD 3225K

Exchange H The contents of register H are

XCHG None and L with D exchanged with the contents of register
and E D, and the contents of register L are
exchanged with the contents of register
 E.
Example − XCHG

The instruction loads the contents of the

H and L registers into the stack pointer
Copy H and L register. The contents of the H register
registers to provide the high-order address and the
SPHL None
the stack contents of the L register provide the
pointer low-order address.
Example − SPHL

The contents of the L register are

exchanged with the stack location
pointed out by the contents of the stack
Exchange H pointer register.
XTHL None and L with top
The contents of the H register are
of stack
exchanged with the next stack location
(SP+1).
Example − XTHL

The contents of the register pair

designated in the operand are copied
onto the stack in the following sequence.
The stack pointer register is
decremented and the contents of the
Push the high order register (B, D, H, A) are
PUSH Reg. pair register pair copied into that location.
onto the stack
The stack pointer register is
decremented again and the contents of
the low-order register (C, E, L, flags) are
copied to that location.
Example − PUSH K

The contents of the memory location

pointed out by the stack pointer register
are copied to the low-order register (C,
E, L, status flags) of the operand.

Pop off stack The stack pointer is incremented by 1

POP Reg. pair to the register and the contents of that memory
pair location are copied to the high-order
register (B, D, H, A) of the operand.
The stack pointer register is again
incremented by 1.
Example − POPK
 Output the The contents of the accumulator are
data from the copied into the I/O port specified by the
OUT 8-bit port address accumulator to operand.
a port with
8bit address Example − OUT K9L

Input data to The contents of the input port

accumulator designated in the operand are read and
IN 8-bit port address from a port loaded into the accumulator.
with 8-bit
Example − IN5KL
address

8085 – sample Programs

Now, let us take a look at some program demonstrations using the above
instructions −

Adding Two 8-bit Numbers

Write a program to add data at 3005H & 3006H memory location and store the
result at 3007H memory location.
Problem demo −
(3005H) = 14H
(3006H) = 89H
Result −
14H + 89H = 9DH
The program code can be written like this −
LXI H 3005H : "HL points 3005H"
MOV A, M : "Getting first operand"
INX H : "HL points 3006H"
ADD M : "Add second operand"
INX H : "HL points 3007H"
MOV M, A : "Store result at 3007H"
HLT : "Exit program"

Exchanging the Memory Locations

Write a program to exchange the data at 5000M& 6000M memory location.
LDA 5000M : "Getting the contents at5000M location into accumulator"
MOV B, A : "Save the contents into B register"
LDA 6000M : "Getting the contents at 6000M location into accumulator"
STA 5000M : "Store the contents of accumulator at address 5000M"
MOV A, B : "Get the saved contents back into A register"
STA 6000M : "Store the contents of accumulator at address 6000M"

Arrange Numbers in an Ascending Order

Write a program to arrange first 10 numbers from memory address 3000H in an
ascending order.
MVI B, 09 :"Initialize counter"
START :"LXI H, 3000H: Initialize memory pointer"
MVI C, 09H :"Initialize counter 2"
BACK: MOV A, M :"Get the number"
INX H :"Increment memory pointer"
CMP M :"Compare number with next number"
JC SKIP :"If less, don’t interchange"
JZ SKIP :"If equal, don’t interchange"
MOV D, M
MOV M, A
DCX H
MOV M, D
INX H :"Interchange two numbers"
SKIP:DCR C :"Decrement counter 2"
JNZ BACK :"If not zero, repeat"
DCR B :"Decrement counter 1"
JNZ START
HLT :"Terminate program execution"

8085 Addressing Modes & Interrupts

Addressing Modes in 8085

These are the instructions used to transfer the data from one register to another
register, from the memory to the register, and from the register to the memory
without any alteration in the content. Addressing modes in 8085 is classified into 5
groups −

Immediate addressing mode

In this mode, the 8/16-bit data is specified in the instruction itself as one of its
operand. For example: MVI K, 20F: means 20F is copied into register K.

Register addressing mode

In this mode, the data is copied from one register to another. For example: MOV
K, B: means data in register B is copied to register K.
 Direct addressing mode
In this mode, the data is directly copied from the given address to the
register. For example: LDB 5000K: means the data at address 5000K is copied to
register B.

Indirect addressing mode

In this mode, the data is transferred from one register to another by using the
address pointed by the register. For example: MOV K, B: means data is
transferred from the memory address pointed by the register to the register K.

Implied addressing mode

This mode doesn’t require any operand; the data is specified by the opcode
itself. For example: CMP.

Interrupts in 8085
Interrupts are the signals generated by the external devices to request the
microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST
7.5, RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter −
 Vector interrupt − In this type of interrupt, the interrupt address is known
to the processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
 Non-Vector interrupt − In this type of interrupt, the interrupt address is
not known to the processor so, the interrupt address needs to be sent
externally by the device to perform interrupts. For example: INTR.
 Maskable interrupt − In this type of interrupt, we can disable the interrupt
by writing some instructions into the program. For example: RST7.5,
RST6.5, RST5.5.
 Non-Maskable interrupt − In this type of interrupt, we cannot disable the
interrupt by writing some instructions into the program. For
example: TRAP.
 Software interrupt − In this type of interrupt, the programmer has to add
the instructions into the program to execute the interrupt. There are 8
software interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5,
RST6, and RST7.
 Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware
interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA.

Interrupt Service Routine (ISR)

A small program or a routine that when executed, services the corresponding
interrupting source is called an ISR.
 TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts.
Bydefault, it is enabled until it gets acknowledged. In case of failure, it executes as
ISR and sends the data to backup memory. This interrupt transfers the control to
the location 0024H.

RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register
into the stack and branches to 003CH address.

RST 6.5
It is a maskable interrupt, having the third highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register
into the stack and branches to 0034H address.

RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor saves the
content of the PC register into the stack and branches to 002CH address.

INTR
It is a maskable interrupt, having the lowest priority among all interrupts. It can
be disabled by resetting the microprocessor.
When INTR signal goes high, the following events can occur −
 The microprocessor checks the status of INTR signal during the execution of
each instruction.
 When the INTR signal is high, then the microprocessor completes its current
instruction and sends active low interrupt acknowledge signal.
 When instructions are received, then the microprocessor saves the address
of the next instruction on stack and executes the received instruction.