3.

A source program is usually in

Computer a) Assembly language

b) Machine level language
Architecture c) High-level language
d) Natural language

Answer: c
Explanation: The program written and
before being compiled or assembled is
called as a source program.
4. Which memory device is generally
made of semiconductors?
a) RAM
b) Hard-disk
UNIT I BASIC STRUCTURE c) Floppy disk
d) Cd disk
OF A COMPUTER SYSTEM
Answer: a
1. The format is usually used to Explanation: Memory devices are
store data. usually made of semiconductors for
a) BCD faster manipulation of the contents.
b) Decimal
c) Hexadecimal 5. The small extremely fast, RAM’s are
d) Octal called as
a) Cache
Answer: a b) Heaps
Explanation: The data usually used by c) Accumulators
computers have to be stored and d) Stacks
represented in a particular format for
ease of use. Answer: a
Explanation: These small and fast
2. The 8-bit encoding format used to memory devices are compared to RAM
store data in a computer is because they optimize the performance
a) ASCII of the system and they only keep files
b) EBCDIC which are required by the current
c) ANCI process in them
d) USCII
6. The ALU makes use of to
Answer: b store the intermediate results.
Explanation: The data to be stored in a) Accumulators
the computers have to be encoded in a b) Registers
particular way so as to provide secure c) Heap
processing of the data. d) Stack
Answer: a a) Single bus
Explanation: The ALU is the b) Multiple bus
computational center of the CPU. It c) Star bus
performs all mathematical and logical d) Rambus
operations. In order to perform better, it
uses some internal memory spaces to Answer: a
store immediate results. Explanation: BUS is a bunch of wires
which carry address, control signals and
7. The control unit controls other units data. It is used to connect various
by generating components of the computer.
a) Control signals
b) Timing signals 11. The I/O interface required to
c) Transfer signals connect the I/O device to the bus
d) Command Signals consists of
a) Address decoder and registers
Answer: b b) Control circuits
Explanation: This unit is used to control c) Address decoder, registers and Control
and coordinate between the various circuits
parts and components of the CPU. d) Only Control circuits

8. are numbers and encoded Answer: c

characters, generally used as operands. Explanation: The I/O devices are
a) Input connected to the CPU via BUS and to
b) Data interact with the BUS they have an
c) Information interface.
d) Stored Values
12. To reduce the memory access time
Answer: b we generally make use of
Explanation: None. a) Heaps
b) Higher capacity RAM’s
9. The Input devices can send c) SDRAM’s
information to the processor. d) Cache’s
a) When the SIN status flag is set
b) When the data arrives regardless of Answer: d
the SIN flag Explanation: The time required to
c) Neither of the cases access a part of the memory for data
d) Either of the cases retrieval.

Answer: a 13. is generally used to increase

Explanation: The input devices use the apparent size of physical memory.
buffers to store the data received and a) Secondary memory
when the buffer has some data it sends b) Virtual memory
it to the processor. c) Hard-disk
d) Disks
10. bus structure is usually used
to connect I/O devices.
Answer: b LOCA
Explanation: Virtual memory is like an c) Adds the values of both LOCA and R0
extension to the existing memory. and stores it in R0
d) Adds the value of LOCA with a value
14. MFC stands for in accumulator and stores it in R0
a) Memory Format Caches
b) Memory Function Complete Answer: c
c) Memory Find Command Explanation: None.
d) Mass Format Command
3. Which registers can interact with the
Answer: b secondary storage?
Explanation: This is a system command a) MAR
enabled when a memory function is b) PC
completed by a process. c) IR
d) R0
15. The time delay between two
successive initiations of memory Answer: a
operation Explanation: MAR can interact with
a) Memory access time secondary storage in order to fetch data
b) Memory search time from it.
c) Memory cycle time
d) Instruction delay 4. During the execution of a program
which gets initialized first?
Answer: c a) MDR
Explanation: The time is taken to finish b) IR
one task and to start another. c) PC
d) MAR

1. The decoded instruction is stored in Answer: c

Explanation: For the execution of a
a) IR process first the instruction is placed in
b) PC the PC.
c) Registers
d) MDR 5. Which of the register/s of the
processor is/are connected to Memory
Answer: a Bus?
Explanation: The instruction after a) PC
obtained from the PC, is decoded and b) MAR
operands are fetched and stored in the c) IR
IR. d) Both PC and MAR

2. The instruction -> Add LOCA, R0 does Answer: b

Explanation: MAR is connected to the
a) Adds the value of LOCA to R0 and memory BUS in order to access the
stores in the temp register memory.
b) Adds the value of R0 to the address of
6. ISP stands for processing part of the CPU are
a) Instruction Set Processor collectively called as a data path.
b) Information Standard Processing
c) Interchange Standard Protocol 10. is used to store data in
d) Interrupt Service Procedure registers.
a) D flip flop
Answer: a b) JK flip flop
Explanation: None. c) RS flip flop
d) None of the mentioned
7. The internal components of the
processor are connected by Answer: a
a) Processor intra-connectivity circuitry Explanation: None.
b) Processor bus
c) Memory bus
d) Rambus 1. The main virtue for using single Bus
structure is
Answer: b a) Fast data transfers
Explanation: The processor BUS is used b) Cost effective connectivity and speed
to connect the various parts in order to c) Cost effective connectivity and ease
provide a direct connection to the CPU. of attaching peripheral devices
d) None of the mentioned
8. is used to choose between
incrementing the PC or performing ALU Answer: c
operations. Explanation: By using a single BUS
a) Conditional codes structure we can minimize the amount
b) Multiplexer of hardware (wire) required and thereby
c) Control unit reducing the cost.
d) None of the mentioned
2. are used to overcome the
Answer: b difference in data transfer speeds of
Explanation: The multiplexer circuit is various devices.
used to choose between the two as it a) Speed enhancing circuitory
can give different results based on the b) Bridge circuits
input. c) Multiple Buses
d) Buffer registers
9. The registers, ALU and the
interconnection between them are Answer: d
collectively called as Explanation: By using Buffer registers,
a) process route the processor sends the data to the I/O
b) information trail device at the processor speed and the
c) information path data gets stored in the buffer. After that
d) data path the data gets sent to or from the buffer
to the devices at the device speed.
Answer: d
Explanation: The Operational and 3. To extend the connectivity of the
processor bus we use
a) PCI bus b) IR
b) SCSI bus c) Temp
c) Controllers d) Z
d) Multiple bus
Answer: d
Answer: a Explanation: The Z register is a special
Explanation: PCI BUS is used to connect register which can interact with the
other peripheral devices that require a processor BUS only.
direct connection with the processor.
8. In multiple Bus organisation, the
4. IBM developed a bus standard for registers are collectively placed and
their line of computers ‘PC AT’ called referred as
a) Set registers
a) IB bus b) Register file
b) M-bus c) Register Block
c) ISA d) Map registers
d) None of the mentioned
Answer: b
Answer: c Explanation: None.
Explanation: None.
9. The main advantage of multiple bus
5. The bus used to connect the monitor organisation over a single bus is
to the CPU is a) Reduction in the number of cycles for
a) PCI bus execution
b) SCSI bus b) Increase in size of the registers
c) Memory bus c) Better Connectivity
d) Rambus d) None of the mentioned

Answer: b Answer: a
Explanation: SCSI BUS is usually used to Explanation: None.
connect video devices to the processor.
10. The ISA standard Buses are used to
6. ANSI stands for connect
a) American National Standards Institute a) RAM and processor
b) American National Standard Interface b) GPU and processor
c) American Network Standard c) Harddisk and Processor
Interfacing d) CD/DVD drives and Processor
d) American Network Security Interrupt
Answer: c
Answer: a Explanation: None.
Explanation: None.

7. register Connected to the 1. During the execution of the

Processor bus is a single-way transfer instructions, a copy of the instructions is
capable. placed in the
a) PC a) Register
b) RAM b) ANSA
c) System heap c) Super-scalar
d) Cache d) All of the mentioned

Answer: d Answer: c
Explanation: None. Explanation: In super-scalar
architecture, the instructions are set in
2. Two processors A and B have clock groups and they’re decoded and
frequencies of 700 Mhz and 900 Mhz executed together reducing the amount
respectively. Suppose A can execute an of time required to process them.
instruction with an average of 3 steps
and B can execute with an average of 5 5. The clock rate of the processor can be
steps. For the execution of the same improved by
instruction which processor is faster? a) Improving the IC technology of the
a) A logic circuits
b) B b) Reducing the amount of processing
c) Both take the same time done in one step
d) Insufficient information c) By using the overclocking method
d) All of the mentioned
Answer: a
Explanation: The performance of a Answer: d
system can be found out using the Basic Explanation: The clock rate(frequency
performance formula. of the processor) is the hardware
dependent quantity it is fixed for a given
3. A processor performing fetch or processor.
decoding of different instruction during
the execution of another instruction is 6. An optimizing Compiler does
called
a) Super-scaling a) Better compilation of the given piece
b) Pipe-lining of code
c) Parallel Computation b) Takes advantage of the type of
d) None of the mentioned processor and reduces its process time
c) Does better memory management
Answer: b d) None of the mentioned
Explanation: Pipe-lining is the process
of improving the performance of the Answer: b
system by processing different Explanation: An optimizing compiler is
instructions at the same time, with only a compiler designed for the specific
one instruction performing one specific purpose of increasing the operation
operation. speed of the processor by reducing the
time taken to compile the program
4. For a given FINITE number of instructions.
instructions to be executed, which
architecture of the processor provides 7. The ultimate goal of a compiler is to
for a faster execution?
a) ISA a) Reduce the clock cycles for a
programming task Answer: b
b) Reduce the size of the object code Explanation: When a looping or
c) Be versatile branching operation is carried out the
d) Be able to detect even the smallest of offset value is stored in the cache along
errors with the data.

Answer: a 11. The average number of steps taken

Explanation: None. to execute the set of instructions can be
made to be less than one by following
8. SPEC stands for
a) Standard Performance Evaluation a) ISA
Code b) Pipe-lining
b) System Processing Enhancing Code c) Super-scaling
c) System Performance Evaluation d) Sequential
Corporation
d) Standard Processing Enhancement Answer: c
Corporation Explanation: The number of steps
required to execute a given set of
Answer: c instructions is sufficiently reduced by
Explanation: SPEC is a corporation that using super-scaling. In this method, a set
started to standardize the evaluation of instructions are grouped together and
method of a system’s performance. are processed.

9. As of 2000, the reference system to 12. If a processor clock is rated as 1250

find the performance of a system is million cycles per second, then its clock
period is
a) Ultra SPARC 10
a) 1.9 * 10-10 sec
b) SUN SPARC
c) SUN II b) 1.6 * 10-9 sec
d) None of the mentioned c) 1.25 * 10-10 sec
d) 8 * 10-10 sec
Answer: a
Explanation: In SPEC system of Answer: d
measuring a system’s performance, a Explanation: None.
system is used as a reference against
which other systems are compared and 13. If the instruction, Add R1, R2, R3 is
performance is determined. executed in a system that is pipe-lined,
then the value of S is (Where S is a term
10. When Performing a looping of the Basic performance equation)?
operation, the instruction gets stored in a) 3
the b) ~2
a) Registers c) ~1
b) Cache d) 6
c) System Heap
d) System stack Answer: c
Explanation: S is the number of steps
required to execute the instructions. 2. In the case of, Zero-address
instruction method the operands are
14. CISC stands for stored in
a) Complete Instruction Sequential a) Registers
Compilation b) Accumulators
b) Computer Integrated Sequential c) Push down stack
Compiler d) Cache
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Answer: c
Compilation Explanation: In this case, the operands
are implicitly loaded onto the ALU.
Answer: c
Explanation: CISC is a type of system 3. Add #45, when this instruction is
architecture where complex instructions executed the following happen/s
are grouped together and executed to
improve system performance. a) The processor raises an error and
requests for one more operand
15. As of 2000, the reference system to b) The value stored in memory location
find the SPEC rating are built with 45 is retrieved and one more operand is
Processor. requested
a) Intel Atom SParc 300Mhz c) The value 45 gets added to the value
b) Ultra SPARC -IIi 300MHZ on the stack and is pushed onto the
c) Amd Neutrino series stack
d) ASUS A series 450 Mhz d) None of the mentioned

Answer: b Answer: b
Explanation: None. Explanation: None.

4. The addressing mode which makes use

1. The instruction, Add #45,R1 does of in-direction pointers is
a) Indirect addressing mode
a) Adds the value of 45 to the address of b) Index addressing mode
R1 and stores 45 in that address c) Relative addressing mode
b) Adds 45 to the value of R1 and stores d) Offset addressing mode
it in R1
c) Finds the memory location 45 and Answer: a
adds that content to that of R1 Explanation: In this addressing mode,
d) None of the mentioned the value of the register serves as
another memory location and hence we
Answer: b use pointers to get the data.
Explanation: The instruction is using
immediate addressing mode hence the 5. In the following indexed addressing
value is stored in the location 45 is mode instruction, MOV 5(R1), LOC the
added. effective address is
a) EA = 5+R1
b) EA = R1
c) EA = [R1] b) Direct
d) EA = 5+[R1] c) Definite
d) Relative
Answer: d
Explanation: This instruction is in Base Answer: a
with offset addressing mode. Explanation: None.

6. The addressing mode/s, which uses 9. The effective address of the following
the PC instead of a general purpose instruction is MUL 5(R1,R2).
register is a) 5+R1+R2
a) Indexed with offset b) 5+(R1*R2)
b) Relative c) 5+[R1]+[R2]
c) Direct d) 5*([R1]+[R2])
d) Both Indexed with offset and direct
Answer: c
Answer: b Explanation: The addressing mode used
Explanation: In this, the contents of the is base with offset and index.
PC are directly incremented.
10. addressing mode is most
7. When we use auto increment or auto suitable to change the normal sequence
decrements, which of the following of execution of instructions.
is/are true? a) Relative
1) In both, the address is used to b) Indirect
retrieve the operand and then the c) Index with Offset
address gets altered d) Immediate
2) In auto increment, the operand is
retrieved first and then the address Answer: a
altered Explanation: The relative addressing
3) Both of them can be used on general mode is used for this since it directly
purpose registers as well as memory updates the PC.
locations
a) 1, 2, 3
b) 2 1. Which method/s of representation of
c) 1, 3 numbers occupies a large amount of
d) 2, 3 memory than others?
a) Sign-magnitude
Answer: d b) 1’s complement
Explanation: In the case of, auto c) 2’s complement
increment the increment is done d) 1’s & 2’s compliment
afterward and in auto decrement the
decrement is done first. Answer: a
Explanation: It takes more memory as
8. The addressing mode, where you one bit used up to store the sign.
directly specify the operand value is
2. Which representation is most efficient
a) Immediate to perform arithmetic operations on the
numbers? Answer: b
a) Sign-magnitude Explanation: First the 2’s complement
b) 1’s complement is found and that is added to the number
c) 2’S complement and the overflow is ignored.
d) None of the mentioned
6. When we subtract -3 from 2 , the
Answer: c answer in 2’s complement form is
Explanation: The two’s complement
form is more suitable to perform a) 0001
arithmetic operations as there is no b) 1101
need to involve the sign of the number c) 0101
into consideration. d) 1001

3. Which method of representation has Answer: c

two representations for ‘0’? Explanation: First the 2’s complement
a) Sign-magnitude is found and that is added to the number
b) 1’s complement and the overflow is ignored.
c) 2’s complement
d) None of the mentioned 7. The processor keeps track of the
results of its operations using flags
Answer: a called
Explanation: One is positive and one for a) Conditional code flags
negative. b) Test output flags
c) Type flags
4. When we perform subtraction on -7 d) None of the mentioned
and 1 the answer in 2’s complement
form is Answer: a
a) 1010 Explanation: These flags are used to
b) 1110 indicate if there is an overflow or carry
c) 0110 or zero result occurrence.
d) 1000
8. The register used to store the flags is
Answer: d called as
Explanation: First the 2’s complement a) Flag register
is found and that is added to the number b) Status register
and the overflow is ignored. c) Test register
d) Log register
5. When we perform subtraction on -7
and -5 the answer in 2’s complement Answer: b
form is Explanation: The status register stores
a) 11110 the condition codes of the system.
b) 1110
c) 1010 9. The Flag ‘V’ is set to 1 indicates that
d) 0010
a) The operation is valid
b) The operation is validated
c) The operation has resulted in an
overflow a) And gate
d) None of the mentioned b) Nand gate
c) Nor gate
Answer: c d) Xor gate
Explanation: This is used to check the
overflow occurs in the operation. Answer: d
Explanation: None.
10. In some pipelined systems, a
different instruction is used to add to 14. In the implementation of a Multiplier
numbers which can affect the flags upon circuit in the system we make use of
execution. That instruction is
a) AddSetCC a) Counter
b) AddCC b) Flip flop
c) Add++ c) Shift register
d) SumSetCC d) Push down stack

Answer: a Answer: c
Explanation: By using this instruction Explanation: The shift registers are
the condition flags won’t be affected at used to store the multiplied answer.
all.
15. When 1101 is used to divide
11. The most efficient method followed 100010010 the remainder is
by computers to multiply two unsigned a) 101
numbers is b) 11
a) Booth algorithm c) 0
b) Bit pair recording of multipliers d) 1
c) Restoring algorithm
d) Non restoring algorithm Answer: d
Explanation: None.
Answer: b
Explanation: None.
1. The smallest entity of memory is
12. For the addition of large integers, called
most of the systems make use of a) Cell
a) Fast adders b) Block
b) Full adders c) Instance
c) Carry look-ahead adders d) Unit
d) None of the mentioned
Answer: a
Answer: c Explanation: Each data is made up of a
Explanation: In this method, the carries number of units.
for each step are generated first.
2. The collection of the above
13. In a normal n-bit adder, to find out if mentioned entities where data is stored
an overflow as occurred we make use of is called
a) Block 6. When using the Big Endian assignment
b) Set to store a number, the sign bit of the
c) Word number is stored in
d) Byte a) The higher order byte of the word
b) The lower order byte of the word
Answer: c c) Can’t say
Explanation: Each readable part of the d) None of the mentioned
data is called blocks.
Answer: a
3. An 24 bit address generates an Explanation: None.
address space of locations.
a) 1024 7. To get the physical address from the
b) 4096 logical address generated by CPU we use
c) 248
d) 16,777,216 a) MAR
b) MMU
Answer: d c) Overlays
Explanation: The number of d) TLB
addressable locations in the system is
called as address space. Answer: b
Explanation: Memory Management Unit,
4. If a system is 64 bit machine, then the is used to add the offset to the logical
length of each word will be address generated by the CPU to get the
a) 4 bytes physical address.
b) 8 bytes
c) 16 bytes 8. method is used to map logical
d) 12 bytes addresses of variable length onto
physical memory.
Answer: b a) Paging
Explanation: A 64 bit system means, b) Overlays
that at a time 64 bit instruction can be c) Segmentation
executed. d) Paging with segmentation

5. The type of memory assignment used Answer: c

in Intel processors is Explanation: Segmentation is a process
a) Little Endian in which memory is divided into groups
b) Big Endian of variable length called segments.
c) Medium Endian
d) None of the mentioned 9. During the transfer of data between
the processor and memory we use
Answer: a
Explanation: The method of address a) Cache
allocation to data to be stored is called b) TLB
as memory assignment. c) Buffers
d) Registers
Answer: d b) Relocation register
Explanation: None. c) Page table
d) Shift register
10. Physical memory is divided into sets
of finite size called as Answer: b
a) Frames Explanation: In the MMU the relocation
b) Pages register stores the offset address.
c) Blocks
d) Vectors 4. The technique used to store programs
larger than the memory is
Answer: a a) Overlays
Explanation: None. b) Extension registers
c) Buffers
d) Both Extension registers and Buffers
1. Add #%01011101,R1 , when this
instruction is executed then Answer: a
a) The binary addition between the Explanation: In this, only a part of the
operands takes place program getting executed is stored on
b) The Numerical value represented by the memory and later swapped in for
the binary value is added to the value of the other part.
R1
c) The addition doesn’t take place, 5. The unit which acts as an
whereas this is similar to a MOV intermediate agent between memory
instruction and backing store to reduce process
d) None of the mentioned time is
a) TLB’s
Answer: a b) Registers
Explanation: This performs operations c) Page tables
in binary mode directly. d) Cache

2. If we want to perform memory or Answer: d

arithmetic operations on data in Hexa- Explanation: The cache’s help in data
decimal mode then we use transfers by storing most recently used
symbol before the operand. memory pages.
a) ~
b) ! 6. Does the Load instruction do the
c) $ following operation/s?
d) * a) Loads the contents of a disc onto a
memory location
Answer: c b) Loads the contents of a location onto
Explanation: None. the accumulators
c) Load the contents of the PCB onto the
3. When generating physical addresses register
from a logical address the offset is d) None of the mentioned
stored in
a) Translation look-aside buffer
Answer: b c) Dynamic loading
Explanation: The load instruction is d) Both Dynamic linking and loading
basically used to load the contents of a
memory location onto a register. Answer: c
Explanation: In this method only when
7. Complete the following analogy:- the routine is required is loaded and
Registers are to RAM’s as Cache’s are to hence saves memory.

a) System stacks
b) Overlays 1. RTN stands for
c) Page Table a) Register Transfer Notation
d) TLB b) Register Transmission Notation
c) Regular Transmission Notation
Answer: d d) Regular Transfer Notation
Explanation: None.
Answer: a
8. The BOOT sector files of the system Explanation: This is the way of writing
are stored in the assembly language code with the
a) Harddisk help of register notations.
b) ROM
c) RAM 2. The instruction, Add Loc,R1 in RTN is
d) Fast solid state chips in the
motherboard a) AddSetCC Loc+R1
b) R1=Loc+R1
Answer: b c) Not possible to write in RTN
Explanation: The files which are d) R1<-[Loc]+[R1]
required for the starting up of a system
are stored on the ROM. Answer: d
Explanation: None.
9. The transfer of large chunks of data
with the involvement of the processor is 3. Can you perform an addition on three
done by operands simultaneously in ALN using
a) DMA controller Add instruction?
b) Arbitrator a) Yes
c) User system programs b) Not possible using Add, we’ve to use
d) None of the mentioned AddSetCC
c) Not permitted
Answer: a d) None of the mentioned
Explanation: This mode of transfer
involves the transfer of a large block of Answer: c
data from the memory. Explanation: You cannot perform an
addition on three operands
10. Which of the following techniques simultaneously because the third
used to effectively utilize main memory? operand is where the result is stored.
a) Address binding
b) Dynamic linking
4. The instruction, Add R1,R2,R3 in RTN d) Decoding the data in MDR and placing
is it in IR
a) R3=R1+R2+R3
b) R3<-[R1]+[R2]+[R3] Answer: d
c) R3=[R1]+[R2] Explanation: The fetch ends with the
d) R3<-[R1]+[R2] instruction getting decoded and being
placed in the IR and the PC getting
Answer: d incremented.
Explanation: In RTN the first operand is
the destination and the second operand 8. While using the iterative construct
is the source. (Branching) in execution
instruction is used to check the
5. In a system, which has 32 registers condition.
the register id is long. a) TestAndSet
a) 16 bit b) Branch
b) 8 bits c) TestCondn
c) 5 bits d) None of the mentioned
d) 6 bits
Answer: b
Answer: c Explanation: Branch instruction is used
Explanation: The ID is the name tag to check the test condition and to
given to each of the registers and used perform the memory jump with the help
to identify them. of offset.

6. The two phases of executing an 9. When using Branching, the usual

instruction are sequencing of the PC is altered. A new
a) Instruction decoding and storage instruction is loaded which is called as
b) Instruction fetch and instruction
execution a) Branch target
c) Instruction execution and storage b) Loop target
d) Instruction fetch and Instruction c) Forward target
processing d) Jump instruction

Answer: b Answer: a
Explanation: First, the instructions are Explanation: None.
fetched and decoded and then they’re
executed and stored. 10. The condition flag Z is set to 1 to
indicate
7. The Instruction fetch phase ends with a) The operation has resulted in an error
b) The operation requires an interrupt
a) Placing the data from the address in call
MAR into MDR c) The result is zero
b) Placing the address of the data into d) There is no empty register available
MAR
c) Completing the execution of the data Answer: c
and placing its storage address into MAR Explanation: This condition flag is used
to check if the arithmetic operation c) Comments
yields a zero output. d) Assembler Directives

Answer: d
1. converts the programs Explanation: The directives help the
written in assembly language into program in getting compiled and hence
machine instructions. won’t be there in the object code.
a) Machine compiler
b) Interpreter 5. The assembler directive EQU, when
c) Assembler used in the instruction: Sum EQU 200
d) Converter does
a) Finds the first occurrence of Sum and
Answer: c assigns value 200 to it
Explanation: An assembler is a software b) Replaces every occurrence of Sum
used to convert the programs into with 200
machine instructions. c) Re-assigns the address of Sum by
adding 200 to its original address
2. The instructions like MOV or ADD are d) Assigns 200 bytes of memory starting
called as the location of Sum
a) OP-Code
b) Operators Answer: b
c) Commands Explanation: This basically is used to
d) None of the mentioned replace the variable with a constant
value.
Answer: a
Explanation: This OP – codes tell the 6. The purpose of the ORIGIN directive is
system what operation to perform on
the operands. a) To indicate the starting position in
memory, where the program block is to
3. The alternate way of writing the be stored
instruction, ADD #5,R1 is b) To indicate the starting of the
a) ADD [5],[R1]; computation code
b) ADDI 5,R1; c) To indicate the purpose of the code
c) ADDIME 5,[R1]; d) To list the locations of all the
d) There is no other way registers used

Answer: b Answer: a
Explanation: The ADDI instruction, Explanation: This does the function
means the addition is in immediate similar to the main statement.
addressing mode.
7. The directive used to perform
4. Instructions which won’t appear in initialization before the execution of the
the object program are called as code is
a) Redundant instructions a) Reserve
b) Exceptions b) Store
c) Dataword condition is satisfied
d) EQU c) Finds the Branch offset and replaces
the Branch target with it
Answer: c d) Replaces the target with the value
Explanation: None. specified by the DATAWORD directive

8. directive is used to specify and Answer: c

assign the memory required for the Explanation: When the assembler
block of code. comes across the branch code, it
a) Allocate immediately finds the branch offset and
b) Assign replaces it with it.
c) Set
d) Reserve 12. The assembler stores all the names
and their corresponding values in
Answer: d a) Special purpose Register
Explanation: This instruction is used to b) Symbol Table
allocate a block of memory and to store c) Value map Set
the object code of the program there. d) None of the mentioned

9. directive specifies the end of Answer: b

execution of a program. Explanation: The table where the
a) End assembler stores the variable names
b) Return along with their corresponding memory
c) Stop locations and values.
d) Terminate
13. The assembler stores the object
Answer: b code in
Explanation: This instruction directive a) Main memory
is used to terminate the program b) Cache
execution. c) RAM
d) Magnetic disk
10. The last statement of the source
program should be Answer: d
a) Stop Explanation: After compiling the object
b) Return code, the assembler stores it in the
c) OP magnetic disk and waits for further
d) End execution.

Answer: d 14. The utility program used to bring the

Explanation: This enables the processor object code into memory for execution
to load some other process. is
a) Loader
11. When dealing with the branching b) Fetcher
code the assembler c) Extractor
a) Replaces the target with its address d) Linker
b) Does not replace until the test
Answer: a c) Having one routine call the other
Explanation: The program is used to d) None of the mentioned
load the program into memory.
Answer: c
15. To overcome the problems of the Explanation: None.
assembler in dealing with branching
code we use 4. The order in which the return
a) Interpreter addresses are generated and used is
b) Debugger
c) Op-Assembler a) LIFO
d) Two-pass assembler b) FIFO
c) Random
Answer: d d) Highest priority
Explanation: This creates entries into
the symbol table first and then creates Answer: a
the object code. Explanation: That is the routine called
first is returned first.

1. The return address of the Sub-routine 5. In case of nested subroutines the

is pointed to by return addresses are stored in
a) IR
b) PC a) System heap
c) MAR b) Special memory buffers
d) Special memory registers c) Processor stack
d) Registers
Answer: b
Explanation: The return address from Answer: c
the subroutine is pointed to by the PC. Explanation: In this case, there will be
more number of return addresses it is
2. The location to return to, from the stored on the processor stack.
subroutine is stored in
a) TLB 6. The appropriate return addresses are
b) PC obtained with the help of in case of
c) MAR nested routines.
d) Link registers a) MAR
b) MDR
Answer: d c) Buffers
Explanation: The registers store the d) Stack-pointers
return address of the routine and is
pointed to by the PC. Answer: d
Explanation: The pointers are used to
3. What is subroutine nesting? point to the location on the stack where
a) Having multiple subroutines in a the address is stored.
program
b) Using a linking nest statement to put 7. When parameters are being passed on
many subroutines under the same name to the subroutines they are stored in
 b) ii and iii
a) Registers c) iv
b) Memory locations d) iii and iv
c) Processor stacks
d) All of the mentioned Answer: d
Explanation: None.
Answer: d
Explanation: In the case of, parameter
passing the data can be stored on any of 1. The private work space dedicated to a
the storage space. subroutine is called as
a) System heap
8. The most efficient way of handling b) Reserve
parameter passing is by using c) Stack frame
a) General purpose registers d) Allocation
b) Stacks
c) Memory locations Answer: c
d) None of the mentioned Explanation: This work space is where
the intermediate values of the
Answer: a subroutines are stored.
Explanation: By using general purpose
registers for the parameter passing we 2. If the subroutine exceeds the private
make the process more efficient. space allocated to it then the values are
pushed onto
9. The most Flexible way of logging the a) Stack
return addresses of the subroutines is by b) System heap
using c) Reserve Space
a) Registers d) Stack frame
b) Stacks
c) Memory locations Answer: a
d) None of the mentioned Explanation: If the allocated work
space is exceeded then the data is
Answer: b pushed onto the system stack.
Explanation: The stacks are used as
Logs for return addresses of the 3. pointer is used to point to
subroutines. parameters passed or local parameters
of the subroutine.
10. The wrong statement/s regarding a) Stack pointer
interrupts and subroutines among the b) Frame pointer
following is/are c) Parameter register
i) The sub-routine and interrupts have a d) Log register
return statement
ii) Both of them alter the content of the Answer: b
PC Explanation: This pointer is used to
iii) Both are software oriented track the current position of the stack
iv) Both can be initiated by the user being used.
a) i, ii and iv
4. The reserved memory or private b) The saved contents of the calling sub
space of the subroutine gets deallocated routine
when c) The return addresses of the called sub
a) The stop instruction is executed by routine
the routine d) None of the mentioned
b) The pointer reaches the end of the
space Answer: a
c) When the routine’s return statement Explanation: None.
is executed
d) None of the mentioned 8. The stack frame for each subroutine
is present in
Answer: c a) Main memory
Explanation: The work space allocated b) System Heap
to a subroutine gets deallocated when c) Processor Stack
the routine is completed. d) None of the mentioned

5. The private space gets allocated to Answer: c

each subroutine when Explanation: The memory for the work
a) The first statement of the routine is space is allocated from the processor
executed stack.
b) When the context switch takes place
c) When the routine gets called 9. The data structure suitable for
d) When the Allocate instruction is scheduling processes is
executed a) List
b) Heap
Answer: c c) Queue
Explanation: When the call statement is d) Stack
executed, simultaneously space also gets
allocated. Answer: c
Explanation: The Queue data structure
6. the most suitable data is generally used for scheduling as it is
structure used to store the return two directional.
addresses in the case of nested
subroutines. 10. The sub-routine service procedure is
a) Heap similar to that of the interrupt service
b) Stack routine in
c) Queue a) Method of context switch
d) List b) Returning
c) Process execution
Answer: b d) Method of context switch & Process
Explanation: None. execution

7. In the case of nested subroutines, the Answer: d

stack top is always Explanation: The Subroutine service
a) The saved contents of the called sub procedure is the same as the interrupt
routine service routine in all aspects, except the
fact that interrupt might not be related mapping have a bigger buffer space
to the process being executed. c) The devices have to deal with fewer
address lines
d) No advantage as such
1. In memory-mapped I/O
a) The I/O devices and the memory Answer: c
share the same address space Explanation: Since the I/O mapped
b) The I/O devices have a separate devices have a separate address space
address space the address lines are limited by the
c) The memory and I/O devices have an amount of the space allocated.
associated address space
d) A part of the memory is specifically 5. The system is notified of a read or
set aside for the I/O operation write operation by
a) Appending an extra bit of the address
Answer: a b) Enabling the read or write bits of the
Explanation: Its the different modes of devices
accessing the i/o devices. c) Raising an appropriate interrupt signal
d) Sending a special signal along the BUS
2. The usual BUS structure used to
connect the I/O devices is Answer: d
a) Star BUS structure Explanation: It is necessary for the
b) Multiple BUS structure processor to send a signal intimating the
c) Single BUS structure request as either read or write.
d) Node to Node BUS structure
6. To overcome the lag in the operating
Answer: c speeds of the I/O device and the
Explanation: BUS is a collection of processor we use
address, control and data lines used to a) BUffer spaces
connect the various devices of the b) Status flags
computer. c) Interrupt signals
d) Exceptions
3. In intel’s IA-32 architecture there is a
separate 16 bit address space for the I/O Answer: b
devices. Explanation: The processor operating is
a) False much faster than that of the I/O
b) True devices, so by using the status flags the
processor need not wait till the I/O
Answer: b operation is done. It can continue with
Explanation: This type of access is its work until the status flag is set.
called as I/O mapped devices.
7. The method of accessing the I/O
4. The advantage of I/O mapped devices devices by repeatedly checking the
to memory mapped is status flags is
a) The former offers faster transfer of a) Program-controlled I/O
data b) Memory-mapped I/O
b) The devices connected using I/O
c) I/O mapped c) Reviewing
d) None of the mentioned d) Echoing

Answer: a Answer: a
Explanation: In this method, the Explanation: None.
processor constantly checks the status
flags, and when it finds that the flag is
set it performs the appropriate 1. The interrupt-request line is a part of
operation. the
a) Data line
8. The method of synchronising the b) Control line
processor with the I/O device in which c) Address line
the device sends a signal when it is d) None of the mentioned
ready is?
a) Exceptions Answer: b
b) Signal handling Explanation: The Interrupt-request line
c) Interrupts is a control line along which the device
d) DMA is allowed to send the interrupt signal.

Answer: c 2. The return address from the

Explanation: This is a method of interrupt-service routine is stored on the
accessing the I/O devices which gives
the complete power to the devices, a) System heap
enabling them to intimate the processor b) Processor register
when they’re ready for transfer. c) Processor stack
d) Memory
9. The method which offers higher
speeds of I/O transfers is Answer: c
a) Interrupts Explanation: The Processor after
b) Memory mapping servicing the interrupts as to load the
c) Program-controlled I/O address of the previous process and this
d) DMA address is stored in the stack.

Answer: d 3. The signal sent to the device from the

Explanation: In DMA the I/O devices are processor to the device after receiving
directly allowed to interact with the an interrupt is
memory without the intervention of the a) Interrupt-acknowledge
processor and the transfers take place in b) Return signal
the form of blocks increasing the speed c) Service signal
of operation. d) Permission signal

10. The process wherein the processor Answer: a

constantly checks the status flags is Explanation: The Processor upon
called as receiving the interrupt should let the
a) Polling device know that its request is received.
b) Inspection
4. When the process is returned after an Answer: a
interrupt service should be Explanation: None.
loaded again.
i) Register contents 8. type circuits are generally
ii) Condition codes used for interrupt service lines.
iii) Stack contents i) open-collector
iv) Return addresses ii) open-drain
a) i, iv iii) XOR
b) ii, iii and iv iv) XNOR
c) iii, iv a) i, ii
d) i, ii b) ii
c) ii, iii
Answer: d d) ii, iv
Explanation: None.
Answer: a
5. The time between the receiver of an Explanation: None.
interrupt and its service is
a) Interrupt delay 9. The resistor which is attached to the
b) Interrupt latency service line is called
c) Cycle time a) Push-down resistor
d) Switching time b) Pull-up resistor
c) Break down resistor
Answer: b d) Line resistor
Explanation: The delay in servicing of
an interrupt happens due to the time is Answer: b
taken for contact switch to take place. Explanation: This resistor is used to pull
up the voltage of the interrupt service
6. Interrupts form an important part of line.
systems.
a) Batch processing 10. An interrupt that can be temporarily
b) Multitasking ignored is
c) Real-time processing a) Vectored interrupt
d) Multi-user b) Non-maskable interrupt
c) Maskable interrupt
Answer: c d) High priority interrupt
Explanation: This forms an important
part of the Real time system since if a Answer: c
process arrives with greater priority then Explanation: The maskable interrupts
it raises an interrupt and the other are usually low priority interrupts which
process is stopped and the interrupt will can be ignored if a higher priority
be serviced. process is being executed.

7. A single Interrupt line can be used to 11. The 8085 microprocessor responds to
service n different devices. the presence of an interrupt
a) True
b) False a) As soon as the trap pin becomes
‘LOW’ for its completion. Hence trap is
b) By checking the trap pin for ‘high’ unmaskable.
status at the end of each instruction
fetch 14. From amongst the following given
c) By checking the trap pin for ‘high’ scenarios determine the right one to
status at the end of execution of each justify interrupt mode of data transfer.
instruction i) Bulk transfer of several kilo-byte
d) By checking the trap pin for ‘high’ ii) Moderately large data transfer of
status at regular intervals more than 1kb
iii) Short events like mouse action
Answer: c iv) Keyboard inputs
Explanation: The 8085 microprocessor a) i and ii
are designed to complete the execution b) ii
of the current instruction and then to c) i, ii and iv
service the interrupts. d) iv

12. CPU as two modes privileged and Answer: d

non-privileged. In order to change the Explanation: None.
mode from privileged to non-privileged.
a) A hardware interrupt is needed 15. How can the processor ignore other
b) A software interrupt is needed interrupts when it is servicing one
c) Either hardware or software interrupt
is needed a) By turning off the interrupt request
d) A non-privileged instruction (which line
does not generate an interrupt)is b) By disabling the devices from sending
needed the interrupts
c) BY using edge-triggered request lines
Answer: b d) All of the mentioned
Explanation: A software interrupt by
some program which needs some CPU Answer: d
service, at that time the two modes can Explanation: None.
be interchanged.

13. Which interrupt is unmaskable? 1. When dealing with multiple devices

a) RST 5.5 interrupts, which mechanism is easy to
b) RST 7.5 implement?
c) TRAP a) Polling method
d) Both RST 5.5 and 7.5 b) Vectored interrupts
c) Interrupt nesting
Answer: c d) None of the mentioned
Explanation: The trap is a non-
maskable interrupt as it deals with the Answer: a
ongoing process in the processor. The Explanation: In this method, the
trap is initiated by the process being processor checks the IRQ bits of all the
executed due to lack of data required devices, whichever is enabled first that
device is serviced.
2. The interrupt servicing mechanism in Answer: b
which the requesting device identifies Explanation: None.
itself to the processor to be serviced is
6. The processor indicates to the devices
a) Polling that it is ready to receive interrupts
b) Vectored interrupts
c) Interrupt nesting a) By enabling the interrupt request line
d) Simultaneous requesting b) By enabling the IRQ bits
c) By activating the interrupt
Answer: b acknowledge line
Explanation: None. d) None of the mentioned

3. In vectored interrupts, how does the Answer: c

device identify itself to the processor? Explanation: When the processor
a) By sending its device id activates the acknowledge line the
b) By sending the machine code for the devices send their interrupts to the
interrupt service routine processor.
c) By sending the starting address of the
service routine 7. We describe a protocol of input
d) None of the mentioned device communication below:
i) Each device has a distinct address.
Answer: c ii) The BUS controller scans each device
Explanation: By sending the starting in a sequence of increasing address
address of the routine the device ids the value to determine if the entity wishes
routine required and thereby identifying to communicate
itself. iii) The device ready to communicate
leaves its data in the I/O register
4. The code sent by the device in iv) The data is picked up and the
vectored interrupt is long. controller moves to the step a
a) upto 16 bits Identify the form of communication best
b) upto 32 bits describes the I/O mode amongst the
c) upto 24 bits following.
d) 4-8 bits a) Programmed mode of data transfer
b) DMA
Answer: d c) Interrupt mode
Explanation: None. d) Polling
5. The starting address sent by the Answer: d
device in vectored interrupt is called as Explanation: In polling, the processor
checks each of the devices if they wish
a) Location id to perform data transfer and if they do
b) Interrupt vector it performs the particular operation.
c) Service location
d) Service id 8. Which one of the following is true
with regard to a CPU having a single
interrupt request line and single
interrupt grant line? a) Interrupt request
i) Neither vectored nor multiple b) No interrupt request
interrupting devices is possible. c) Both No interrupt and Interrupt
ii) Vectored interrupts is not possible but request
multiple interrupting devices is possible. d) None of the mentioned
iii) Vectored interrupts is possible and
multiple interrupting devices is not Answer: b
possible. Explanation: In daisy chaining since
iv) Both vectored and multiple there is only one request line and only
interrupting devices are possible. one acknowledges line, the acknowledge
a) iii signal passes from device to device until
b) i, iv the one with the interrupt is found.
c) ii, iii
d) iii, iv 12. interrupt method uses
register whose bits are set separately by
Answer: a interrupt signal for each device.
Explanation: None. a) Parallel priority interrupt
b) Serial priority interrupt
9. Which table handle stores the c) Daisy chaining
addresses of the interrupt handling sub- d) None of the mentioned
routines?
a) Interrupt-vector table Answer: a
b) Vector table Explanation: None.
c) Symbol link table
d) None of the mentioned 13. register is used for
the purpose of controlling the status of
Answer: a each interrupt request in parallel
Explanation: None. priority interrupt.
a) Mass
10. method is used to b) Mark
establish priority by serially connecting c) Make
all devices that request an interrupt. d) Mask
a) Vectored-interrupting
b) Daisy chain Answer: d
c) Priority Explanation: None.
d) Polling
14. The added output of the bits of the
Answer: b interrupt register and the mask register
Explanation: In the Daisy chain is set as an input of
mechanism, all the devices are a) Priority decoder
connected using a single request line b) Priority encoder
and they’re serviced based on the c) Process id encoder
interrupting device’s priority. d) Multiplexer

11. In daisy chaining device 0 will pass Answer: b

the signal only if it has Explanation: In a parallel priority
system, the priority of the device is b) Compiler
obtained by adding the contents of the c) Assembler
interrupt register and the mask register. d) Scanner

15. Interrupts initiated by an instruction Answer: a

is called as Explanation: Debugger is a program
a) Internal used to detect and correct errors in the
b) External program.
c) Hardware
d) Software 4. The two facilities provided by the
debugger is
Answer: b a) Trace points
Explanation: None. b) Break points
c) Compile
d) Both Trace and Break points
1. If during the execution of an
instruction an exception is raised then Answer: d
Explanation: The debugger provides us
a) The instruction is executed and the with the two facilities to improve the
exception is handled checking of errors.
b) The instruction is halted and the
exception is handled 5. In trace mode of operation is
c) The processor completes the
execution and saves the data and then a) The program is interrupted after each
handle the exception detection
d) None of the mentioned b) The program will not be stopped and
the errors are sorted out after the
Answer: b complete program is scanned
Explanation: Since the interrupt was c) There is no effect on the program, i.e
raised during the execution of the the program is executed without
instruction, the instruction cannot be rectification of errors
executed and the exception is served d) The program is halted only at specific
immediately. points

2. is/are types of exceptions. Answer: a

a) Trap Explanation: In trace mode, the
b) Interrupt program is checked line by line and if
c) System calls errors are detected then exceptions are
d) All of the mentioned raised right away.

Answer: d 6. What is the operation in Breakpoint

Explanation: None. mode?
a) The program is interrupted after each
3. The program used to find out errors is detection
called b) The program will not be stopped and
a) Debugger the errors are sorted out after the
complete program is scanned memory allocated to other users
c) There is no effect on the program, i.e d) All of the mentioned
the program is executed without
rectification of errors Answer: d
d) The program is halted only at specific Explanation: None.
points
10. How is a privilege exception dealt
Answer: d with?
Explanation: The Breakpoint mode of a) The program is halted and the system
operation allows the program to be switches into supervisor mode and
halted at only specific locations. restarts the program execution
b) The Program is stopped and removed
7. What are the different modes of from the queue
operation of a computer? c) The system switches the mode and
a) User and System mode starts the execution of a new process
b) User and Supervisor mode d) The system switches mode and runs
c) Supervisor and Trace mode the debugger
d) Supervisor, User and Trace mode
Answer: a
Answer: b Explanation: None.
Explanation: The user programs are in
the user mode and the system crucial
programs are in the supervisor mode. 1. The DMA differs from the interrupt
mode by
8. The instructions which can be run a) The involvement of the processor for
only supervisor mode are? the operation
a) Non-privileged instructions b) The method of accessing the I/O
b) System instructions devices
c) Privileged instructions c) The amount of data transfer possible
d) Exception instructions d) None of the mentioned

Answer: c Answer: d
Explanation: These instructions are Explanation: DMA is an approach of
those which can are crucial for the performing data transfers in bulk
system’s performance and hence cannot between memory and the external
be adultered by user programs, so is run device without the intervention of the
only in supervisor mode. processor.

9. A privilege exception is raised 2. The DMA transfers are performed by a

control circuit called as
a) When a process tries to change the a) Device interface
mode of the system b) DMA controller
b) When a process tries to change the c) Data controller
priority level of the other processes d) Overlooker
c) When a process tries to access the
Answer: b a) Read operation is performed
Explanation: The Controller performs b) Write operation is performed
the functions that would normally be c) Read & Write operation is performed
carried out by the processor. d) None of the mentioned

3. In DMA transfers, the required signals Answer: a

and addresses are given by the Explanation: None.

a) Processor 7. The controller is connected to the

b) Device drivers
c) DMA controllers a) Processor BUS
d) The program itself b) System BUS
c) External BUS
Answer: c d) None of the mentioned
Explanation: The DMA controller acts as
a processor for DMA transfers and Answer: b
overlooks the entire process. Explanation: The controller is directly
connected to the system BUS to provide
4. After the completion of the DMA faster transfer of data.
transfer, the processor is notified by
8. Can a single DMA controller perform
a) Acknowledge signal operations on two different disks
b) Interrupt signal simultaneously?
c) WMFC signal a) True
d) None of the mentioned b) False

Answer: b Answer: a
Explanation: The controller raises an Explanation: The DMA controller can
interrupt signal to notify the processor perform operations on two different
that the transfer was complete. disks if the appropriate details are
known.
5. The DMA controller has
registers. 9. The technique whereby the DMA
a) 4 controller steals the access cycles of the
b) 2 processor to operate is called
c) 3
d) 1 a) Fast conning
b) Memory Con
Answer: c c) Cycle stealing
Explanation: The Controller uses the d) Memory stealing
registers to store the starting address,
word count and the status of the Answer: c
operation. Explanation: The controller takes over
the processor’s access cycles and
6. When the R/W bit of the status performs memory operations.
register of the DMA controller is set to 1.
10. The technique where the controller Answer: c
is given complete access to main Explanation: None.
memory is
a) Cycle stealing 14. When the process requests for a DMA
b) Memory stealing transfer?
c) Memory Con a) Then the process is temporarily
d) Burst mode suspended
b) The process continues execution
Answer: d c) Another process gets executed
Explanation: The controller is given full d) process is temporarily suspended &
control of the memory access cycles and Another process gets executed
can transfer blocks at a faster rate.
Answer: d
11. The controller uses to help Explanation: The process requesting
with the transfers when handling the transfer is paused and the operation
network interfaces. is performed, meanwhile another
a) Input Buffer storage process is run on the processor.
b) Signal enhancers
c) Bridge circuits 15. The DMA transfer is initiated by
d) All of the mentioned
a) Processor
Answer: a b) The process being executed
Explanation: The controller stores the c) I/O devices
data to transfer in the buffer and then d) OS
transfers it.
Answer: c
12. To overcome the conflict over the Explanation: The transfer can only be
possession of the BUS we use initiated by an instruction of a program
a) Optimizers being executed.
b) BUS arbitrators
c) Multiple BUS structure
d) None of the mentioned 1. To resolve the clash over the access of
the system BUS we use
Answer: b a) Multiple BUS
Explanation: The BUS arbitrator is used b) BUS arbitrator
to overcome the contention over the c) Priority access
BUS possession. d) None of the mentioned

13. The registers of the controller are Answer: b

Explanation: The BUS arbitrator is used
a) 64 bits to allow a device to access the BUS
b) 24 bits based on certain parameters.
c) 32 bits
d) 16 bits 2. The device which is allowed to
initiate data transfers on the BUS at any
time is called
a) BUS master a) Acknowledge signal
b) Processor b) BUS grant signal
c) BUS arbitrator c) Response signal
d) Controller d) None of the mentioned

Answer: a Answer: b
Explanation: The device which is Explanation: The Grant signal is passed
currently accessing the BUS is called as from one device to the other until the
the BUS master. device that has requested is found.

3. BUS arbitration approach uses 7. In Centralised Arbitration

the involvement of the processor. is/are is the BUS master.
a) Centralised arbitration a) Processor
b) Distributed arbitration b) DMA controller
c) Random arbitration c) Device
d) All of the mentioned d) Both Processor and DMA controller

Answer: a Answer: d
Explanation: In this approach, the Explanation: The BUS master is the one
processor takes into account the various that decides which will get the BUS.
parameters and assigns the BUS to that
device. 8. Once the BUS is granted to a device

4. The circuit used for the request line is a) It activates the BUS busy line
a b) Performs the required operation
a) Open-collector c) Raises an interrupt
b) EX-OR circuit d) All of the mentioned
c) Open-drain
d) Nand circuit Answer: a
Explanation: The BUS busy activated
Answer: c indicates that the BUS is already
Explanation: None. allocated to a device and is being used.

5. The Centralised BUS arbitration is 9. The BUS busy line is made of

similar to interrupt circuit.
a) Priority a) Open-drain circuit
b) Parallel b) Open-collector circuit
c) Single c) EX-Or circuit
d) Daisy chain d) Nor circuit

Answer: d Answer: b
Explanation: None. Explanation: None.

6. When the processor receives the 10. After the device completes its
request from a device, it responds by operation assumes the control of
sending the BUS.
a) Another device a) By NANDing the signals passed on all
b) Processor the 4 lines
c) Controller b) By ANDing the signals passed on all
d) None of the mentioned the 4 lines
c) By ORing the signals passed on all the
Answer: b 4 lines
Explanation: After the device d) None of the mentioned
completes the operation it releases the
BUS and the processor takes over it. Answer: c
Explanation: The OR output of all the 4
11. The BUS busy line is used lines is obtained and the device with the
larger value is assigned the BUS.
a) To indicate the processor is busy
b) To indicate that the BUS master is 15. If two devices A and B contesting for
busy the BUS have ID’s 5 and 6 respectively,
c) To indicate the BUS is already which device gets the BUS based on the
allocated Distributed arbitration.
d) None of the mentioned a) Device A
b) Device B
Answer: c c) Insufficient information
Explanation: None. d) None of the mentioned
12. Distributed arbitration makes use of Answer: b
Explanation: The device Id’s of both the
a) BUS master devices are passed on the lines and since
b) Processor the value of B is greater after the Or
c) Arbitrator operation it gets the BUS.
d) 4-bit ID

Answer: d 1. The primary function of the BUS is

Explanation: The device uses a 4bit ID
number and based on this the BUS is a) To connect the various devices to the
allocated. cpu
b) To provide a path for communication
13. In Distributed arbitration, the device between the processor and other devices
requesting the BUS c) To facilitate data transfer between
a) Asserts the Start arbitration signal various devices
b) Sends an interrupt signal d) All of the mentioned
c) Sends an acknowledge signal
d) None of the mentioned Answer: a
Explanation: The BUS is used to allow
Answer: a the passage of commands and data
Explanation: None. between cpu and devices.
14. How is a device selected in 2. The classification of BUSes into
Distributed arbitration? synchronous and asynchronous is based
on 6. The delays caused in the switching of
a) The devices connected to them the timing signals is due to
b) The type of data transfer a) Memory access time
c) The Timing of data transfers b) WMFC
d) None of the mentioned c) Propagation delay
d) Processor delay
Answer: c
Explanation: The BUS is classified into Answer: c
different types for the convenience of Explanation: The time taken for the
use and depending on the device. signal to reach the BUS from the device
or the circuit accounts for this delay.
3. The device which starts data transfer
is called 7. The time for which the data is to be
a) Master on the BUS is affected by
b) Transactor a) Propagation delay of the circuit
c) Distributor b) Setup time of the device
d) Initiator c) Memory access time
d) Propagation delay of the circuit &
Answer: d Setup time of the device
Explanation: The device which starts
the data transfer is called an initiator. Answer: d
Explanation: The time for which the
4. The device which interacts with the data is held is larger than the time taken
initiator is for propagation delay and setup time.
a) Slave
b) Master 8. The Master strobes the slave at the
c) Responder end of each clock cycle in Synchronous
d) Friend BUS.
a) True
Answer: a b) False
Explanation: The device which receives
the commands from the initiator for Answer: a
data transfer. Explanation: None.

5. In synchronous BUS, the devices get 9. Which is fed into the BUS first by the
the timing signals from initiator?
a) Timing generator in the device a) Data
b) A common clock line b) Address
c) Timing signals are not used at all c) Commands or controls
d) None of the mentioned d) Address, Commands or controls

Answer: b Answer: d
Explanation: The devices receive their Explanation: None.
timing signals from the clock line of the
BUS. 10. signal is used as an
acknowledgement signal by the slave in
Multiple cycle transfers. c) After the slave gets the commands
a) Ack signal d) None of the mentioned
b) Slave ready signal
c) Master ready signal Answer: b
d) Slave received signal Explanation: This signal is activated by
the master to tell the slave that the
Answer: b required commands are on the BUS.
Explanation: The slave once it receives
the commands and address from the 4. In IBM’s S360/370 systems lines
master strobes the ready line indicating are used to select the I/O devices.
to the master that the commands are a) SCAN in and out
received. b) Connect
c) Search
d) Peripheral
1. The master indicates that the address
is loaded onto the BUS, by activating Answer: a
signal. Explanation: The signal is used to scan
a) MSYN and connect to input or output devices.
b) SSYN
c) WMFC 5. The meter in and out lines are used
d) INTR for
a) Monitoring the usage of devices
Answer: a b) Monitoring the amount of data
Explanation: The signal activated by transferred
the master in the asynchronous mode of c) Measure the CPU usage
transmission is used to intimate the d) None of the mentioned
slave the required data is on the BUS.
Answer: a
2. The devices with variable speeds are Explanation: The line is used to monitor
usually connected using asynchronous the usage of the device for a process.
BUS.
a) True 6. MRDC stands for
b) False a) Memory Read Enable
b) Memory Ready Command
Answer: a c) Memory Re-direct Command
Explanation: The devices with variable d) None of the mentioned
speeds are connected using
asynchronous BUS, as the devices share Answer: b
a master-slave relationship. Explanation: The command is used to
initiate a read from memory operation.
3. The MSYN signal is initiated
7. The BUS that allows I/O, memory and
a) Soon after the address and commands Processor to coexist is
are loaded a) Attributed BUS
b) Soon after the decoding of the b) Processor BUS
address
c) Backplane BUS Answer: a
d) External BUS Explanation: The interface circuits act
as a hardware interface between the
Answer: c device and the software side.
Explanation: None.
2. The side of the interface circuits, that
8. The transmission on the asynchronous has the data path and the control signals
BUS is also called to transfer data between interface and
a) Switch mode transmission device is
b) Variable transfer a) BUS side
c) Bulk transfer b) Port side
d) Hand-Shake transmission c) Hardwell side
d) Software side
Answer: d
Explanation: The asynchronous Answer: b
transmission is termed as Hand-Shake Explanation: This side connects the
transfer because the master intimates device to the motherboard.
the slave after each step of the transfer.
3. What is the interface circuit?
9. Asynchronous mode of transmission is a) Helps in installing of the software
suitable for systems with multiple driver for the device
peripheral devices. b) Houses the buffer that helps in data
a) True transfer
b) False c) Helps in the decoding of the address
on the address BUs
Answer: a d) None of the mentioned
Explanation: This mode of transmission
is suitable for multiple device situation Answer: c
as it supports variable speed transfer. Explanation: Once the address is put on
the BUS the interface circuit decodes
10. The asynchronous BUS mode of the address and uses the buffer space to
transmission allows for a faster mode of transfer data.
data transfer.
a) True 4. The conversion from parallel to serial
b) False data transmission and vice versa takes
place inside the interface circuits.
Answer: b a) True
Explanation: None. b) False

Answer: a
1. serves as an intermediary Explanation: By doing this the interface
between the device and the BUSes. circuits provide a better interconnection
a) Interface circuits between devices.
b) Device drivers
c) Buffers 5. The parallel mode of communication
d) None of the mentioned is not suitable for long devices because
of a) Mouse
a) Timing skew b) Magnetic disk
b) Memory access delay c) Visual display terminal
c) Latency d) Card punch
d) None of the mentioned
Answer: a
Answer: a Explanation: In batch processing
Explanation: None. systems the processes are grouped into
batches and they’re executed in
6. The Interface circuits generate the batches.
appropriate timing signals required by
the BUS control scheme. 10. The use of spooler programs or
a) True Hardware allows PC operators
b) False to do the processing work at the same
time a printing operation is in progress.
Answer: a a) Registers
Explanation: The interface circuits b) Memory
generate the required clock signal for c) Buffer
the synchronous mode of transfer. d) CPU

7. The status flags required for data Answer: c

transfer is present in Explanation: When the processor is
a) Device busy with the process the data to be
b) Device driver printed is stored in the buffer.
c) Interface circuit
d) None of the mentioned
1. is used as an intermediate to
Answer: c extend the processor BUS.
Explanation: The circuit holds the flags a) Bridge
which are required for data transfers. b) Router
c) Connector
8. User programmable terminals that d) Gateway
combine VDT hardware with built-in
microprocessor is Answer: a
a) KIPs Explanation: The bridge circuit is
b) Pc basically used to extend the processor
c) Mainframe BUS to connect devices.
d) Intelligent terminals
2. is an extension of the
Answer: d processor BUS.
Explanation: None. a) SCSI BUS
b) USB
9. Which most popular input device is c) PCI BUS
used today for interactive processing d) None of the mentioned
and for the one line entry of data for
batch processing?
Answer: c Answer: b
Explanation: The PCI BUS is used as an Explanation: The SCSI BUS is used to
extension of the processor BUS and connect disks and video controllers.
devices connected to it, is like
connected to the Processor itself. 7. ISO stands for
a) International Standards Organisation
3. What is the full form of ISA? b) International Software Organisation
a) International American Standard c) Industrial Standards Organisation
b) Industry Standard Architecture d) Industrial Software Organisation
c) International Standard Architecture
d) None of the mentioned Answer: a
Explanation: The ISO is yet another
Answer: b architectural standard, used to design
Explanation: The ISA is an architectural systems.
standard developed by IBM for its PC’s.
8. The system developed by IBM with ISA
4. What is the full form of ANSI? architecture is
a) American National Standards Institute a) SPARC
b) Architectural National Standards b) SUN-SPARC
Institute c) PC-AT
c) Asian National Standards Institute d) None of the mentioned
d) None of the mentioned
Answer: c
Answer: a Explanation: None.
Explanation: The ANSI is one of the
standard architecture used by companies 9. IDE disk is connected to the PCI BUS
in designing the systems. using interface.
a) ISA
5. The video devices are connected to b) ISO
BUS. c) ANSI
a) PCI d) IEEE
b) USB
c) HDMI Answer: a
d) SCSI Explanation: None.

Answer: d 10. IDE stands for

Explanation: The SCSI BUS is used to a) Integrated Device Electronics
connect the video devices to a processor b) International Device Encoding
by providing a parallel BUS. c) Industrial Decoder Electronics
d) International Decoder Encoder
6. SCSI stands for
a) Signal Computer System Interface Answer: a
b) Small Computer System Interface Explanation: The IDE interface is used
c) Small Coding System Interface to connect the hard disk to the
d) Signal Coding System Interface processor in most of the Pentium
processors.
 4. The output of the encoder circuit
1. The circuit enables the is/are
generation of the ASCII code when the a) ASCII code
key is pressed. b) ASCII code and the valid signal
a) Generator c) Encoded signal
b) Debouncing d) None of the mentioned
c) Encoder
d) Logger Answer: b
Explanation: The encoder outputs the
Answer: c ASCII value along with the valid signal
Explanation: The signal generated upon which indicates that a key was pressed.
the pressing of a button is encoded by
the encoder circuit into the 5. The disadvantage of using a parallel
corresponding ASCII value. mode of communication is
a) It is costly
2. To overcome multiple signals being b) Leads to erroneous data transfer
generated upon a single press of the c) Security of data
button, we make use of d) All of the mentioned
a) Generator circuit
b) Debouncing circuit Answer: a
c) Multiplexer Explanation: The parallel mode of data
d) XOR circuit transfer is costly as it involves data
being sent over parallel lines.
Answer: b
Explanation: When the button is 6. In a 32 bit processor, the A0 bit of the
pressed, the contact surfaces bounce address line is connected to of the
and hence it might lead to the parallel port interface.
generation of multiple signals. In order a) Valid bit
to overcome this, we use Debouncing b) Idle bit
circuits. c) Interrupt enable bit
d) Status or data register
3. The best mode of connection between
devices which need to send or receive Answer: d
large amounts of data over a short Explanation: None.
distance is
a) BUS 7. The Status flag circuit is implemented
b) Serial port using
c) Parallel port a) RS flip flop
d) Isochronous port b) D flip flop
c) JK flip flop
Answer: c d) Xor circuit
Explanation: The parallel port transfers
around 8 to 16 bits of data Answer: b
simultaneously over the lines, hence Explanation: The circuit is implemented
increasing transfer rates. using the edge triggered D flip flop, that
is triggered on the rising edge of the Answer: d
valid signal. Explanation: In the isochronous mode
of transmission, each bit of the data is
8. In the output interface of the parallel sent per each cycle.
port, along with the valid signal
is also sent. 2. The transformation between the
a) Data Parallel and serial ports is done with the
b) Idle signal help of
c) Interrupt a) Flip flops
d) Acknowledge signal b) Logic circuits
c) Shift registers
Answer: b d) None of the mentioned
Explanation: The idle signal is used to
check if the device is idle and ready to Answer: c
receive data. Explanation: The Shift registers are
used to output the data in the desired
9. DDR stands for format based on the need.
a) Data Direction Register
b) Data Decoding Register 3. The serial port is used to connect
c) Data Decoding Rate basically and processor.
d) None of the mentioned a) I/O devices
b) Speakers
Answer: a c) Printer
Explanation: This register is used to d) Monitor
control the flow of data from the
DATAOUT register. Answer: a
Explanation: The serial port is used to
10. In a general 8-bit parallel interface, connect the keyboard and other devices
the INTR line is connected to which input or output one bit at a time.
a) Status and Control unit
b) DDR 4. The double buffer is used for
c) Register select
d) None of the mentioned a) Enabling retrieval of multiple bits of
input
Answer: a b) Combining the input and output
Explanation: None. operations
c) Extending the buffer capacity
d) None of the mentioned
1. The mode of transmission of data,
where one bit is sent for each clock Answer: a
cycle is Explanation: None.
a) Asynchronous
b) Parallel 5. to increase the flexibility of
c) Serial the serial ports.
d) Isochronous a) The wires used for ports is changed
b) The ports are made to allow different
clock signals for input and output 9. The standard used in serial ports to
c) The drivers are modified facilitate communication is
d) All of the mentioned a) RS-246
b) RS-LNK
Answer: b c) RS-232-C
Explanation: The ports are made more d) Both RS-246 and RS-LNK
flexible by enabling the input or output
of different clock signals for different Answer: c
devices. Explanation: This is a standard that
acts as a protocol for message
6. UART stands for communication involving serial ports.
a) Universal Asynchronous Relay
Transmission 10. In a serial port interface, the INTR
b) Universal Accumulator Register line is connected to
Transfer a) Status register
c) Universal Asynchronous Receiver b) Shift register
Transmitter c) Chip select
d) None of the mentioned d) None of the mentioned

Answer: c Answer: a
Explanation: The UART is a standard Explanation: None.
developed for designing serial ports.

7. The key feature of UART is 1. The PCI follows a set of standards

a) Its architectural design primarily used in PC’s.
b) Its simple implementation a) Intel
c) Its general purpose usage b) Motorola
d) Its enhancement of connecting low c) IBM
speed devices d) SUN

Answer: d Answer: c
Explanation: None. Explanation: The PCI BUS has a closer
resemblance to IBM architecture.
8. The data transfer in UART is done in
2. The is the BUS used in
a) Asynchronous start stop format Macintosh PC’s.
b) Synchronous start stop format a) NuBUS
c) Isochronous format b) EISA
d) EBDIC format c) PCI
d) None of the mentioned
Answer: a
Explanation: This basically means that Answer: a
the data transfer is done in Explanation: The NuBUS is an extension
asynchronous mode. of the processor BUS in Macintosh PC’s.
3. The key feature of the PCI BUS is 7. provides a separate physical
connection to the memory.
a) Low cost connectivity a) PCI BUS
b) Plug and Play capability b) PCI interface
c) Expansion of Bandwidth c) PCI bridge
d) None of the mentioned d) Switch circuit

Answer: b Answer: c
Explanation: The PCI BUS was the first Explanation: The PCI bridge is a circuit
to introduce plug and play interface for that acts as a bridge between the BUS
I/O devices. and the memory.

4. PCI stands for 8. When transferring data over the PCI

a) Peripheral Component Interconnect BUS, the master as to hold the address
b) Peripheral Computer Internet until the completion of the transfer to
c) Processor Computer Interconnect the slave.
d) Processor Cable Interconnect a) True
b) False
Answer: a
Explanation: The PCI BUS is used as an Answer: b
extension for the processor BUS. Explanation: The address is stored by
the slave in a buffer and hence it is not
5. The PCI BUS supports address required by the master to hold it.
space/s.
a) I/O 9. The master is also called as in
b) Memory PCI terminology.
c) Configuration a) Initiator
d) All of the mentioned b) Commander
c) Chief
Answer: d d) Starter
Explanation: The PCI BUS is mainly built
to provide a wide range of connectivity Answer: a
for devices. Explanation: The Master is also called
as an initiator in PCI terminology as it is
6. address space gives the PCI its the one that initiates a data transfer.
plug and plays capability.
a) Configuration 10. Signals whose names end in are
b) I/O asserted in the low voltage state.
c) Memory a) $
d) All of the mentioned b) #
c) *
Answer: a d) !
Explanation: The configuration address
space is used to store the details of the Answer: b
connected device. Explanation: None.
1. A complete transfer operation over to indicate the time required by the
the BUS, involving the address and a device.
burst of data is called
a) Transaction 5. signal is used to enable
b) Transfer commands.
c) Move a) FRAME#
d) Procedure b) IRDY#
c) TMY#
Answer: a d) c/BE#
Explanation: None.
Answer: d
2. The device connected to the BUS are Explanation: The signal is used to
given addresses of bit. enable 4 command lines.
a) 24
b) 64 6. IRDY# signal is used for
c) 32 a) Selecting the interrupt line
d) 16 b) Sending an interrupt
c) Saying that the initiator is ready
Answer: b d) None of the mentioned
Explanation: Each of the devices
connected to the BUS will be allocated Answer: c
an address during the initialization Explanation: The initiator transmits this
phase. signal to tell the target that it is ready.

3. The PCI BUS has interrupt 7. The signal used to indicate that the
request lines. slave is ready is
a) 6 a) SLRY#
b) 1 b) TRDY#
c) 4 c) DSDY#
d) 3 d) None of the mentioned

Answer: c Answer: b
Explanation: The interrupt request lines Explanation: None.
are used by the devices connected to
raise the interrupts. 8. DEVSEL# signal is used
a) To select the device
4. signal is sent by the initiator to b) To list all the devices connected
indicate the duration of the transaction. c) By the device to indicate that it is
a) FRAME# ready for a transaction
b) IRDY# d) None of the mentioned
c) TMY#
d) SELD# Answer: c
Explanation: This is signal is activated
Answer: a by the device after it as recognized the
Explanation: The FRAME signal is used address and commands put on the BUS.
9. The signal used to initiate device Answer: d
select Explanation: The initiator involves in
a) IRDY# the arbitration process and after winning
b) S/BE the BUS it’ll hand over the control to the
c) DEVSEL# target controller.
d) IDSEL#
3. In SCSI transfers the processor is not
Answer: d aware of the data being transferred.
Explanation: This signal is used to a) True
initialization of device select. b) False

10. The PCi BUS allows us to connect Answer: a

I/O devices. Explanation: The processor or the
a) 21 controller is unaware of the data being
b) 13 transferred.
c) 9
d) 11 4. What is DB(P) line?
a) That the data line is carrying the
Answer: a device information
Explanation: The PCI BUS allows only 21 b) That the data line is carrying the
devices to be connected as only the parity information
higher order 21 bits of the 32 bit address c) That the data line is partly closed
space is used to specify the device. d) That the data line is temporarily
occupied

1. The key features of the SCSI BUS are Answer: b

Explanation: None.
a) The cost effective connective media
b) The ability overlap data transfer 5. The BSY signal signifies
requests a) The BUs is busy
c) The highly efficient data transmission b) The controller is busy
d) None of the mentioned c) The Initiator is busy
d) The Target is Busy
Answer: b
Explanation: The SCSI BUS can overlap Answer: a
various data transfer requests by the Explanation: This signal is generally
devices. initiated when the BUS is currently
occupied in an operation.
2. In a data transfer operation involving
SCSI BUS, the control is with 6. The SEL signal signifies
a) Initiator a) The initiator is selected
b) Target b) The device for BUS control is selected
c) SCSI controller c) That the target is being selected
d) Target Controller d) None of the mentioned
Answer: b Answer: a
Explanation: This signal is usually Explanation: The SCSI uses distributed
asserted during the selection or arbitration to select the device to give
reselection process. the BUS control.

7. signal is asserted when the

initiator wishes to send a message to the 1. SCSI stands for
target. a) Small Computer System Interface
a) MSG b) Switch Computer system Interface
b) APP c) Small Component System Interface
c) SMS d) None of the mentioned
d) ATN
Answer: a
Answer: d Explanation: The SCSI BUS is one of the
Explanation: The ATN signal is short for expansion BUSes used in a system.
attention, which is used to intimate the
target that the initiator sent a message 2. ANSI stands for
to it. a) American National System Interface
b) ASCII National Standard Interface
8. The MSG signal is used c) American Network System Interface
a) To send a message to the target d) American National Standard Institute
b) To receive a message from the
mailbox Answer: d
c) To tell that the information being sent Explanation: This a standard for
is a message designing BUSes and other system
d) None of the mentioned components.

Answer: c 3. A narrow SCSI BUS has data

Explanation: None. lines.
a) 6
9. is used to reset all the device b) 8
controls to their startup state. c) 16
a) SRT d) 4
b) RST
c) ATN Answer: b
d) None of the mentioned Explanation: The SCSI BUS which is
narrow is capable of transferring 8 bits
Answer: b of data at a time.
Explanation: None.
4. Single ended transmission means
10. The SCSI BUS uses
arbitration. a) That all the signals have a similar bit
a) Distributed pattern
b) Centralised b) That the signals have a common
c) Daisy chain source
d) Hybrid c) That the signals have a common
ground return c) Switch
d) That the signals have a similar voltage d) None of the mentioned
signature
Answer: a
Answer: c Explanation: This is used to coordinate
Explanation: These type of signals are a and monitor the data transfer over the
common feature of the SCSI BUS. BUS.

5. HVD stands for 9. The mode of data transfer used by

a) High Voltage Differential the controller is
b) High Voltage Density a) Interrupt
c) High Video Definition b) DMA
d) None of the mentioned c) Asynchronous
d) Synchronous
Answer: a
Explanation: This is a type of signaling Answer: b
which uses 5v of current. Explanation: None.

6. For better transfer rates on the SCSI 10. The data is stored on the disk in the
BUS the length of the cable is limited to form of blocks called
a) Pages
a) 2m b) Frames
b) 4m c) Sectors
c) 1.3m d) Tables
d) 1.6m
Answer: c
Answer: d Explanation: The data is stored on the
Explanation: To increase the disk in the form of a collection of blocks
transmission rate in SCSI in SE mode of called as sectors.
transfer the wire length is restricted to
1.6m.
1. The transfer rate, when the USB is
7. The maximum number of devices that operating in low-speed of operation is
can be connected to SCSI BUS is
a) 12 a) 5 Mb/s
b) 10 b) 12 Mb/s
c) 16 c) 2.5 Mb/s
d) 8 d) 1.5 Mb/s

Answer: c Answer: d
Explanation: None. Explanation: The USB has two rates of
operation the low-speed and the full-
8. The SCSI BUS is connected to the speed one.
processor through
a) SCSI Controller 2. The high speed mode of operation of
b) Bridge the USB was introduced by
a) ISA 6. USB is a parallel mode of transmission
b) USB 3.0 of data and this enables for the fast
c) USB 2.0 speeds of data transfers.
d) ANSI a) True
b) False
Answer: c
Explanation: The high-speed mode of Answer: b
operation was introduced with USB 2.0, Explanation: The USB does a serial
which enabled the USB to operate at 480 mode of data transfer.
Mb/s.
7. In USB the devices can communicate
3. The sampling process in speaker with each other.
output is a process. a) True
a) Asynchronous b) False
b) Synchronous
c) Isochronous Answer: b
d) None of the mentioned Explanation: It allows only the host to
communicate with the devices and not
Answer: c between themselves.
Explanation: The isochronous process
means each bit of data is separated by a 8. The device can send a message to the
time interval. host by taking part in for the
communication path.
4. The USB device follows a) Arbitration
structure. b) Polling
a) List c) Prioritizing
b) Huffman d) None of the mentioned
c) Hash
d) Tree Answer: b
Explanation: None.
Answer: d
Explanation: The USB has a tree 9. When the USB is connected to a
structure with the root hub at the system, its root hub is connected to the
centre.
a) PCI BUS
5. The I/O devices form the of the b) SCSI BUS
tree structure. c) Processor BUS
a) Leaves d) IDE
b) Subordinate roots
c) Left subtrees Answer: c
d) Right subtrees Explanation: The USB’s root is
connected to the processor directly
Answer: a using the BUS.
Explanation: The I/o devices form the
leaves of the structure. 10. The devices connected to USB is
assigned a address.
a) 9 bit c) Full-Duplex
b) 16 bit d) Both Simplex and Full-Duplex
c) 4 bit
d) 7 bit Answer: c
Explanation: This means that the pipe
Answer: d is bi-directional in sending messages or
Explanation: To make it easier for information.
recognition the devices are given 7 bit
addresses. 15. The type/s of packets sent by the
USB is/are
11. The USB address space can be shared a) Data
by the user’s memory space. b) Address
a) True c) Control
b) False d) Both Data and Control

Answer: b Answer: d
Explanation: The USB memory space is Explanation: This means that the USB
not under any address spaces and cannot gets both data and control signals
be accessed. required for the transfer operation.

12. The initial address of a device just

connected to the HUB is 1. The first field of any packet is
a) AHFG890 a) PID
b) 0000000 b) ADDR
c) FFFFFFF c) ENDP
d) 0101010 d) CRC16

Answer: b Answer: a
Explanation: By standard, the usual Explanation: The PID is the field that is
address of a new device is zero. used to identify the device (the device
id).
13. Locations in the device to or from
which data transfers can take place is 2. The 4 bit PID’s are transmitted twice.
called a) True
a) End points b) False
b) Hosts
c) Source Answer: a
d) None of the mentioned Explanation: The fields are transmitted
twice, once with the true values and the
Answer: a second time with the complemented
Explanation: None. values.

14. A USB pipe is a channel. 3. The last field in the packet is

a) Simplex a) PID
b) Half-Duplex b) ADDR
c) ENDP c) Packets
d) CRC d) Tokens

Answer: d Answer: a
Explanation: The last 5 bits of the Explanation: To support the isochronous
packet is used for error checking, that is mode of operation the usb transmission
cyclic redundancy check. is divided into frames.

4. The CRC bits are computed based on 8. The signal is used to indicate
the values of the the beginning of a new frame.
a) PID a) Start
b) ADDR b) SOF
c) ENDP c) BEG
d) Both ADDR and ENDP d) None of the mentioned

Answer: d Answer: b
Explanation: The CRC bits are Explanation: The SOF(State Of Frame)
calculated based on the values of the is used to indicate the beginning of a
address and endp. new frame.

5. The data packets can contain data 9. The SOF is transmitted every
upto a) 1s
a) 512 bytes b) 5s
b) 256 bytes c) 1ms
c) 1024 bytes d) 1Us
d) 2 KB
Answer: c
Answer: c Explanation: None.
Explanation: None.
10. The power specification of usb is
6. The most important objective of the
USB is to provide a) 5v
a) Isochronous transmission b) 10v
b) Plug and play c) 24v
c) Easy device connection d) 10v
d) All of the mentioned
Answer: a
Answer: d Explanation: None.
Explanation: The above are all the
common features of the USB.

7. The transmission over the USB is

divided into
a) Frames UNIT II ARITHMETIC FOR
b) Pages COMPUTERS
1. The logic operations are simpler to 5. In full adders the sum circuit is
implement using logic circuits. implemented using
a) True a) And & or gates
b) False b) NAND gate
c) XOR
Answer: a d) XNOR
Explanation: The logic operation
includes AND, OR, XOR etc. Answer: c
Explanation: sum = a ^ b ^ c (‘^’
2. The logic operations are implemented indicates XOR operation).
using circuits.
a) Bridge 6. The usual implementation of the carry
b) Logical circuit involves
c) Combinatorial a) And & or gates
d) Gate b) XOR
c) NAND
Answer: c d) XNOR
Explanation: The combinatorial circuits
means, using the basic universal gates. Answer: b
Explanation: In case of full and half
3. The carry generation function: ci + 1 adders this method is used.
= yici + xici + xiyi, is implemented in
7. A gate is used to detect the
a) Half adders occurrence of an overflow.
b) Full adders a) NAND
c) Ripple adders b) XOR
d) Fast adders c) XNOR
d) AND
Answer: b
Explanation: In this the carry for the Answer: b
next step is generated in the previous Explanation: The overflow is detected
steps operation. by cn^cn-1 (‘^’ indicates XOR
operation).
4. Which option is true regarding the
carry in the ripple adders? 8. In a normal adder circuit, the delay
a) Are generated at the beginning only obtained in a generation of the output is
b) Must travel through the configuration
c) Is generated at the end of each a) 2n + 2
operation b) 2n
d) None of the mentioned c) n + 2
d) None of the mentioned
Answer: b
Explanation: The carry must pass Answer: a
through the configuration of the circuit Explanation: The 2n delay cause of the
till it reaches the particular step. carry generation and the 2 delay cause
of the XOR operation.
9. The final addition sum of the c) Cache
numbers, 0110 & 0110 is d) None of the mentioned
a) 1101
b) 1111 Answer: b
c) 1001 Explanation: The value is stored in a
d) 1010 shift register so that each bit can be
accessed separately.
Answer: a
Explanation: None. 4. The is used to coordinate the
operation of the multiplier.
10. The delay reduced to in the carry a) Controller
look ahead adder is b) Coordinator
a) 5 c) Control sequencer
b) 8 d) None of the mentioned
c) 10
d) 2n Answer: c
Explanation: This performs the required
Answer: a sequencing of the various parts of the
Explanation: None. circuit.

5. The multiplicand and the control

1. The product of 1101 & 1011 is signals are passed through to the n-bit
a) 10001111 adder via
b) 10101010 a) MUX
c) 11110000 b) DEMUX
d) 11001100 c) Encoder
d) Decoder
Answer: a
Explanation: The above operation is Answer: a
performed using binary multiplication. Explanation: None.

2. We make use of circuits to 6. The product of -13 & 11 is

implement multiplication.
a) Flip flops a) 1100110011
b) Combinatorial b) 1101110001
c) Fast adders c) 1010101010
d) None of the mentioned d) 1111111000

Answer: c Answer: b
Explanation: The fast adders are used Explanation: None.
to add the multiplied numbers.
7. The method used to reduce the
3. The multiplier is stored in maximum number of summands by half
a) PC Register is
b) Shift register a) Fast multiplication
b) Bit-pair recording
c) Quick multiplication Answer: a
d) None of the mentioned Explanation: By doing this the
computer is capable of accommodating
Answer: b the large float numbers also.
Explanation: It reduces the number of
summands by concatenating them. 2. The numbers written to the power of
10 in the representation of decimal
8. The bits 1 & 1 are recorded as numbers are called as
in bit-pair recording. a) Height factors
a) -1 b) Size factors
b) 0 c) Scale factors
c) +1 d) None of the mentioned
d) both -1 and 0
Answer: c
Answer: d Explanation: These are called as scale
Explanation: Its ‘-1’ when the previous factors cause they’re responsible in
bit is 0 and ‘0’ when the previous bit is determining the degree of specification
1. of a number.

9. The multiplier -6(11010) is recorded 3. If the decimal point is placed to the

as right of the first significant digit, then
a) 0-1-2 the number is called
b) 0-1+1-10 a) Orthogonal
c) -2-10 b) Normalized
d) None of the mentioned c) Determinate
d) None of the mentioned
Answer: a
Explanation: None. Answer: b
Explanation: None.
10. CSA stands for?
a) Computer Speed Addition 4. constitute the
b) Carry Save Addition representation of the floating number.
c) Computer Service Architecture a) Sign
d) None of the mentioned b) Significant digits
c) Scale factor
Answer: a d) All of the mentioned
Explanation: The CSA is used to speed
up the addition of multiplicands. Answer: d
Explanation: The following factors are
responsible for the representation of the
1. The decimal numbers represented in number.
the computer are called as floating point
numbers, as the decimal point floats 5. The sign followed by the string of
through the number. digits is called as
a) True a) Significant
b) False b) Determinant
c) Mantissa c) 0 to 255
d) Exponent d) None of the mentioned

Answer: c Answer: a
Explanation: The mantissa also consists Explanation: Since the exponent field
of the decimal point. has only 8 bits to store the value.

6. In IEEE 32-bit representations, the 10. In double precision format, the size
mantissa of the fraction is said to occupy of the mantissa is
bits. a) 32 bit
a) 24 b) 52 bit
b) 23 c) 64 bit
c) 20 d) 72 bit
d) 16
Answer: b
Answer: b Explanation: The double precision
Explanation: The mantissa is made to format is also called as 64 bit
occupy 23 bits, with 8 bit exponent. representation.

7. The normalized representation of

0.0010110 * 2 9 is 1. have been developed
a) 0 10001000 0010110 specifically for pipelined systems.
b) 0 10000101 0110 a) Utility software
c) 0 10101010 1110 b) Speed up utilities
d) 0 11110100 11100 c) Optimizing compilers
d) None of the mentioned
Answer: b
Explanation: Normalized representation Answer: c
is done by shifting the decimal point. Explanation: The compilers which are
designed to remove redundant parts of
8. The 32 bit representation of the the code are called as optimizing
decimal number is called as compilers.

a) Double-precision 2. The pipelining process is also called

b) Single-precision as
c) Extended format a) Superscalar operation
d) None of the mentioned b) Assembly line operation
c) Von Neumann cycle
Answer: b d) None of the mentioned
Explanation: None.
Answer: b
9. In 32 bit representation the scale Explanation: It is called so because it
factor as a range of performs its operation at the assembly
a) -128 to 127 level.
b) -256 to 255
3. The fetch and execution cycles are 7. To increase the speed of memory
interleaved with the help of access in pipelining, we make use of
a) Modification in processor architecture
b) Clock a) Special memory locations
c) Special unit b) Special purpose registers
d) Control unit c) Cache
d) Buffers
Answer: b
Explanation: The time cycle of the Answer: c
clock is adjusted to perform the Explanation: By using the cache we can
interleaving. reduce the speed of memory access by a
factor of 10.
4. Each stage in pipelining should be
completed within cycle. 8. The periods of time when the unit is
a) 1 idle is called as
b) 2 a) Stalls
c) 3 b) Bubbles
d) 4 c) Hazards
d) Both Stalls and Bubbles
Answer: a
Explanation: The stages in the Answer: d
pipelining should get completed within Explanation: The stalls are a type of
one cycle to increase the speed of hazards that affect a pipelined system.
performance.
9. The contention for the usage of a
5. In pipelining the task which requires hardware device is called
the least time is performed first. a) Structural hazard
a) True b) Stalk
b) False c) Deadlock
d) None of the mentioned
Answer: b
Explanation: This is done to avoid Answer: a
starvation of the longer task. Explanation: None.

6. If a unit completes its task before the 10. The situation wherein the data of
allotted time period, then operands are not available is called
a) It’ll perform some other task in the
remaining time a) Data hazard
b) Its time gets reallocated to a b) Stock
different task c) Deadlock
c) It’ll remain idle for the remaining d) Structural hazard
time
d) None of the mentioned Answer: a
Explanation: Data hazards are generally
Answer: c caused when the data is not ready on
Explanation: None. the destination side.
 Answer: b
1. The throughput of a super scalar Explanation: The processor since as
processor is executed the following instructions even
a) less than 1 though an exception was raised, hence
b) 1 the exception is treated as imprecise.
c) More than 1
d) Not Known 5. In super-scalar mode, all the similar
instructions are grouped and executed
Answer: c together.
Explanation: The throughput of a a) True
processor is measured by using the b) False
number of instructions executed per
second. Answer: a
Explanation: The instructions are
2. When the processor executes multiple grouped meaning that the instructions
instructions at a time it is said to use fetch and decode and other cycles are
overlapped.
a) single issue
b) Multiplicity 6. In super-scalar processors,
c) Visualization mode of execution is used.
d) Multiple issues a) In-order
b) Post order
Answer: d c) Out of order
Explanation: None. d) None of the mentioned

3. The plays a very vital role in Answer: c

case of super scalar processors. Explanation: It follows out of order
a) Compilers execution to speed up the execution of
b) Motherboard instructions.
c) Memory
d) Peripherals 7. Since it uses the out of order mode of
execution, the results are stored in
Answer: a
Explanation: The compilers are a) Buffers
programmed to arrange the instructions b) Special memory locations
to get more throughput. c) Temporary registers
d) TLB
4. If an exception is raised and the
succeeding instructions are executed Answer: c
completely, then the processor is said to Explanation: The results are stored in
have temporary locations and are arranged
a) Exception handling afterward.
b) Imprecise exceptions
c) Error correction 8. The step where in the results stored
d) None of the mentioned in the temporary register is transferred
into the permanent register is called as
 2. The computer architecture aimed at
a) Final step reducing the time of execution of
b) Commitment step instructions is
c) Last step a) CISC
d) Inception step b) RISC
c) ISA
Answer: b d) ANNA
Explanation: None.
Answer: b
9. A special unit used to govern the out Explanation: The RISC stands for
of order execution of the instructions is Reduced Instruction Set Computer.
called as
a) Commitment unit 3. The Sun micro systems processors
b) Temporal unit usually follow architecture.
c) Monitor a) CISC
d) Supervisory unit b) ISA
c) ULTRA SPARC
Answer: a d) RISC
Explanation: This unit monitors the
execution of the instructions and makes Answer: d
sure that the final result is in order. Explanation: The Risc machine aims at
reducing the instruction set of the
10. The commitment unit uses a queue computer.
called
a) Record buffer 4. The RISC processor has a more
b) Commitment buffer complicated design than CISC.
c) Storage buffer a) True
d) None of the mentioned b) False

Answer: a Answer: b
Explanation: None. Explanation: The RISC processor design
is more simpler than CISC and it consists
of fewer transistors.
1. The CISC stands for
a) Computer Instruction Set Compliment 5. The iconic feature of the RISC
b) Complete Instruction Set Compliment machine among the following is
c) Computer Indexed Set Components a) Reduced number of addressing modes
d) Complex Instruction set computer b) Increased memory size
c) Having a branch delay slot
Answer: d d) All of the mentioned
Explanation: CISC is a computer
architecture where in the processor Answer: c
performs more complex operations in Explanation: A branch delay slot is an
one step. instruction space immediately following
a jump or branch.
6. Both the CISC and RISC architectures and the instructions take over a cycle to
have been developed to reduce the complete.

a) Cost 10. Which of the architecture is power

b) Time delay efficient?
c) Semantic gap a) CISC
d) All of the mentioned b) RISC
c) ISA
Answer: c d) IANA
Explanation: The semantic gap is the
gap between the high level language and Answer: b
the low level language. Explanation: Hence the RISC
architecture is followed in the design of
7. Out of the following which is not a mobile devices.
CISC machine.
a) IBM 370/168
b) VAX 11/780
c) Intel 80486
d) Motorola A567
UNIT III PROCESSOR AND
Answer: d CONTROL UNIT
Explanation: None.
1. For converting a virtual address into
8. Pipe-lining is a unique feature of the physical address, the programs are
divided into
a) RISC
a) Pages
b) CISC
b) Frames
c) ISA
c) Segments
d) IANA
d) Blocks
Answer: a
Answer: a
Explanation: The RISC machine
Explanation: On the physical memory
architecture was the first to implement
side the memory is divided into pages.
pipe-lining.
2. The memory allocated to each page is
9. In CISC architecture most of the
contiguous.
complex instructions are stored in
a) True
a) Register
b) False
b) Diodes
c) CMOS Answer: a
d) Transistors Explanation: Each page might be
allocated memory deferentially but the
Answer: d
memory for one page will be continuous.
Explanation: In CISC architecture more
emphasis is given on the instruction set 3. The pages size shouldn’t be too small,
as this would lead to
a) Transfer errors to one particular entry in the page
b) Increase in operation time table.
c) Increase in access time
d) Decrease in performance 7. The page length shouldn’t be too long
because
Answer: c a) It reduces the program efficiency
Explanation: The access time of the b) It increases the access time
magnetic disk is much longer than the c) It leads to wastage of memory
access time of the memory. d) None of the mentioned

4. The cache bridges the speed gap Answer: c

between and Explanation: If the size is more than
a) RAM and ROM the required size then the extra space
b) RAM and Secondary memory gets wasted.
c) Processor and RAM
d) None of the mentioned 8. The lower order bits of the virtual
address forms the
Answer: c a) Page number
Explanation: The Cache is a hardware b) Frame number
implementation to reduce the access c) Block number
time for processor operations. d) Offset

5. The virtual memory bridges the size Answer: d

and speed gap between and Explanation: This gives the offset
within the page table.
a) RAM and ROM
b) RAM and Secondary memory 9. The area in the main memory that
c) Processor and RAM can hold one page is called as
d) None of the mentioned
a) Page entry
Answer: b b) Page frame
Explanation: The virtual memory c) Frame
basically works as an extension of the d) Block
RAM.
Answer: b
6. The higher order bits of the virtual Explanation: None.
address generated by the processor
forms the 10. The starting address of the page
a) Table number table is stored in
b) Frame number a) TLB
c) List number b) R0
d) Page number c) Page table base register
d) None of the mentioned
Answer: d
Explanation: The higher order bits Answer: c
indicate the page number which points Explanation: The register is used to
hold the address which is used to access Answer: c
the table. Explanation: The page table
information is used for every read and
access operation.
1. The bits used to indicate the status of
the page in the memory is called 5. If the page table is large then it is
a) Control bits stored in
b) Status bits a) Processor
c) Progress bit b) Main memory
d) None of the mentioned c) Disk
d) Secondary storage
Answer: a
Explanation: These bits are used to Answer: b
store the status information of the Explanation: By storing the table on the
program. RAM the required operation’s speed is
increased.
2. The bit is used to indicate
the validity of the page. 6. When the page table is placed in the
a) Valid bit main memory, the is used
b) Invalid bit to store the recently accessed pages.
c) Correct bit a) MMU
d) None of the mentioned b) TLB
c) R0
Answer: a d) Table
Explanation: The os first validates the
page and then only moves from the page Answer: b
table. Explanation: The TLB is used to store
the page numbers of the recently
3. The bit used to store whether the accessed pages.
page has been modified or not is called
as 7. The TLB is incorporated as part of the
a) Dirty bit
b) Modify bit a) Processor
c) Relocation bit b) MMU
d) None of the mentioned c) Disk
d) RAM
Answer: a
Explanation: This bit is set after the Answer: b
page in the table gets modified. Explanation: None.

4. The page table should be ideally 8. Whenever a request to the page that
situated within is not present in the main memory is
a) Processor accessed is triggered.
b) TLB a) Interrupt
c) MMU b) Request
d) Cache
c) Page fault 2. The word length in the 68000
d) None of the mentioned computer is
a) 32 bit
Answer: c b) 64 bit
Explanation: When a page fault is c) 16 bit
triggered, the os brings the required d) 8 bit
page into memory.
Answer: c
9. The general purpose registers are Explanation: The length of an
combined into a block called as instruction that can be read or accessed
a) Register bank at a time is referred to as word length.
b) Register Case
c) Register file 3. Is 68000 computer Byte addressable?
d) None of the mentioned a) True
b) False
Answer: c
Explanation: To make the access of the Answer: a
registers easier, we classify them into Explanation: The ability of a system to
register files. access the entire data of a process by
reading consecutive bytes is called as
10. What does the RUN signal do? Byte addressability
a) It causes the termination of a signal
b) It causes a particular signal to 4. The register in 68000 can contain up
perform its operation to bits.
c) It causes a particular signal to end a) 24
d) It increments the step counter by one b) 32
c) 16
Answer: d d) 64
Explanation: The RUN signal increments
the step counter by one for each clock Answer: b
cycle. Explanation: None.

5. The 68000 has a max of how many

1. register is designated to point data registers?
to the 68000 processor stack. a) 16
a) A7 register b) 20
b) B2 register c) 10
c) There is no such designation d) 8
d) Any general purpose register is
selected at random Answer: d
Explanation: The data registers are
Answer: a solely used for the purpose of storing
Explanation: The processor stack is the data items of the process.
place used to store the ongoing and
upcoming process information 6. When an operand is stored in a
register it is
a) Stored in the lower order bits of the directly related to the address space of
register the system.
b) Stored in the higher order bits of the
register 10. Instructions which can handle any
c) Stored in any of the bits at random type of addressing mode are said to be
d) None of the mentioned
a) Omniscient
Answer: a b) Orthogonal
Explanation: The data always gets c) Versatile
stored from the lower order to the d) None of the mentioned
higher order bits, except in the case of
Little Endian architecture. Answer: b
Explanation: These instructions do not
7. The status register of the 68000 has require the mentioning of any one type
condition codes. of addressing mode.
a) 7
b) 4
c) 5 1. The instructions in 68000 can deal
d) 8 with operands of three different sizes.
a) True
Answer: c b) False
Explanation: The register which is used
to basically store the condition flags is Answer: a
called as a status register. Explanation: The operands are of
different sizes because of the difference
8. The 68000 uses address in the values.
assignment.
a) Big Endian 2. As the instructions can deal with
b) Little Endian variable size operands we use
c) X-Little Endian to resolve this.
d) X-Big Endian a) Delimiter
b) Size indicator mnemonic
Answer: a c) Special assemblers
Explanation: The way the data gets d) None of the mentioned
stored in a memory is called an address
assignment. Answer: b
Explanation: To indicate the size of the
9. The addresses generated by the 68000 operand we use a separate variable
is bit. mnemonic to indicate it.
a) 32
b) 16 3. The starting address is denoted using
c) 24 directive.
d) 42 a) EQU
b) ORIGIN
Answer: c c) ORG
Explanation: The size of the address is d) PLACE
Answer: c with the branch condition
Explanation: The starting address is the d) None of the mentioned
location where the program is stored.
Answer: d
4. The constant can be declared using Explanation: None.
directive.
a) DATAWORD 8. The 68000 uses method
b) PLACE to access I/O devices buffers.
c) CONS a) Memory mapped
d) DC b) I/O mapped
c) Buffer mapped
Answer: d d) None of the mentioned
Explanation: To declare Global
constants we use this directive. Answer: a
Explanation: In this method, both the
5. To allocate a block of memory we use I/O device and the memory share a
directive. common address space.
a) RESERVE
b) DS 9. instruction is used to
c) DATAWORD set up a frame pointer for the
d) PLACE subroutines in 68000.
a) CREATE
Answer: b b) LINK
Explanation: None. c) UNLK
d) FRAME
6. The Branch instruction in 68000
provides how many types of offsets? Answer: b
a) 3 Explanation: This pointer is used to
b) 1 monitor the stack.
c) 0
d) 2 10. The LINK instruction is always
followed by instruction.
Answer: d a) MOV
Explanation: The Branch instruction b) UNLK
basically just adds a constant value to c) ORG
the address present in the PC, to change d) MOVEM
the instruction to be executed.
Answer: d
7. The purpose of using DBcc as a branch Explanation: None.
instruction is
a) It provides two conditions to be
satisfied for a branch to occur 1. ARM stands for
b) It provides a counter to check the a) Advanced Rate Machines
number of times the branch as taken b) Advanced RISC Machines
place c) Artificial Running Machines
c) It is used to check the condition along d) Aviary Running Machines
Answer: b Answer: d
Explanation: ARM is a type of system Explanation: None.
architecture.
6. The address system supported by ARM
2. The main importance of ARM micro- systems is/are
processors is providing operation with a) Little Endian
b) Big Endian
a) Low cost and low power consumption c) X-Little Endian
b) Higher degree of multi-tasking d) Both Little & Big Endian
c) Lower error or glitches
d) Efficient memory management Answer: d
Explanation: The way in which, the
Answer: a data gets stored in the system or the
Explanation: The Stand alone feature of way of address allocation is called as
the ARM processors is that they’re address system.
economically viable.
7. Memory can be accessed in ARM
3. ARM processors where basically systems by instructions.
designed for i) Store
a) Main frame systems ii) MOVE
b) Distributed systems iii) Load
c) Mobile systems iv) arithmetic
d) Super computers v) logical
a) i, ii, iii
Answer: c b) i, ii
Explanation: These ARM processors are c) i, iv, v
designed for handheld devices. d) iii, iv, v
4. The ARM processors don’t support Answer: b
Byte addressability. Explanation: None.
a) True
b) False 8. RISC stands for
a) Restricted Instruction Sequencing
Answer: b Computer
Explanation: The ability to store data in b) Restricted Instruction Sequential
the form of consecutive bytes. Compiler
c) Reduced Instruction Set Computer
5. The address space in ARM is
d) Reduced Induction Set Computer
a) 224 Answer: c
b) 264 Explanation: This is a system
c) 216 architecture, in which the performance
of the system is improved by reducing
d) 232
the size of the instruction set.
9. In the ARM, PC is implemented using c) 4 byte
d) 8 byte
a) Caches
b) Heaps Answer: c
c) General purpose register Explanation: The data is encrypted to
d) Stack make them secure.

Answer: c 13. All instructions in ARM are

Explanation: PC is the place where the conditionally executed.
next instruction about to be executed is a) True
stored. b) False

10. The additional duplicate register Answer: a

used in ARM machines are called as Explanation: None.

a) Copied-registers 14. The addressing mode where the EA

b) Banked registers of the operand is the contents of Rn is
c) EXtra registers
d) Extential registers a) Pre-indexed mode
b) Pre-indexed with write back mode
Answer: b c) Post-indexed mode
Explanation: The duplicate registers are d) None of the mentioned
used in situations of context switching.
Answer: c
11. The banked registers are used for Explanation: None.

a) Switching between supervisor and 15. The effective address of the

interrupt mode instruction written in Post-indexed
b) Extended storing mode, MOVE[Rn]+Rm is
c) Same as other general purpose a) EA = [Rn]
registers b) EA = [Rn + Rm]
d) None of the mentioned c) EA = [Rn] + Rm
d) EA = [Rm] + Rn
Answer: a
Explanation: When switching from one Answer: a
mode to another, instead of storing the Explanation: Effective address is the
register contents somewhere else it’ll be address that the computer acquires from
kept in the duplicate registers and the the current instruction being executed.
new values are stored in the actual
registers.
1. symbol is used to signify
12. Each instruction in ARM machines is write back mode.
encoded into Word. a) #
a) 2 byte b) ^
b) 3 byte c) &
d) !
Answer: d 5. The ability to shift or rotate in the
Explanation: None. same instruction along with other
operation is performed with the help of
2. The instructions which are used to
load or store multiple operands are a) Switching circuit
called as b) Barrel switcher circuit
a) Banked instructions c) Integrated Switching circuit
b) Lump transfer instructions d) Multiplexer circuit
c) Block transfer instructions
d) DMA instructions Answer: b
Explanation: These switching circuits
Answer: c are used to basically switch fast and to
Explanation: These instructions are perform better.
generally used to perform memory
transfer operations. 6. instruction is used to get
the 1’s complement of the operand.
3. The Instruction, LDM R10!, a) COMP
{R0,R1,R6,R7} b) BIC
a) Loads the contents of R10 into R1, R0, c) ~CMP
R6 and R7 d) MVN
b) Creates a copy of the contents of R10
in the other registers except for the Answer: d
above mentioned ones Explanation: The complement of all the
c) Loads the contents of the registers bits of a data is its 1’s compliment.
R1, R0, R6 and R7 to R10
d) Writes the contents of R10 into the 7. The offset used in the conditional
above mentioned registers and clears branching is bit.
R10 a) 24
b) 32
Answer: a c) 16
Explanation: The LDM instruction is d) 8
used to load data into multiple
locations. Answer: a
Explanation: The offset is used to get
4. The instruction, MLA R0,R1,R2,R3 the new branching address of the
performs process.
a) R0<-[R1]+[R2]+[R3]
b) R3<-[R0]+[R1]+[R2] 8. The BEQ instructions is used
c) R0<-[R1]*[R2]+[R3]
d) R3<-[R0]*[R1]+[R2] a) To check the equality condition
between the operands and then branch
Answer: c b) To check if the Operand is greater
Explanation: The MLA instruction is than the condition value and then
used perform addition and multiplication branch
together. c) To check if the flag Z is set to 1 and
then causes branch Answer: c
d) None of the mentioned Explanation: None.

Answer: c 12. directive specifies the

Explanation: This instruction is start of the execution.
basically used to check the branch a) START
enable bit. b) ENTRY
c) MAIN
9. The condition to check whether the d) ORIGIN
branch should happen or not is given by
Answer: b
a) The lower order 8 bits of the Explanation: This directive indicates
instruction the beginning of the executable part of
b) The higher order 4 bits of the the program.
instruction
c) The lower order 4 bits of the 13. directives are used to
instruction initialize operands.
d) The higher order 8 bits of the a) INT
instruction b) DATAWORD
c) RESERVE
Answer: b d) DCD
Explanation: None.
Answer: d
10. Which of the two instructions sets Explanation: These directives are used
the condition flag upon execution? to initialize the operands to a user
i) ADDS R0,R1,R2 defined value or a default value.
ii) ADD R0,R1,R2
a) i 14. directive is used to
b) ii name the register used for execution of
c) Both i and ii an instruction.
d) Insufficient data a) ASSIGN
b) RN
Answer: a c) NAME
Explanation: This instruction sets the d) DECLARE
condition flag without considering
whether a carry or overflow has Answer: b
happened or not. Explanation: This instruction is used to
list the registers used for execution.
11. directive is used to
indicate the beginning of the program 15. The pseudo instruction used to load
instruction or data. an address into the register is
a) EQU a) LOAD
b) START b) ADR
c) AREA c) ASSIGN
d) SPACE d) PSLOAD
Answer: b Answer: d
Explanation: None. Explanation: The size of the floating
numbers that can be stored in the
floating register.
1. The address space of the IA-32 is
5. The size of the floating registers can
a)216 be extended upto
b) 232 a) 128 bit
b) 256 bit
c) 264
c) 80 bit
d) 28 d) 64 bit
Answer: b Answer: c
Explanation: The number of Explanation: None.
addressable locations in the memory is
called as address space. 6. The IA-32 architecture associates
different parts of memory called
2. The addressing method used in IA-32 with different usages.
is a) Frames
a) Little Endian b) Pages
b) Big Endian c) Tables
c) X-Little Endian d) Segments
d) Both Little and Big Endian
Answer: d
Answer: a Explanation: The memory is divided
Explanation: The method of addressing into parts called as segments.
the data in the system.
7. The PC is incorporated with the help
3. The floating point numbers are stored of general purpose registers.
in general purpose register in IA-32. a) True
a) True b) False
b) False
Answer: b
Answer: b Explanation: Registers are not used to
Explanation: The floating registers are incorporate PC as in other architectures,
not stored in general purpose registers but a separate space is allocated to it.
as they have a real part and a decimal
part. 8. IOPL stands for
a) Input/Output Privilege level
4. The Floating point registers of IA-32 b) Input Output Process Link
can operate on operands up to c) Internal Output Process Link
d) Internal Offset Privilege Level
a) 128 bit
b) 256 bit Answer: a
c) 80 bit Explanation: This indicates the security
d) 64 bit
between the transfers between the I/O Answer: c
devices and memory. Explanation: This is used to extend the
size of the register.
9. In IA-32 architecture along with the
general flags, the other conditional flags 13. The instruction, ADD R1, R2, R3 is
provided are decoded as
a) IOPL a) R1<-[R1]+[R2]+[R3]
b) IF b) R3<-[R1]+[R2]
c) TF c) R3<-[R1]+[R2]+[R3]
d) All of the mentioned d) R1<-[R2]+[R3]

Answer: d Answer: d
Explanation: These flags are basically Explanation: None.
used to check the system for exceptions.
14. The instruction JG loop does
10. The register used to serve as PC is a) jumps to the memory location loop if
called as the result of the most recent arithmetic
a) Indirection register op is even
b) Instruction pointer b) jumps to the memory location loop if
c) R-32 the result of the most recent arithmetic
d) None of the mentioned op is greater than 0
c) jumps to the memory location loop if
Answer: b the test condition is satisfied with the
Explanation: The PC is used to store the value of loop
next instruction that is going to be d) none of the mentioned
executed.
Answer: b
11. The IA-32 processor can switch Explanation: This instruction is used to
between 16 bit operation and 32 bit cause a branch based on the outcome of
operation with the help of instruction the arithmetic operation.
prefix bit.
a) True 15. The LEA mnemonic is used to
b) False
a) Load the effective address of an
Answer: a instruction
Explanation: This switching enables a b) Load the values of operands onto an
wide range of operations to be accumulator
performed. c) Declare the values as global constants
d) Store the outcome of the operation at
12. The Bit extension of the register is a memory location
denoted with the help of
symbol. Answer: a
a) $ Explanation: The effective address is
b) ` the address of the memory location
c) E required for the execution of the
d) ~ instruction.
 5. The instruction used to cause
1. The instructions of IA-32 machines are unconditional jump is
of length up to a) UJG
a) 4 bytes b) JG
b) 8 bytes c) JMP
c) 16 bytes d) GOTO
d) 12 bytes
Answer: c
Answer: d Explanation: This statement causes a
Explanation: The size of instruction jump from one instruction to another
that can be executed at once. without the condition.

2. The bit present in the op code, 6. instruction is used to

indicating which of the operands is the check the bit of the condition flags.
source is called as a) TEST
a) SRC bit b) TB
b) Indirection bit c) CHECK
c) Direction bit d) BT
d) FRM bit
Answer: d
Answer: c Explanation: This is used to check the
Explanation: None. condition flags for exceptions.

3. The directive is used to 7. REPINS instruction is used to

allocate 4 bytes of memory.
a) DD a) Transfer a block of data serially from
b) ALLOC an Input device to the processor
c) RESERVE b) Transfer a block of data parallelly
d) SPACE from Input device to the processor
c) Transfer a block of data serially from
Answer: a an Input device to the output device
Explanation: None. d) Transfer a block of data parallelly
from Input device to the output device
4. .data directive is used
a) To indicate the ending of the data Answer: b
section Explanation: None.
b) To indicate the beginning of the data
section 8. Which of the following statements
c) To declare all the source operands regarding Stacks is/are True?
d) To Initialize the operands i) The stack always grows towards higher
addresses
Answer: b ii) The stack always grows towards lower
Explanation: This is used to indicate addresses
the starting of the section of data. iii) The stack has a fixed size
iv) The width of the stack is 32 bits
a) i and iii
b) i and iv 12. Which architecture is suitable for a
c) ii and iv wide range of data types?
d) iii and iv a) ARM
b) 68000
Answer: c c) IA-32
Explanation: The stack is a data d) ASUS firebird
structure which is fixed at one end and
grows at the other. Answer: c
Explanation: None.
9. The instruction used to multiply
operands yielding a double integer 13. In case of multimedia extension
outcome is instructions, the pixels are encoded into
a) MUL a data item of
b) IMUL a) 16 bit
c) DMUL b) 32 bit
d) EMUL c) 24 bit
d) 8 bit
Answer: b
Explanation: This instruction is used to Answer: d
carry out multiplication on large integral Explanation: None.
values.
14. The MMX (Multimedia Extension)
10. SIMD stands for operands are stored in
a) Single Instruction Multiple Data a) General purpose registers
b) Simple Instruction Multiple Decoding b) Banked registers
c) Sequential Instruction Multiple c) Float point registers
Decoding d) Graphic registers
d) System Information Mutable Data
Answer: c
Answer: a Explanation: These operands are used
Explanation: This is the instruction used for graphic related operations.
to perform an operation on multiple
types of data. 15. The division operation in IA-32 is a
single operand instruction so it is
11. The IA-32 system follows assumed that
design. a) The divisor is stored in the EAX
a) RISC register
b) CISC b) The dividend is stored in the EAC
c) SIMD register
d) None of the mentioned c) The divisor is stored in the
accumulator
Answer: b d) The dividend is stored in the
Explanation: This system architecture is accumulator
used to reduce the steps involved in
execution by performing complex Answer: a
operations in one step. Explanation: In the case of a division
the divisor is pre-loaded onto the ALU. a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard

Answer: a
UNIT IV PARALLELISIM Explanation: Data hazards are generally
caused when the data is not ready on
1. Any condition that causes a processor the destination side.
to stall is called as
a) Hazard 5. The stalling of the processor due to
b) Page fault the unavailability of the instructions is
c) System error called as
d) None of the mentioned a) Control hazard
b) structural hazard
Answer: a c) Input hazard
Explanation: An hazard causes a delay d) None of the mentioned
in the execution process of the
processor. Answer: a
Explanation: The control hazard also
2. The periods of time when the unit is called as instruction hazard is usually
idle is called as caused by a cache miss.
a) Stalls
b) Bubbles 6. The time lost due to the branch
c) Hazards instruction is often referred to as
d) Both Stalls and Bubbles
a) Latency
Answer: d b) Delay
Explanation: The stalls are a type of c) Branch penalty
hazards that affect a pipe-lined system. d) None of the mentioned
3. The contention for the usage of a Answer: c
hardware device is called Explanation: This time also retards the
a) Structural hazard performance speed of the processor.
b) Stalk
c) Deadlock 7. The pipeline bubbling is a method
d) None of the mentioned used to prevent data hazard and
structural hazards.
Answer: a a) True
Explanation: The processor contends b) False
for the usage of the hardware and might
enter into a deadlock state. Answer: a
Explanation: The periods of time when
4. The situation wherein the data of the unit is idle is called a Bubble.
operands are not available is called
8. method is used in 1. The set of loosely connected
centralized systems to perform out of computers are called as
order execution. a) LAN
a) Scorecard b) WAN
b) Score boarding c) Workstation
c) Optimizing d) Cluster
d) Redundancy
Answer: d
Answer: b Explanation: In a computer cluster all
Explanation: In a scoreboard, the data the participating computers work
dependencies of every instruction are together on a particular task.
logged. Instructions are released only
when the scoreboard determines that 2. Each computer in a cluster is
there are no conflicts with previously connected using
issued and incomplete instructions. a) UTP
b) Rj-45
9. The algorithm followed in most of the c) STP
systems to perform out of order d) Coaxial cable
execution is
a) Tomasulo algorithm Answer: b
b) Score carding Explanation: The computers are
c) Reader-writer algorithm connected to each other using a LAN
d) None of the mentioned connector cable.

Answer: a 3. The computer cluster architecture

Explanation: The Tomasulo algorithm is emerged as a result of
a hardware algorithm developed in 1967 a) ISA
by Robert Tomasulo from IBM. It allows b) Workstation
sequential instructions that would c) Super computers
normally be stalled due to certain d) Distributed systems
dependencies to execute non-
sequentially (out-of-order execution). Answer: d
Explanation: A distributed system is a
10. The problem where process computer system spread out over a
concurrency becomes an issue is called geographic area.
as
a) Philosophers problem 4. The software which governs the group
b) Bakery problem of computers is
c) Bankers problem a) Driver Rd45
d) Reader-writer problem b) Interface UI
c) Clustering middleware
Answer: d d) Distributor
Explanation: None.
Answer: c
Explanation: The software helps to
project a single system image to the Answer: a
user. Explanation: None.

5. The simplest form of a cluster is 9. The most common modes of

approach. communication in clusters are
a) Beowolf a) Message queues
b) Sequoia b) Message passing interface
c) Stone c) PVm
d) None of the mentioned d) Both Message passing interface and
PVm
Answer: a
Explanation: None. Answer: d
Explanation: None.
6. The cluster formation in which the
work is divided equally among the 10. The method followed in case of node
systems is failure, wherein the node gets disabled
a) Load-configuration is
b) Load-Division a) STONITH
c) Light head b) Fibre channel
d) Both Load-configuration and Load- c) Fencing
Division d) None of the mentioned

Answer: a Answer: a
Explanation: This approach the work Explanation: None.
gets divided among the systems equally.

7. In the client server model of the 1. VLIW stands for?

cluster approach is used. a) Very Long Instruction Word
a) Load configuration b) Very Long Instruction Width
b) FIFO c) Very Large Instruction Word
c) Bankers algorithm d) Very Long Instruction Width
d) Round robin
Answer: a
Answer: d Explanation: It is the architecture
Explanation: By using this approach the designed to perform multiple operations
performance of the cluster can be in parallel.
enhanced.
2. The important feature of the VLIW is
8. The beowolf structure follows the
approach of a relationship a) ILP
between the systems. b) Cost effectiveness
a) Master-slave c) Performance
b) Asynchronous d) None of the mentioned
c) Synchronous
d) Isochronous Answer: a
Explanation: ILP stands for Instruction
Level Parallelism. c) SSD slots
d) Scheduling hardware
3. The main difference between the
VLIW and the other approaches to Answer: d
improve performance is Explanation: As the compiler only
a) Cost effectiveness decides the schedule of execution the
b) Increase in performance schedule is not required here.
c) Lack of complex hardware design
d) All of the mentioned 7. The VLIW architecture follows
approach to achieve parallelism.
Answer: c a) MISD
Explanation: The Pipe-lining and super- b) SISD
scalar architectures involved the usage c) SIMD
of complex hardware circuits for the d) MIMD
implementation.
Answer: d
4. In VLIW the decision for the order of Explanation: The MIMD stands for
execution of the instructions depends on Multiple Instructions Multiple Data.
the program itself.
a) True 8. The following instruction is allowed in
b) False VLIW:

Answer: a f12 = f0 * f4, f8 = f8 + f12, f0 = dm(i0,

m3), f4 = pm(i8, m9);
Explanation: In other words, the order
of execution of instructions has nothing a) True
to do with the physical hardware b) False
implementation of the system.
Answer: a
5. The parallel execution of operations Explanation: The above mentioned
in VLIW is done according to the instruction is a complex 48 bit
schedule determined by instruction used to perform operations
a) Task scheduler on floating numbers.
b) Interpreter
c) Compiler 9. To compute the direction of the
d) Encoder branch the VLIW uses
a) Seekers
Answer: c b) Heuristics
Explanation: The compiler first checks c) Direction counter
the code for interdependencies and then d) Compass
determines the schedule for its
execution. Answer: b
Explanation: None.
6. The VLIW processors are much simpler
as they do not require of 10. EPIC stands for?
a) Computational register a) Explicitly Parallel Instruction
b) Complex logic circuits Computing
b) External Peripheral Integrating operation is complete
Component d) Assign a device to perform the read
c) External Parallel Instruction operation
Computing
d) None of the mentioned Answer: c
Explanation: The MFC stands for
Answer: a memory Function Complete.
Explanation: None.
4. is the bottleneck, when it
comes computer performance.
a) Memory access time
b) Memory cycle time
c) Delay
UNIT V MEMORY & I/O d) Latency
SYSTEMS
Answer: b
1. The duration between the read and Explanation: The processor can execute
the mfc signal is instructions faster than they’re fetched,
a) Access time hence cycle time is the bottleneck for
b) Latency performance.
c) Delay
5. The logical addresses generated by
d) Cycle time
the cpu are mapped onto physical
Answer: a memory by
Explanation: The time between the a) Relocation register
issue of a read signal and the completion b) TLB
of it is called memory access time. c) MMU
d) None of the mentioned
2. The minimum time delay between
two successive memory read operations Answer: c
is Explanation: The MMU stands for
a) Cycle time memory management unit, which is used
b) Latency to map logical address onto the physical
c) Delay address.
d) None of the mentioned
6. VLSI stands for
Answer: a a) Very Large Scale Integration
Explanation: The Time taken by the cpu b) Very Large Stand-alone Integration
to end one read operation and to start c) Volatile Layer System Interface
one more is cycle time. d) None of the mentioned

3. MFC is used to Answer: a

a) Issue a read signal Explanation: None.
b) Signal to the device that the memory
read operation is complete 7. The cells in a row are connected to a
common line called
c) Signal the processor the memory
a) Work line
b) Word line a) 128 X 8
c) Length line b) 256 X 4
d) Principle diagonal c) 512 X 2
d) 1024 X 1
Answer: b
Explanation: This means that the cell Answer: d
contents together form one word of Explanation: All the others require less
instruction or data. than 10 address bits.

8. The cells in each column are 12. Circuits that can hold their state as
connected to long as power is applied is
a) Word line a) Dynamic memory
b) Data line b) Static memory
c) Read line c) Register
d) Sense/ Write line d) Cache

Answer: d Answer: b
Explanation: The cells in each column Explanation: None.
are connected to the sense/write circuit
using two bit lines and which is in turn 13. The number of external connections
connected to the data lines. required in 16 X 8 memory organisation
is
9. The word line is driven by the a) 14
a) Chip select b) 19
b) Address decoder c) 15
c) Data line d) 12
d) Control line
Answer: a
Answer: b Explanation: In the 14, 8-data lines,4-
Explanation: None. address lines and 2 are sense/write and
CS signals.
10. A 16 X 8 Organisation of memory
cells, can store upto 14. The advantage of CMOS SRAM over
a) 256 bits the transistor one’s is
b) 1024 bits a) Low cost
c) 512 bits b) High efficiency
d) 128 bits c) High durability
d) Low power consumption
Answer: d
Explanation: It can store upto 128 bits Answer: d
as each cell can hold one bit of data. Explanation: This is because the cell
consumes power only when it is being
11. A memory organisation that can hold accessed.
upto 1024 bits and has a minimum of 10
address lines can be organized into
15. In a 4M-bit chip organisation has a Answer: b
total of 19 external connections.then it Explanation: Since capacitors are used
has address if 8 data lines are the charge dissipates over time.
there.
a) 10 4. The capacitors lose the charge over
b) 8 time due to
c) 9 a) The leakage resistance of the
d) 12 capacitor
b) The small current in the transistor
Answer: c after being turned on
Explanation: To have 8 data lines and c) The defect of the capacitor
19 external connections it has to have 9 d) None of the mentioned
address lines(i.e 512 x 8 organisation).
Answer: a
Explanation: The capacitor loses charge
1. The Reason for the disregarding of the due to the backward current of the
SRAM’s is transistor and due to the small
a) Low Efficiency resistance.
b) High power consumption
c) High Cost 5. circuit is used to restore
d) All of the mentioned the capacitor value.
a) Sense amplify
Answer: c b) Signal amplifier
Explanation: The reason for the high c) Delta modulator
cost of the SRAM is because of the usage d) None of the mentioned
of more number of transistors.
Answer: a
2. The disadvantage of DRAM over SRAM Explanation: The sense amplifier
is/are detects if the value is above or below
a) Lower data storage capacities the threshold and then restores it.
b) Higher heat dissipation
c) The cells are not static 6. To reduce the number of external
d) All of the mentioned connections required, we make use of

Answer: c a) De-multiplexer
Explanation: This means that the cells b) Multiplexer
won’t hold their state indefinitely. c) Encoder
d) Decoder
3. The reason for the cells to lose their
state over time is Answer: b
a) The lower voltage levels Explanation: We multiplex the various
b) Usage of capacitors to store the address lines onto fewer pins.
charge
c) Use of Shift registers 7. The processor must take into account
d) None of the mentioned the delay in accessing the memory
location, such memories are called
 1. The difference between DRAM’s and
a) Delay integrated SDRAM’s is/are
b) Asynchronous memories a) The DRAM’s will not use the master
c) Synchronous memories slave relationship in data transfer
d) Isochronous memories b) The SDRAM’s make use of clock
c) The SDRAM’s are more power efficient
Answer: b d) None of the mentioned
Explanation: None.
Answer: d
8. To get the row address of the required Explanation: The SDRAM’s make use of
data is enabled. clock signals to synchronize their
a) CAS operation.
b) RAS
c) CS 2. The difference in the address and
d) Sense/write data connection between DRAM’s and
SDRAM’s is
Answer: b a) The usage of more number of pins in
Explanation: This makes the contents of SDRAM’s
the row required refreshed. b) The requirement of more address
lines in SDRAM’s
9. In order to read multiple bytes of a c) The usage of a buffer in SDRAM’s
row at the same time, we make use of d) None of the mentioned
a) Latch Answer: c
b) Shift register Explanation: The SDRAM uses buffered
c) Cache storage of address and data.
d) Memory extension
3. A is used to restore the
Answer: a contents of the cells.
Explanation: The latch makes it easy to a) Sense amplifier
ready multiple bytes of data of the same b) Refresh counter
row simultaneously by just giving the c) Restorer
consecutive column address. d) None of the mentioned
10. The block transfer capability of the Answer: b
DRAM is called Explanation: The Counter helps to
a) Burst mode restore the charge on the capacitor.
b) Block mode
c) Fast page mode 4. The mode register is used to
d) Fast frame mode a) Select the row or column data
transfer mode
Answer: c b) Select the mode of operation
Explanation: None. c) Select mode of storing the data
d) All of the mentioned
Answer: b triggered.
Explanation: The mode register is used
to choose between burst mode or bit 9. DDR SDRAM’s perform faster data
mode of operation. transfer by
a) Integrating the hardware
5. In a SDRAM each row is refreshed b) Transferring on both edges
every 64ms. c) Improving the clock speeds
a) True d) Increasing the bandwidth
b) False
Answer: b
Answer: a Explanation: By transferring data on
Explanation: None. both the edges the bandwidth is
effectively doubled.
6. The time taken to transfer a word of
data to or from the memory is called as 10. To improve the data retrieval rate

a) Access time a) The memory is divided into two banks

b) Cycle time b) The hardware is changed
c) Memory latency c) The clock frequency is increased
d) None of the mentioned d) None of the mentioned

Answer: c Answer: a
Explanation: The performance of the Explanation: The division of memory
memory is measured by means of into two banks makes it easy to access
latency. two different words at each edge of the
clock.
7. In SDRAM’s buffers are used to store
data that is read or written.
a) True 1. The chip can be disabled or cut off
b) False from an external connection using

Answer: a a) Chip select

Explanation: In SDRAM’s all the bytes of b) LOCK
data to be read or written are stored in c) ACPT
the buffer until the operation is d) RESET
complete.
Answer: a
8. The SDRAM performs operation on the Explanation: The chip gets enabled if
the CS is set otherwise the chip gets
a) Rising edge of the clock disabled.
b) Falling edge of the clock
c) Middle state of the clock 2. To organise large memory chips we
d) Transition state of the clock make use of
a) Integrated chips
Answer: a b) Upgraded hardware
Explanation: The SDRAM’s are edge-
c) Memory modules b) Memory controller unit
d) None of the mentioned c) Page table
d) Overlay generator
Answer: c
Explanation: The cell blocks are Answer: b
arranged and put in a memory module. Explanation: This unit multiplexes the
various address lines to lesser pins on
3. The less space consideration as lead the chip.
to the development of (for
large memories). 7. The controller multiplexes the
a) SIMM’s addresses after getting the signal.
b) DIMS’s a) INTR
c) SRAM’s b) ACK
d) Both SIMM’s and DIMS’s c) RESET
d) Request
Answer: d
Explanation: The SIMM (single inline Answer: d
memory module) or DIMM (dual inline Explanation: The controller gets the
memory module) occupy less space request from the device needing the
while providing greater memory space. memory read or write operation and
then it multiplexes the address.
4. The SRAM’s are basically used as
8. The RAS and CAS signals are provided
a) Registers by the
b) Caches a) Mode register
c) TLB b) CS
d) Buffer c) Memory controller
d) None of the mentioned
Answer: b
Explanation: The SRAM’s are used as Answer: c
caches as their operation speed is very Explanation: The multiplexed signal of
high. the controller is split into RAS and CAS.

5. The higher order bits of the address 9. Consider a memory organised into 8K
are used to rows, and that it takes 4 cycles to
a) Specify the row address complete a read operation. Then the
b) Specify the column address refresh overhead of the chip is
c) Input the CS a) 0.0021
d) None of the mentioned b) 0.0038
c) 0.0064
Answer: a d) 0.0128
Explanation: None.
Answer: b
6. The address lines multiplexing is done Explanation: The refresh overhead is
using calculated by taking into account the
a) MMU
total time for refreshing and the interval reduced from the Vsupply about 2v.
of each refresh.
4. The data is transferred over the
10. When DRAM’s are used to build a RAMBUS as
complex large memory, then the a) Packets
controller only provides the refresh b) Blocks
counter. c) Swing voltages
a) True d) Bits
b) False
Answer: c
Answer: a Explanation: By using voltage swings to
Explanation: None. transfer data, the transfer rate along
with efficiency is improved.

1. RAMBUS is better than the other 5. The type of signaling used in RAMBUS
memory chips in terms of is
a) Efficiency a) CLK signaling
b) Speed of operation b) Differential signaling
c) Wider bandwidth c) Integral signaling
d) All of the mentioned d) None of the mentioned

Answer: b Answer: b
Explanation: The RAMBUS is much Explanation: The differential signaling
advanced mode of memory storage. basically means using voltage swings to
transmit data.
2. The key feature of the RAMBUS tech is
6. The special communication used in
a) Greater memory utilisation RAMBUS are
b) Efficiency a) RAMBUS channel
c) Speed of transfer b) D-link
d) None of the mentioned c) Dial-up
d) None of the mentioned
Answer: c
Explanation: The RAMBUS was Answer: a
developed basically to lessen the data Explanation: The special
transfer time. communication link is used to provide
the necessary design and required
3. The increase in operation speed is hardware for the transmission.
done by
a) Reducing the reference voltage 7. The original design of the RAMBUS
b) Increasing the clk frequency required for data lines.
c) Using enhanced hardware a) 4
d) None of the mentioned b) 6
c) 8
Answer: a d) 9
Explanation: The reference voltage is
Answer: d transistor is closed then, the value of
Explanation: Out of the 9 data lines, 8 zero is stored in the ROM.
were used for data transmission and the
one left was used for parity checking. 2. PROM stands for
a) Programmable Read Only Memory
8. The RAMBUS requires specially b) Pre-fed Read Only Memory
designed memory chips similar to c) Pre-required Read Only Memory
a) SRAM d) Programmed Read Only Memory
b) SDRAM
c) DRAM Answer: a
d) DDRRAM Explanation: It allows the user to
program the ROM.
Answer: c
Explanation: The special memory chip 3. The PROM is more effective than ROM
should be able to transmit data on both chips in regard to
the edges and is called as RDRAM’s. a) Cost
b) Memory management
9. A RAMBUS which has 18 data lines is c) Speed of operation
called as d) Both Cost and Speed of operation
a) Extended RAMBUS
b) Direct RAMBUS Answer: d
c) Multiple RAMBUS Explanation: The PROM is cheaper than
d) Indirect RAMBUS ROM as they can be programmed
manually.
Answer: b
Explanation: The direct RAMBUS is used 4. The difference between the EPROM
to transmit 2 bytes of data at a time. and ROM circuitry is
a) The usage of MOSFET’s over
10. The RDRAM chips assembled into transistors
larger memory modules called b) The usage of JFET’s over transistors
a) RRIM c) The usage of an extra transistor
b) DIMM d) None of the mentioned
c) SIMM
d) All of the mentioned Answer: c
Explanation: The EPROM uses an extra
Answer: a transistor where the ground connection
Explanation: None. is there in the ROM chip.

5. The ROM chips are mainly used to

1. If the transistor gate is closed, then store
the ROM stores a value of 1. a) System files
a) True b) Root directories
b) False c) Boot files
d) Driver files
Answer: b
Explanation: If the gate of the
Answer: c schemes used
Explanation: The ROM chips are used to d) All of the mentioned
store boot files required for the system
startup. Answer: a
Explanation: None.
6. The contents of the EPROM are erased
by 10. The memory devices which are
a) Overcharging the chip similar to EEPROM but differ in the cost
b) Exposing the chip to UV rays effectiveness is
c) Exposing the chip to IR rays a) Memory sticks
d) Discharging the Chip b) Blue-ray devices
c) Flash memory
Answer: b d) CMOS
Explanation: To erase the contents of
the EPROM the chip is exposed to the UV Answer: c
rays, which dissipate the charge on the Explanation: The flash memory
transistor. functions similar to the EEPROM but is
much cheaper.
7. The disadvantage of the EPROM chip
is 11. The only difference between the
a) The high cost factor EEPROM and flash memory is that the
b) The low efficiency latter doesn’t allow bulk data to be
c) The low speed of operation written.
d) The need to remove the chip a) True
physically to reprogram it b) False

Answer: d Answer: a
Explanation: None. Explanation: This is not permitted as
the previous contents of the cells will be
8. EEPROM stands for Electrically overwritten.
Erasable Programmable Read Only
Memory. 12. The flash memories find application
a) True in
b) False a) Super computers
b) Mainframe systems
Answer: a c) Distributed systems
Explanation: The disadvantages of the d) Portable devices
EPROM led to the development of the
EEPROM. Answer: d
Explanation: The flash memories low
9. The disadvantage of the EEPROM power requirement enables them to be
is/are used in a wide range of hand held
a) The requirement of different voltages devices.
to read, write and store information
b) The Latency read operation 13. The memory module obtained by
c) The inefficient memory mapping placing a number of flash chips for
higher memory storage called as Answer: b
Explanation: As they require a large
a) FIMM number of transistors, their cost per bit
b) SIMM increases.
c) Flash card
d) RIMM 2. The drawback of building a large
memory with DRAM is
Answer: c a) The large cost factor
Explanation: None. b) The inefficient memory organisation
c) The Slow speed of operation
14. The flash memory modules designed d) All of the mentioned
to replace the functioning of a hard disk
is Answer: c
a) RIMM Explanation: The DRAM’s were used for
b) Flash drives large memory modules for a long time
c) FIMM until a substitute was found.
d) DIMM
3. To overcome the slow operating
Answer: b speeds of the secondary memory we
Explanation: The flash drives have been make use of faster flash drives.
developed to provide faster operation a) True
but with lesser space. b) False

15. The reason for the fast operating Answer: a

speeds of the flash drives is Explanation: To improve the speed we
use flash drives at the cost of memory
a) The absence of any movable parts space.
b) The integrated electronic hardware
c) The improved bandwidth connection 4. The fastest data access is provided
d) All of the mentioned using
a) Caches
Answer: a b) DRAM’s
Explanation: Since the flash drives have c) SRAM’s
no movable parts their access and seek d) Registers
times are reasonably reduced.
Answer: d
Explanation: The fastest data access is
1. The standard SRAM chips are costly as provided using registers as these
memory locations are situated inside the
a) They use highly advanced micro-
processor.
electronic devices
b) They house 6 transistor per chip 5. The memory which is used to store
c) They require specially designed PCB’s the copy of data or instructions stored in
d) None of the mentioned larger memories, inside the CPU is
called
a) Level 1 cache
b) Level 2 cache a) True
c) Registers b) False
d) TLB
Answer: b
Answer: a Explanation: As the speed of operation
Explanation: These memory devices are increases the cost increases and the size
generally used to map onto the data decreases.
stored in the larger memories.
10. If we use the flash drives instead of
6. The larger memory placed between the harddisks, then the secondary
the primary cache and the memory is storage can go above primary memory in
called the hierarchy.
a) Level 1 cache a) True
b) Level 2 cache b) False
c) EEPROM
d) TLB Answer: b
Explanation: The flash drives will
Answer: b increase the speed of transfer but still it
Explanation: This is basically used to won’t be faster than primary memory.
provide effective memory mapping.

7. The next level of memory hierarchy 1. The reason for the implementation of
after the L2 cache is the cache memory is
a) Secondary storage a) To increase the internal memory of
b) TLB the system
c) Main memory b) The difference in speeds of operation
d) Register of the processor and memory
c) To reduce the memory access and
Answer: d cycle time
Explanation: None. d) All of the mentioned

8. The last on the hierarchy scale of Answer: b

memory devices is Explanation: This difference in the
a) Main memory speeds of operation of the system
b) Secondary memory caused it to be inefficient.
c) TLB
d) Flash drives 2. The effectiveness of the cache
memory is based on the property of
Answer: b
Explanation: The secondary memory is a) Locality of reference
the slowest memory device. b) Memory localisation
c) Memory size
9. In the memory hierarchy, as the speed d) None of the mentioned
of operation increases the memory size
also increases. Answer: a
Explanation: This means that the cache
depends on the location in the memory 6. The algorithm to remove and place
that is referenced often. new contents into the cache is called

3. The temporal aspect of the locality of a) Replacement algorithm

reference means b) Renewal algorithm
a) That the recently executed c) Updation
instruction won’t be executed soon d) None of the mentioned
b) That the recently executed
instruction is temporarily not referenced Answer: a
c) That the recently executed Explanation: As the cache gets full,
instruction will be executed soon again older contents of the cache are swapped
d) None of the mentioned out with newer contents. This decision is
taken by the algorithm.
Answer: c
Explanation: None. 7. The write-through procedure is used

4. The spatial aspect of the locality of a) To write onto the memory directly
reference means b) To write and read from memory
a) That the recently executed simultaneously
instruction is executed again next c) To write directly on the memory and
b) That the recently executed won’t be the cache simultaneously
executed again d) None of the mentioned
c) That the instruction executed will be
executed at a later time Answer: c
d) That the instruction in close proximity Explanation: When write operation is
of the instruction executed will be issued then the corresponding operation
executed in future is performed.

Answer: d 8. The bit used to signify that the cache

Explanation: The spatial aspect of location is updated is
locality of reference tells that the a) Dirty bit
nearby instruction is more likely to be b) Update bit
executed in future. c) Reference bit
d) Flag bit
5. The correspondence between the
main memory blocks and those in the Answer: a
cache is given by Explanation: When the cache location is
a) Hash function updated in order to signal to the
b) Mapping function processor this bit is used.
c) Locale function
d) Assign function 9. The copy-back protocol is used

Answer: b a) To copy the contents of the memory

Explanation: The mapping function is onto the cache
used to map the contents of the memory b) To update the contents of the
to the cache. memory from the cache
c) To remove the contents of the cache operation has missed and it brings the
and push it on to the memory required block into the cache.
d) None of the mentioned
3. In protocol the information
Answer: b is directly written into the main
Explanation: This is another way of memory.
performing the write operation, wherein a) Write through
the cache is updated first and then the b) Write back
memory. c) Write first
d) None of the mentioned
10. The approach where the memory
contents are transferred directly to the Answer: a
processor from the memory is called Explanation: In case of the miss, then
the data gets written directly in main
a) Read-later memory.
b) Read-through
c) Early-start 4. The only draw back of using the early
d) None of the mentioned start protocol is
a) Time delay
Answer: c b) Complexity of circuit
Explanation: None. c) Latency
d) High miss rate

1. The memory blocks are mapped on to Answer: b

the cache with the help of Explanation: In this protocol, the
a) Hash functions required block is read and directly sent
b) Vectors to the processor.
c) Mapping functions
d) None of the mentioned 5. The method of mapping the
consecutive memory blocks to
Answer: c consecutive cache blocks is called
Explanation: The mapping functions are
used to map the memory blocks on to a) Set associative
their corresponding cache block. b) Associative
c) Direct
2. During a write operation if the d) Indirect
required block is not present in the
cache then occurs. Answer: c
a) Write latency Explanation: This method is most
b) Write hit simple to implement as it involves direct
c) Write delay mapping of memory blocks.
d) Write miss
6. While using the direct mapping
Answer: d technique, in a 16 bit system the higher
Explanation: This indicates that the order 5 bits are used for
a) Tag
b) Block c) Associative search
c) Word d) None of the mentioned
d) Id
Answer: c
Answer: a Explanation: None.
Explanation: The tag is used to identify
the block mapped onto one particular 11. The set-associative map technique is
cache block. a combination of the direct and
associative technique.
7. In direct mapping the presence of the a) True
block in memory is checked with the b) False
help of block field.
a) True Answer: a
b) False Explanation: The combination of the
efficiency of the associative method and
Answer: b the cheapness of the direct mapping, we
Explanation: The tag field is used to get the set-associative mapping.
check the presence of a mem block.
12. In set-associative technique, the
8. In associative mapping, in a 16 bit blocks are grouped into sets.
system the tag field has bits. a) 4
a) 12 b) 8
b) 8 c) 12
c) 9 d) 6
d) 10
Answer: d
Answer: a Explanation: The set-associative
Explanation: The Tag field is used as an technique groups the blocks into
id for the different memory blocks different sets.
mapped to the cache.
13. A control bit called has to
9. The associative mapping is costlier be provided to each block in set-
than direct mapping. associative.
a) True a) Idol bit
b) False b) Valid bit
c) Reference bit
Answer: a d) All of the mentioned
Explanation: In associative mapping, all
the tags have to be searched to find the Answer: b
block. Explanation: The valid bit is used to
indicate that the block holds valid
10. The technique of searching for a information.
block by going through all the tags is
14. The bit used to indicate whether the
a) Linear search block was recently used or not is
b) Binary search
a) Idol bit 3. In memory interleaving, the lower
b) Control bit order bits of the address is used to
c) Reference bit
d) Dirty bit a) Get the data
b) Get the address of the module
Answer: d c) Get the address of the data within the
Explanation: The dirty bit is used to module
show that the block was recently d) None of the mentioned
modified and for a replacement
algorithm. Answer: b
Explanation: To implement parallelism
15. Data which is not up-to date is in data access we use interleaving.
called as
a) Spoilt data 4. The number successful accesses to
b) Stale data memory stated as a fraction is called as
c) Dirty data
d) None of the mentioned a) Hit rate
b) Miss rate
Answer: b c) Success rate
Explanation: None. d) Access rate

Answer: a
1. The main memory is structured into Explanation: The hit rate is an
modules each with its own address important factor in performance
register called measurement.
a) ABR
b) TLB 5. The number failed attempts to access
c) PC memory, stated in the form of a fraction
d) IR is called as
a) Hit rate
Answer: a b) Miss rate
Explanation: ABR stands for Address c) Failure rate
Buffer Register. d) Delay rate

2. When consecutive memory locations Answer: b

are accessed only one module is Explanation: The miss rate is a key
accessed at a time. factor in deciding the type of
a) True replacement algorithm.
b) False
6. In associative mapping during LRU,
Answer: a the counter of the new block is set to
Explanation: In a modular approach to ‘0’ and all the others are incremented
memory structuring only one module can by one, when occurs.
be accessed at a time. a) Delay
b) Miss
c) Hit a) True
d) Delayed hit b) False

Answer: b Answer: a
Explanation: Miss usually occurs when Explanation: The extra time needed to
the memory block required is not bring the data into memory in case of a
present in the cache. miss is called as miss penalty.

7. In LRU, the referenced blocks counter

is set to’0′ and that of the previous 1. The CPU is also called as
blocks are incremented by one and a) Processor hub
others remain same, in the case of b) ISP
c) Controller
a) Hit d) All of the mentioned
b) Miss
c) Delay Answer: b
d) None of the mentioned Explanation: ISP stands for Instruction
Set Processor.
Answer: a
Explanation: If the referenced block is 2. A common strategy for performance is
present in the memory it is called as hit. making various functional units operate
parallelly.
8. If hit rates are well below 0.9, then a) True
they’re called as speedy computers. b) False
a) True
b) False Answer: a
Explanation: By parallelly accessing
Answer: b data we can have a pipelined processor.
Explanation: It has to be above 0.9 for
speedy computers. 3. The PC gets incremented

9. The extra time needed to bring the a) After the instruction decoding
data into memory in case of a miss is b) After the IR instruction gets executed
called as c) After the fetch cycle
a) Delay d) None of the mentioned
b) Propagation time
c) Miss penalty Answer: c
d) None of the mentioned Explanation: The PC always points to
the next instruction to be executed.
Answer: c
Explanation: None. 4. Which register in the processor is
single directional?
10. The miss penalty can be reduced by a) MAR
improving the mechanisms for data b) MDR
transfer between the different levels of c) PC
hierarchy. d) Temp
Answer: a Answer: d
Explanation: The MAR is single Explanation: None.
directional as it just takes the address
from the processor bus and passes it to 9. When two or more clock cycles are
the external bus. used to complete data transfer it is
called as
5. The transparent register/s is/are a) Single phase clocking
b) Multi-phase clocking
a) Y c) Edge triggered clocking
b) Z d) None of the mentioned
c) Temp
d) All of the mentioned Answer: b
Explanation: This is basically used in
Answer: d systems without edge-triggered flip
Explanation: These registers are usually flops.
used to store temporary values.
10. signal is used to show
6. Which register is connected to the complete of memory operation.
MUX? a) MFC
a) Y b) WMFC
b) Z c) CFC
c) R0 d) None of the mentioned
d) Temp
Answer: a
Answer: a Explanation: MFC stands for Memory
Explanation: The MUX can either read Function Complete.
the operand from the Y register or
increment the PC.
1. Is the below code segment correct,
7. The registers, ALU and the for the addition of two numbers?
interconnecting path together are called
as R1in, Yin
a) Control path R2out, Select Y, ADD, Zin
b) Flow path
c) Data path Zout, R3in
d) None of the mentioned
a) True
Answer: c b) False
Explanation: None.
Answer: a
8. The input and output of the registers Explanation: This is the gate transfer
are governed by notation, which indicates the usage of
a) Transistors switches to control the flow of data.
b) Diodes
c) Gates 2. The completion of the memory
d) Switches operation is indicated using
signal. 6. To extend the connectivity of the
a) MFC processor bus we use
b) WMFC a) PCI bus
c) CFC b) SCSI bus
d) None of the mentioned c) Controllers
d) Multiple bus
Answer: a
Explanation: MFC stands for Memory Answer: a
Function Complete. Explanation: The PCI BUS basically is
used to connect to memory devices.
3. signal enables the
processor to wait for the memory 7. The bus used to connect the monitor
operation to complete. to the CPU is
a) MFC a) PCI bus
b) TLB b) SCSI bus
c) WMFC c) Memory bus
d) ALB d) Rambus

Answer: c Answer: b
Explanation: This signal stands for Wait Explanation: The SCSI (Small
For Memory Function Complete. Component System Interconnect) is used
to connect to display devices.
4. The small extremely fast, RAM’s all
called as 8. The ISA standard Buses are used to
a) Cache connect
b) Heaps a) RAM and processor
c) Accumulators b) GPU and processor
d) Stacks c) Harddisk and Processor
d) CD/DVD drives and Processor
Answer: b
Explanation: Cache’s are extremely Answer: c
essential in single BUS organisation to Explanation: None.
achieve fast operation.
9. ANSI stands for
5. The main virtue for using single Bus a) American National Standards Institute
structure is b) American National Standard Interface
a) Fast data transfers c) American Network Standard
b) Cost effective connectivity and speed Interfacing
c) Cost effective connectivity and ease d) American Network Security Interrupt
of attaching peripheral devices
d) None of the mentioned Answer: a
Explanation: It is one of the standards
Answer: c of developing a BUS.
Explanation: None.
10. IBM developed a bus standard for
their line of computers ‘PC AT’ called
 4. For a 3 BUS architecture, is the below
a) IB bus code correct for adding three numbers?
b) M-bus
c) ISA PCout, R = B, Marin, READ, Inc PC
d) None of the mentioned WMFC

Answer: c MDRout, R = B, IRin

Explanation: None.
R4outa, R5outb, Select A, ADD, R6in, End

a) True
1. The general purpose registers are
b) False
combined into a block called as
a) Register bank Answer: a
b) Register Case Explanation: We have assumed the
c) Register file names of the three BUSes have A, B and
d) None of the mentioned C.
Answer: c 5. The main advantage of multiple bus
Explanation: To make the access of the organisation over a single bus is
registers easier, we classify them into
register files. a) Reduction in the number of cycles for
execution
2. In technology, the
b) Increase in size of the registers
implementation of the register file is by
c) Better Connectivity
using an array of memory locations.
d) None of the mentioned
a) VLSI
b) ANSI Answer: a
c) ISA Explanation: None.
d) ASCI
6. CISC stands for
Answer: a a) Complete Instruction Sequential
Explanation: By doing so the access of Compilation
the registers can be made faster. b) Computer Integrated Sequential
Compiler
3. In a three BUS architecture, how
c) Complex Instruction Set Computer
many input and output ports are there?
d) Complex Instruction Sequential
a) 2 output and 2 input
Compilation
b) 1 output and 2 input
c) 2 output and 1 input Answer: c
d) 1 output and 1 input Explanation: The CISC machines are
well adept at handling multiple BUS
Answer: c
organisation.
Explanation: That is enabling reading
from two locations and writing into one. 7. If the instruction Add R1, R2, R3 is
executed in a system which is pipelined,
then the value of S is (Where S is term of
the Basic performance equation). 1. are the different type/s of
a) 3 generating control signals.
b) ~2 a) Micro-programmed
c) ~1 b) Hardwired
d) 6 c) Micro-instruction
d) Both Micro-programmed and
Answer: c Hardwired
Explanation: The value will be much
lower in case of multiple BUS Answer: d
organisation. Explanation: The above is used to
generate control signals in different
8. In multiple BUS organisation types of system architectures.
is used to select any of the
BUSes for input into ALU. 2. The type of control signal is
a) MUX generated based on
b) DE-MUX a) contents of the step counter
c) En-CDS b) Contents of IR
d) None of the mentioned c) Contents of condition flags
d) All of the mentioned
Answer: a
Explanation: The MUX can be used to Answer: d
either select the BUS or to increment Explanation: Based on the information
the PC. above the type of control signal is
decided.
9. There exists a separate block
consisting of various units to decode an 3. What does the hardwired control
instruction. generator consist of?
a) True a) Decoder/encoder
b) False b) Condition codes
c) Control step counter
Answer: a d) All of the mentioned
Explanation: This block is used to
decode the instruction and place it in Answer: d
the IR. Explanation: The CU uses the above
blocks and IR to produce the necessary
10. There exists a separate block to signal.
increment the PC in multiple BUS
organisation. 4. What does the end instruction do?
a) True a) It ends the generation of a signal
b) False b) It ends the complete generation
process
Answer: a c) It starts a new instruction fetch cycle
Explanation: None. and resets the counter
d) It is used to shift the control to the
processor
Answer: c 9. The disadvantage/s of the hardwired
Explanation: It is basically used to start approach is
the generation of a new signal. a) It is less flexible
b) It cannot be used for complex
5. The Zin signal to the processor is instructions
generated using, Zin = T1+T6 ADD + c) It is costly
T4.BR… d) less flexible & cannot be used for
a) True complex instructions
b) False
Answer: d
Answer: a Explanation: The more complex the
Explanation: The signal is generated instruction set less applicable to a
using the logic of the formula above. hardwired approach.

6. What does the RUN signal do? 10. The End signal is generated using,
a) It causes the termination of a signal End = T7.ADD + T5.BR + (T5.N+ T4.-
b) It causes a particular signal to N).BRN…
perform its operation a) True
c) It causes a particular signal to end b) False
d) It increments the step counter by one
Answer: a
Answer: d Explanation: None.
Explanation: The RUN signal increments
the step counter by one for each clock
cycle. 1. In micro-programmed approach, the
signals are generated by
7. The name hardwired came because a) Machine instructions
the sequence of operations carried out is b) System programs
determined by the wiring. c) Utility tools
a) True d) None of the mentioned
b) False
Answer: a
Answer: a Explanation: The machine instructions
Explanation: In other words hardwired generate the signals.
is another name for Hardware Control
signal generator. 2. A word whose individual bits
represent a control signal is
8. The benefit of using this approach is a) Command word
b) Control word
a) It is cost effective c) Co-ordination word
b) It is highly efficient d) Generation word
c) It is very reliable
d) It increases the speed of operation Answer: b
Explanation: The control word is used
Answer: d to get the different types of control
Explanation: None. signals required.
3. A sequence of control words 7. Every time a new instruction is loaded
corresponding to a control sequence is into IR the output of is loaded
called into UPC.
a) Micro routine a) Starting address generator
b) Micro function b) Loader
c) Micro procedure c) Linker
d) None of the mentioned d) Clock

Answer: a Answer: a
Explanation: The micro routines are Explanation: The starting address
used to perform a particular task. generator is used to load the address of
the next micro instruction.
4. Individual control words of the micro
routine are called as 8. The case/s where micro-programmed
a) Micro task can perform well
b) Micro operation a) When it requires to check the
c) Micro instruction condition codes
d) Micro command b) When it has to choose between the
two alternatives
Answer: c c) When it is triggered by an interrupt
Explanation: The each instruction d) None of the mentioned
which put together performs the task.
Answer: d
5. The special memory used to store the Explanation: None.
micro routines of a computer is
9. The signals are grouped such that
a) Control table mutually exclusive signals are put
b) Control store together.
c) Control mart a) True
d) Control shop b) False

Answer: b Answer: a
Explanation: The control store is used Explanation: This is done to improve
as a reference to get the required the efficiency of the controller.
control routine.
10. Highly encoded schemes that use
6. To read the control words sequentially compact codes to specify a small
is used. number of functions in each micro
a) PC instruction is
b) IR a) Horizontal organisation
c) UPC b) Vertical organisation
d) None of the mentioned c) Diagonal organisation
d) None of the mentioned
Answer: c
Explanation: The UPC stands for Micro Answer: b
program counter. Explanation: None.
 5. In associative mapping during LRU,
1. The directly mapped cache no the counter of the new block is set to
replacement algorithm is required. ‘0’ and all the others are incremented
a) True by one when occurs.
b) False a) Delay
b) Miss
Answer: a c) Hit
Explanation: The position of each block d) Delayed hit
is pre-determined in the direct mapped
cache, hence no need for replacement. Answer: b
Explanation: Miss usually occurs when
2. The surroundings of the recently the memory block required is not
accessed block is called as present in the cache.
a) Neighborhood
b) Neighbour 6. The LRU provides very bad
c) Locality of reference performance when it comes to
d) None of the mentioned
a) Blocks being accessed is sequential
Answer: c b) When the blocks are randomised
Explanation: The locality of reference c) When the consecutive blocks accessed
is a key factor in many of the are in the extremes
replacement algorithms. d) None of the mentioned
3. In set associative and associative Answer: a
mapping there exists less flexibility. Explanation: The LRU in case of the
a) True sequential blocks as to waste its one
b) False cycle just incrementing the counters.

Answer: b 7. The algorithm which removes the

Explanation: The above two methods of recently used page first is
mapping the decision of which block to a) LRU
be removed rests with the cache b) MRU
controller. c) OFM
d) None of the mentioned
4. The algorithm which replaces the
block which has not been referenced for Answer: b
a while is called Explanation: In MRU it is assumed that
a) LRU the page accessed now is less likely to
b) ORF be accessed again.
c) Direct
d) Both LRU and ORF 8. The LRU can be improved by providing
a little randomness in the access.
Answer: a a) True
Explanation: LRU stands for Least b) False
Recently Used first.
Answer: a low cost
Explanation: None. c) To provide speedy operation at low
power consumption
9. In LRU, the referenced blocks counter d) All of the mentioned
is set to’0′ and that of the previous
blocks are incremented by one and Answer: b
others remain same, in the case of Explanation: An optimal system
provides the best performance at low
a) Hit costs.
b) Miss
c) Delay 3. A common measure of performance is
d) None of the mentioned
a) Price/performance ratio
Answer: a b) Performance/price ratio
Explanation: If the referenced block is c) Operation/price ratio
present in the memory it is called as a d) None of the mentioned
hit.
Answer: a
10. The counter that keeps track of how Explanation: If this measure is less than
many times a block is most likely used is one then the system is optimal.

a) Count 4. The performance depends on

b) Reference counter
c) Use counter a) The speed of execution only
d) Probable counter b) The speed of fetch and execution
c) The speed of fetch only
Answer: b d) The hardware of the system only
Explanation: None.
Answer: b
Explanation: The performance of a
1. The key factor/s in commercial system is decided by how quick an
success of a computer is/are instruction is brought into the system
a) Performance and executed.
b) Cost
c) Speed 5. The main purpose of having memory
d) Both Performance and Cost hierarchy is to
a) Reduce access time
Answer: d b) Provide large capacity
Explanation: The performance and cost c) Reduce propagation time
of the computer system is a key decider d) Reduce access time & Provide large
in the commercial success of the system. capacity

2. The main objective of the computer Answer: d

system is Explanation: By using the memory
a) To provide optimal power operation Hierarchy, we can increase the
b) To provide the best performance at performance of the system.
6. The memory transfers between two 10. If the instruction Add R1, R2, R3 is
variable speed devices are always done executed in a system which is pipelined,
at the speed of the faster device. then the value of S is (Where S is a term
a) True of the Basic performance equation).
b) False a) 3
b) ~2
Answer: a c) ~1
Explanation: None. d) 6

7. An effective to introduce parallelism Answer: c

in memory access is by Explanation: Pipelining is a process of
a) Memory interleaving fetching an instruction during the
b) TLB execution of other instruction.
c) Pages
d) Frames
1. The physical memory is not as large as
Answer: a the address space spanned by the
Explanation: Interleaving divides the processor.
memory into modules. a) True
b) False
8. The performance of the system is
greatly influenced by increasing the Answer: a
level 1 cache. Explanation: This is one of the main
a) True reasons for the usage of virtual
b) False memories.

Answer: a 2. The program is divided into operable

Explanation: This is so because the L1 parts called as
cache is onboard the processor. a) Frames
b) Segments
9. Two processors A and B have clock c) Pages
frequencies of 700 Mhz and 900 Mhz d) Sheets
respectively. Suppose A can execute an
instruction with an average of 3 steps Answer: b
and B can execute with an average of 5 Explanation: The program is divided
steps. For the execution of the same into parts called as segments for ease of
instruction which processor is faster. execution.
a) A
b) B 3. The techniques which move the
c) Both take the same time program blocks to or from the physical
d) Insufficient information memory is called as
a) Paging
Answer: a b) Virtual memory organisation
Explanation: None. c) Overlays
d) Framing
Answer: b program
Explanation: By using this technique d) All of the mentioned
the program execution is accomplished
with a usage of less space. Answer: d
Explanation: None.
4. The binary address issued to data or
instructions are called as 8. The DMA doesn’t make use of the
a) Physical address MMU for bulk data transfers.
b) Location a) True
c) Relocatable address b) False
d) Logical address
Answer: b
Answer: d Explanation: The DMA stands for Direct
Explanation: The logical address is the Memory Access, in which a block of data
random address generated by the gets directly transferred from the
processor. memory.

5. is used to implement 9. The virtual memory basically stores

virtual memory organisation. the next segment of data to be executed
a) Page table on the
b) Frame table a) Secondary storage
c) MMU b) Disks
d) None of the mentioned c) RAM
d) ROM
Answer: c
Explanation: The MMU stands for Answer: a
Memory Management Unit. Explanation: None.

6. translates the logical address 10. The associatively mapped virtual

into a physical address. memory makes use of
a) MMU a) TLB
b) Translator b) Page table
c) Compiler c) Frame table
d) Linker d) None of the mentioned

Answer: a Answer: a
Explanation: The MMU translates the Explanation: TLB stands for Translation
logical address into a physical address by Look-aside Buffer.
adding an offset.

7. The main aim of virtual memory 1. The main reason for the
organisation is discontinuation of semi conductor based
a) To provide effective memory access storage devices for providing large
b) To provide better memory transfer storage space is
c) To improve the execution of the a) Lack of sufficient resources
b) High cost per bit value
c) Lack of speed of operation 5. The drawback of Manchester encoding
d) None of the mentioned is
a) The cost of the encoding scheme
Answer: b b) The speed of encoding the data
Explanation: In the case of semi c) The Latency offered
conductor based memory technology, we d) The low bit storage density provided
get speed but the increase in the
integration of various devices the cost is Answer: d
high. Explanation: The space required to
represent each bit must be large enough
2. The digital information is stored on to accommodate two changes in
the hard disk by magnetization.
a) Applying a suitable electric pulse
b) Applying a suitable magnetic field 6. The read/write heads must be near to
c) Applying a suitable nuclear field disk surfaces for better storage.
d) By using optic waves a) True
b) False
Answer: a
Explanation: The digital data is sorted Answer: a
on the magnetized discs by magnetizing Explanation: By maintaining the heads
the areas. near to the surface greater bit densities
can be achieved.
3. For the synchronization of the read
head, we make use of a 7. pushes the heads away from
a) Framing bit the surface as they rotate at their
b) Synchronization bit standard rates.
c) Clock a) Magnetic tension
d) Dirty bit b) Electric force
c) Air pressure
Answer: c d) None of the mentioned
Explanation: The clock makes it easy to
distinguish between different values red Answer: c
by a head. Explanation: Due to the speed of
rotation of the discs air pressure
4. One of the most widely used schemes develops in the hard disk.
of encoding used is
a) NRZ-polar 8. The air pressure can be countered by
b) RZ-polar putting in the head-disc surface
c) Manchester arrangement.
d) Block encoding a) Air filter
b) Spring mechanism
Answer: c c) coolant
Explanation: The Manchester encoding d) None of the mentioned
used is also called as phase encoding and
it is used to encode both clock and data. Answer: b
Explanation: The spring mechanism
pushes the head along the surface to b) Cylinder
reduce the air pressure effect. c) Group
d) Set
9. The method of placing the heads and
the discs in an air tight environment is Answer: b
also called as Explanation: The data is stored in these
a) RAID Arrays sections called as cylinders.
b) ATP tech
c) Winchester technology 3. The data can be accessed from the
d) Fleming reduction disk using
a) Surface number
Answer: c b) Sector number
Explanation: The Disks and the heads c) Track number
operate faster due to the absence of the d) All of the mentioned
dust particles.
Answer: d
10. A hard disk with 20 surfaces will Explanation: None.
have heads.
a) 10 4. The read and write operations usually
b) 5 start at of the sector.
c) 1 a) Center
d) 20 b) Middle
c) From the last used point
Answer: d d) Boundaries
Explanation: Each surface will have its
own head to perform read/write Answer: d
operation. Explanation: The heads read and write
data from the ends to the center.

1. The disk system consists of which of 5. To distinguish between two sectors we

the following? make use of
i. Disk a) Inter sector gap
ii. Disk drive b) Splitting bit
iii. Disk controller c) Numbering bit
a) i and ii d) None of the mentioned
b) i, ii and iii
c) ii and iii Answer: a
d) i Explanation: This means that we leave
a little gap between each sector to
Answer: b differentiate between them.
Explanation: None.
6. The process divides the disk
2. The set of corresponding tracks on all into sectors and tracks.
surfaces of a stack of disks form a a) Creation
b) Initiation
a) Cluster
c) Formatting 9. is used to deal with the
d) Modification difference in the transfer rates between
the drive and the bus.
Answer: c a) Data repeaters
Explanation: The formatting process b) Enhancers
deletes the data present and does the c) Data buffers
creation of sectors and tracks. d) None of the mentioned

7. The access time is composed of Answer: c

Explanation: The buffers are added to
a) Seek time store the data from the fast device and
b) Rotational delay to send it to the slower device at its
c) Latency rate.
d) Both Seek time and Rotational delay
10. is used to detect and
Answer: d correct the errors that may occur during
Explanation: The seek time refers to data transfers.
the time required to move the head to a) ECC
the required disk. b) CRC
c) Checksum
8. The disk drive is connected to the
d) None of the mentioned
system by using the
a) PCI bus Answer: a
b) SCSI bus Explanation: ECC stands for Error
c) HDMI Correcting Code.
d) ISA

Answer: b
Explanation: None.