Assignment 1.1

veCAD-CAD-MAN-TR2008001
ISSN:
veCAD Technical Documentation
S-edit Tutorial on two-input OR gate

design and simulation using T-spice
Mohamed Khalil-Hani, PhD

Dr. Shaikh Nasir bin Shaikh Husin
En. Zulkifli bin Md. Yusof
Version Date: 13 Jan 2010 (Issue 1.2)
Abstract/Summary:
This tutorial shows a step-by step guide on how to design an OR gate using
S-edit and how to simulate the extracted netlist file using T-spice simulation
tool.
Contents:
1. About this S-edit Tutorial

2. S-edit tutorial
Revision history:
Version Date Author Change

Issue 1.1 2010-1-13 Annuar Front page formatting
Issue 1.2 2010-1-13 Liew Tek Introduction
Yee
Please send comments and inquiries to:
VLSI-ECAD Research Laboratory (veCAD)

Faculty of Electrical Engineering
University Teknologi Malaysia (UTM)
81310 Skudai, Johor.
vecad@fke.utm.my
www.fke.utm.my/vecad
1
About this S-edit Tutorial
VLSI-ECAD RESEARCH LABORATORY
UNIVERSITI TEKNOLOGI MALAYSIA
Introduction This tutorial is intended to give Tanner EDA an introduction of

Tanner EDA S-edit. Tanner EDA S-edit is used to capture the design at
schematic level. The traditional method for capturing (i.e
describing) your transistor-level or gate level design is via the S-
Edit schematic editor. Schematic editors provide simple, intuitive
means to draw, to place and to connect individual components
that make up your design. The resulting schematic drawing must
accurately describe the main electrical properties of all
components and their interconnections. Also included in the
schematic are the power supply and ground connections, as well
as all “pins” for the input and output signals of your circuit. This
information is crucial for generating the corresponding netlist,
which is used in later stages of the design. The generation of a
complete circuit schematic is therefore the first important step in
the design flow.
This tutorial requires the following hardware and software:

Hardware &  A PC running the Windows NT, 2000 or XP operating systems.
Software  Tanner v8 for Windows.
Requirements Vista and above: run as Administrator and Windows XP
compatibility mode
Prerequisite This tutorial assumes that you have familiar with the following items:
Knowledge  Basic knowledge on OR gate design
Objectives 1. To expose the user to some of the basic functions of S-

Edit user interface.
2. To expose the user to the T-spice simulation tool.
Assignment 1. Two-input OR gate design using S-Edit.

Deliverables 2. Proven functionality of circuit simulation.
3. Neat report (design files, simulation files, netlist, etc…).
Discussions 1. What would happen if you edit the module parameters in

netlist file?
2. In your opinion, what is the netlist file? Give points to
support your answers.
Reference [1] Jan M. Rabaey, Anantha Chandrakasan, “Digital Integrated

Circuits: A Design Perspective”, second edition, Prentice Hall,
Upper Saddle River, New Jersey 2003
2
Creating 2-input OR gate: Schematic Entry
1. Launch S-Edit by double clicking on the „sedit.exe‟ in „T-Spice Pro v6.02‟ folder.
2. Now start the design by placing components. Click on the „Symbol Browser, ‟ to
add in necessary components.
3. Select MOSFET_N and then click place, MOSFET_P and place, Gnd and place and
vdd. Close symbol browser after finish adding components.
3
4. The components are shown in figure below. Some of the components are overlap each
other such as MOSFET_N and MOSFET_P.
5. Mouse option:
Left click Scroll button Right click

When no buttons are pressed
When „alt‟ is pressed
When „shift‟ is pressed
When „control‟ is pressed
4
6. To move the component, hold „alt‟ click on the desired symbol to arrange.
To scroll: use „left‟, „right‟, „up‟, „down‟

To zoom: use „+‟ or „-‟, „Home‟ will zoom
automatically for you
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7. Since OR gate requires 2 NMOS and PMOS respectively, hence both components
have to be copied. Select NMOS then and then press „ctrl‟ key and drag. Repeat the
same step for PMOS.
6
8. Connect all nodes using „wire .
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9. Add in input and output ports.
8
10. Connect all ports using either wire connection or name connection . Use „Node
label ‟ to name the ports. Ports with same name will be connected.
Click here to name the

node
11. Once all the connections are done, click page>pin test to make sure all the nodes are
connected.
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Creating an 2-input OR gate: Generate Netlist
1. Click this symbol to generate netlist.
2. In order to simulate the netlist, some parameters need to be defined. There are:
Include MOSFET definition file
Define power supplies
Provide input signals
Type of simulation
Print the waveforms
i. Include MOSFET definition file:

.include TSMC_SCN025Parameters.txt
The MOSFET Definition file which must be same

directory as working directory
ii. Define Power Supplies:

vvss vss 0 0
vvdd vdd 0 2.5
Voltage Default Voltage2 with respect

name to voltage1, in this
Voltage 1 case voltage2 is
respect to ground, 0V
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iii. Provide Input Signals:
va_bar a_bar GND pulse(0 2.5 0 2n 2n 23n 50n)
Voltage Node voltage Type of simulation waveworm

name with respect to
ground
Period
Pulse
width
Rise time Fall time
pulse(0 2.5 0 2n 2n 23n 50n)
Initial Peak Initial Rise Fall Pulse period

value value delay time time width
iv. Type of Simulation

.tran 1n 100n
Transient resolution Simulation

response time
v. Print Waveform
.print tran v(y) v(b_bar) v(a_bar)
Print output Ports to be

Print printed
transient
output
Don‟t forget to add „.END‟ at the end of the file.
*For more information, please refer to Tannel EDA reference manual, „Device
Statement‟ section.
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eg netlist:
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Creating an 2-input OR gate: Simulate Netlist
1. Click to simulate the netlist.
2. The input file is specified automatically. Choose where to save the output file. Click
„start simulation‟ to begin.
3. Click to expand the simulated waveform.
13

Assignment 1.1

Uploaded by

Assignment 1.1

Uploaded by

veCAD-CAD-MAN-TR2008001

veCAD Technical Documentation

S-edit Tutorial on two-input OR gate

Mohamed Khalil-Hani, PhD

Version Date: 13 Jan 2010 (Issue 1.2)

1. About this S-edit Tutorial

Version Date Author Change

Please send comments and inquiries to:

VLSI-ECAD Research Laboratory (veCAD)

Introduction This tutorial is intended to give Tanner EDA an introduction of

This tutorial requires the following hardware and software:

Objectives 1. To expose the user to some of the basic functions of S-

Assignment 1. Two-input OR gate design using S-Edit.

Discussions 1. What would happen if you edit the module parameters in

Reference [1] Jan M. Rabaey, Anantha Chandrakasan, “Digital Integrated

Left click Scroll button Right click

To scroll: use „left‟, „right‟, „up‟, „down‟

Click here to name the

1. Click this symbol to generate netlist.

i. Include MOSFET definition file:

The MOSFET Definition file which must be same

ii. Define Power Supplies:

Voltage Default Voltage2 with respect

Voltage Node voltage Type of simulation waveworm

Rise time Fall time

pulse(0 2.5 0 2n 2n 23n 50n)

Initial Peak Initial Rise Fall Pulse period

iv. Type of Simulation

Transient resolution Simulation

Print output Ports to be

Don‟t forget to add „.END‟ at the end of the file.

1. Click to simulate the netlist.

3. Click to expand the simulated waveform.

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