EC3492 Digital Signal Processing Lecture Notes 1
EC3492 Digital Signal Processing Lecture Notes 1
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Features:
• Advanced VLIW CPU of TMS 320C67X consists 32 general purpose
register. Each register has 32-Bits.
• It has 8 functional units, each functional unit consists of two multiplier
and 6 Arithmetic Logic units.
• It can execute 8 instructions per cycle. Highly effective RISC codes can
be developed.
• Industry’s first assembly optimizer for fast development and improved
Parallelization
• Variable-width instructions: Flexibility of data types of 8/16/32-bit data
support, providing efficient memory support
• It provides hardware support for single precision 32-Bits and double
precision 64-Bits IEEE floating point operations.
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The program fetch, instruction dispatch and instruction decode unit can
deliver up to eight 32 bit instructions to the functional unit every CPU clock
cycle.
The processing of instruction occurs in each of the two data paths, each
contains four functional units and 16, 32-bit general-purpose registers.
A control register file provides the means to configure and control various
processor operation.
➢ Two 32–bit paths for storing data to memory from the register file
o ST1 for register file A
o ST2 for register file B
➢ Two data address paths (DA1 and DA2)
➢ Two register file data cross paths (1X and 2X).
Internal Memory
The c67x DSP has a 32 bit, byte addressable address space.
Internal memory is organized in separate data and prog spaces.
When off chip memory is used, these spaces are unified on most devices to a
single memory space via the external; memory interface (EMIF).
Memory and peripheral options
A variety of memory and peripherals options are available for the C6000
platform.
• Large on chip RAM, up-to 7M bits
• Program cache.
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• 2 level cache.
• 32 bit external memory interface supports SDRAM, SBSRAM,
SRAM, and other asynchronous memories for a board range of
external memory requirement and max system performance.
• DMA controller transfers data between address ranges in the memory
map without intervention by the CPU.
• EDMA controller performs the same functions as the DMA controller.
• HPI is a parallel port through which a host processor can directly
access the CPU’s memory space.
• Expansion bus is a replacement for the HPI, as well as an expansion of
the EMIF.
• McBSP is based on the standard serial port interface
Timers in the C67X devices are two 32-bit general-purpose timers used for
these functions.
• Time event.
• Count event.
• Generate pulses.
• Interrupt the CPU.
• Send synchronization events to the DMA/EDMA controllers.
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