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Tuhin Karak
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© © All Rights Reserved
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Design of Conventional Folded Cascode Amplifier

2023JVL2740 Rishabh Gupta, M.Tech VDTT(Vlsi Design Tools and Technology) student @IIT-D, INDIA

CWD of the Assignment-


/afs/iitd.ac.in/user/j/jv/jvl232740/Analog/folded_cascode/FC

Literature Survey-
Frequency Response and Settling ‘Time of Oper;tion~ Amplifiers B. YESHWANT KAMATH, STUDENT
MEMBER, IEEE, ROBERT G. MEYER, MEMBER,IEEE, AND PAUL R. GRAY, MEMBER, IEEE

> Learnt about the effects of pole-zero pairs (doublets) on the frequency response and settling time of
operational amplifier.

The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier Rida S.
Assaad, Student Member, IEEE, and Jose Silva-Martinez, Senior Member, IEEE

> Gone through the paper to implement the conventional folded cascode amplifier. However, the
improved Recycling folded cascode amplifer was compared with the conventional amplifier in this paper
in detail.

Abstract-
A conventional folded cascode amplifier is designed and simulated in TSMC 180nm PDK and the
simulation results are compared with theoretical results.

Introduction -

The design is implemented with an approach to obtain dimensions and parameters of device.
The power of the circuit was taken as a reference which helps in the calculation of the tail current.
The PMOS architecture is implemented to get the high ICMR as compared to that of the NMOS
differential input pair architecture.

In the circuit design implementation, the


> drain current (Id),
>Transconductance(gm),
>aspect ratio (W/L)
and overdrive voltage (Vgs-Vth) is calculated and accordingly Vds value is chosen to operate the device
in saturation region.

Note – The calculated width was large then the multipliers are used in the design in differential inputs
and current mirrors to reduce the effect of IR drop in the layout consideration has been taken care in
the design implementation.
The length (L) of current mirrors used in the design is ~ 3to4 times of the PDK minimum L as to reduce
the effect of channel length modulation which increases the output impedance and variation of current
due to input voltage variation which changes Vds of other PMOS and NMOS devices in the circuit.

The slew rate for the Conventional FC is given by: 2I/CL.

Fig1 Schematic of Conventional Folded Cascode Amplifier with Biasing circuit

Devices Corresponding FC(W(um)/L (nm)) Multipliers Given in paper


referenced in Fig2 Devices Used Used in the design Effective
W(um)/L(nm)
M0 M8 Tail PMOS 8/540 16 128/540
M1/M2 M10/M11 Diff I/P 8/360 16 128/360
M9/M10 M0/M2 Wide 8/540 8 64/540
Swing
M7/M8 M4/M5 PCAS 8/180 8 64/180
M5/M6 M6/M7 NCAS 8/180 2 16/180
M3/M4 M3/M1 NTAIL 8/540 4 32/540
Fig2 Conventional Folded Cascode Amplifier

Different analyses was performed as shown-

Dc –

For operating points estimation and was done to make sure all the transistors was operating in
saturation .

Stb-

For gain and phase margin.

Transient -

For slew rate calculation.

Xf -

For PSRR

Noise -

For output and input noise


Fig3 Testbench for dc and stability analysis.

Fig4 ADE operating regions and analyses


Note all the mosfets was in saturation region however M14 was used as a linear resistor in biasing so the
operating region is 1 as shown.

Fig5 Stability summary

Fig6 Loop Gain Phase/db20


Fig7 Noise@1K – 100K

Fig8 Low frequency noise (fn) dominates as shown for M3/M1/M10

However, if we increase the frequency range from 1K – 10G the thermal noise id dominates as shown
Fig9 Noise@1K – 10G

Fig 10 High frequency noise (id) dominates as shown for M3/M1/M10


Fig 11 Output Noise

Fig 12 Power in Watts


Fig 13 PSRR

Fig 14a Slew Rate


Fig 14b Slew Rate

Conclusion
The design provides a gain of 58dB and phase margin around 80 degrees with PSRR ~ 63 dB & slew rate
44.13 V/us with power consumption of about 1.2 mW with load cap 5.6p F.

Refrences -
The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier Rida S. Assaad,
Student Member, IEEE, and Jose Silva-Martinez, Senior Member, IEEE

Frequency Response and Settling ‘Time of Oper;tion~ Amplifiers B. YESHWANT KAMATH, STUDENT
MEMBER, IEEE, ROBERT G. MEYER, MEMBER,IEEE, AND PAUL R. GRAY, MEMBER, IEEE

CMOS: Circuit Design, Layout, and Simulation (IEEE Press Series on Microelectronic Systems)
R. Jacob Baker is a Professor of Electrical and Computer Engineering at the University of Nevada, Las
Vegas. For additional information see CMOSedu.com

Design of Analog CMOS Integrated Circuits (Behzad Razavi)

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