Micom P40 Agile: Ge Grid Solutions

GE
Grid Solutions
MiCOM P40 Agile

P841B
Technical Manual
Dual-CB Autoreclose IED
Hardware Version: M
Software Version: 79
Publication Reference: P841B-TM-EN-1.1
Contents
Chapter 1 Introduction 1
1 Chapter Overview 3
2 Foreword 4
2.1 Target Audience 4
2.2 Typographical Conventions 4
2.3 Nomenclature 5
2.4 Compliance 5
3 Product Scope 6
3.1 Product Versions 6
3.2 Ordering Options 7
4 Features and Functions 9
4.1 Protection Functions 9
4.2 Control Functions 9
4.3 Measurement Functions 10
4.4 Communication Functions 10
5 Logic Diagrams 11
6 Functional Overview 13
Chapter 2 Safety Information 15

2 Health and Safety 18
3 Symbols 19
4 Installation, Commissioning and Servicing 20
4.1 Lifting Hazards 20
4.2 Electrical Hazards 20
4.3 UL/CSA/CUL Requirements 21
4.4 Fusing Requirements 21
4.5 Equipment Connections 22
4.6 Protection Class 1 Equipment Requirements 22
4.7 Pre-energisation Checklist 23
4.8 Peripheral Circuitry 23
4.9 Upgrading/Servicing 25
5 Decommissioning and Disposal 26
6 Regulatory Compliance 27
6.1 EMC Compliance: 2014/30/EU 27
6.2 LVD Compliance: 2014/35/EU 27
6.3 R&TTE Compliance: 2014/53/EU 27
6.4 UL/CUL Compliance 27
6.5 ATEX Compliance: 2014/34/EU 27
Chapter 3 Hardware Design 29

2 Hardware Architecture 32
3 Mechanical Implementation 33
3.1 Housing Variants 33
3.2 List of Boards 34
4 Front Panel 35
4.1 Front Panel 35
4.1.1 Front Panel Compartments 35
4.1.2 Keypad 36
4.1.3 Front Serial Port (SK1) 36
Contents P841B
4.1.4 Front Parallel Port (SK2) 37

4.1.5 Fixed Function LEDs 37
4.1.6 Function Keys 37
4.1.7 Programable LEDs 38
5 Rear Panel 39
6 Boards and Modules 41
6.1 PCBs 41
6.2 Subassemblies 41
6.3 Main Processor Board 42
6.4 Power Supply Board 43
6.4.1 Watchdog 45
6.4.2 Rear Serial Port 46
6.5 Input Module - 1 Transformer Board 47
6.5.1 Input Module Circuit Description 48
6.5.2 Transformer Board 49
6.5.3 Input Board 50
6.6 Standard Output Relay Board 51
6.7 IRIG-B Board 52
6.8 Fibre Optic Board 53
6.9 Rear Communication Board 54
6.10 Ethernet Board 54
6.11 Redundant Ethernet Board 56
Chapter 4 Software Design 59

2 Sofware Design Overview 62
3 System Level Software 63
3.1 Real Time Operating System 63
3.2 System Services Software 63
3.3 Self-Diagnostic Software 63
3.4 Startup Self-Testing 63
3.4.1 System Boot 63
3.4.2 System Level Software Initialisation 64
3.4.3 Platform Software Initialisation and Monitoring 64
3.5 Continuous Self-Testing 64
4 Platform Software 66
4.1 Record Logging 66
4.2 Settings Database 66
4.3 Interfaces 66
5 Protection and Control Functions 67
5.1 Acquisition of Samples 67
5.2 Frequency Tracking 67
5.3 Direct Use of Sample Values 67
5.4 Fourier Signal Processing 67
5.5 Programmable Scheme Logic 68
5.6 Event Recording 69
5.7 Disturbance Recorder 69
5.8 Fault Locator 69
5.9 Function Key Interface 69
Chapter 5 Configuration 71
2 Settings Application Software 74
3 Using the HMI Panel 75
3.1 Navigating the HMI Panel 76
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3.2 Getting Started 76

3.3 Default Display 77
3.4 Default Display Navigation 78
3.5 Password Entry 79
3.6 Processing Alarms and Records 80
3.7 Menu Structure 80
3.8 Changing the Settings 81
3.9 Direct Access (The Hotkey menu) 82
3.9.1 Setting Group Selection Using Hotkeys 82
3.9.2 Control Inputs 83
3.9.3 Circuit Breaker Control 83
3.10 Function Keys 84
4 Line Parameters 86
4.1 Tripping Mode 86
4.1.1 CB Trip Conversion Logic Diagram 87
4.2 Residual Compensation 87
4.3 Mutual Compensation 88
5 Date and Time Configuration 90
5.1 Time Zone Compensation 90
5.2 Daylight Saving Time Compensation 90
6 Settings Group Selection 91
Chapter 6 Autoreclose 93
2 Introduction to Autoreclose 96
3 Autoreclose Implementation 97
3.1 Autoreclose Logic Inputs from External Sources 98
3.1.1 Circuit Breaker Healthy Input 98
3.1.2 Inhibit Autoreclose Input 98
3.1.3 Block Autoreclose Input 98
3.1.4 Reset Lockout Input 99
3.1.5 Pole Discrepancy Input 99
3.1.6 External Trip Indication 99
3.2 Autoreclose Logic Inputs 99
3.2.1 Trip Initiation Signals 99
3.2.2 Circuit Breaker Status Inputs 99
3.2.3 System Check Signals 99
3.3 Autoreclose Logic Outputs 99
3.4 Autoreclose Operating Sequence 100
3.4.1 AR Timing Sequence - Transient Fault 100
3.4.2 AR Timing Sequence - Evolving/Permanent Fault 100
3.4.3 AR Timing Sequence - Evolving/Permanent Fault Single-phase 101
3.4.4 AR Timing Sequence - Transient Fault Dual CB 101
3.4.5 AR Timing Sequence - Evolving/Permanent Fault Dual CB 102
3.4.6 AR Timing Sequence - Persistent Fault 103
4 Autoreclose System Map 105
4.1 Autoreclose System Map Diagrams 107
4.2 Autoreclose Internal Signals 116
4.3 Autoreclose DDB Signals 121
5 Logic Modules 133
5.1 Circuit Breaker Status Monitor 133
5.1.1 CB State Monitor 134
5.2 Circuit Breaker Open Logic 134
5.2.1 Circuit Breaker Open Logic Diagram 135
5.3 Circuit Breaker in Service Logic 135
5.3.1 Circuit Breaker in Service Logic Diagram 136
5.4 Autoreclose Enable Logic 136
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5.4.1 Autoreclose Enable Logic Diagram 136

5.5 Autoreclose Leader/Follower 136
5.5.1 Leader/Follower CB Selection Logic Diagram 137
5.5.2 Leader Follower Logic Diagram 138
5.6 Autoreclose Modes 139
5.6.1 Single-Phase and Three-Phase Autoreclose 139
5.6.2 Autoreclose Modes Enable Logic Diagram 140
5.7 AR Force Three-Phase Trip Logic 141
5.7.1 Force Three-Phase Trip Logic Diagram 141
5.8 Autoreclose Initiation Logic 142
5.8.1 Autoreclose Initiation Logic Diagram 143
5.8.2 Autoreclose Trip Test Logic Diagram 143
5.8.3 External Trip Logic Diagram for CB1 144
5.8.4 External Trip Logic Diagram for CB2 145
5.8.5 Protection Reoperation and Evolving Fault Logic Diagram 146
5.8.6 Fault Memory Logic Diagram 146
5.9 Autoreclose In Progress 146
5.9.1 Autoreclose In Progress Logic Diagram for CB1 147
5.9.2 Autoreclose In Progress Logic Diagram for CB2 148
5.10 Sequence Counter 148
5.10.1 Autoreclose Sequence Counter Logic Diagram 149
5.11 Autoreclose Cycle Selection 149
5.11.1 Single Phase Autoreclose Cycle Selection Logic Diagram 150
5.11.2 3-phase Autoreclose Cycle Selection 151
5.12 Dead Time Control 151
5.12.1 Dead Time Start Enable Logic Diagram 152
5.12.2 Single-phase Leader Dead Time Logic Diagram 153
5.12.3 3-phase Leader Dead Time Logic Diagram 154
5.12.4 Follower Enable Logic Diagram 155
5.12.5 Single-phase Follower Timing Logic Diagram 156
5.12.6 Three-phase Follower Timing Logic Diagram 157
5.13 Circuit Breaker Autoclose 157
5.13.1 Circuit Breaker Autoclose Logic Diagram 158
5.14 Reclaim Time 158
5.14.1 Prepare Reclaim Initiation Logic Diagram 159
5.14.2 Reclaim Time Logic Diagram 160
5.14.3 Succesful Autoreclose Signals Logic Diagram 161
5.14.4 Autoreclose Reset Successful Indication Logic Diagram 162
5.15 CB Healthy and System Check Timers 162
5.15.1 CB Healthy and System Check Timers Logic Diagram 163
5.16 Autoreclose Shot Counters 163
5.16.1 Autoreclose Shot Counters Logic Diagram 165
5.17 Circuit Breaker Control 166
5.17.1 CB Control Logic Diagram 166
5.18 Circuit Breaker Trip Time Monitoring 167
5.18.1 CB Trip Time Monitoring Logic Diagram 168
5.19 Autoreclose Lockout 169
5.19.1 CB Lockout Logic Diagram 170
5.20 Reset Circuit Breaker Lockout 171
5.20.1 Reset CB Lockout Logic Diagram 173
5.21 Pole Discrepancy 173
5.21.1 Pole Discrepancy Logic Diagram 174
5.22 Circuit Breaker Trip Conversion 174
5.22.1 CB Trip Conversion Logic Diagram 175
5.23 Monitor Checks for CB Closure 175
5.23.1 Voltage Monitor for CB Closure 176
5.23.2 Check Synchronisation Monitor for CB Closure 177
5.24 Synchronisation Checks for CB Closure 178
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5.24.1 Three-phase Autoreclose Leader Check Logic Diagram 180

5.24.2 Three-phase Autoreclose Follower Check Logic Diagram 182
5.24.3 CB Manual Close System Check Logic Diagram 184
6 Setting Guidelines 185
6.1 De-ionising Time Guidance 185
6.2 Dead Timer Setting Guidelines 185
6.2.1 Example Dead Time Calculation 185
6.3 Reclaim Time Setting Guidelines 186
6.4 Autoreclose Shot Counters 186
Chapter 7 CB Fail Protection 189

2 Circuit Breaker Fail Protection 192
3 Circuit Breaker Fail Implementation 193
3.1 Circuit Breaker Fail Timers 193
3.2 Zero Crossing Detection 193
4 Circuit Breaker Fail Logic 195
4.1 Circuit Breaker Fail Logic - Part 1 195
5 Application Notes 199
5.1 Reset Mechanisms for CB Fail Timers 199
5.2 Setting Guidelines (CB fail Timer) 199
5.3 Setting Guidelines (Undercurrent) 200
Chapter 8 Current Protection Functions 201

2 Phase Fault Overcurrent Protection 204
2.1 POC Implementation 204
2.2 Directional Element 204
2.3 POC Logic 206
3 Negative Sequence Overcurrent Protection 207
3.1 Negative Sequence Overcurrent Protection Implementation 207
3.3 NPSOC Logic 208
3.4 Application Notes 208
3.4.1 Setting Guidelines (Current Threshold) 208
3.4.2 Setting Guidelines (Time Delay) 208
3.4.3 Setting Guidelines (Directional element) 208
4 Earth Fault Protection 210
4.1 Earth Fault Protection Implementation 210
4.2 IDG Curve 210
4.3.1 Residual Voltage Polarisation 211
4.3.2 Negative Sequence Polarisation 212
4.4 Earth Fault Protection Logic 213
4.5.1 Residual Voltage Polarisation Setting Guidelines 213
4.5.2 Setting Guidelines (Directional Element) 213
5 Sensitive Earth Fault Protection 215
5.1 SEF Protection Implementation 215
5.2 EPATR B Curve 215
5.3 Sensitive Earth Fault Protection Logic 216
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Contents P841B
5.4.1 Insulated Systems 217

5.4.2 Setting Guidelines (Insulated Systems) 218
6 High Impedance REF 220
6.1 High Impedance REF Principle 220
7 Thermal Overload Protection 222
7.1 Single Time Constant Characteristic 222
7.2 Dual Time Constant Characteristic 222
7.3 Thermal Overload Protection Implementation 223
7.4 Thermal Overload Protection Logic 223
7.5.1 Setting Guidelines for Dual Time Constant Characteristic 223
7.5.2 Setting Guidelines for Single Time Constant Characteristic 225
8 Broken Conductor Protection 226
8.1 Broken Conductor Protection Implementation 226
8.2 Broken Conductor Protection Logic 226
8.3.1 Setting Guidelines 226
Chapter 9 Voltage Protection Functions 229

2 Undervoltage Protection 232
2.1 Undervoltage Protection Implementation 232
2.2 Undervoltage Protection Logic 233
2.3.1 Undervoltage Setting Guidelines 234
3 Overvoltage Protection 235
3.1 Overvoltage Protection Implementation 235
3.2 Overvoltage Protection Logic 236
3.3.1 Overvoltage Setting Guidelines 237
4 Compensated Overvoltage 238
5 Residual Overvoltage Protection 239
5.1 Residual Overvoltage Protection Implementation 239
5.2 Residual Overvoltage Logic 240
5.3.1 Calculation for Solidly Earthed Systems 240
5.3.2 Calculation for Impedance Earthed Systems 241
Chapter 10 Frequency Protection Functions 243

2 Frequency Protection 246
2.1 Underfrequency Protection 246
2.1.1 Underfrequency Protection Implementation 246
2.1.2 Underfrequency Protection logic 247
2.1.3 Application Notes 247
2.2 Overfrequency Protection 247
2.2.1 Overfrequency Protection Implementation 247
2.2.2 Overfrequency Protection logic 248
2.2.3 Application Notes 248
3 Independent R.O.C.O.F Protection 249
3.1 Indepenent R.O.C.O.F Protection Implementation 249
3.2 Independent R.O.C.O.F Protection Logic 249
Chapter 11 Current Transformer Requirements 251
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2 Recommended CT Classes 254
3 Current Differential Requirements 255
4 Determining Vk for IEEE C-class CT 256
5 Worked Examples 257
5.1 Overcurrent Elements 257
5.2 Overcurrent Elements 257
Chapter 12 Monitoring and Control 259

2 Event Records 262
2.1 Event Types 262
2.1.1 Opto-input Events 263
2.1.2 Contact Events 263
2.1.3 Alarm Events 263
2.1.4 Fault Record Events 264
2.1.5 Maintenance Events 264
2.1.6 Protection Events 264
2.1.7 Security Events 265
2.1.8 Platform Events 265
3 Disturbance Recorder 266
4 Measurements 267
4.1 Measured Quantities 267
4.2 Measurement Setup 267
4.4 Opto-input Time Stamping 267
5 CB Condition Monitoring 268
5.1 Broken Current Accumulator 269
5.2 CB Trip Counter 270
5.3 CB Operating Time Accumulator 271
5.4 Excessive Fault Frequency Counter 272
5.5 Reset Lockout Alarm 273
5.6 CB Condition Monitoring Logic 274
5.7 Reset Circuit Breaker Lockout 275
5.7.1 Reset CB Lockout Logic Diagram 277
5.8.1 Setting the Thresholds for the Total Broken Current 277
5.8.2 Setting the thresholds for the Number of Operations 278
5.8.3 Setting the thresholds for the Operating Time 278
5.8.4 Setting the Thresholds for Excesssive Fault Frequency 278
6 CB State Monitoring 279
6.1 CB State Monitor 280
7 Circuit Breaker Control 281
7.1 CB Control using the IED Menu 281
7.2 CB Control using the Hotkeys 282
7.3 CB Control using the Function Keys 282
7.4 CB Control using the Opto-inputs 283
7.5 Remote CB Control 283
7.6 CB Healthy Check 284
7.7 Synchronisation Check 284
7.8 CB Control AR Implications 284
7.9 CB Control Logic Diagram 285
8 Pole Dead Function 287
8.1 Pole Dead Logic 287
9 System Checks 288
9.1 System Checks Implementation 288
P841B-TM-EN-1.1 vii
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9.1.1 VT Connections 288

9.1.2 Voltage Monitoring 289
9.1.3 Check Synchronisation 289
9.1.4 Check Syncronisation Vector Diagram 289
9.2 Voltage Monitor for CB Closure 291
9.3 Check Synchronisation Monitor for CB Closure 292
9.4 System Check PSL 294
9.5.1 Predictive Closure of Circuit Breakers 294
9.5.2 Voltage and Phase Angle Correction 294
Chapter 13 Supervision 297

2 Voltage Transformer Supervision 300
2.1 Loss of One or Two Phase Voltages 300
2.2 Loss of all Three Phase Voltages 300
2.3 Absence of all Three Phase Voltages on Line Energisation 300
2.4 VTS Implementation 301
2.5 VTS Logic 302
3 Current Transformer Supervision 304
3.1 CTS Implementation 304
3.2 Standard CTS Logic 305
3.3 CTS Blocking 305
4 Trip Circuit Supervision 306
4.1 Trip Circuit Supervision Scheme 1 306
4.1.1 Resistor Values 306
4.1.2 PSL for TCS Scheme 1 307
Chapter 14 Digital I/O and PSL Configuration 311

2 Configuring Digital Inputs and Outputs 314
3 Scheme Logic 315
3.1 PSL Editor 316
3.2 PSL Schemes 316
3.3 PSL Scheme Version Control 316
4 Configuring the Opto-Inputs 317
5 Assigning the Output Relays 318
6 Fixed Function LEDs 319
6.1 Trip LED Logic 319
7 Configuring Programmable LEDs 320
8 Function Keys 322
9 Control Inputs 323
Chapter 15 Electrical Teleprotection 325

2 Introduction 328
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3 Teleprotection Scheme Principles 329

3.1 Direct Tripping 329
3.2 Permissive Tripping 329
4 Implementation 330
5 Configuration 331
6 Connecting to Electrical InterMiCOM 333
6.1 Short Distance 333
6.2 Long Distance 333
7 Application Notes 334
Chapter 16 Communications 337

2 Communication Interfaces 340
3 Serial Communication 341
3.1 EIA(RS)232 Bus 341
3.2 EIA(RS)485 Bus 341
3.2.1 EIA(RS)485 Biasing Requirements 342
3.3 K-Bus 342
4 Standard Ethernet Communication 344
4.1 Hot-Standby Ethernet Failover 344
5 Redundant Ethernet Communication 345
5.1 Supported Protocols 345
5.2 Parallel Redundancy Protocol 346
5.3 High-Availability Seamless Redundancy (HSR) 347
5.3.1 HSR Multicast Topology 347
5.3.2 HSR Unicast Topology 347
5.3.3 HSR Application in the Substation 348
5.4 Rapid Spanning Tree Protocol 349
5.5 Self Healing Protocol 350
5.6 Dual Homing Protocol 351
5.7 Configuring IP Addresses 353
5.7.1 Configuring the IED IP Address 354
5.7.2 Configuring the REB IP Address 354
5.8 PRP/HSR Configurator 356
5.8.1 Connecting the IED to a PC 357
5.8.2 Installing the Configurator 357
5.8.3 Starting the Configurator 357
5.8.4 PRP/HSR Device Identification 358
5.8.5 Selecting the Device Mode 358
5.8.6 PRP/HSR IP Address Configuration 358
5.8.7 SNTP IP Address Configuration 358
5.8.8 Check for Connected Equipment 358
5.8.9 PRP Configuration 358
5.8.10 HSR Configuration 359
5.8.11 Filtering Database 359
5.8.12 End of Session 360
5.9 RSTP Configurator 360
5.9.1 Connecting the IED to a PC 360
5.9.2 Installing the Configurator 361
5.9.3 Starting the Configurator 361
5.9.4 RSTP Device Identification 361
5.9.5 RSTP IP Address Configuration 362
5.9.6 SNTP IP Address Configuration 362
5.9.8 RSTP Configuration 362
5.10 Switch Manager 363
P841B-TM-EN-1.1 ix
Contents P841B
5.10.1 Installation 364

5.10.2 Setup 365
5.10.3 Network Setup 365
5.10.4 Bandwidth Used 365
5.10.5 Reset Counters 365
5.10.7 Mirroring Function 366
5.10.8 Ports On/Off 366
5.10.9 VLAN 366
6 Simple Network Management Protocol (SNMP) 367
6.1 SNMP Management Information Bases 367
6.2 Main Processor MIBS Structure 367
6.3 Redundant Ethernet Board MIB Structure 368
6.4 Accessing the MIB 372
6.5 Main Processor SNMP Configuration 372
7 Data Protocols 374
7.1 Courier 374
7.1.1 Physical Connection and Link Layer 374
7.1.2 Courier Database 375
7.1.3 Settings Categories 375
7.1.4 Setting Changes 375
7.1.5 Event Extraction 375
7.1.6 Disturbance Record Extraction 377
7.1.7 Programmable Scheme Logic Settings 377
7.1.8 Time Synchronisation 377
7.1.9 Courier Configuration 378
7.2 IEC 60870-5-103 379
7.2.2 Initialisation 380
7.2.3 Time Synchronisation 380
7.2.4 Spontaneous Events 380
7.2.5 General Interrogation (GI) 380
7.2.6 Cyclic Measurements 380
7.2.7 Commands 380
7.2.8 Test Mode 381
7.2.9 Disturbance Records 381
7.2.10 Command/Monitor Blocking 381
7.2.11 IEC 60870-5-103 Configuration 381
7.3 DNP 3.0 382
7.3.2 Object 1 Binary Inputs 383
7.3.3 Object 10 Binary Outputs 383
7.3.4 Object 20 Binary Counters 384
7.3.5 Object 30 Analogue Input 384
7.3.6 Object 40 Analogue Output 385
7.3.7 Object 50 Time Synchronisation 385
7.3.8 DNP3 Device Profile 385
7.3.9 DNP3 Configuration 393
7.4 IEC 61850 394
7.4.1 Benefits of IEC 61850 394
7.4.2 IEC 61850 Interoperability 395
7.4.3 The IEC 61850 Data Model 395
7.4.4 IEC 61850 in MiCOM IEDs 396
7.4.5 IEC 61850 Data Model Implementation 396
7.4.6 IEC 61850 Communication Services Implementation 396
7.4.7 IEC 61850 Peer-to-peer (GOOSE) communications 397
7.4.8 Mapping GOOSE Messages to Virtual Inputs 397
7.4.9 Ethernet Functionality 397
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7.4.10 IEC 61850 Configuration 397

8 Read Only Mode 399
8.1 IEC 60870-5-103 Protocol Blocking 399
8.2 Courier Protocol Blocking 399
8.3 IEC 61850 Protocol Blocking 400
8.4 Read-Only Settings 400
8.5 Read-Only DDB Signals 400
9 Time Synchronisation 401
9.1 Demodulated IRIG-B 401
9.1.1 IRIG-B Implementation 402
9.2 SNTP 402
9.2.1 Loss of SNTP Server Signal Alarm 402
9.3 Time Synchronsiation using the Communication Protocols 402
Chapter 17 Cyber-Security 403

1 Overview 405
2 The Need for Cyber-Security 406
3 Standards 407
3.1 NERC Compliance 407
3.1.1 CIP 002 408
3.1.2 CIP 003 408
3.1.3 CIP 004 408
3.1.4 CIP 005 408
3.1.5 CIP 006 408
3.1.6 CIP 007 409
3.1.7 CIP 008 409
3.1.8 CIP 009 409
3.2 IEEE 1686-2007 409
4 Cyber-Security Implementation 411
4.1 NERC-Compliant Display 411
4.2 Four-level Access 412
4.2.1 Blank Passwords 413
4.2.2 Password Rules 414
4.2.3 Access Level DDBs 414
4.3 Enhanced Password Security 414
4.3.1 Password Strengthening 414
4.3.2 Password Validation 415
4.3.3 Password Blocking 415
4.4 Password Recovery 416
4.4.1 Entry of the Recovery Password 416
4.4.2 Password Encryption 417
4.5 Disabling Physical Ports 417
4.6 Disabling Logical Ports 417
4.7 Security Events Management 418
4.8 Logging Out 420
Chapter 18 Installation 421

2 Handling the Goods 424
2.1 Receipt of the Goods 424
2.2 Unpacking the Goods 424
2.3 Storing the Goods 424
2.4 Dismantling the Goods 424
3 Mounting the Device 425
3.1 Flush Panel Mounting 425
3.2 Rack Mounting 426
P841B-TM-EN-1.1 xi
Contents P841B
4 Cables and Connectors 428

4.1 Terminal Blocks 428
4.2 Power Supply Connections 429
4.3 Earth Connnection 429
4.4 Current Transformers 429
4.5 Voltage Transformer Connections 430
4.6 Watchdog Connections 430
4.7 EIA(RS)485 and K-Bus Connections 430
4.8 IRIG-B Connection 430
4.9 Opto-input Connections 430
4.10 Output Relay Connections 430
4.11 Ethernet Metallic Connections 431
4.12 Ethernet Fibre Connections 431
4.13 RS232 connection 431
4.14 Download/Monitor Port 431
4.15 GPS Fibre Connection 431
4.16 Fibre Communication Connections 431
5 Case Dimensions 432
5.1 Case Dimensions 40TE 432
Chapter 19 Commissioning Instructions 435

2 General Guidelines 438
3 Commissioning Test Menu 439
3.1 Opto I/P Status Cell (Opto-input Status) 439
3.2 Relay O/P Status Cell (Relay Output Status) 439
3.3 Test Port Status Cell 439
3.4 Monitor Bit 1 to 8 Cells 439
3.5 Test Mode Cell 440
3.6 Test Pattern Cell 440
3.7 Contact Test Cell 440
3.8 Test LEDs Cell 440
3.9 Test Autoreclose Cell 440
3.10 Static Test Mode 441
3.11 Loopback Mode 441
3.12 IM64 Test Pattern 442
3.13 IM64 Test Mode 442
3.14 Red and Green LED Status Cells 442
3.15 Using a Monitor Port Test Box 442
4 Commissioning Equipment 443
4.1 Recommended Commissioning Equipment 443
4.2 Essential Commissioning Equipment 443
4.3 Advisory Test Equipment 444
5 Product Checks 445
5.1 Product Checks with the IED De-energised 445
5.1.1 Visual Inspection 445
5.1.2 Current Transformer Shorting Contacts 446
5.1.3 Insulation 446
5.1.4 External Wiring 446
5.1.5 Watchdog Contacts 446
5.1.6 Power Supply 447
5.2 Product Checks with the IED Energised 447
5.2.1 Watchdog Contacts 447
5.2.2 Test LCD 448
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5.2.3 Date and Time 448

5.2.4 Test LEDs 449
5.2.5 Test Alarm and Out-of-Service LEDs 449
5.2.6 Test Trip LED 449
5.2.7 Test User-programmable LEDs 449
5.2.8 Test Field Voltage Supply 449
5.2.9 Test Opto-inputs 449
5.2.10 Test Output Relays 450
5.2.11 Test Serial Communication Port RP1 450
5.2.12 Test Serial Communication Port RP2 451
5.2.13 Test Ethernet Communication 452
5.3 Secondary Injection Tests 452
5.3.1 Test Current Inputs 452
5.3.2 Test Voltage Inputs 453
6 Electrical Intermicom Communication Loopback 454
6.1 Setting up the Loopback 454
6.2 Loopback Test 454
6.2.1 InterMicom Command Bits 455
6.2.2 InterMicom Channel Diagnostics 455
6.2.3 Simulating a Channel Failure 455
7 Setting Checks 456
7.1 Apply Application-specific Settings 456
7.1.1 Transferring Settings from a Settings File 456
7.1.2 Entering settings using the HMI 456
8 Protection Timing Checks 458
8.1 Overcurrent Check 458
8.2 Connecting the Test Circuit 458
8.3 Performing the Test 458
8.4 Check the Operating Time 458
9 System Check and Check Synchronism 460
9.1 Check Synchronism Pass 460
9.2 Check Synchronism Fail 460
10 Check Trip and Autoreclose Cycle 461
11 Onload Checks 462
11.1 Confirm Voltage Connections 462
11.2 Confirm Current Connections 462
11.3 On-load Directional Test 463
12 Final Checks 464
Chapter 20 Maintenance and Troubleshooting 465

2 Maintenance 468
2.1 Maintenance Checks 468
2.1.1 Alarms 468
2.1.2 Opto-isolators 468
2.1.3 Output Relays 468
2.1.4 Measurement Accuracy 468
2.2 Replacing the Device 469
2.3 Repairing the Device 470
2.4 Removing the front panel 470
2.5 Replacing PCBs 471
2.5.1 Replacing the main processor board 471
2.5.2 Replacement of communications boards 472
2.5.3 Replacement of the input module 473
2.5.4 Replacement of the power supply board 473
2.5.5 Replacement of the I/O boards 474
2.6 Recalibration 474
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2.7 Changing the battery 474

2.7.1 Post Modification Tests 475
2.7.2 Battery Disposal 475
2.8 Cleaning 475
3 Troubleshooting 476
3.1 Self-Diagnostic Software 476
3.2 Power-up Errors 476
3.3 Error Message or Code on Power-up 476
3.4 Out of Service LED on at power-up 477
3.5 Error Code during Operation 478
3.5.1 Backup Battery 478
3.6 Mal-operation during testing 478
3.6.1 Failure of Output Contacts 478
3.6.2 Failure of Opto-inputs 478
3.6.3 Incorrect Analogue Signals 479
3.7 Coprocessor board failures 479
3.7.1 Signalling failure alarm (on its own) 479
3.7.2 C diff failure alarm (on its own) 479
3.7.3 Signalling failure and C diff failure alarms together 479
3.7.4 Incompatible IED 479
3.7.5 Comms changed 479
3.7.6 IEEE C37.94 fail 480
3.8 PSL Editor Troubleshooting 480
3.8.1 Diagram Reconstruction 480
3.8.2 PSL Version Check 480
3.9 Repair and Modification Procedure 480
Chapter 21 Technical Specifications 483

2 Interfaces 486
2.1 Front Serial Port 486
2.2 Download/Monitor Port 486
2.3 Rear Serial Port 1 486
2.4 Fibre Rear Serial Port 1 486
2.5 Rear Serial Port 2 487
2.6 Optional Rear Serial Port (SK5) 487
2.7 IRIG-B (Demodulated) 487
2.8 IRIG-B (Modulated) 487
2.9 Rear Ethernet Port Copper 488
2.10 Rear Ethernet Port Fibre 488
2.10.1 100 Base FX Receiver Characteristics 488
2.10.2 100 Base FX Transmitter Characteristics 488
3 Protection Functions 490
3.1 Autoreclose and Check Synychronism 490
3.2 Phase Overcurrent Protection 490
3.2.1 Transient Overreach and Overshoot 490
3.2.2 Phase Overcurrent Directional Parameters 490
3.3 Earth Fault Protection 490
3.3.1 Earth Fault Directional Parameters 491
3.4 Sensitive Earth Fault Protection 491
3.4.1 Sensitive Earth Fault Protection Directional Element 491
3.5 High Impedance Restricted Earth Fault Protection 492
3.6 Negative Sequence Overcurrent Protection 492
3.6.1 NPSOC Directional Parameters 492
3.7 Circuit Breaker Fail and Undercurrent Protection 492
3.8 Broken Conductor Protection 493
3.9 Thermal Overload Protection 493
xiv P841B-TM-EN-1.1
P841B Contents
4 Monitoring, Control and Supervision 494

4.1 Voltage Transformer Supervision 494
4.2 Standard Current Transformer Supervision 494
4.3 Differential Current Transformer Supervision 494
4.4 CB State and Condition Monitoring 494
4.5 PSL Timers 495
5 Measurements and Recording 496
5.1 General 496
5.2 Disturbance Records 496
5.3 Event, Fault and Maintenance Records 496
6 Ratings 497
6.1 AC Measuring Inputs 497
6.2 Current Transformer Inputs 497
6.3 Voltage Transformer Inputs 497
6.4 Auxiliary Supply Voltage 497
6.5 Nominal Burden 498
6.6 Power Supply Interruption 498
6.7 Battery Backup 499
7 Input / Output Connections 500
7.1 Isolated Digital Inputs 500
7.1.1 Nominal Pickup and Reset Thresholds 500
7.2 Standard Output Contacts 500
7.3 High Break Output Contacts 501
7.4 Watchdog Contacts 501
8 Mechanical Specifications 502
8.1 Physical Parameters 502
8.2 Enclosure Protection 502
8.3 Mechanical Robustness 502
8.4 Transit Packaging Performance 502
9 Type Tests 503
9.1 Insulation 503
9.2 Creepage Distances and Clearances 503
9.3 High Voltage (Dielectric) Withstand 503
9.4 Impulse Voltage Withstand Test 503
10 Environmental Conditions 504
10.1 Ambient Temperature Range 504
10.2 Temperature Endurance Test 504
10.3 Ambient Humidity Range 504
10.4 Corrosive Environments 504
11 Electromagnetic Compatibility 505
11.1 1 MHz Burst High Frequency Disturbance Test 505
11.2 Damped Oscillatory Test 505
11.3 Immunity to Electrostatic Discharge 505
11.4 Electrical Fast Transient or Burst Requirements 505
11.5 Surge Withstand Capability 505
11.6 Surge Immunity Test 506
11.7 Immunity to Radiated Electromagnetic Energy 506
11.8 Radiated Immunity from Digital Communications 506
11.9 Radiated Immunity from Digital Radio Telephones 506
11.10 Immunity to Conducted Disturbances Induced by Radio Frequency Fields 506
11.11 Magnetic Field Immunity 507
11.12 Conducted Emissions 507
11.13 Radiated Emissions 507
11.14 Power Frequency 507
12 Standards Compliance 508
P841B-TM-EN-1.1 xv
Contents P841B
12.1 EMC Compliance: 2004/108/EC 508

12.2 Product Safety: 2006/95/EC 508
12.3 R&TTE Compliance 508
12.4 UL/CUL Compliance 508
Appendix A Ordering Options 509
Appendix B Settings and Signals 511
Appendix C Wiring Diagrams 513
xvi P841B-TM-EN-1.1
Table of Figures
Figure 1: P40L family - version evolution 7
Figure 2: Key to logic diagrams 12
Figure 3: Functional Overview 13
Figure 4: Hardware architecture 32
Figure 5: Exploded view of IED 33
Figure 6: Front panel (60TE) 35
Figure 7: Rear view of populated case 39
Figure 8: Terminal block types 40
Figure 9: Rear connection to terminal block 41
Figure 10: Main processor board 42
Figure 11: Power supply board 43
Figure 12: Power supply assembly 44
Figure 13: Power supply terminals 45
Figure 14: Watchdog contact terminals 46
Figure 15: Rear serial port terminals 47
Figure 16: Input module - 1 transformer board 47
Figure 17: Input module schematic 48
Figure 18: Transformer board 49
Figure 19: Input board 50
Figure 20: Standard output relay board - 8 contacts 51
Figure 21: IRIG-B board 52
Figure 22: Fibre optic board 53
Figure 23: Rear communication board 54
Figure 24: Ethernet board 54
Figure 25: Redundant Ethernet board 56
Figure 26: Software Architecture 62
Figure 27: Frequency Response (indicative only) 68
Figure 28: Navigating the HMI 76
Figure 29: Default display navigation 78
Figure 30: Circuit Breaker Trip Conversion Logic Diagram (Module 63) 87
Figure 31: Autoreclose sequence for a Transient Fault 100
Figure 32: Autoreclose sequence for an evolving or permanent fault 101
Figure 33: Autoreclose sequence for an evolving or permanent fault - single-phase operation 101
Figure 34: Dual CB Autoreclose Sequence for a Transient Fault 102
Figure 35: Autoreclose Sequence for an evolving/permanent fault on a dual CB application 103
Figure 36: Autoreclose Sequence for a persistent fault on a multishot dual CB application set 103
for single-phase operation
Figure 37: Key to logic diagrams 106
Figure 38: Autoreclose System Map - part 1 107
Table of Figures P841B

Figure 48: CB State logic diagram (Module 1) 134
Figure 49: Circuit Breaker Open logic diagram (Module 3) 135
Figure 50: CB In Service logic diagram (Module 4) 136
Figure 51: Autoreclose Enable logic diagram (Module 5) 136
Figure 52: Leader/Follower CB Selection Logic Diagram (Module 6) 137
Figure 53: Leader/Follower logic diagram (Module 7 & 8) 138
Figure 54: Autoreclose Modes Enable logic diagram (Module 9) 140
Figure 55: Force three-phase trip logic diagram (Module 10) 141
Figure 56: Autoreclose Initiation logic diagram (Module 11) 143
Figure 57: Autoreclose Trip Test logic diagram (Module 12) 143
Figure 58: Autoreclose initiation by internal single and three phase trip or external trip for CB1 144
(Module 13)
Figure 59: Autoreclose initiation by internal single and three phase trip or external trip for CB2 145
(Module 14)
Figure 60: Protection Reoperation and Evolving Fault logic diagram (Module 20) 146
Figure 61: Fault Memory logic diagram (Module 15) 146
Figure 62: Autoreclose In Progress logic diagram for CB1 (Module 16) 147
Figure 63: Autoreclose In Progress logic diagram for CB2 (Module 17) 148
Figure 64: Autoreclose Sequence Counter logic diagram (Module 18) 149
Figure 65: Single-phase Autoreclose Cycle Selection logic diagram (Module 19) 150
Figure 66: Three-phase Autoreclose Cycle Selection logic diagram (Module 21) 151
Figure 67: Dead time Start Enable logic diagram (Module 22) 152
Figure 68: Single-phase Leader Dead Time logic diagram (Module 24) 153
Figure 69: Three-phase Leader CB Dead Time logic diagram (Module 25) 154
Figure 70: Follower Enable logic diagram (Module 27) 155
Figure 71: Single-phase Follower CB timing logic diagram (Module 28) 156
Figure 72: Three-phase Follower CB timing logic diagram (Module 29) 157
Figure 73: Circuit Breaker Autoclose Logic Diagram (Modules 32 & 33) 158
Figure 74: Prepare Reclaim Initiation logic diagram (Module 34) 159
Figure 75: Reclaim Time logic diagram (Module 35) 160
Figure 76: Successful Autoreclose Signals logic diagram (Module 36) 161
Figure 77: Autoreclose Reset Successful Indication logic diagram (Modules 37 & 38) 162
xviii P841B-TM-EN-1.1
P841B Table of Figures
Figure 78: Circuit Breaker Healthy and System Check Timers Healthy logic diagram (Module 39) 163
Figure 79: Autoreclose Shot Counters logic diagram (Modules 41 & 42) 165
Figure 80: CB1 Control Logic (Module 43) 166
Figure 82: Circuit Breaker Trip Time Monitoring logic diagram (Modules 53 & 54) 168
Figure 83: CB1 Lockout Logic Diagram (Module 55) 170
Figure 84: CB2 Lockout Logic Diagram (Module 56) 171
Figure 85: Reset Circuit Breaker Lockout Logic Diagram (Modules 57 & 58) 173
Figure 86: Pole Discrepancy Logic Diagram (Module 62) 174
Figure 87: Circuit Breaker Trip Conversion Logic Diagram (Module 63) 175
Figure 88: Voltage Monitor for CB Closure (Module 59) 176
Figure 89: Check Synchronisation Monitor for CB1 closure (Module 60) 177
Figure 91: Three-phase AR System Check logic diagram for CB1 as leader (Module 45) 180
Figure 92: Three-phase AR System Check logic diagram for CB2 as leader (Module 46) 181
Figure 93: Three-phase AR System Check logic d for CB1 as follower (Module 47) 182
Figure 94: Three-phase AR System Check logic diagram for CB2 as follower (Module 48) 183
Figure 95: CB Manual Close System Check Logic Diagram (Modules 51 & 52) 184
Figure 96: Circuit Breaker Fail logic - part 1 195
Figure 100: CB Fail timing 200
Figure 101: Phase Overcurrent Protection logic diagram 206
Figure 102: Negative Phase Sequence Overcurrent Protection logic diagram 208
Figure 103: IDG Characteristic 211
Figure 104: Earth Fault Protection logic diagram 213
Figure 105: EPATR B characteristic shown for TMS = 1.0 216
Figure 106: Sensitive Earth Fault Protection logic diagram 216
Figure 107: Current distribution in an insulated system with C phase fault 217
Figure 108: Phasor diagrams for insulated system with C phase fault 218
Figure 109: Positioning of core balance current transformers 219
Figure 110: High Impedance REF principle 220
Figure 111: High Impedance REF Connection 221
Figure 112: Thermal overload protection logic diagram 223
Figure 113: Spreadsheet calculation for dual time constant thermal characteristic 224
Figure 114: Dual time constant thermal characteristic 224
Figure 115: Broken conductor logic 226
Figure 116: Undervoltage - single and three phase tripping mode (single stage) 233
Figure 117: Overvoltage - single and three phase tripping mode (single stage) 236
P841B-TM-EN-1.1 xix
Figure 118: Residual Overvoltage logic 240

Figure 119: Residual voltage for a solidly earthed system 241
Figure 120: Residual voltage for an impedance earthed system 242
Figure 121: Underfrequency logic (single stage) 247
Figure 122: Overfrequency logic (single stage) 248
Figure 123: Rate of change of frequency logic (single stage) 249
Figure 124: Fault recorder stop conditions 264
Figure 125: Broken Current Accumulator logic diagram 269
Figure 126: CB Trip Counter logic diagram 270
Figure 127: Operating Time Accumulator 271
Figure 128: Excessive Fault Frequency logic diagram 272
Figure 129: Reset Lockout Alarm logic diagram 273
Figure 130: CB1 Condition Monitoring logic diagram 274
Figure 131: CB2 Condition Monitoring logic diagram 275
Figure 132: Reset Circuit Breaker Lockout Logic Diagram (Modules 57 & 58) 277
Figure 133: CB State logic diagram (Module 1) 280
Figure 134: Hotkey menu navigation 282
Figure 135: Default function key PSL 283
Figure 136: Remote Control of Circuit Breaker 284
Figure 139: Pole Dead logic 287
Figure 140: Check Synchronisation vector diagram 290
Figure 141: Voltage Monitor for CB Closure (Module 59) 291
Figure 144: System Check PSL 294
Figure 145: VTS logic 302
Figure 146: Standard CTS 305
Figure 147: TCS Scheme 1 306
Figure 148: PSL for TCS Scheme 1 307
Figure 153: Scheme Logic Interfaces 315
Figure 154: Trip LED logic 319
Figure 155: Example assignment of InterMiCOM signals within the PSL 332
Figure 156: Direct connection 333
Figure 157: Indirect connection using modems 333
xx P841B-TM-EN-1.1
P841B Table of Figures
Figure 158: RS485 biasing circuit 342

Figure 159: Remote communication using K-Bus 343
Figure 160: IED attached to separate LANs 346
Figure 161: HSR multicast topology 347
Figure 162: HSR unicast topology 348
Figure 163: HSR application in the substation 349
Figure 164: IED attached to redundant Ethernet star or ring circuit 349
Figure 165: IED, bay computer and Ethernet switch with self healing ring facilities 350
Figure 166: Redundant Ethernet ring architecture with IED, bay computer and Ethernet switches 350
Figure 167: Redundant Ethernet ring architecture with IED, bay computer and Ethernet switches 351
after failure
Figure 168: Dual homing mechanism 352
Figure 169: Application of Dual Homing Star at substation level 353
Figure 170: IED and REB IP address configuration 354
Figure 171: Connection using (a) an Ethernet switch and (b) a media converter 357
Figure 172: Connection using (a) an Ethernet switch and (b) a media converter 361
Figure 173: Control input behaviour 384
Figure 174: Data model layers in IEC61850 395
Figure 175: GPS Satellite timing signal 401
Figure 176: Default display navigation 412
Figure 177: Location of battery isolation strip 425
Figure 178: Rack mounting of products 426
Figure 179: Terminal block types 428
Figure 180: 40TE case dimensions 432
Figure 183: RP1 physical connection 450
Figure 184: Remote communication using K-bus 451
Figure 185: InterMicom loopback testing 454
Figure 186: Possible terminal block types 470
Figure 187: Front panel assembly 472
P841B-TM-EN-1.1 xxi
xxii P841B-TM-EN-1.1
CHAPTER 1
INTRODUCTION
Chapter 1 - Introduction P841B
2 P841B-TM-EN-1.1
P841B Chapter 1 - Introduction
1 CHAPTER OVERVIEW
This chapter provides some general information about the technical manual and an introduction to the device(s)
described in this technical manual.
This chapter contains the following sections:
Chapter Overview 3
Foreword 4
Product Scope 6
Features and Functions 9
Logic Diagrams 11
Functional Overview 13
P841B-TM-EN-1.1 3
2 FOREWORD
This technical manual provides a functional and technical description of General Electric's P841B, as well as a
comprehensive set of instructions for using the device. The level at which this manual is written assumes that you
are already familiar with protection engineering and have experience in this discipline. The description of principles
and theory is limited to that which is necessary to understand the product. For further details on general
protection engineering theory, we refer you to General Electric's publication NPAG, which is available online or
from our contact centre.
We have attempted to make this manual as accurate, comprehensive and user-friendly as possible. However we
cannot guarantee that it is free from errors. Nor can we state that it cannot be improved. We would therefore be
very pleased to hear from you if you discover any errors, or have any suggestions for improvement. Our policy is to
provide the information necessary to help you safely specify, engineer, install, commission, maintain, and
eventually dispose of this product. We consider that this manual provides the necessary information, but if you
consider that more details are needed, please contact us.
All feedback should be sent to our contact centre via:
contact.centre@ge.com
2.1 TARGET AUDIENCE

This manual is aimed towards all professionals charged with installing, commissioning, maintaining,
troubleshooting, or operating any of the products within the specified product range. This includes installation and
commissioning personnel as well as engineers who will be responsible for operating the product.
The level at which this manual is written assumes that installation and commissioning engineers have knowledge
of handling electronic equipment. Also, system and protection engineers have a thorough knowledge of protection
systems and associated equipment.
2.2 TYPOGRAPHICAL CONVENTIONS

The following typographical conventions are used throughout this manual.
● The names for special keys appear in capital letters.
For example: ENTER
● When describing software applications, menu items, buttons, labels etc as they appear on the screen are
written in bold type.
For example: Select Save from the file menu.
● Filenames and paths use the courier font
For example: Example\File.text
● Special terminology is written with leading capitals
For example: Sensitive Earth Fault
● If reference is made to the IED's internal settings and signals database, the menu group heading (column)
text is written in upper case italics
For example: The SYSTEM DATA column
● If reference is made to the IED's internal settings and signals database, the setting cells and DDB signals are
written in bold italics
For example: The Language cell in the SYSTEM DATA column
● If reference is made to the IED's internal settings and signals database, the value of a cell's content is
written in the Courier font
For example: The Language cell in the SYSTEM DATA column contains the value English
4 P841B-TM-EN-1.1
2.3 NOMENCLATURE
Due to the technical nature of this manual, many special terms, abbreviations and acronyms are used throughout
the manual. Some of these terms are well-known industry-specific terms while others may be special product-
specific terms used by General Electric. The first instance of any acronym or term used in a particular chapter is
explained. In addition, a separate glossary is available on the General Electric website, or from the General Electric
contact centre.
We would like to highlight the following changes of nomenclature however:
● The word 'relay' is no longer used to describe the device itself. Instead, the device is referred to as the 'IED'
(Intelligent Electronic Device), the 'device', or the 'product'. The word 'relay' is used purely to describe the
electromechanical components within the device, i.e. the output relays.
● British English is used throughout this manual.
● The British term 'Earth' is used in favour of the American term 'Ground'.
2.4 COMPLIANCE
The device has undergone a range of extensive testing and certification processes to ensure and prove
compatibility with all target markets. A detailed description of these criteria can be found in the Technical
Specifications chapter.
P841B-TM-EN-1.1 5
3 PRODUCT SCOPE
The MICOM P841 is a multifunctional line terminal IED for control and back-up protection in transmission feeder
bays. It is suitable for single and dual breaker applications. It is used in applications such as breaker-and-a-half, or
ring bus topologies, where two circuit breakers feed each line.
The P841B is available in three variants; models C, D and E. The difference between the variants is the type of
output contacts used. These differences are summarised in the table below:
Feature Model C Model D Model E

Number of CT Inputs 8 8 8
Number of VT inputs 5 5 5
Opto coupled digital inputs 24 24 24
Standard relay output contacts 32 16 8
High speed high break output contacts 8 12
The 5 VTs in this model allow flexible configuration options, where one can be used to measure the residual
voltage if required. To do this, you must first set all relevant residual voltage input settings to measured, then the
VT2 Selection setting to Broken Delta.
3.1 PRODUCT VERSIONS

This product belongs to the P40L family. Although this technical manual is specific to this product, it is useful to
know where the product fits into the family and to describe the evolution path of the entire product family. The
following diagram attempts to do this:
6 P841B-TM-EN-1.1
P445: J37
P54x No Distance: K47
P841A: K47
All other products: K57
Conventional Stream NCIT Stream
P445: P41
P54x No Distance: M61
P446, P546, P841B: M72
P841A: M61
All other products: M71
 XCPU3
 Cyber security
 NCIT (now obsolete)
 New Protection
functions
Subcycle Diff Stream
P445: P45
P54x No Distance: M65 P543, P545: M63
P446, P546, P841B: M74
P841A: M65 Non-distance
 XCPU3
 New Protection  Subcycle differential for
 Cyber security
functions non-distance versions
 NCIT (9-2LE interface)
P445: P46
P54x No Distance: M66 P543, P545: M83
P446, P546, P841B: P80
P841A: M66 Non-distance
 Current Differential  IEC 61850 Edition 2

 IEC 61850 Edition 2
Starters for P54x  IEEE 1588 support
 IEEE 1588 support
 Other improvements  40TE case
Multi-end
subcycle
stream
P445: P49
P841A: M81 P54A, P54B: P01
P54x No Distance: M69
All other products: M82 P54C, P54E: M01 P546, P841B: P86
P841A: M69
(except P445) Non-distance
 IM6 4 3 2 b its p er cha nnel  tRe clai m exte nd
 Voltage functio n setta ble  System sp lit
 IEC 61850 Edition 2  Multi-end
hystere sis  Curren t Di fferential Starters
 Enh ance curr ent differential  IEEE 1588 support  Subcycle for P 54x
supervision Isef  Use r A larms increased
V00062
Figure 1: P40L family - version evolution
3.2 ORDERING OPTIONS

All current models and variants for this product are defined in an interactive spreadsheet called the CORTEC. This is
available on the company website.
Alternatively, you can obtain it via the Contact Centre at:
P841B-TM-EN-1.1 7
A copy of the CORTEC is also supplied as a static table in the Appendices of this document. However, it should only
be used for guidance as it provides a snapshot of the interactive data taken at the time of publication.
8 P841B-TM-EN-1.1
4 FEATURES AND FUNCTIONS
4.1 PROTECTION FUNCTIONS
Feature IEC 61850 ANSI

Tripping Mode (1 & 3 pole) PTRC
ABC and ACB phase rotation
Phase overcurrent , with optional directionality (4 stages) OcpPTOC/RDIR 50/51/67
Earth/Ground overcurrent stages, with optional directionality (4
EfdPTOC/RDIR 50N/51N/ 67N
stages)
Sensitive earth fault (SEF) (4 stages) SenPTOC/RDIR 50N/51N/67N
High impedance restricted earth fault (REF) SenRefPDIF 64
Negative sequence overcurrent stages, with optional
NgcPTOC/RDIR 67/46
directionality (4 stages)
Broken conductor, used to detect open circuit faults 46
Thermal overload protection ThmPTTR 49
Undervoltage protection (2 stages) VtpPhsPTUV 27
Overvoltage protection (2 stages) VtpPhsPTOV 59
Remote overvoltage protection (2 stages) VtpCmpPTOV 59R
Residual voltage protection (2 stages) VtpResPTOV 59N
Underfrequency protection (4 stages) FrqPTUF 81
Overfrequency protection (2 stages) FrqPTOF 81
Rate of change of frequency protection (4 stages) DfpPFRC 81
High speed breaker fail suitable for re-tripping and back-
RBRF 50BF
tripping (2 stages)
Current Transformer supervision 46
Voltage transformer supervision 47/27
Auto-reclose (4 shots) RREC 79
Check synchronisation (2 stages) RSYN 25
4.2 CONTROL FUNCTIONS

Watchdog contacts
Read-only mode
Function keys FnkGGIO
Programmable LEDs LedGGIO
Programmable hotkeys
Programmable allocation of digital inputs and outputs
Fully customizable menu texts
Circuit breaker control, status & condition monitoring XCBR 52
CT supervision
VT supervision
Trip circuit and coil supervision
Control inputs PloGGIO1
P841B-TM-EN-1.1 9

Power-up diagnostics and continuous self-monitoring
Dual rated 1A and 5A CT inputs
Alternative setting groups (4)
Graphical programmable scheme logic (PSL)
Fault locator RFLO
4.3 MEASUREMENT FUNCTIONS
Measurement Function IEC 61850 ANSI

Measurement of all instantaneous & integrated values
MET
(Exact range of measurements depend on the device model)
Disturbance recorder for waveform capture – specified in samples per cycle RDRE DFR
Fault Records
Maintenance Records
Event Records / Event logging Event records
Time Stamping of Opto-inputs Yes Yes
4.4 COMMUNICATION FUNCTIONS
Feature ANSI
NERC compliant cyber-security
Front RS232 serial communication port for configuration 16S
Rear serial RS485 communication port for SCADA control 16S
2 Additional rear serial communication ports for SCADA control and
16S
teleprotection (fibre and copper) (optional)
Ethernet communication (optional) 16E
Redundant Ethernet communication (optional) 16E
Courier Protocol 16S
IEC 61850 edition 1 16E
IEC 60870-5-103 (optional) 16S
DNP3.0 over serial link (optional) 16S
DNP3.0 over Ethernet (optional) 16E
SNMP 16E
IRIG-B time synchronisation (optional) CLK
10 P841B-TM-EN-1.1
5 LOGIC DIAGRAMS
This technical manual contains many logic diagrams, which should help to explain the functionality of the device.
Although this manual has been designed to be as specific as possible to the chosen product, it may contain
diagrams, which have elements applicable to other products. If this is the case, a qualifying note will accompany
the relevant part.
The logic diagrams follow a convention for the elements used, using defined colours and shapes. A key to this
convention is provided below. We recommend viewing the logic diagrams in colour rather than in black and white.
The electronic version of the technical manual is in colour, but the printed version may not be. If you need coloured
diagrams, they can be provided on request by calling the contact centre and quoting the diagram number.
P841B-TM-EN-1.1 11
Key:
Energising Quantity AND gate &
Internal Signal OR gate 1
DDB Signal XOR gate XOR
Internal function NOT gate
Setting cell Logic 0 0
Setting value Timer
Hardcoded setting
Pulse / Latch
Measurement Cell S
SR Latch Q
R
Internal Calculation
S
SR Latch Q
Derived setting Reset Dominant RD
HMI key Latched on positive edge
Connection / Node Inverted logic input

1
Switch Soft switch 2
Switch Multiplier X
Bandpass filter
Comparator for detecting
undervalues

V00063 overvalues
Figure 2: Key to logic diagrams
12 P841B-TM-EN-1.1
6 FUNCTIONAL OVERVIEW
This diagram is applicable to two products in the P40L family; P841A and P841B. Use the key on the diagram to
determine the features relevant to the product described in this technical manual.
BUS
2 nd Remote Remote Loca l

F a ult Records Disturba nce
comm . port comm . port Communica tion Record
M ea surements
X S elf monitoring
49 50/51 50 N/ 50BF-2 67 67N 67N 67 / 25 -2 79 -2 46BC CTS

51N SEF 46
V re f
LINE
I
V
V ref
IEs en
X IM
27/
81 FL 50BF VTS 59N 79 25 PSL LEDs
59
LINE
conve ntiona l IEC GOOSE prote ction

always model B
sig na lling communica tion
X avaialble optional only
Multifunction IEDs P841
BUS
Ne utra l Curre nt
from pa ra lle l line
(if pre se nt)
V00055
Figure 3: Functional Overview
P841B-TM-EN-1.1 13
14 P841B-TM-EN-1.1
CHAPTER 2
SAFETY INFORMATION
Chapter 2 - Safety Information P841B
16 P841B-TM-EN-1.1
P841B Chapter 2 - Safety Information
1 CHAPTER OVERVIEW
This chapter provides information about the safe handling of the equipment. The equipment must be properly
installed and handled in order to maintain it in a safe condition and to keep personnel safe at all times. You must
be familiar with information contained in this chapter before unpacking, installing, commissioning, or servicing the
equipment.
Chapter Overview 17
Health and Safety 18
Symbols 19
Installation, Commissioning and Servicing 20
Decommissioning and Disposal 26
Regulatory Compliance 27
P841B-TM-EN-1.1 17
2 HEALTH AND SAFETY

Personnel associated with the equipment must be familiar with the contents of this Safety Information.
When electrical equipment is in operation, dangerous voltages are present in certain parts of the equipment.
Improper use of the equipment and failure to observe warning notices will endanger personnel.
Only qualified personnel may work on or operate the equipment. Qualified personnel are individuals who are:
● familiar with the installation, commissioning, and operation of the equipment and the system to which it is
being connected.
● familiar with accepted safety engineering practises and are authorised to energise and de-energise
equipment in the correct manner.
● trained in the care and use of safety apparatus in accordance with safety engineering practises
● trained in emergency procedures (first aid).
The documentation provides instructions for installing, commissioning and operating the equipment. It cannot,
however cover all conceivable circumstances. In the event of questions or problems, do not take any action
without proper authorisation. Please contact your local sales office and request the necessary information.
18 P841B-TM-EN-1.1
3 SYMBOLS
Throughout this manual you will come across the following symbols. You will also see these symbols on parts of
the equipment.
Caution:
Refer to equipment documentation. Failure to do so could result in damage to the
equipment
Warning:
Risk of electric shock
Warning:
Risk of damage to eyesight
Earth terminal. Note: This symbol may also be used for a protective conductor (earth) terminal if that terminal
is part of a terminal block or sub-assembly.
Protective conductor (earth) terminal
Instructions on disposal requirements
Note:
The term 'Earth' used in this manual is the direct equivalent of the North American term 'Ground'.
P841B-TM-EN-1.1 19
4 INSTALLATION, COMMISSIONING AND SERVICING
4.1 LIFTING HAZARDS

Many injuries are caused by:
● Lifting heavy objects
● Lifting things incorrectly
● Pushing or pulling heavy objects
● Using the same muscles repetitively
Plan carefully, identify any possible hazards and determine how best to move the product. Look at other ways of
moving the load to avoid manual handling. Use the correct lifting techniques and Personal Protective Equipment
(PPE) to reduce the risk of injury.
4.2 ELECTRICAL HAZARDS
Caution:
All personnel involved in installing, commissioning, or servicing this equipment must be
familiar with the correct working procedures.
Caution:
Consult the equipment documentation before installing, commissioning, or servicing
the equipment.
Caution:
Always use the equipment as specified. Failure to do so will jeopardise the protection
provided by the equipment.
Warning:
Removal of equipment panels or covers may expose hazardous live parts. Do not touch
until the electrical power is removed. Take care when there is unlocked access to the
rear of the equipment.
Warning:
Isolate the equipment before working on the terminal strips.
Warning:
Use a suitable protective barrier for areas with restricted space, where there is a risk of
electric shock due to exposed terminals.
Caution:
Disconnect power before disassembling. Disassembly of the equipment may expose
sensitive electronic circuitry. Take suitable precautions against electrostatic voltage
discharge (ESD) to avoid damage to the equipment.
20 P841B-TM-EN-1.1
Warning:
NEVER look into optical fibres or optical output connections. Always use optical power
meters to determine operation or signal level.
Warning:
Testing may leave capacitors charged to dangerous voltage levels. Discharge
capacitors by reducing test voltages to zero before disconnecting test leads.
Caution:
Operate the equipment within the specified electrical and environmental limits.
Caution:
Before cleaning the equipment, ensure that no connections are energised. Use a lint
free cloth dampened with clean water.
Note:
Contact fingers of test plugs are normally protected by petroleum jelly, which should not be removed.
4.3 UL/CSA/CUL REQUIREMENTS

The information in this section is applicable only to equipment carrying UL/CSA/CUL markings.
Caution:
Equipment intended for rack or panel mounting is for use on a flat surface of a Type 1
enclosure, as defined by Underwriters Laboratories (UL).
Caution:
To maintain compliance with UL and CSA/CUL, install the equipment using UL/CSA-
recognised parts for: cables, protective fuses, fuse holders and circuit breakers,
insulation crimp terminals, and replacement internal batteries.
4.4 FUSING REQUIREMENTS
Caution:
Where UL/CSA listing of the equipment is required for external fuse protection, a UL or
CSA Listed fuse must be used for the auxiliary supply. The listed protective fuse type is:
Class J time delay fuse, with a maximum current rating of 15 A and a minimum DC
rating of 250 V dc (for example type AJT15).
Caution:
Where UL/CSA listing of the equipment is not required, a high rupture capacity (HRC)
fuse type with a maximum current rating of 16 Amps and a minimum dc rating of 250 V
dc may be used for the auxiliary supply (for example Red Spot type NIT or TIA).
For P50 models, use a 1A maximum T-type fuse.
For P60 models, use a 4A maximum T-type fuse.
P841B-TM-EN-1.1 21
Caution:
Digital input circuits should be protected by a high rupture capacity NIT or TIA fuse with
maximum rating of 16 A. for safety reasons, current transformer circuits must never be
fused. Other circuits should be appropriately fused to protect the wire used.
Caution:
CTs must NOT be fused since open circuiting them may produce lethal hazardous
voltages
4.5 EQUIPMENT CONNECTIONS
Warning:
Terminals exposed during installation, commissioning and maintenance may present a
hazardous voltage unless the equipment is electrically isolated.
Caution:
Tighten M4 clamping screws of heavy duty terminal block connectors to a nominal
torque of 1.3 Nm.
Tighten captive screws of terminal blocks to 0.5 Nm minimum and 0.6 Nm maximum.
Caution:
Always use insulated crimp terminations for voltage and current connections.
Caution:
Always use the correct crimp terminal and tool according to the wire size.
Caution:
Watchdog (self-monitoring) contacts are provided to indicate the health of the device
on some products. We strongly recommend that you hard wire these contacts into the
substation's automation system, for alarm purposes.
4.6 PROTECTION CLASS 1 EQUIPMENT REQUIREMENTS
Caution:
Earth the equipment with the supplied PCT (Protective Conductor Terminal).
Caution:
Do not remove the PCT.
Caution:
The PCT is sometimes used to terminate cable screens. Always check the PCT’s integrity
after adding or removing such earth connections.
22 P841B-TM-EN-1.1
Caution:
Use a locknut or similar mechanism to ensure the integrity of stud-connected PCTs.
Caution:
The recommended minimum PCT wire size is 2.5 mm² for countries whose mains supply
is 230 V (e.g. Europe) and 3.3 mm² for countries whose mains supply is 110 V (e.g. North
America). This may be superseded by local or country wiring regulations.
For P60 products, the recommended minimum PCT wire size is 6 mm². See product
documentation for details.
Caution:
The PCT connection must have low-inductance and be as short as possible.
Caution:
All connections to the equipment must have a defined potential. Connections that are
pre-wired, but not used, should be earthed, or connected to a common grouped
potential.
4.7 PRE-ENERGISATION CHECKLIST
Caution:
Check voltage rating/polarity (rating label/equipment documentation).
Caution:
Check CT circuit rating (rating label) and integrity of connections.
Caution:
Check protective fuse or miniature circuit breaker (MCB) rating.
Caution:
Check integrity of the PCT connection.
Caution:
Check voltage and current rating of external wiring, ensuring it is appropriate for the
application.
4.8 PERIPHERAL CIRCUITRY
Warning:
Do not open the secondary circuit of a live CT since the high voltage produced may be
lethal to personnel and could damage insulation. Short the secondary of the line CT
before opening any connections to it.
P841B-TM-EN-1.1 23
Note:
For most General Electric equipment with ring-terminal connections, the threaded terminal block for current transformer
termination is automatically shorted if the module is removed. Therefore external shorting of the CTs may not be required.
Check the equipment documentation and wiring diagrams first to see if this applies.
Caution:
Where external components such as resistors or voltage dependent resistors (VDRs) are
used, these may present a risk of electric shock or burns if touched.
Warning:
Take extreme care when using external test blocks and test plugs such as the MMLG,
MMLB and P990, as hazardous voltages may be exposed. Ensure that CT shorting links
are in place before removing test plugs, to avoid potentially lethal voltages.
Warning:
Data communication cables with accessible screens and/or screen conductors,
(including optical fibre cables with metallic elements), may create an electric shock
hazard in a sub-station environment if both ends of the cable screen are not connected
to the same equipotential bonded earthing system.
To reduce the risk of electric shock due to transferred potential hazards:
i. The installation shall include all necessary protection measures to ensure that no
fault currents can flow in the connected cable screen conductor.
ii. The connected cable shall have its screen conductor connected to the protective
conductor terminal (PCT) of the connected equipment at both ends. This connection
may be inherent in the connectors provided on the equipment but, if there is any doubt,
this must be confirmed by a continuity test.
iii. The protective conductor terminal (PCT) of each piece of connected equipment shall
be connected directly to the same equipotential bonded earthing system.
iv. If, for any reason, both ends of the cable screen are not connected to the same
equipotential bonded earth system, precautions must be taken to ensure that such
screen connections are made safe before work is done to, or in proximity to, any such
cables.
v. No equipment shall be connected to any download or maintenance circuits or

connectors of this product except temporarily and for maintenance purposes only.
vi. Equipment temporarily connected to this product for maintenance purposes shall be
protectively earthed (if the temporary equipment is required to be protectively
earthed), directly to the same equipotential bonded earthing system as the product.
Warning:
Small Form-factor Pluggable (SFP) modules which provide copper Ethernet connections
typically do not provide any additional safety isolation. Copper Ethernet SFP modules
must only be used in connector positions intended for this type of connection.
24 P841B-TM-EN-1.1
4.9 UPGRADING/SERVICING
Warning:
Do not insert or withdraw modules, PCBs or expansion boards from the equipment
while energised, as this may result in damage to the equipment. Hazardous live
voltages would also be exposed, endangering personnel.
Caution:
Internal modules and assemblies can be heavy and may have sharp edges. Take care
when inserting or removing modules into or out of the IED.
P841B-TM-EN-1.1 25
5 DECOMMISSIONING AND DISPOSAL
Caution:
Before decommissioning, completely isolate the equipment power supplies (both poles
of any dc supply). The auxiliary supply input may have capacitors in parallel, which may
still be charged. To avoid electric shock, discharge the capacitors using the external
terminals before decommissioning.
Caution:
Avoid incineration or disposal to water courses. Dispose of the equipment in a safe,
responsible and environmentally friendly manner, and if applicable, in accordance with
country-specific regulations.
26 P841B-TM-EN-1.1
6 REGULATORY COMPLIANCE
Compliance with the European Commission Directive on EMC and LVD is demonstrated using a technical file.
6.1 EMC COMPLIANCE: 2014/30/EU

The product specific Declaration of Conformity (DoC) lists the relevant harmonised standard(s) or conformity
assessment used to demonstrate compliance with the EMC directive.
6.2 LVD COMPLIANCE: 2014/35/EU

The product specific Declaration of Conformity (DoC) lists the relevant harmonized standard(s) or conformity
assessment used to demonstrate compliance with the LVD directive.
Safety related information, such as the installation I overvoltage category, pollution degree and operating
temperature ranges are specified in the Technical Data section of the relevant product documentation and/or on
the product labelling.
Unless otherwise stated in the Technical Data section of the relevant product documentation, the equipment is
intended for indoor use only. Where the equipment is required for use in an outdoor location, it must be mounted
in a specific cabinet or housing to provide the equipment with the appropriate level of protection from the
expected outdoor environment.
6.3 R&TTE COMPLIANCE: 2014/53/EU

Radio and Telecommunications Terminal Equipment (R&TTE) directive 2014/53/EU.
Conformity is demonstrated by compliance to both the EMC directive and the Low Voltage directive, to zero volts.
6.4 UL/CUL COMPLIANCE

If marked with this logo, the product is compliant with the requirements of the Canadian and USA Underwriters
Laboratories.
The relevant UL file number and ID is shown on the equipment.
6.5 ATEX COMPLIANCE: 2014/34/EU

Products marked with the 'explosion protection' Ex symbol (shown in the example, below) are compliant with the
ATEX directive. The product specific Declaration of Conformity (DoC) lists the Notified Body, Type Examination
Certificate, and relevant harmonized standard or conformity assessment used to demonstrate compliance with
the ATEX directive.
The ATEX Equipment Protection level, Equipment group, and Zone definition will be marked on the
product.
For example:
Where:
P841B-TM-EN-1.1 27
'II' Equipment Group: Industrial.
'(2)G' High protection equipment category, for control of equipment in gas atmospheres in Zone 1 and 2.
This equipment (with parentheses marking around the zone number) is not itself suitable for operation
within a potentially explosive atmosphere.
28 P841B-TM-EN-1.1
CHAPTER 3
HARDWARE DESIGN
Chapter 3 - Hardware Design P841B
30 P841B-TM-EN-1.1
P841B Chapter 3 - Hardware Design
1 CHAPTER OVERVIEW
This chapter provides information about the product's hardware design.
Chapter Overview 31
Hardware Architecture 32
Mechanical Implementation 33
Front Panel 35
Rear Panel 39
Boards and Modules 41
P841B-TM-EN-1.1 31
2 HARDWARE ARCHITECTURE
The main components comprising devices based on the Px4x platform are as follows:
● The housing, consisting of a front panel and connections at the rear
● The Main processor module consisting of the main CPU (Central Processing Unit), memory and an interface
to the front panel HMI (Human Machine Interface)
● A selection of plug-in boards and modules with presentation at the rear for the power supply,
communication functions, digital I/O, analogue inputs, and time synchronisation connectivity
All boards and modules are connected by a parallel data and address bus, which allows the processor module to
send and receive information to and from the other modules as required. There is also a separate serial data bus
for conveying sampled data from the input module to the CPU. These parallel and serial databuses are shown as a
single interconnection module in the following figure, which shows typical modules and the flow of data between
them.
Keypad
Output relay boards Output relay contacts
Processor module
Front panel HMI
LCD
Opto-input boards Digital inputs
LEDs
I/O
Front port
CTs Power system currents
Memory
Interconnection
Flash memory for settings VTs Power system voltages

Analogue Inputs
Battery-backed SRAM
for records
RS485 modules RS485 communication

Watchdog
contacts Watchdog module
IRIG-B module Time synchronisation
+ LED
Ethernet modules Ethernet communication

Auxiliary
PSU module
Supply Communications
Note: Not all modules are applicable to all products
V00233
Figure 4: Hardware architecture
32 P841B-TM-EN-1.1
3 MECHANICAL IMPLEMENTATION
All products based on the Px4x platform have common hardware architecture. The hardware is modular and
consists of the following main parts:
● Case and terminal blocks
● Boards and modules
● Front panel
The case comprises the housing metalwork and terminal blocks at the rear. The boards fasten into the terminal
blocks and are connected together by a ribbon cable. This ribbon cable connects to the processor in the front
panel.
The following diagram shows an exploded view of a typical product. The diagram shown does not necessarily
represent exactly the product model described in this manual.
Figure 5: Exploded view of IED
3.1 HOUSING VARIANTS

The Px4x range of products are implemented in a range of case sizes. Case dimensions for industrial products
usually follow modular measurement units based on rack sizes. These are: U for height and TE for width, where:
● 1U = 1.75 inches = 44.45 mm
● 1TE = 0.2 inches = 5.08 mm
The products are available in panel-mount or standalone versions. All products are nominally 4U high. This equates
to 177.8 mm or 7 inches.
The cases are pre-finished steel with a conductive covering of aluminium and zinc. This provides good grounding
at all joints, providing a low resistance path to earth that is essential for performance in the presence of external
noise.
The case width depends on the product type and its hardware options. There are three different case widths for
the described range of products: 40TE, 60TE and 80TE. The case dimensions and compatibility criteria are as
follows:
Case width (TE) Case width (mm) Case width (inches)
40TE 203.2 8
P841B-TM-EN-1.1 33
Case width (TE) Case width (mm) Case width (inches)

60TE 304.8 12
80TE 406.4 16
Note:
Not all case sizes are available for all models.
3.2 LIST OF BOARDS

The product's hardware consists of several modules drawn from a standard range. The exact specification and
number of hardware modules depends on the model number and variant. Depending on the exact model, the
product in question will use a selection of the following boards.
Board Use
Main Processor board - 40TE or smaller Main Processor board – without support for function keys
Main Processor board - 60TE or larger Main Processor board – with support for function keys
Power supply board - 24/54V DC Power supply input. Accepts DC voltage between 24V and 54V
Transformer board Contains the voltage and current transformers
Input board Contains the A/D conversion circuitry
Input board with opto-inputs Contains the A/D conversion circuitry + 8 digital opto-inputs
IRIG-B board - modulated input Interface board for modulated IRIG-B timing signal
IRIG-B board - demodulated input Interface board for demodulated IRIG-B timing signal
Fibre board Interface board for fibre-based RS485 connection
Fibre board + IRIG-B Interface board for fibre-based RS485 connection + demodulated IRIG-B
2nd rear communications board Interface board for RS232 / RS485 connections
2nd rear communications board with IRIG-B
Interface board for RS232 / RS485 + IRIG-B connections
input
100MhZ Ethernet board Standard 100MHz Ethernet board for LAN connection (fibre + copper)
100MhZ Ethernet board with modulated IRIG-B Standard 100MHz Ethernet board (fibre / copper) + modulated IRIG-B
100MhZ Ethernet board with demodulated IRIG-B Standard 100MHz Ethernet board (fibre / copper)+ demodulated IRIG-B
High-break output relay board Output relay board with high breaking capacity relays
Redundant Ethernet SHP+ modulated IRIG-B Redundant SHP Ethernet board (2 fibre ports) + modulated IRIG-B input
Redundant Ethernet SHP + demodulated IRIG-B Redundant SHP Ethernet board (2 fibre ports) + demodulated IRIG-B input
Redundant Ethernet RSTP + modulated IRIG-B Redundant RSTP Ethernet board (2 fibre ports) + modulated IRIG-B input
Redundant Ethernet RSTP+ demodulated IRIG-B Redundant RSTP Ethernet board (2 fibre ports) + demodulated IRIG-B input
Redundant Ethernet DHP+ modulated IRIG-B Redundant DHP Ethernet board (2 fibre ports) + modulated IRIG-B input
Redundant Ethernet DHP+ demodulated IRIG-B Redundant DHP Ethernet board (2 fibre ports) + demodulated IRIG-B input
Redundant Ethernet PRP+ modulated IRIG-B Redundant PRP Ethernet board (2 fibre ports) + modulated IRIG-B input
Redundant Ethernet PRP+ demodulated IRIG-B Redundant PRP Ethernet board (2 fibre ports) + demodulated IRIG-B input
Redundant Ethernet HSR + modulated IRIG-B Redundant HSR Ethernet board (2 fibre ports) + demodulated IRIG-B input
Redundant Ethernet HSR+ demodulated IRIG-B Redundant HSR Ethernet board (2 fibre ports) + demodulated IRIG-B input
Output relay output board Standard output relay board
34 P841B-TM-EN-1.1
4 FRONT PANEL
4.1 FRONT PANEL

Depending on the exact model and chosen options, the product will be housed in either a 40TE, 60TE or 80TE case.
By way of example, the following diagram shows the front panel of a typical 60TE unit. The front panels of the
products based on 40TE and 80TE cases have a lot of commonality and differ only in the number of hotkeys and
user-programmable LEDs. The hinged covers at the top and bottom of the front panel are shown open. An optional
transparent front cover physically protects the front panel.
Figure 6: Front panel (60TE)
The front panel consists of:

● Top and bottom compartments with hinged cover
● LCD display
● Keypad
● 9 pin D-type serial port
● 25 pin D-type parallel port
● Fixed function LEDs
● Function keys and LEDs (60TE and 80TE models)
● Programmable LEDs (60TE and 80TE models)
4.1.1 FRONT PANEL COMPARTMENTS

The top compartment contains labels for the:
● Serial number
● Current and voltage ratings.
P841B-TM-EN-1.1 35
The bottom compartment contains:

● A compartment for a 1/2 AA size backup battery (used to back up the real time clock and event, fault, and
disturbance records).
● A 9-pin female D-type front port for an EIA(RS)232 serial connection to a PC.
● A 25-pin female D-type parallel port for monitoring internal signals and downloading software and
language text.
4.1.2 KEYPAD
The keypad consists of the following keys:
4 arrow keys to navigate the menus (organised around the Enter key)
An enter key for executing the chosen option
A clear key for clearing the last command
A read key for viewing larger blocks of text (arrow keys now used for
scrolling)
2 hot keys for scrolling through the default display and for control of
setting groups. These are situated directly below the LCD display.
4.1.2.1 LIQUID CRYSTAL DISPLAY

The LCD is a high resolution monochrome display with 16 characters by 3 lines and controllable back light.
4.1.3 FRONT SERIAL PORT (SK1)

The front serial port is a 9-pin female D-type connector, providing RS232 serial data communication. It is situated
under the bottom hinged cover, and is used to communicate with a locally connected PC. It is used to transfer
settings data between the PC and the IED.
The port is intended for temporary connection during testing, installation and commissioning. It is not intended to
be used for permanent SCADA communications. This port supports the Courier communication protocol only.
Courier is a proprietary communication protocol to allow communication with a range of protection equipment,
and between the device and the Windows-based support software package.
This port can be considered as a DCE (Data Communication Equipment) port, so you can connect this port device
to a PC with an EIA(RS)232 serial cable up to 15 m in length.
The inactivity timer for the front port is set to 15 minutes. This controls how long the unit maintains its level of
password access on the front port. If no messages are received on the front port for 15 minutes, any password
access level that has been enabled is cancelled.
36 P841B-TM-EN-1.1
Note:
The front serial port does not support automatic extraction of event and disturbance records, although this data can be
accessed manually.
4.1.3.1 FRONT SERIAL PORT (SK1) CONNECTIONS

The port pin-out follows the standard for Data Communication Equipment (DCE) device with the following pin
connections on a 9-pin connector.
Pin number Description
2 Tx Transmit data
3 Rx Receive data
5 0 V Zero volts common
You must use the correct serial cable, or the communication will not work. A straight-through serial cable is
required, connecting pin 2 to pin 2, pin 3 to pin 3, and pin 5 to pin 5.
Once the physical connection from the unit to the PC is made, the PC’s communication settings must be set to
match those of the IED. The following table shows the unit’s communication settings for the front port.
Protocol Courier
Baud rate 19,200 bps
Courier address 1
Message format 11 bit - 1 start bit, 8 data bits, 1 parity bit (even parity), 1 stop bit
4.1.4 FRONT PARALLEL PORT (SK2)

The front parallel port uses a 25 pin D-type connector. It is used for commissioning, downloading firmware updates
and menu text editing.
4.1.5 FIXED FUNCTION LEDS

Four fixed-function LEDs on the left-hand side of the front panel indicate the following conditions.
● Trip (Red) switches ON when the IED issues a trip signal. It is reset when the associated fault record is
cleared from the front display. Also the trip LED can be configured as self-resetting.
● Alarm (Yellow) flashes when the IED registers an alarm. This may be triggered by a fault, event or
maintenance record. The LED flashes until the alarms have been accepted (read), then changes to
constantly ON. When the alarms are cleared, the LED switches OFF.
● Out of service (Yellow) is ON when the IED's functions are unavailable.
● Healthy (Green) is ON when the IED is in correct working order, and should be ON at all times. It goes OFF if
the unit’s self-tests show there is an error in the hardware or software. The state of the healthy LED is
reflected by the watchdog contacts at the back of the unit.
4.1.6 FUNCTION KEYS

The programmable function keys are available for custom use for some models.
Factory default settings associate specific functions to these keys, but by using programmable scheme logic, you
can change the default functions of these keys to fit specific needs. Adjacent to these function keys are
programmable LEDs, which are usually set to be associated with their respective function keys.
P841B-TM-EN-1.1 37
4.1.7 PROGRAMABLE LEDS

The device has a number of programmable LEDs, which can be associated with PSL-generated signals. The
programmable LEDs for most models are tri-colour and can be set to RED, YELLOW or GREEN. However the
programmable LEDs for some models are single-colour (red) only. The single-colour LEDs can be recognised by
virtue of the fact they are large and slightly oval, whereas the tri-colour LEDs are small and round.
38 P841B-TM-EN-1.1
5 REAR PANEL
The MiCOM Px40 series uses a modular construction. Most of the internal workings are on boards and modules
which fit into slots. Some of the boards plug into terminal blocks, which are bolted onto the rear of the unit.
However, some boards such as the communications boards have their own connectors. The rear panel consists of
these terminal blocks plus the rears of the communications boards.
The back panel cut-outs and slot allocations vary. This depends on the product, the type of boards and the
terminal blocks needed to populate the case. The following diagram shows a typical rear view of a case populated
with various boards.
Figure 7: Rear view of populated case
Note:
This diagram is just an example and may not show the exact product described in this manual. It also does not show the full
range of available boards, just a typical arrangement.
Not all slots are the same size. The slot width depends on the type of board or terminal block. For example, HD
(heavy duty) terminal blocks, as required for the analogue inputs, require a wider slot size than MD (medium duty)
terminal blocks. The board positions are not generally interchangeable. Each slot is designed to house a particular
type of board. Again this is model-dependent.
The device may use one or more of the terminal block types shown in the following diagram. The terminal blocks
are fastened to the rear panel with screws.
● Heavy duty (HD) terminal blocks for CT and VT circuits
● Medium duty (MD) terminal blocks for the power supply, opto-inputs, relay outputs and rear
communications port
● MiDOS terminal blocks for CT and VT circuits
● RTD/CLIO terminal block for connection to analogue transducers
P841B-TM-EN-1.1 39
,
Figure 8: Terminal block types
Note:
Not all products use all types of terminal blocks. The product described in this manual may use one or more of the above
types.
40 P841B-TM-EN-1.1
6 BOARDS AND MODULES

Each product comprises a selection of PCBs (Printed Circuit Boards) and subassemblies, depending on the chosen
configuration.
6.1 PCBS
A PCB typically consists of the components, a front connector for connecting into the main system parallel bus via
a ribbon cable, and an interface to the rear. This rear interface may be:
● Directly presented to the outside world (as is the case for communication boards such as Ethernet Boards)
● Presented to a connector, which in turn connects into a terminal block bolted onto the rear of the case (as is
the case for most of the other board types)
Figure 9: Rear connection to terminal block
6.2 SUBASSEMBLIES
A sub-assembly consists of two or more boards bolted together with spacers and connected with electrical
connectors. It may also have other special requirements such as being encased in a metal housing for shielding
against electromagnetic radiation.
Boards are designated by a part number beginning with ZN, whereas pre-assembled sub-assemblies are
designated with a part number beginning with GN. Sub-assemblies, which are put together at the production
stage, do not have a separate part number.
P841B-TM-EN-1.1 41
The products in the Px40 series typically contain two sub-assemblies:

● The power supply assembly comprising:
○ A power supply board
○ An output relay board
● The input module comprising:
○ One or more transformer boards, which contains the voltage and current transformers (partially or
fully populated)
○ One or more input boards
○ Metal protective covers for EM (electromagnetic) shielding
The input module is pre-assembled and is therefore assigned a GN number, whereas the power supply module is
assembled at production stage and does not therefore have an individual part number.
6.3 MAIN PROCESSOR BOARD
Figure 10: Main processor board
The main processor board performs all calculations and controls the operation of all other modules in the IED,
including the data communication and user interfaces. This is the only board that does not fit into one of the slots.
It resides in the front panel and connects to the rest of the system using an internal ribbon cable.
The LCD and LEDs are mounted on the processor board along with the front panel communication ports.
The memory on the main processor board is split into two categories: volatile and non-volatile. The volatile
memory is fast access SRAM, used by the processor to run the software and store data during calculations. The
non-volatile memory is sub-divided into two groups:
● Flash memory to store software code, text and configuration data including the present setting values.
● Battery-backed SRAM to store disturbance, event, fault and maintenance record data.
There are two board types available depending on the size of the case:
● For models in 40TE cases
● For models in 60TE cases and larger
42 P841B-TM-EN-1.1
6.4 POWER SUPPLY BOARD
Figure 11: Power supply board
The power supply board provides power to the unit. One of three different configurations of the power supply
board can be fitted to the unit. This is specified at the time of order and depends on the magnitude of the supply
voltage that will be connected to it.
There are three board types, which support the following voltage ranges:
● 24/54 V DC
● 48/125 V DC or 40-100V AC
● 110/250 V DC or 100-240V AC
The power supply board connector plugs into a medium duty terminal block. This terminal block is always
positioned on the right hand side of the unit looking from the rear.
The power supply board is usually assembled together with a relay output board to form a complete subassembly,
as shown in the following diagram.
P841B-TM-EN-1.1 43
Figure 12: Power supply assembly
The power supply outputs are used to provide isolated power supply rails to the various modules within the unit.
Three voltage levels are used by the unit’s modules:
● 5.1 V for all of the digital circuits
● +/- 16 V for the analogue electronics such as on the input board
● 22 V for driving the output relay coils.
All power supply voltages, including the 0 V earth line, are distributed around the unit by the 64-way ribbon cable.
The power supply board incorporates inrush current limiting. This limits the peak inrush current to approximately
10 A.
Power is applied to pins 1 and 2 of the terminal block, where pin 1 is negative and pin 2 is positive. The pin
numbers are clearly marked on the terminal block as shown in the following diagram.
44 P841B-TM-EN-1.1
Figure 13: Power supply terminals
6.4.1 WATCHDOG
The Watchdog contacts are also hosted on the power supply board. The Watchdog facility provides two output
relay contacts, one normally open and one normally closed. These are used to indicate the health of the device
and are driven by the main processor board, which continually monitors the hardware and software when the
device is in service.
P841B-TM-EN-1.1 45
Figure 14: Watchdog contact terminals
6.4.2 REAR SERIAL PORT

The rear serial port (RP1) is housed on the power supply board. This is a three-terminal EIA(RS)485 serial
communications port and is intended for use with a permanently wired connection to a remote control centre for
SCADA communication. The interface supports half-duplex communication and provides optical isolation for the
serial data being transmitted and received.
The physical connectivity is achieved using three screw terminals; two for the signal connection, and the third for
the earth shield of the cable. These are located on pins 16, 17 and 18 of the power supply terminal block, which is
on the far right looking from the rear. The interface can be selected between RS485 and K-bus. When the K-Bus
option is selected, the two signal connections are not polarity conscious.
The polarity independent K-bus can only be used for the Courier data protocol. The polarity conscious MODBUS,
IEC 60870-5-103 and DNP3.0 protocols need RS485.
The following diagram shows the rear serial port. The pin assignments are as follows:
● Pin 16: Earth shield
● Pin 17: Negative signal
● Pin 18: Positive signal
46 P841B-TM-EN-1.1
Figure 15: Rear serial port terminals
An additional serial port with D-type presentation is available as an optional board, if required.
6.5 INPUT MODULE - 1 TRANSFORMER BOARD
Figure 16: Input module - 1 transformer board
The input module consists of the main input board coupled together with an instrument transformer board. The
instrument transformer board contains the voltage and current transformers, which isolate and scale the
analogue input signals delivered by the system transformers. The input board contains the A/D conversion and
digital processing circuitry, as well as eight digital isolated inputs (opto-inputs).
The boards are connected together physically and electrically. The module is encased in a metal housing for
shielding against electromagnetic interference.
P841B-TM-EN-1.1 47
6.5.1 INPUT MODULE CIRCUIT DESCRIPTION
Optical 8 digital inputs Optical

Isolator Isolator
Noise Noise
filter filter
Parallel Bus
Buffer
Transformer
board
VT
or
CT
Serial Serial Link

A/D Converter
interface
VT
or
CT
V00239
Figure 17: Input module schematic
A/D Conversion
The differential analogue inputs from the CT and VT transformers are presented to the main input board as shown.
Each differential input is first converted to a single input quantity referenced to the input board’s earth potential.
The analogue inputs are sampled and converted to digital, then filtered to remove unwanted properties. The
samples are then passed through a serial interface module which outputs data on the serial sample data bus.
The calibration coefficients are stored in non-volatile memory. These are used by the processor board to correct
for any amplitude or phase errors introduced by the transformers and analogue circuitry.
Opto-isolated inputs
The other function of the input board is to read in the state of the digital inputs. As with the analogue inputs, the
digital inputs must be electrically isolated from the power system. This is achieved by means of the 8 on-board
optical isolators for connection of up to 8 digital signals. The digital signals are passed through an optional noise
filter before being buffered and presented to the unit’s processing boards in the form of a parallel data bus.
This selectable filtering allows the use of a pre-set filter of ½ cycle which renders the input immune to induced
power-system noise on the wiring. Although this method is secure it can be slow, particularly for inter-tripping. This
can be improved by switching off the ½ cycle filter, in which case one of the following methods to reduce ac noise
should be considered.
● Use double pole switching on the input
● Use screened twisted cable on the input circuit
48 P841B-TM-EN-1.1
The opto-isolated logic inputs can be configured for the nominal battery voltage of the circuit for which they are a
part, allowing different voltages for different circuits such as signalling and tripping.
Note:
The opto-input circuitry can be provided without the A/D circuitry as a separate board, which can provide supplementary
opto-inputs.
6.5.2 TRANSFORMER BOARD
Figure 18: Transformer board
The transformer board hosts the current and voltage transformers. These are used to step down the currents and
voltages originating from the power systems' current and voltage transformers to levels that can be used by the
devices' electronic circuitry. In addition to this, the on-board CT and VT transformers provide electrical isolation
between the unit and the power system.
The transformer board is connected physically and electrically to the input board to form a complete input module.
For terminal connections, please refer to the wiring diagrams.
P841B-TM-EN-1.1 49
6.5.3 INPUT BOARD
Figure 19: Input board
The input board is used to convert the analogue signals delivered by the current and voltage transformers into
digital quantities used by the IED. This input board also has on-board opto-input circuitry, providing eight optically-
isolated digital inputs and associated noise filtering and buffering. These opto-inputs are presented to the user by
means of a MD terminal block, which sits adjacent to the analogue inputs HD terminal block.
The input board is connected physically and electrically to the transformer board to form a complete input module.
The terminal numbers of the opto-inputs are as follows:
Terminal Number Opto-input
Terminal 1 Opto 1 -ve
Terminal 2 Opto 1 +ve
Terminal 13 Opto 7 –ve
Terminal 15 Opto 8 –ve
50 P841B-TM-EN-1.1
Terminal Number Opto-input

Terminal 17 Common
Terminal 18 Common
6.6 STANDARD OUTPUT RELAY BOARD
Figure 20: Standard output relay board - 8 contacts
This output relay board has 8 relays with 6 Normally Open contacts and 2 Changeover contacts.
The output relay board is provided together with the power supply board as a complete assembly, or
independently for the purposes of relay output expansion.
There are two cut-out locations in the board. These can be removed to allow power supply components to
protrude when coupling the output relay board to the power supply board. If the output relay board is to be used
independently, these cut-out locations remain intact.
The terminal numbers are as follows:
Terminal Number Output Relay
Terminal 1 Relay 1 NO
P841B-TM-EN-1.1 51
Terminal Number Output Relay

Terminal 13 Relay 7 changeover
Terminal 15 Relay 7 common
Terminal 18 Relay 8 common
6.7 IRIG-B BOARD
Figure 21: IRIG-B board
The IRIG-B board can be fitted to provide an accurate timing reference for the device. The IRIG-B signal is
connected to the board via a BNC connector. The timing information is used to synchronise the IED's internal real-
time clock to an accuracy of 1 ms. The internal clock is then used for time tagging events, fault, maintenance and
disturbance records.
IRIG-B interface is available in modulated or demodulated formats.
The IRIG-B facility is provided in combination with other functionality on a number of additional boards, such as:
● Fibre board with IRIG-B
● Second rear communications board with IRIG-B
● Ethernet board with IRIG-B
● Redundant Ethernet board with IRIG-B
There are three types of each of these boards; one type which accepts a modulated IRIG-B input, one type which
accepts a demodulated IRIG-B input and one type which accepts a universal IRIG-B input.
52 P841B-TM-EN-1.1
6.8 FIBRE OPTIC BOARD
Figure 22: Fibre optic board
This board provides an interface for communicating with a master station. This communication link can use all
compatible protocols (Courier, IEC 60870-5-103, MODBUS and DNP 3.0). It is a fibre-optic alternative to the metallic
RS485 port presented on the power supply terminal block. The metallic and fibre optic ports are mutually exclusive.
The fibre optic port uses BFOC 2.5 ST connectors.
The board comes in two varieties; one with an IRIG-B input and one without:
P841B-TM-EN-1.1 53
6.9 REAR COMMUNICATION BOARD
Figure 23: Rear communication board
The optional communications board containing the secondary communication ports provide two serial interfaces
presented on 9 pin D-type connectors. These interfaces are known as SK4 and SK5. Both connectors are female
connectors, but are configured as DTE ports. This means pin 2 is used to transmit information and pin 3 to receive.
SK4 can be used with RS232, RS485 and K-bus. SK5 can only be used with RS232 and is used for electrical
teleprotection. The optional rear communications board and IRIG-B board are mutually exclusive since they use
the same hardware slot. However, the board comes in two varieties; one with an IRIG-B input and one without.
6.10 ETHERNET BOARD
Figure 24: Ethernet board
54 P841B-TM-EN-1.1
This is a communications board that provides a standard 100-Base Ethernet interface. This board supports one
electrical copper connection and one fibre-pair connection.
There are several variants for this board as follows:
● 100 Mbps Ethernet board
● 100 Mbps Ethernet with on-board modulated IRIG-B input
● 100 Mbps Ethernet with on-board unmodulated IRIG-B input
● 100 Mbps Ethernet with on-board universal IRIG-B input
Three of the variants provide an IRIG-B interface. IRIG-B provides a timing reference for the unit – one board for
modulated IRIG-B, one for demodulated and one board for universal IRIG-B. The IRIG B signal is connected to the
board with a BNC connector.
The Ethernet and other connection details are described below:
IRIG-B Connector
● Centre connection: Signal
● Outer connection: Earth
LEDs
LED Function On Off Flashing
Green Link Link ok Link broken
Yellow Activity Traffic
Optical Fibre Connectors

Connector Function
Rx Receive
Tx Transmit
RJ45 connector
Pin Signal name Signal definition
1 TXP Transmit (positive)
2 TXN Transmit (negative)
3 RXP Receive (positive)
4 - Not used
5 - Not used
6 RXN Receive (negative)
7 - Not used
8 - Not used
P841B-TM-EN-1.1 55
6.11 REDUNDANT ETHERNET BOARD
Figure 25: Redundant Ethernet board
This board provides dual redundant Ethernet (supported by two fibre pairs) together with an IRIG-B interface for
timing.
Different board variants are available, depending on the redundancy protocol and the type of IRIG-B signal
(unmodulated or modulated). The available redundancy protocols are:
● SHP (Self-Healing Protocol)
● RSTP (Rapid Spanning Tree Protocol)
● DHP (Dual Homing Protocol)
● PRP (Parallel Redundancy Protocol)
● HSR (High-availability Seamless Redundancy)
There are several variants for this board as follows:

● 100 Mbps redundant Ethernet running RSTP, with on-board modulated IRIG-B
● 100 Mbps redundant Ethernet running RSTP, with on-board unmodulated IRIG-B
● 100 Mbps redundant Ethernet running SHP, with on-board modulated IRIG-B
● 100 Mbps redundant Ethernet running SHP, with on-board unmodulated IRIG-B
● 100 Mbps redundant Ethernet running DHP, with on-board modulated IRIG-B
● 100 Mbps redundant Ethernet running DHP, with on-board unmodulated IRIG-B
● 100 Mbps redundant Ethernet running PRP + HSR, with on-board modulated IRIG-B
● 100 Mbps redundant Ethernet running PRP + HSR, with on-board demodulated IRIG-B
● 100 Mbps redundant Ethernet running RSTP + PRP + HSR (two fibre pairs), with on-board universal IRIG-B
● 100 Mbps redundant Ethernet running RSTP + PRP + HSR (two copper pairs), with on-board universal IRIG-B
The Ethernet and other connection details are described below:
IRIG-B Connector
● Centre connection: Signal
● Outer connection: Earth
56 P841B-TM-EN-1.1
Link Fail Connector (Ethernet Board Watchdog Relay)

Pin Closed Open
1-2 Link fail Channel 1 (A) Link ok Channel 1 (A)
2-3 Link fail Channel 2 (B) Link ok Channel 2 (B)
LEDs
LED Function On Off Flashing
Green Link Link ok Link broken
Yellow Activity SHP running PRP, RSTP or DHP traffic
Optical Fibre Connectors (ST)

Connector DHP RSTP SHP PRP
A RXA RX1 RS RXA
B TXA TX1 ES TXA
C RXB RX2 RP RXB
D TXB TX2 EP TXB
RJ45connector
4 - Not used
5 - Not used
7 - Not used
8 - Not used
P841B-TM-EN-1.1 57
58 P841B-TM-EN-1.1
CHAPTER 4
SOFTWARE DESIGN
Chapter 4 - Software Design P841B
60 P841B-TM-EN-1.1
P841B Chapter 4 - Software Design
1 CHAPTER OVERVIEW
This chapter describes the software design of the IED.
Chapter Overview 61
Sofware Design Overview 62
System Level Software 63
Platform Software 66
Protection and Control Functions 67
P841B-TM-EN-1.1 61
2 SOFWARE DESIGN OVERVIEW

The device software can be conceptually categorized into several elements as follows:
● The system level software
● The platform software
● The protection and control software
These elements are not distinguishable to the user, and the distinction is made purely for the purposes of
explanation. The following figure shows the software architecture.
Protection and Control Software Layer

Protection Task
Programmable & fixed Coprocessor protection
scheme logic algorithms
Fault locator Disturbance
Signal processing Protection algorithms task recorder task
Supervisor task
Records
and control
Protection
settings
Platform Software Layer
Event, fault,
Remote
disturbance,
Settings database communications
maintenance record
Sampling function interfaces
logging
Front panel Local

interface communications
(LCD + Keypad) interfaces
Sample data + digital Control of interfaces to keypad , LCD, LEDs,

logic inputs front & rear ports.
Control of output contacts
and programmable LEDs Self-checking maintenance records
System Level Software Layer

System services (e.g. device drivers) / Real time operating system / Self-diagnostic software
Hardware Device Layer

LEDs / LCD / Keypad / Memory / FPGA
V00307
Figure 26: Software Architecture
The software, which executes on the main processor, can be divided into a number of functions as illustrated
above. Each function is further broken down into a number of separate tasks. These tasks are then run according
to a scheduler. They are run at either a fixed rate or they are event driven. The tasks communicate with each other
as and when required.
62 P841B-TM-EN-1.1
3 SYSTEM LEVEL SOFTWARE
3.1 REAL TIME OPERATING SYSTEM

The real-time operating system is used to schedule the processing of the various tasks. This ensures that they are
processed in the time available and in the desired order of priority. The operating system also plays a part in
controlling the communication between the software tasks, through the use of operating system messages.
3.2 SYSTEM SERVICES SOFTWARE

The system services software provides the layer between the hardware and the higher-level functionality of the
platform software and the protection and control software. For example, the system services software provides
drivers for items such as the LCD display, the keypad and the remote communication ports. It also controls things
like the booting of the processor and the downloading of the processor code into RAM at startup.
3.3 SELF-DIAGNOSTIC SOFTWARE

The device includes several self-monitoring functions to check the operation of its hardware and software while in
service. If there is a problem with the hardware or software, it should be able to detect and report the problem, and
attempt to resolve the problem by performing a reboot. In this case, the device would be out of service for a short
time, during which the ‘Healthy’ LED on the front of the device is switched OFF and the watchdog contact at the
rear is ON. If the restart fails to resolve the problem, the unit takes itself permanently out of service; the ‘Healthy’
LED stays OFF and watchdog contact stays ON.
If a problem is detected by the self-monitoring functions, the device attempts to store a maintenance record to
allow the nature of the problem to be communicated to the user.
The self-monitoring is implemented in two stages: firstly a thorough diagnostic check which is performed on boot-
up, and secondly a continuous self-checking operation, which checks the operation of the critical functions whilst
it is in service.
3.4 STARTUP SELF-TESTING

The self-testing takes a few seconds to complete, during which time the IED's measurement, recording, control,
and protection functions are unavailable. On a successful start-up and self-test, the ‘health-state’ LED on the front
of the unit is switched on. If a problem is detected during the start-up testing, the device remains out of service
until it is manually restored to working order.
The operations that are performed at start-up are:
1. System boot
2. System software initialisation
3. Platform software initialisation and monitoring
3.4.1 SYSTEM BOOT

The integrity of the Flash memory is verified using a checksum before the program code and stored data is loaded
into RAM for execution by the processor. When the loading has been completed, the data held in RAM is compared
to that held in the Flash memory to ensure that no errors have occurred in the data transfer and that the two are
the same. The entry point of the software code in RAM is then called. This is the IED's initialisation code.
P841B-TM-EN-1.1 63
3.4.2 SYSTEM LEVEL SOFTWARE INITIALISATION

The initialization process initializes the processor registers and interrupts, starts the watchdog timers (used by the
hardware to determine whether the software is still running), starts the real-time operating system and creates
and starts the supervisor task. In the initialization process the device checks the following:
● The status of the backup battery
● The integrity of the battery-backed SRAM that is used to store event, fault and disturbance records
● The operation of the LCD controller
● The watchdog operation
At the conclusion of the initialization software the supervisor task begins the process of starting the platform
software. Coprocessor board checks are also made as follows:
● A check is made for the presence of the coprocessor board
● The RAM on the coprocessor board is checked with a test bit pattern before the coprocessor board is
transferred from flash memory
If any of these checks produces an error, the coprocessor board is left out of service. The other protection
functions provided by the main processor board are left in service.
3.4.3 PLATFORM SOFTWARE INITIALISATION AND MONITORING

When starting the platform software, the IED checks the following:
● The integrity of the data held in non-volatile memory (using a checksum)
● The operation of the real-time clock
● The optional IRIG-B function (if applicable)
● The presence and condition of the input board
● The analog data acquisition system (it does this by sampling the reference voltage)
At the successful conclusion of all of these tests the unit is entered into service and the application software is
started up.
3.5 CONTINUOUS SELF-TESTING

When the IED is in service, it continually checks the operation of the critical parts of its hardware and software. The
checking is carried out by the system services software and the results are reported to the platform software. The
functions that are checked are as follows:
● The Flash memory containing all program code and language text is verified by a checksum.
● The code and constant data held in system memory is checked against the corresponding data in Flash
memory to check for data corruption.
● The system memory containing all data other than the code and constant data is verified with a checksum.
● The integrity of the digital signal I/O data from the opto-inputs and the output relay coils is checked by the
data acquisition function every time it is executed.
● The operation of the analog data acquisition system is continuously checked by the acquisition function
every time it is executed. This is done by sampling the reference voltages.
● The operation of the optional Ethernet board is checked by the software on the main processor card. If the
Ethernet board fails to respond an alarm is raised and the card is reset in an attempt to resolve the problem.
● The operation of the optional IRIG-B function is checked by the software that reads the time and date from
the board.
In the event that one of the checks detects an error in any of the subsystems, the platform software is notified and
it attempts to log a maintenance record.
64 P841B-TM-EN-1.1
If the problem is with the battery status or the IRIG-B board, the device continues in operation. For problems
detected in any other area, the device initiates a shutdown and re-boot, resulting in a period of up to 10 seconds
when the functionality is unavailable.
A restart should clear most problems that may occur. If, however, the diagnostic self-check detects the same
problem that caused the IED to restart, it is clear that the restart has not cleared the problem, and the device takes
itself permanently out of service. This is indicated by the ‘’health-state’ LED on the front of the device, which
switches OFF, and the watchdog contact which switches ON.
P841B-TM-EN-1.1 65
4 PLATFORM SOFTWARE
The platform software has three main functions:
● To control the logging of records generated by the protection software, including alarms, events, faults, and
maintenance records
● To store and maintain a database of all of the settings in non-volatile memory
● To provide the internal interface between the settings database and the user interfaces, using the front
panel interface and the front and rear communication ports
4.1 RECORD LOGGING

The logging function is used to store all alarms, events, faults and maintenance records. The records are stored in
non-volatile memory to provide a log of what has happened. The IED maintains four types of log on a first in first
out basis (FIFO). These are:
● Alarms
● Event records
● Fault records
● Maintenance records
The logs are maintained such that the oldest record is overwritten with the newest record. The logging function
can be initiated from the protection software. The platform software is responsible for logging a maintenance
record in the event of an IED failure. This includes errors that have been detected by the platform software itself or
errors that are detected by either the system services or the protection software function. See the Monitoring and
Control chapter for further details on record logging.
4.2 SETTINGS DATABASE

The settings database contains all the settings and data, which are stored in non-volatile memory. The platform
software manages the settings database and ensures that only one user interface can modify the settings at any
one time. This is a necessary restriction to avoid conflict between different parts of the software during a setting
change.
Changes to protection settings and disturbance recorder settings, are first written to a temporary location SRAM
memory. This is sometimes called 'Scratchpad' memory. These settings are not written into non-volatile memory
immediately. This is because a batch of such changes should not be activated one by one, but as part of a
complete scheme. Once the complete scheme has been stored in SRAM, the batch of settings can be committed to
the non-volatile memory where they will become active.
4.3 INTERFACES
The settings and measurements database must be accessible from all of the interfaces to allow read and modify
operations. The platform software presents the data in the appropriate format for each of the interfaces (LCD
display, keypad and all the communications interfaces).
66 P841B-TM-EN-1.1
5 PROTECTION AND CONTROL FUNCTIONS

The protection and control software processes all of the protection elements and measurement functions. To
achieve this it has to communicate with the system services software, the platform software as well as organise its
own operations.
The protection task software has the highest priority of any of the software tasks in the main processor board. This
ensures the fastest possible protection response.
The protection and control software provides a supervisory task, which controls the start-up of the task and deals
with the exchange of messages between the task and the platform software.
5.1 ACQUISITION OF SAMPLES

After initialization, the protection and control task waits until there are enough samples to process. The acquisition
of samples on the main processor board is controlled by a ‘sampling function’ which is called by the system
services software.
This sampling function takes samples from the input module and stores them in a two-cycle FIFO buffer. These
samples are also stored concurrently by the coprocessor. The sample rate is 48 samples per cycle. This results in a
nominal sample rate of 2,400 samples per second for a 50 hz system and 2,880 samples per second for a 60 Hz
system. However the sample rate is not fixed. It tracks the power system frequency as described in the next
section.
In normal operation, the protection task is executed 16 times per cycle.
5.2 FREQUENCY TRACKING

The device provides a frequency tracking algorithm so that there are always 48 samples per cycle irrespective of
frequency drift. The frequency range in which 48 samples per second are provided is between 45 Hz and 66 z. If
the frequency falls outside this range, the sample rate reverts to its default rate of 2,400 Hz for 50 Hz or 2,880 Hz
for 60 Hz.
The frequency tracking of the analog input signals is achieved by a recursive Fourier algorithm which is applied to
one of the input signals. It works by detecting a change in the signal’s measured phase angle. The calculated value
of the frequency is used to modify the sample rate being used by the input module, in order to achieve a constant
sample rate per cycle of the power waveform. The value of the tracked frequency is also stored for use by the
protection and control task.
The frequency tracks off any voltage or current in the order VA, VB, VC, IA, IB, IC, down to 10%Vn for voltage and
5%In for current.
5.3 DIRECT USE OF SAMPLE VALUES

Most of the IED’s protection functionality uses the Fourier components calculated by the device’s signal processing
software. However RMS measurements and some special protection algorithms available in some products use
the sampled values directly.
The disturbance recorder also uses the samples from the input module, in an unprocessed form. This is for
waveform recording and the calculation of true RMS values of current, voltage and power for metering purposes.
In the case of special protection algorithms, using the sampled values directly provides exceptionally fast response
because you do not have to wait for the signal processing task to calculate the fundamental. You can act on the
sampled values immediately.
5.4 FOURIER SIGNAL PROCESSING

All backup protection and measurement functions use single-cycle fourier digital filtering to extract the power
frequency component. This filtering is performed on the main processor board.
P841B-TM-EN-1.1 67
When the protection and control task is re-started by the sampling function, it calculates the Fourier components
for the analog signals. Although some protection algorithms use some Fourier-derived harmonics (e.g. second
harmonic for magnetizing inrush), most protection functions are based on the Fourier-derived fundamental
components of the measured analog signals. The Fourier components of the input current and voltage signals are
stored in memory so that they can be accessed by all of the protection elements’ algorithms.
The Fourier components are calculated using single-cycle Fourier algorithm. This Fourier algorithm always uses
the most recent 48 samples from the 2-cycle buffer.
Most protection algorithms use the fundamental component. In this case, the Fourier algorithm extracts the power
frequency fundamental component from the signal to produce its magnitude and phase angle. This can be
represented in either polar format or rectangular format, depending on the functions and algorithms using it.
The Fourier function acts as a filter, with zero gain at DC and unity gain at the fundamental, but with good
harmonic rejection for all harmonic frequencies up to the nyquist frequency. Frequencies beyond this nyquist
frequency are known as alias frequencies, which are introduced when the sampling frequency becomes less than
twice the frequency component being sampled. However, the Alias frequencies are significantly attenuated by an
anti-aliasing filter (low pass filter), which acts on the analog signals before they are sampled. The ideal cut-off point
of an anti-aliasing low pass filter would be set at:
(samples per cycle) ´ (fundamental frequency)/2
At 48samples per cycle, this would be nominally 1200 Hz for a 50 Hz system, or 1440 Hz for a 60 Hz system.
The following figure shows the nominal frequency response of the anti-alias filter and the Fourier filter for a 48-
sample single cycle fourier algorithm acting on the fundamental component:
1
Ideal anti-alias filter response
0.8
Fourier Response
0.6 Real anti-alias filter without anti-alias filter
response
0.4
Fourier Response
0.2 with anti-alias filter
1 2 3... 24 Alias frequency

50 Hz 1200 Hz 2400 Hz
V00306
Figure 27: Frequency Response (indicative only)
5.5 PROGRAMMABLE SCHEME LOGIC

The purpose of the programmable scheme logic (PSL) is to allow you to configure your own protection schemes to
suit your particular application. This is done with programmable logic gates and delay timers. To allow greater
flexibility, different PSL is allowed for each of the four setting groups.
The input to the PSL is any combination of the status of the digital input signals from the opto-isolators on the
input board, the outputs of the protection elements such as protection starts and trips, and the outputs of the fixed
protection scheme logic (FSL). The fixed scheme logic provides the standard protection schemes. The PSL consists
of software logic gates and timers. The logic gates can be programmed to perform a range of different logic
functions and can accept any number of inputs. The timers are used either to create a programmable delay,
and/or to condition the logic outputs, such as to create a pulse of fixed duration on the output regardless of the
length of the pulse on the input. The outputs of the PSL are the LEDs on the front panel of the relay and the output
contacts at the rear.
The execution of the PSL logic is event driven. The logic is processed whenever any of its inputs change, for
example as a result of a change in one of the digital input signals or a trip output from a protection element. Also,
only the part of the PSL logic that is affected by the particular input change that has occurred is processed. This
68 P841B-TM-EN-1.1
reduces the amount of processing time that is used by the PSL. The protection & control software updates the logic
delay timers and checks for a change in the PSL input signals every time it runs.
The PSL can be configured to create very complex schemes. Because of this PSL desing is achieved by means of a
PC support package called the PSL Editor. This is available as part of the settings application software MiCOm S1
Agile, or as a standalone software module.
5.6 EVENT RECORDING

A change in any digital input signal or protection element output signal is used to indicate that an event has taken
place. When this happens, the protection and control task sends a message to the supervisor task to indicate that
an event is available to be processed and writes the event data to a fast buffer controlled by the supervisor task.
When the supervisor task receives an event record, it instructs the platform software to create the appropriate log
in non-volatile memory (battery backed-up SRAM). The operation of the record logging to battery backed-up SRAM
is slower than the supervisor buffer. This means that the protection software is not delayed waiting for the records
to be logged by the platform software. However, in the rare case when a large number of records to be logged are
created in a short period of time, it is possible that some will be lost, if the supervisor buffer is full before the
platform software is able to create a new log in battery backed-up SRAM. If this occurs then an event is logged to
indicate this loss of information.
Maintenance records are created in a similar manner, with the supervisor task instructing the platform software to
log a record when it receives a maintenance record message. However, it is possible that a maintenance record
may be triggered by a fatal error in the relay in which case it may not be possible to successfully store a
maintenance record, depending on the nature of the problem.
For more information, see the Monitoring and Control chapter.
5.7 DISTURBANCE RECORDER

The disturbance recorder operates as a separate task from the protection and control task. It can record the
waveforms for up to 12 calibrated analog channels and the values of up to 32 digital signals. The recording time is
user selectable. Up to 50 seconds of data can be recorded. A minimum number of 5 records with a capacity of 10
seconds each, up to a maximum of 50 records with a capacity of 10 seconds each can be set. The disturbance
recorder is supplied with data by the protection and control task once per cycle. The disturbance recorder collates
the data that it receives into the required length disturbance record. The disturbance records can be extracted by
settings application software such as MiCOM S1 Agile, which can also store the data in COMTRADE format,
therefore allowing the use of other packages to view the recorded data.
For more information, see the Monitoring and Control chapter.
5.8 FAULT LOCATOR

The fault locator uses 12 cycles of the analog input signals to calculate the fault location. The result is returned to
the protection and control task, which includes it in the fault record. The pre-fault and post-fault voltages are also
presented in the fault record. When the fault record is complete, including the fault location, the protection and
control task sends a message to the supervisor task to log the fault record.
The Fault Locator is not available on all models.
5.9 FUNCTION KEY INTERFACE

The function keys interface directly into the PSL as digital input signals. A change of state is only recognized when
a key press is executed on average for longer than 200 ms. The time to register a change of state depends on
whether the function key press is executed at the start or the end of a protection task cycle, with the additional
hardware and software scan time included. A function key press can provide a latched (toggled mode) or output
on key press only (normal mode) depending on how it is programmed. It can be configured to individual protection
scheme requirements. The latched state signal for each function key is written to non-volatile memory and read
P841B-TM-EN-1.1 69
from non-volatile memory during relay power up thus allowing the function key state to be reinstated after power-
up, should power be inadvertently lost.
70 P841B-TM-EN-1.1
CHAPTER 5
CONFIGURATION
Chapter 5 - Configuration P841B
72 P841B-TM-EN-1.1
P841B Chapter 5 - Configuration
1 CHAPTER OVERVIEW
Each product has different configuration parameters according to the functions it has been designed to perform.
There is, however, a common methodology used across the entire product series to set these parameters.
Some of the communications setup can only be carried out using the HMI, and cannot be carried out using
settings applications software. This chapter includes concise instructions of how to configure the device,
particularly with respect to the communications setup, as well as a description of the common methodology used
to configure the device in general.
Chapter Overview 73
Settings Application Software 74
Using the HMI Panel 75
Line Parameters 86
Date and Time Configuration 90
Settings Group Selection 91
P841B-TM-EN-1.1 73
2 SETTINGS APPLICATION SOFTWARE

To configure this device you will need to use the Settings Application Software. The settings application software
used in this range of IEDs is called MiCOM S1 Agile. It is a collection of software tools, which is used for setting up
and managing the IEDs.
Although you can change many settings using the front panel HMI, some of the features cannot be configured
without the Settings Application Software; for example the programmable scheme logic, or IEC61850
communications.
If you do not already have a copy of the Settings Application Software, you can obtain it from General Electric
contact centre.
To configure your product, you will need a data model that matches your product. When you launch the Settings
Application Software, you will be presented with a panel that allows you to invoke the “Data Model Manager”. This
will close the other aspects of the software in order to allow an efficient import of the chosen data model. If you
don’t have, or can’t find, the data model relating to your product, please call the General Electric contact centre.
When you have loaded all the data models you need, you should restart the Settings Application Software and
start to create a model of your system using the “System Explorer” panel.
The software is designed to be intuitive, but help is available in an online help system and also the Settings
Application Software user guide P40-M&CR-SAS-UG-EN-n, where 'Language' is a 2 letter code designating the
language version of the user guide and 'n' is the latest version of the settings application software.
74 P841B-TM-EN-1.1
3 USING THE HMI PANEL

Using the HMI, you can:
● Display and modify settings
● View the digital I/O signal status
● Display measurements
● Display fault records
● Reset fault and alarm indications
The keypad provides full access to the device functionality using a range of menu options. The information is
displayed on the LCD.
Keys Description Function
To change the menu level or change between settings in a

Up and down cursor keys
particular column, or changing values within a cell
To change default display, change between column

Left and right cursor keys
headings, or changing values within a cell
ENTER key For changing and executing settings
For executing commands and settings for which shortcuts

Hotkeys
have been defined
Cancel key To return to column header from any menu cell
Read key To read alarm messages
Function keys (not all models) For executing user programmable functions
Note:
As the LCD display has a resolution of 16 characters by 3 lines, some of the information is in a condensed mnemonic form.
P841B-TM-EN-1.1 75
3.1 NAVIGATING THE HMI PANEL

The cursor keys are used to navigate the menus. These keys have an auto-repeat function if held down
continuously. This can be used to speed up both setting value changes and menu navigation. The longer the key is
held pressed, the faster the rate of change or movement.
The navigation map below shows how to navigate the menu items.
Default display Default display

option option
Alarm message
Default display options
Column 00 Subsequent column headings Last Column

System data
Vertical cursor keys move

Horizontal cursor
between setting rows
Row 01 keys move Row 01
Language between values
within a cell
The Cancel key
returns to
column header
Subsequent rows Subsequent rows
V00400
Figure 28: Navigating the HMI
3.2 GETTING STARTED

When you first start the IED, it will go through its power up procedure. After a few seconds it will settle down into
one of the top level menus. There are two menus at this level:
● The Alarms menu for when there are alarms present
● The default display menu for when there are no alarms present.
If there are alarms present, the yellow Alarms LED will be flashing and the menu display will read as follows:
Alarms / Faults
Present
HOTKEY
76 P841B-TM-EN-1.1
Even though the device itself should be in full working order when you first start it, an alarm could still be present,
for example, if there is no network connection for a device fitted with a network card. If this is the case, you can
read the alarm by pressing the 'Read' key.
ALARMS
NIC Link Fail
If the device is fitted with an Ethernet card, you will first need to connect the device to an active Ethernet network
to clear the alarm and get the default display.
If there are other alarms present, these must also be cleared before you can get into the default display menu
options.
3.3 DEFAULT DISPLAY

The HMI contains a range of possible options that you can choose to be the default display. The options available
are:
NERC Compliant banner

If the device is a cyber-security model, it will provide a NERC-compliant default display. If the device does not
contain the cyber-security option, this display option is not available.
ACCESS ONLY FOR

AUTHORISED USERS
HOTKEY
Date and time

For example:
11:09:15
23 Nov 2011
HOTKEY
Description (user-defined)
For example:
Description
MiCOM P14NB
HOTKEY
Plant reference (user-defined)

For example:
P841B-TM-EN-1.1 77
Plant Reference
MiCOM
HOTKEY
Access Level
For example:
Access Level
3
HOTKEY
In addition to the above, there are also displays for the system voltages, currents, power and frequency etc.,
depending on the device model.
3.4 DEFAULT DISPLAY NAVIGATION

The following diagram is an example of the default display navigation. In this example, we have used a cyber-
secure model. This is an example only and may not apply in its entirety to all models. The actual display options
available depend on the exact model.
Use the horizontal cursor keys to step through from one display to the next.
NERC compliant
banner
NERC Compliance NERC Compliance

Warning Warning
System Current
Access Level
Measurements
System Voltage
System Frequency
Measurements
System Power
Plant Reference
Measurements
Description Date & Time
V00403
Figure 29: Default display navigation
If the device is cyber-secure but is not yet configured for NERC compliance (see Cyber-security chapter), a warning
will appear when moving from the "NERC compliant" banner. The warning message is as follows:
78 P841B-TM-EN-1.1
DISPLAY NOT NERC

COMPLIANT. OK?
You will have to confirm with the Enter button before you can go any further.
Note:
Whenever the IED has an uncleared alarm the default display is replaced by the text Alarms/ Faults present. You cannot
override this default display. However, you can enter the menu structure from the default display, even if the display shows
the Alarms/Faults present message.
3.5 PASSWORD ENTRY

Configuring the default display (in addition to modification of other settings) requires level 3 access. You will be
prompted for a password before you can make any changes, as follows. The default level 3 password is AAAA.
Enter Password
1. A flashing cursor shows which character field of the password can be changed. Press the up or down cursor
keys to change each character (tip: pressing the up arrow once will return an upper case "A" as required by
the default level 3 password).
2. Use the left and right cursor keys to move between the character fields of the password.
3. Press the Enter key to confirm the password. If you enter an incorrect password, an invalid password
message is displayed then the display reverts to Enter password. On entering a valid password a message
appears indicating that the password is correct and which level of access has been unlocked. If this level is
sufficient to edit the selected setting, the display returns to the setting page to allow the edit to continue. If
the correct level of password has not been entered, the password prompt page appears again.
4. To escape from this prompt press the Clear key. Alternatively, enter the password using the Password
setting in the SYSTEM DATA column. If the keypad is inactive for 15 minutes, the password protection of the
front panel user interface reverts to the default access level.
To manually reset the password protection to the default level, select Password, then press the CLEAR key instead
of entering a password.
Note:
In the SECURITY CONFIG column, you can set the maximum number of attemps, the time window in which the failed attempts
are counted and the time duration for which the user is blocked.
P841B-TM-EN-1.1 79
3.6 PROCESSING ALARMS AND RECORDS

If there are any alarm messages, they will appear on the default display and the yellow alarm LED flashes. The
alarm messages can either be self-resetting or latched. If they are latched, they must be cleared manually.
1. To view the alarm messages, press the Read key. When all alarms have been viewed but not cleared, the
alarm LED changes from flashing to constantly on, and the latest fault record appears (if there is one).
2. Scroll through the pages of the latest fault record, using the cursor keys. When all pages of the fault record
have been viewed, the following prompt appears.
Press Clear To
Reset Alarms
3. To clear all alarm messages, press the Clear key. To return to the display showing alarms or faults present,
and leave the alarms uncleared, press the Read key.
4. Depending on the password configuration settings, you may need to enter a password before the alarm
messages can be cleared.
5. When all alarms are cleared, the yellow alarm LED switches off. If the red LED was on, this will also be
switched off.
Note:
To speed up the procedure, you can enter the alarm viewer using the Read key and subsequently pressing the Clear key. This
goes straight to the fault record display. Press the Clear key again to move straight to the alarm reset prompt, then press the
Clear key again to clear all alarms.
3.7 MENU STRUCTURE

Settings, commands, records and measurements are stored in a local database inside the IED. When using the
Human Machine Interface (HMI) it is convenient to visualise the menu navigation system as a table. Each item in
the menu is known as a cell, which is accessed by reference to a column and row address. Each column and row is
assigned a 2-digit hexadecimal numbers, resulting in a unique 4-digit cell address for every cell in the database.
The main menu groups are allocated columns and the items within the groups are allocated rows, meaning a
particular item within a particular group is a cell.
Each column contains all related items, for example all of the disturbance recorder settings and records are in the
same column.
There are three types of cell:
● Settings: this is for parameters that can be set to different values
● Commands: this is for commands to be executed
● Data: this is for measurements and records to be viewed, which are not settable
Note:
Sometimes the term "Setting" is used generically to describe all of the three types.
The table below, provides an example of the menu structure:

SYSTEM DATA (Col 00) VIEW RECORDS (Col 01) MEASUREMENTS 1 (Col 02) …
Language (Row 01) "Select Event [0...n]" (Row 01) IA Magnitude (Row 01) …
Password (Row 02) Menu Cell Ref (Row 02) IA Phase Angle (Row 02) …
Sys Fn Links (Row 03) Time & Date (Row 03) IB Magnitude (Row 03) …
… … … …
80 P841B-TM-EN-1.1
It is convenient to specify all the settings in a single column, detailing the complete Courier address for each
setting. The above table may therefore be represented as follows:
Setting Column Row Description
SYSTEM DATA 00 00 First Column definition
Language (Row 01) 00 01 First setting within first column
Password (Row 02) 00 02 Second setting within first column
Sys Fn Links (Row 03) 00 03 Third setting within first column
… … …
VIEW RECORDS 01 00 Second Column definition
Select Event [0...n] 01 01 First setting within second column
Menu Cell Ref 01 02 Second setting within second column
Time & Date 01 03 Third setting within second column
… … …
MEASUREMENTS 1 02 00 Third Column definition
IA Magnitude 02 01 First setting within third column
IA Phase Angle 02 02 Second setting within third column
IB Magnitude 02 03 Third setting within third column
… … …
The first three column headers are common throughout much of the product ranges. However the rows within
each of these column headers may differ according to the product type. Many of the column headers are the
same for all products within the series. However, there is no guarantee that the addresses will be the same for a
particular column header. Therefore you should always refer to the product settings documentation and not make
any assumptions.
3.8 CHANGING THE SETTINGS

1. Starting at the default display, press the Down cursor key to show the first column heading.
2. Use the horizontal cursor keys to select the required column heading.
3. Use the vertical cursor keys to view the setting data in the column.
4. To return to the column header, either press the Up cursor key for a second or so, or press the Clear key
once. It is only possible to move across columns at the column heading level.
5. To return to the default display, press the Up cursor key or the Clear key from any of the column headings. If
you use the auto-repeat function of the Up cursor key, you cannot go straight to the default display from
one of the column cells because the auto-repeat stops at the column heading.
6. To change the value of a setting, go to the relevant cell in the menu, then press the Enter key to change the
cell value. A flashing cursor on the LCD shows that the value can be changed. You may be prompted for a
password first.
7. To change the setting value, press the Up and Down cursor keys. If the setting to be changed is a binary
value or a text string, select the required bit or character to be changed using the horizontal cursor keys.
P841B-TM-EN-1.1 81
8. Press the Enter key to confirm the new setting value or the Clear key to discard it. The new setting is
automatically discarded if it is not confirmed within 15 seconds.
9. For protection group settings and disturbance recorder settings, the changes must be confirmed before
they are used. When all required changes have been entered, return to the column heading level and press
the Down cursor key. Before returning to the default display, the following prompt appears.
Update settings?
ENTER or CLEAR
10. Press the Enter key to accept the new settings or press the Clear key to discard the new settings.
Note:
For the protection group and disturbance recorder settings, if the menu time-out occurs before the changes have been
confirmed, the setting values are discarded. Control and support settings, howeverr, are updated immediately after they are
entered, without the Update settings? prompt.
3.9 DIRECT ACCESS (THE HOTKEY MENU)

For settings and commands that need to be executed quickly or on a regular basis, the IED provides a pair of keys
directly below the LCD display. These so called Hotkeys can be used to execute specified settings and commands
directly.
The functions available for direct access using these keys are:
● Setting group selection
● Control inputs
● Circuit Breaker (CB) control functions
The availability of these functions is controlled by the Direct Access cell in the CONFIGURATION column. There are
four options: Disabled, Enabled, CB Ctrl only and Hotkey only.
For the Setting Group selection and Control inputs, this cell must be set to either Enabled or Hotkey only. For
CB Control functions, the cell must be set to Enabled or CB Ctrl only.
3.9.1 SETTING GROUP SELECTION USING HOTKEYS

In some models you can use the hotkey menu to select the settings group. By default, only Setting group 1 is
enabled. Other setting groups will only be available if they are first enabled. To be able to select a different setting
group, you must first enable them in the CONFIGURATION column.
To access the hotkey menu from the default display, you press the key directly below the HOTKEY text on the LCD.
The following screen will appear.
¬User32 STG GP®

HOTKEY MENU
EXIT
Use the right cursor keys to enter the SETTING GROUP menu.
¬Menu User01®
SETTING GROUP 1
Nxt Grp Select
82 P841B-TM-EN-1.1
Select the setting group with Nxt Grp and confirm by pressing Select. If neither of the cursor keys is pressed within
20 seconds of entering a hotkey sub menu, the device reverts to the default display.
3.9.2 CONTROL INPUTS

The control inputs are user-assignable functions. You can use the CTRL I/P CONFIG column to configure the control
inputs for the hotkey menu. In order to do this, use the first setting Hotkey Enabled cell to enable or disable any of
the 32 control inputs. You can then set each control input to latched or pulsed and set its command to On/Off,
Set/Reset, In/Out, or Enabled/Disabled.
By default, the hotkey is enabled for all 32 control inputs and they are set to Set/Reset and are Latched.
To access the hotkey menu from the default display, you press the key directly below the HOTKEY text on the LCD.
The following screen will appear.
¬User32 STG GP®

HOTKEY MENU
EXIT
Press the right cursor key twice to get to the first control input, or the left cursor key to get to the last control input.
¬STP GP User02®
Control Input 1
EXIT SET
Now you can execute the chosen function (Set/Reset in this case).
If neither of the cursor keys is pressed within 20 seconds of entering a hotkey sub menu, the device reverts to the
default display.
3.9.3 CIRCUIT BREAKER CONTROL

You can open and close the controlled circuit breaker with the hotkey to the right, if enabled as described above.
By default, hotkey access to the circuit breakers is disabled.
If hotkeyaccess to the circuit breakers has been enabled, the bottom right hand part of the display will read "Open
or Close" depending on whether the circuit breaker is closed or open respectively:
For example:
Plant Reference
MiCOM
HOTKEY CLOSE
To close the circuit breaker (in this case), press the key directly below CLOSE. You will be given an option to cancel
or confirm.
Execute
CB CLOSE
Cancel Confirm
More detailed information on this can be found in the Monitoring and Control chapter.
P841B-TM-EN-1.1 83
3.10 FUNCTION KEYS

Most products have a number of function keys for programming control functionality using the programmable
scheme logic (PSL).
Each function key has an associated programmable tri-colour LED that can be programmed to give the desired
indication on function key activation.
These function keys can be used to trigger any function that they are connected to as part of the PSL. The function
key commands are in the FUNCTION KEYS column.
The first cell down in the FUNCTION KEYS column is the Fn Key Status cell. This contains a binary string, which
represents the function key commands. Their status can be read from this binary string.
FUNCTION KEYS
Fn Key Status
0000000000
The next cell down (Fn Key 1) allows you to activate or disable the first function key (1). The Lock setting allows a
function key to be locked. This allows function keys that are set to Toggled mode and their DDB signal active
‘high’, to be locked in their active state, preventing any further key presses from deactivating the associated
function. Locking a function key that is set to the Normal mode causes the associated DDB signals to be
permanently off. This safety feature prevents any inadvertent function key presses from activating or deactivating
critical functions.
FUNCTION KEYS
Fn Key 1
Unlocked
The next cell down (Fn Key 1 Mode) allows you to set the function key to Normal or Toggled. In the Toggle mode
the function key DDB signal output stays in the set state until a reset command is given, by activating the function
key on the next key press. In the Normal mode, the function key DDB signal stays energised for as long as the
function key is pressed then resets automatically. If required, a minimum pulse width can be programmed by
adding a minimum pulse timer to the function key DDB output signal.
FUNCTION KEYS
Fn Key 1 Mode
Toggled
The next cell down (Fn Key 1 Label) allows you to change the label assigned to the function. The default label is
Function key 1 in this case. To change the label you need to press the enter key and then change the text on
the bottom line, character by character. This text is displayed when a function key is accessed in the function key
menu, or it can be displayed in the PSL.
FUNCTION KEYS
Fn Key 1 Label
Function Key 1
Subsequent cells allow you to carry out the same procedure as above for the other function keys.
The status of the function keys is stored in non-volatile memory. If the auxiliary supply is interrupted, the status of
all the function keys is restored. The IED only recognises a single function key press at a time and a minimum key
84 P841B-TM-EN-1.1
press duration of approximately 200 ms is required before the key press is recognised. This feature avoids
accidental double presses.
P841B-TM-EN-1.1 85
4 LINE PARAMETERS
This product requires information about the circuit to which it is applied. This includes line impedance, residual
compensation, and phase rotation sequence. For this reason circuit parameter information must be input using
the LINE PARAMETERS settings. These LINE PARAMETERS settings are used by protection elements as well as by the
fault locator.
4.1 TRIPPING MODE

The Tripping Mode setting selects whether the product should trip single-phase or three-phase when
instantaneous protection elements detect single-phase faults.
Selecting 1 and 3 Pole means that the product will only trip the affected phase for a single-phase fault. For
faults involving more than one phase the product will always trip all three phases.
Selecting 3 Pole means that the product will always trip all three phases.
For products controlling more than one circuit breaker, the tripping mode is independent for each circuit breaker.
The product features an autorecloser that can be used for single-phase autoreclose. In that case, if a single-phase
fault evolves into a multi-phase fault during the autoreclose cycle, the product will switch to three-phase tripping.
86 P841B-TM-EN-1.1
4.1.1 CB TRIP CONVERSION LOGIC DIAGRAM

530
Trip Inputs A
1 S 523
Q CB1 Trip OutputA
R
531
Trip Inputs B
1 S 524
Q CB1 Trip OutputB
R
532
Trip Inputs C
1 S 525
Q CB1 Trip OutputC
R
CB1Tripping Mode 1
&
3 Pole 1 S 526
Q CB1 Trip 3ph
858 R
AR Force CB1 3P 1
533
Force 3PTrip CB1
529
CB1 Trip I/P 3Ph
530
Trip Inputs A
1 S 1601
Q CB2 Trip OutputA
R
531
Trip Inputs B
1 S 1602
Q CB2 Trip OutputB
R
532
Trip Inputs C
1 S
1603
Q CB2 Trip OutputC
1 R
CB2Tripping Mode &
3 Pole 1 S 1600
Q CB2 Trip 3ph
1485 R
AR Force CB2 3P 1
Force 3PTrip CB2 1604
1608
CB2 Trip I/P 3Ph
Dwell
522
1 Any Trip
530 100 ms
Trip Inputs A
531
Trip Inputs B
≥ S
Trip Inputs C 532 2 Q
527
2/3 Ph Fault
R
892
Pole Dead A &
1 S 528
Q 3 Ph Fault
R
893
& 1
Pole Dead B 1
&
894 1
Pole Dead C
&
V03387
Figure 30: Circuit Breaker Trip Conversion Logic Diagram (Module 63)
4.2 RESIDUAL COMPENSATION

To improve accuracy of impedance measuring elements such as those used in distance protection and fault
locators, the total loop impedance calculation ZLP/IA can be calibrated by the positive sequence impedance
between the relaying point and the fault (ZF1) using the following equation:
VA
ZF1 =
I A + k ZN ⋅ I N
where:
● VA is the phase A voltage
● IA is the phase A current
● IN is the residual current, derived from the phase currents by the equation:
P841B-TM-EN-1.1 87
I N = I A + I B + IC
● kZN is the residual compensation coefficient given by the complex equation:
Z L 0 − Z L1
k ZN =
3Z L1
where:
● ZL0 is the total zero sequence impedance of the line (a complex value)
● ZL1 is the total positive sequence impedance of the protected line (a complex value)
The complex residual compensation coefficient is defined by two settings: kZN Res Comp (the absolute value) and
kZN Res Angle (the angle in degrees).
Caution:
The kZN Res Angle is different to that in LFZP, SHNB, and LFZR products: If importing
settings from these products, you must subtract angle ÐZL1
4.3 MUTUAL COMPENSATION

On parallel circuits, mutual flux coupling can alter the impedance seen by fault locators and distance zones. A
current input (the Mutual Compensation input) is provided to compensate.
If you want to use Mutual Compensation, the connection polarity must match that shown in the connection
diagram and the element must be Enabled in the settings.
Consider for example an A-phase to earth fault on one circuit of a parallel circuit. The positive sequence
impedance between the relaying point and the fault can be calculated using the following equation:
VA
Z F1 =
I A + kZN ⋅ I N + k Zm ⋅ I M
where:
● VA is the phase A voltage
● IA is the phase A current
● IN is the residual current of the protected line (derived from phase currents)
● IM is the residual current of the parallel line (measured)
● kZN is the residual compensation coefficient
● kZm is the mutual compensation coefficient
In the above equation:
I N = I A + I B + IC
Z L 0 − Z L1
k ZN =
3Z L1
Zm0
k Zm =
3Z L1
88 P841B-TM-EN-1.1
where:
● ZL0 is the total zero sequence impedance of the line (a complex value)
● ZL1 is the total positive sequence impedance of the protected line (complex value)
● Zm0 is the zero sequence mutual impedance between the two circuits (complex value).
If used, you must set the mutual compensation feature kZm using the settings:
● kZm Mutual Set (the absolute value) and
● kZm Mutual Angle (the angle in degrees).
Note:
The following paragraph applies only to distance products and so may not be applicable to your model
In applications where the Mutual Compensation is used to reduce errors in the distance elements, a third setting,
Mutual Cut Off, is used for a fast dynamic control. The ratio IM/IN is compared with the Mutual Cut Off setting. If
the ratio is higher, mutual compensation is suppressed to prevent false-tripping for faults on the parallel line.
Typically a Mutual Cut Off factor of 1.5 is chosen to give a good margin of safety between the requirements of
correct mutual compensation for faults on the protected circuit whilst avoiding maloperations for faults on the
parallel circuit.
P841B-TM-EN-1.1 89
5 DATE AND TIME CONFIGURATION

The date and time setting will normally be updated automatically by the chosen UTC (Universal Time Co-
ordination) time synchronisation mechanism when the device is in service. You can also set the date and time
manually using the Date/Time cell in the DATE AND TIME column.
5.1 TIME ZONE COMPENSATION

The UTC time standard uses Greenwich Mean Time as its standard. Without compensation, the date and time
would be displayed on the device irrespective of its location.
You may wish to display the local time corresponding to its geographical location. You can do this with the settings
LocalTime Enable and LocalTime Offset.
The LocalTime Enable has three setting options; Disabled, Fixed, and Flexible.
With Disabled, no local time zone is maintained. Time synchronisation from any interface will be used to directly
set the master clock. All times displayed on all interfaces will be based on the master clock with no adjustment.
With Fixed, a local time zone adjustment is defined using the LocalTime Offset setting and all non-IEC 61850
interfaces, which uses the Simple Network Time Protocol (SNTP), are compensated to display the local time.
With Flexible, a local time zone adjustment is defined using the LocalTime Offset setting. The non-local and
non-IEC 61850 interfaces can be set to either the UTC zone or the local time zone. The local interfaces are always
set to the local time zone and the Ethernet interface is always set to the UTC zone.
The interfaces where you can select between UTC and Local Time are the serial interfaces RP1, RP2, DNP over
Ethernet (if applicable) and Tunnelled Courier (if applicable). This is achieved by means of the following settings,
each of which can be set to UTC or Local.:
● RP1 Time Zone
● RP2 Time Zone
● DNPOE Time Zone
● Tunnel Time Zone
The LocalTime Offset setting allows you to enter the local time zone compensation from -12 to + 12 hours at 15
minute intervals.
5.2 DAYLIGHT SAVING TIME COMPENSATION

It is possible to compensate for Daylight Saving time using the following settings
● DST Enable
● DST Offset
● DST Start
● DST Start Day
● DST Start Month
● DST Start Mins
● DST End
● DST End Day
● DST End Month
● DST End Mins
These settings are described in the DATE AND TIME settings table in the configuration chapter.
90 P841B-TM-EN-1.1
6 SETTINGS GROUP SELECTION

You can select the setting group using opto inputs, a menu selection, and for some models the hotkey menu or
function keys. You choose which method using the Setting Group setting in the CONFIGURATION column. There are
two possibilities; Select via Menu, or Select via PSL. If you choose Select via Menu, you set the settings group using
the Active Settings setting or with the hotkeys. If you choose Select via PSL , you set the settings group with DDB
signals according to the following table:
SG Select 1X SG Select X1 Selected Setting Group

0 0 1
0 1 2
1 0 3
1 1 4
Each setting group has its own PSL. Once a PSL configuration has been designed it can be allocated to any one of
the 4 setting groups. When downloading or extracting a PSL configuration, you will be prompted to enter the
required setting group to which it will allocated.
P841B-TM-EN-1.1 91
92 P841B-TM-EN-1.1
CHAPTER 6
AUTORECLOSE
Chapter 6 - Autoreclose P841B
94 P841B-TM-EN-1.1
P841B Chapter 6 - Autoreclose
1 CHAPTER OVERVIEW
Selected models of this product provide sophisticated Autoreclose (AR) functionality. The purpose of this chapter is
to describe the operation of this functionality including the principles, logic diagrams and applications.
Chapter Overview 95
Introduction to Autoreclose 96
Autoreclose Implementation 97
Autoreclose System Map 105
Logic Modules 133
Setting Guidelines 185
P841B-TM-EN-1.1 95
2 INTRODUCTION TO AUTORECLOSE
Approximately 80 - 90% of faults on transmission lines and distribution feeders are transient in nature. This means
that most faults do not last long, and are self-clearing if isolated. A common example of a transient fault is an
insulator flashover, which may be caused, for example, by lightning, clashing conductors, or wind-blown debris.
Protection functions detecting the flashover will cause one or more circuit breakers to trip and may also remove
the fault. If the source is removed, the fault does not recur if the line is re-energised.
The remaining 10 – 20% of faults are either semi-permanent or permanent. A small tree branch falling onto the
line for example, could cause a semi-permanent fault. Here the cause of the fault would not be removed by
immediate tripping of the circuit, but could possibly be burnt away during a time-delayed trip. Permanent faults
could be broken conductors, transformer faults, cable faults or machine faults, which must be located and
repaired before the power supply can be restored. In many fault incidents, if the faulty line is immediately tripped
out, and time is allowed for the fault arc to de-ionise, reclosing the circuit breakers will result in the line being
successfully re-energised.
Autoreclose schemes are used to automatically reclose a circuit breaker a set time after it has been opened due to
operation of a protection element. On EHV transmission networks, Autoreclose is usually characterised by high-
speed single-phase operation for the first attempt at reclosure. This is intended to help maintain system stability
during a transient fault condition. On HV/MV distribution networks, Autoreclose is applied mainly to radial feeders,
where system stability problems do not generally arise, and is generally characterised by delayed three-phase
operation with potentially multiple reclosure attempts.
Autoreclosing provides an important benefit on circuits using time-graded protection, in that it allows the use of
instantaneous protection to provide a high speed first trip. With fast tripping, the duration of the power arc
resulting from an overhead line fault is reduced to a minimum. This lessens the chance of damage to the line,
which might otherwise cause a transient fault to develop into a permanent fault. Using instantaneous protection
also prevents blowing of fuses in teed feeders, as well as reducing circuit breaker maintenance by eliminating pre-
arc heating. When instantaneous protection is used with Autoreclose, the scheme is normally arranged to block
the instantaneous protection after the first trip. Therefore, if the fault persists after re-closure, the time-graded
protection will provide discriminative tripping resulting in the isolation of the faulted section. However, for certain
applications, where the majority of the faults are likely to be transient, it is common practise to allow more than
one instantaneous trip before the instantaneous protection is blocked.
Some schemes allow a number of re-closures and time-graded trips after the first instantaneous trip, which may
result in the burning out and clearance of semi-permanent faults. Such a scheme may also be used to allow fuses
to operate in teed feeders where the fault current is low.
When considering feeders that are partly overhead line and partly underground cable, any decision to install
Autoreclose should be subject to analysis of the data (knowledge of the frequency of transient faults). This is
because this type of arrangement probably has a greater proportion of semi-permanent and permanent
faults than for purely overhead feeders. In this case, the advantages of Autoreclose are small. It can even be
disadvantageous because re-closing on to a faulty cable is likely to exacerbate the damage.
96 P841B-TM-EN-1.1
3 AUTORECLOSE IMPLEMENTATION
Before describing this function it is first necessary to understand the following terminology:
● A Shot is an attempt to close a circuit breaker using the Autoreclose function.
● Multi-shot is where more than one Shot is attempted.
● Single-shot is where only one Shot is attempted.
● Dead Time denotes the time between initiation of the Autoreclose operation and the attempt to close the
circuit breaker.
● Reclaim time is the time following the initiation of the circuit breaker closing and the resetting of the
Autoreclose scheme should the Autoreclose attempt be successful and the protection does not detect a
subsequent fault condition.
● High-speed Autoreclose is generally regarded as an Autoreclose application where the Dead Time is less
than 1 second.
● Delayed Autoreclose is generally regarded as an Autoreclose application where the Dead Time is greater
than 1 second.
This product features a multiple-shot Autoreclose function, which is suitable for both High-speed Autoreclose and
Delayed Autoreclose.
The Autoreclose function can be set to perform a single-shot, two-shot, three-shot or four-shot cycle. Dead Times
for all shots can be adjusted independently.
If a circuit breaker closes successfully at the end of the Dead Time, a Reclaim Time starts. If the circuit breaker
does not trip again, the Autoreclose function resets at the end of the Reclaim Time. If the protection trips again
during the Reclaim Time, the sequence advances to the next shot in the programmed cycle. If all programmed
reclose attempts have been made and the circuit breaker does not remain closed, the Autoreclose function goes
into Lockout, whereupon manual intervention is required.
An Autoreclose cycle can be initiated by operation of an internal or external protection element provided it is
mapped correctly, and that the circuit breaker is closed when the protection operates.
You can choose to initiate the Dead Time on:
● Protection operation
● A protection reset
● A Line Dead condition
● Circuit breaker operation
At the end of the relevant Dead Time, provided system conditions are suitable, a circuit breaker close signal is
given. The system conditions to be met for closing are that:
● the system voltages are in synchronism
● or that the dead line/live bus or live line/dead bus conditions exist as indicated by the internal system check
synchronising element
● and that the circuit breaker closing spring, or other energy source, is fully charged as indicated by the circuit
breaker healthy input.
The circuit breaker close signal is removed when the circuit breaker closes.
If the protection trips and the circuit breaker opens during the Reclaim Time, the Autoreclose function either
advances to the next shot in the programmed cycle, or if all programmed reclose attempts have been made, goes
into Lockout. Each time a closure is attempted, a sequence counter is incremented by 1 and the Reclaim Time
starts again.
Autoreclose is configured in the AUTORECLOSE column of the relevant settings group. The function is disabled by
default. If you wish to use it you must enable it first in the CONFIGURATION column.
P841B-TM-EN-1.1 97
The Autoreclose function is a logic controller implemented in software. It takes inputs and processes them
according to defined logic to generates appropriate outputs. The logic is controlled by user prescribed settings and
commands. The controlling logic is complex and so, in order to facilitate its design and understanding, it is
decomposed into smaller logic functions which, when combined together implement the complete scheme. This
section concludes with a summary of:
● the logic inputs to the Autoreclose function,
● the logic outputs from the Autoreclose function
● the Autoreclose operating sequence
● the high-level design of the system logic functionality
3.1 AUTORECLOSE LOGIC INPUTS FROM EXTERNAL SOURCES

Logic inputs control the operation of the Autoreclose function. The logic inputs are mapped using DDB signals in
the PSL.
Generally the inputs are from external equipment connected to opto-isolated inputs. They can also come from
communications inputs, and some are internally derived.
This section provides an overview of the logic inputs originating from external sources.
3.1.1 CIRCUIT BREAKER HEALTHY INPUT

For circuit breakers to close, it needs energy. This energy usually comes from a spring (spring-charged circuit
breakers) or from gas pressure (gas pressurised circuit breakers). After closing, it is necessary to re-establish
sufficient energy in the circuit breaker before it can be closed again.
DDB signal inputs to the Autoreclose function allow the health of circuit breakers to be mapped to the logic. when
asserted, these signals demonstrate that there is sufficient energy available to close and trip the circuit breaker
before initiating a circuit breaker close command. If the signal indicating the health of the circuit breaker is low,
and remains low for a defined period set in the circuit breaker healthy timer, the circuit breaker locks out and stays
open.
If the circuit breaker healthy signal is not mapped in the PSL, the DDB signal defaults to high so that Autoreclose
may proceed.
3.1.2 INHIBIT AUTORECLOSE INPUT

A logic input can be used to inhibit the Autoreclose function. The signal is mapped to the DDB signal Inhibit AR in
the PSL.
Energising the input inhibits any auto-switching of connected circuit breakers. Any Autoreclose in progress is reset
and inhibited but not locked out. This function ensures that auto-switching does not interfere with any manual
switching. A typical application is on a mesh-corner scheme where manual switching is being performed on the
mesh, for which any Autoreclose would cause interference.
For products that are capable of single-phase tripping and Autoreclose, if a single-phase Autoreclose cycle is in
progress and a single pole of the circuit breaker is tripped when the inhibit Autoreclose signal is raised, the circuit
breaker is instructed to trip all phases, ensuring that all poles are in the same state (and avoiding a pole stuck
condition) when subsequent closing of the circuit breaker is attempted.
3.1.3 BLOCK AUTORECLOSE INPUT

External inputs can be used to block the Autoreclose function. If Autoreclose is in progress when the signal is
asserted, it forces a lockout.
Typically this feature is used where Autoreclose may be required for some protections functions but not required
for others. An example is on a transformer feeder, where Autoreclose can be initiated from the feeder protection
but blocked from the transformer protection.
98 P841B-TM-EN-1.1
It can also be used if an Autoreclose cycle is likely to fail for conditions associated with the protected circuit, such
as during the Dead Time, if a circuit breaker indicates that it is not healthy to switch.
3.1.4 RESET LOCKOUT INPUT

If a condition that forced a lockout has been removed, the lockout can be reset by energising a logic input
appropriately mapped in the PSL. Energising the input will also reset any Autoreclose alarms.
3.1.5 POLE DISCREPANCY INPUT

Circuit breakers with independent mechanisms for each pole (phase), normally incorporate a mechanism to cater
for cases where the phases are not together. This automatically trips all three phases if they are either not all open,
or not all closed.
During single-phase Autoreclosing a pole discrepancy condition is necessarily introduced, but the pole discrepancy
device should not operate for this condition. This can be achieved using a delayed action pole discrepancy device
with a delay longer than the single-pole Autoreclose Dead Time (SP AR Dead Time setting).
Alternatively, an input can be used for external devices to indicate a pole discrepancy condition. The pole
discrepancy input is activated by an external device to indicate that all three poles of a circuit breaker are not in
the same position. If mapped in the PSL, energising the input forces three-phase tripping (providing there is not a
single-phase Autoreclose in progress). Otherwise, a signal indicating single-phase Autoreclose in progress can be
used to inhibit the external pole discrepancy device.
3.1.6 EXTERNAL TRIP INDICATION

Protection operation from a different device can be used to initiate the Autoreclose function. By default these
external trip inputs are mapped to initiate Autoreclose and to initiate breaker failure protection (if the functions are
enabled). These inputs are not mapped to the trip outputs. With appropriate mapping in the PSL however, the
external device can use this product to trip connected circuit breakers.
3.2 AUTORECLOSE LOGIC INPUTS

This section provides an overview of the logic inputs, which are derived internally.
3.2.1 TRIP INITIATION SIGNALS

The phase A, phase B and phase C trip inputs are used to initiate single-phase and three-phase autoreclose. For
the Autoreclose to work, you must ensure that these Trip Input signals remain appropriately mapped in the PSL.
3.2.2 CIRCUIT BREAKER STATUS INPUTS

Circuit breaker status information must be available as logic input(s) for Autoreclose to work. You can select
whether to use CB open, CB closed, or both, as inputs. The settings are made in the CB CONTROL column of the
menu, and you need to ensure that the PSL mapping of the chosen input(s) is correct.
3.2.3 SYSTEM CHECK SIGNALS

System Check and Check Synchronization functions produce signals which are used by the Autoreclose logic
ensure that the Autoreclose function is applied only when the system is in a suitable condition.
3.3 AUTORECLOSE LOGIC OUTPUTS

Output signals are provided to provide indication of an Autoreclose in progress (ARIP). An ARIP signal is asserted
when an Autoreclose sequence starts. It remains high from initiation, either until lockout, or until successful
Autoreclose.
An Autoreclose lockout condition resets any ‘Autoreclose in progress’ and associated signals. Signals are available
to indicate that Autoreclose is in progress and that a circuit breakers has been successfully closed.
P841B-TM-EN-1.1 99
3.4 AUTORECLOSE OPERATING SEQUENCE

The Autoreclose sequence is controlled by so-called Dead Timers. Dead Time Control settings are used to select
the conditions that initiate Dead Timers in the Autoreclose sequence (for example protection operate, protection
reset, CB open, etc.). This section describes typical AR operation sequences in which Dead Timers start when
protection operation resets.
Note:
In a multi-shot AR sequence, a number of Dead Timers are used (one for each shot). All Dead Timers are enabled when the
sequence is initiated, but each timer only starts when the particular shot with which it is associated is triggered.
3.4.1 AR TIMING SEQUENCE - TRANSIENT FAULT

The figure below describes the operating sequence for a single-shot Autorecloser for a transient fault that clears
when the faulted line is isolated.
Protection Trip
AR in Progress
CB Open
Dead Time
Auto -close
Reclaim Time
Successful Autoreclose
V03395
Figure 31: Autoreclose sequence for a Transient Fault
Following fault inception, the protection operates and issues a trip signal. At the same time the Autoreclose in
Progress signal is asserted. Shortly afterwards the circuit breaker will open as indicated by the CB Open signal.
Opening of the CB clears the fault and the protection resets. When this happens, the Dead Timer is started and the
output remains high until the Dead Time setting expires, whereupon it resets and the Autorecloser issues the Auto-
close command to close the circuit breaker. As the fault has been cleared, the circuit breaker closes and remains
closed. When the Auto-close pulse is removed, the Reclaim Timer starts. If no further fault is detected before the
Reclaim Timer expires, the Autoreclose is considered to be successful and this is indicated by the Successful
Autoreclose signal.
3.4.2 AR TIMING SEQUENCE - EVOLVING/PERMANENT FAULT

The figure below shows a single-shot AR operating sequence where the fault is not cleared by the first AR cycle.
The sequence starts in a similar way to that of a transient fault, but in this case the fault is not transient (it may be
permanent, or it may evolve into a fault involving more than one phase). This case shows an evolving fault
inception occurring before the Reclaim Time has expired. When the Autorecloser recognises that the protection
has tripped, the cycle is terminated. The Autorecloser goes into Lockout, and the Autoreclose in Progress signal is
reset.
100 P841B-TM-EN-1.1
Protection Trip
AR in Progress
CB Open
Dead Time
Auto-close
Reclaim Time
Autoreclose Lockout
V03396
Figure 32: Autoreclose sequence for an evolving or permanent fault
3.4.3 AR TIMING SEQUENCE - EVOLVING/PERMANENT FAULT SINGLE-PHASE

If the Autorecloser is set for single-phase operation, then single phase operation is only allowed on the first shot.
Subsequent tripping will be three-phase only until the AR has been successful or until AR has locked out as shown
in the figure below.
Protection Trip 1-ph 3-ph
AR in Progress
CB Open
Dead Time
Auto -close
Reclaim Time
Autoreclose Lockout
V03397
Figure 33: Autoreclose sequence for an evolving or permanent fault - single-phase operation
3.4.4 AR TIMING SEQUENCE - TRANSIENT FAULT DUAL CB

The figure below describes the operating sequence for a single-shot on a dual CB (2CB) Autorecloser for a transient
fault that clears when the faulted line is isolated.
P841B-TM-EN-1.1 101
Protection Trip
CB1 AR in Progress
CB2 AR in Progress
CB1 Open
CB2 Open
Dead Time
Auto -close CB1
Follower Time
Auto -close CB2
Reclaim Time
CB1 Successful close
CB2 Successful close
V03398
Figure 34: Dual CB Autoreclose Sequence for a Transient Fault
Following fault inception, the protection operates and issues a trip signal. At the same time an Autoreclose in
Progress signal is asserted for each CB. Shortly afterwards, CB1 will open as indicated by the CB1 Open signal and
after a short delay CB2 opens. Opening of CB2 clears the fault and the protection resets. When this happens, the
Dead Timer is started and the output remains high until the Dead Time setting expires, whereupon it resets and the
Autorecloser issues the Auto-close command to close CB1. When CB1 closes, the Follower Timer starts. When the
Follower Timer expires, the Autorecloser issues the Autoclose command to close CB2. After CB2 has closed, as the
fault has been cleared, both CBs remain closed. When the Auto-close 2 pulse is removed, the Reclaim Timer starts.
If no further fault is detected before the Reclaim Timer expires, the Autoreclose is considered to be successful and
this is indicated by the Successful Autoreclose signals.
3.4.5 AR TIMING SEQUENCE - EVOLVING/PERMANENT FAULT DUAL CB

The figure below shows a single-shot AR operating sequence where the fault is not cleared by the first AR cycle.
The sequence starts in a similar way to that of a transient fault, but in this case the fault is not transient (it may be
permanent, or it may evolve into a fault involving more than one phase). This case shows an evolving fault
inception occurring before the Reclaim Time has expired. When the Autorecloser recognises that the protection
has tripped, the cycle is terminated. The Autorecloser goes to Lockout, and the AR in Progress signals are reset
102 P841B-TM-EN-1.1
Protection Trip
CB1/CB2 AR in Progress
CB1 Open
CB2 Open
Dead Time Shot 1
Auto -close CB1
Follower Time
Auto -close CB2
Reclaim Time
Lockout
V03399
Figure 35: Autoreclose Sequence for an evolving/permanent fault on a dual CB application
3.4.6 AR TIMING SEQUENCE - PERSISTENT FAULT

The figure below shows the start of a multi-shot AR operating sequence where a single-phase fault is not cleared
by the first AR cycle. The sequence starts in a similar way to that of a transient fault, but in this case the fault is not
transient (it may be permanent, or it may evolve into a fault involving more than one phase). This case shows a
second fault inception occurring before the Reclaim Time has expired. The significant point here is that after the
first trip has occurred, the Autorecloser forces the 2 CBs into three-pole operation and different Dead Timers are
used for the single-phase cycle compared with the three-phase cycle.
Protection Trip 1-ph 3-ph
CB1/CB2 AR 1 -ph in
Progress
CB1/CB2 AR 3-ph in
Progress
CB1 Open 1-ph
CB1 Open 3 -ph
CB2 Open 1 -ph
CB2 Open 3 -ph
Dead Time 1 -ph
AR Force CB1 3 -ph
AR Force CB2 3 -ph
Auto -close CB1
Follower Time 1 -ph
Auto -close CB2
Reclaim Time 1 -ph
Dead Time 3 -ph
V03400
Figure 36: Autoreclose Sequence for a persistent fault on a multishot dual CB application set for single-phase
operation
P841B-TM-EN-1.1 103
Note:
For three-phase Autoreclosing, for the first shot only, Autoreclose can be performed without checking that the voltages are in
synchronism using a setting. This setting, CB1L SC Shot 1 or CB2L SC Shot 1, can be enabled to perform synch-checks on shot
1 for CB1 or CB2, or disabled to not perform the checks.
104 P841B-TM-EN-1.1
4 AUTORECLOSE SYSTEM MAP

The Autoreclose System Map describes the System Design of the Autoreclose Logic implemented in this product.
The Autoreclose is implemented in logical software modules. The logical software modules interact by exchanging
signals between themselves, and with other software processes in the product. Interchange between modules is
limited to digital signals which are realised as either DDB signals or so called “internal signals” (IntSigs). DDB signals
are available for mapping in the PSL. Internal signals are similar to DDBs but they are self-contained within the
device's functions and are not user-accessible.
The Autoreclose System Map shows the interconnection of the logic modules that are used in the Autoreclose
system.
The logic diagrams follow a convention for the elements used, using defined colours and shapes. A key to this
convention is provided below. We recommend viewing the logic diagrams in colour rather than in black and white.
The electronic version of the technical manual is in colour, but the printed version is not. However, coloured
diagrams can be provided on request.
P841B-TM-EN-1.1 105
Key:
Energising Quantity AND gate &
Internal Signal OR gate 1
DDB Signal XOR gate XOR
Internal function NOT gate
Setting cell Logic 0 0
Setting value Timer
Hardcoded setting
Pulse / Latch
Measurement Cell S
SR Latch Q
R
Internal Calculation
S
SR Latch Q
Derived setting Reset Dominant RD
HMI key Latched on positive edge
Connection / Node Inverted logic input

1
Switch Soft switch 2
Switch Multiplier X
Bandpass filter
undervalues

V00063 overvalues
Figure 37: Key to logic diagrams
106 P841B-TM-EN-1.1
4.1 AUTORECLOSE SYSTEM MAP DIAGRAMS

CB Status Time CB1 Closed 3 ph AR In Service CB1 NoAR
CB1 Status Input CB1 Open 3 ph ARIP CB2 NoAR
CB1Aux 3ph(52-A) CB1 Closed A ph Leader CB1 Leader CB1
CB1Aux 3ph(52-B) CB1 Open A ph Leader CB2 Follower CB1
CB1Aux A (52-A) CB1 Closed B ph CB1 Close Fail Leader CB2

Module 1
CB1 State Monitor CB1 Open B ph CB2 Close Fail Follower CB2
CB1Aux A (52-B)
CB1Aux B (52-A) CB1 Closed C ph AR CB1 Unhealthy
CB1LFRC
CB1Aux B (52-B) CB1 Open C ph AR CB2 Unhealthy CB2 LFRC
CB1Aux C (52- A) CB1 Status Alm CB1 NoAR SetLCB 1
CB1Aux C (52- B) CB2 NoAR SetLCB 2
CB1 ARIP
CB Status Time CB2 Closed 3 ph CB2 ARIP
CB2 Status Input CB2 Open 3 ph CB1 In Service
CB2 Aux3ph(52-A) CB2 Closed A ph CB2 In Service
CB2 Open A ph Module 7 & 8
CB2 Aux3ph(52-B) AR Enable CB1 Leader/Follower
CB2 Aux A(52-A) Module 2 CB2 Closed B ph AR Enable CB2 Logic 1 & 2
CB2 State Monitor CB2 Open B ph
CB2 Aux A(52-B) CB1 AR Lockout
CB2 Aux B(52-A) CB2 Closed C ph CB2 AR Lockout
CB2 Aux B(52-B) CB2 Open C ph
ResetL -F
CB2 Aux C(52- A) CB2 Status Alm
PrefLCB1
CB2 Aux C(52- B) PrefLCB2
CB1 Open A ph CB1OP1P SetLCB1
CB1 Open B ph CB1OPAny SetLCB2
CB1 Open C ph CB1OP2/3 P FollSPAROK

CB1 Open 3 ph Foll3PAROK
Module 3
CB2 Open A ph CB Open CB2OP1P CB2 LFRC
CB2 Open B ph CB2OPAny CB1 LFRC
CB2 Open C ph CB2OP2/3 P BARCB1
CB2 Open 3 ph BARCB2
CB1 AR Lockout CB1 In Service AR Mode Invalid AR Mode
CB1 Closed 3 ph Num CBs

CB1 CRLo Invalid_AR_Mode
CB1 ARIP Lead/Foll ARMode CB1 LSPAROK
Module 4
CB2 AR Lockout CB In Service CB2 In Service AR In Service CB1L3 PAROK
CB2 Closed 3 ph CB2 CRLo AR Enable CB1 FollSPAROK
CB2 ARIP AR Enable CB2 Foll3PAROK
AR Mode 1P CB2 LSPAROK
Auto-Reclose AR In Service
AR Mode 3P CB2L3 PAROK
HMI Command ARDisabled Seq Counter = 0 CB1FSPAROK
IEC 60870 Command
Seq Counter = 1 Module 9 CB1F3PAROK
AR On Pulse Module 5 Foll AR Mode 1P AR Modes Enable CB2FSPAROK
AR Enable
AR OFF Pulse Foll AR Mode 3P CB2F3PAROK
AR Enable Leader CB1
AR Enable CB1 Leader CB2
AR Enable CB2 FollCB1
Leader Select By PrefLCB1 CB2 LSPAROK
Select Leader PrefLCB2 FolSPAROK
CB2 Lead Module 6 FollCB2

Leader/Follower CB Selection
Num CBs CB1 LSPAROK
Foll3PAROK
CB2 Lead
V03393-1
Figure 38: Autoreclose System Map - part 1
P841B-TM-EN-1.1 107
NUM CBs AR Force CB1 3P NUM CBs CB1 Trip AR MemA

CB1Tripping Mode AR Force CB2 3P CB1 Trip OutputA CB1 Trip AR MemB
CB2Tripping Mode CB1 Ext Trip A CB1 Trip AR MemC
CB1 ARIP CB1 Trip OutputB TAR2 /3PH

CB2 ARIP CB1 Ext Trip B TARAny
Inhibit AR CB1 Trip OutputC TARA
AR In Service CB1 Ext Trip C TARB
Seq Counter= 1 CB1 Ext Trip3 ph TARC
Seq Counter= 2 ARIP ResPRMem
Seq Counter= 3 CB2 Trip AR MemA TMemAny
Module 13
Seq Counter= 4 CB2 Trip AR MemB CB1-pole / 3-pole trip TMEM1Ph
Module 10
CB1 AR Lockout Force 3- phase Trip CB2 Trip AR MemC TMEM2/3Ph
CB2 AR Lockout CB1 Trip AR MemA TMEM3Ph
AR CB1 Unhealthy CB1 Trip AR MemB
AR CB2 Unhealthy CB1 Trip AR MemC
Leader CB1 CB2TARA
Leader CB2 CB2TARB
ARDisabled CB2TARC
TARAny InitAR
CB1LSPAROK ARDisabled
CB1FSPAROK TARAny
CB21LSPAROK
NUM CBs CB2 Trip AR MemA
CB2FSPAROK
CB2 Trip OutputA CB2 Trip AR MemB
Protection function 1 Trip ProtARBlock CB2 Ext Trip A CB2 Trip AR MemC
Protection function n Trip InitAR CB2 Trip OutputB CB2TAR2/3PH
IA< Start CB2 Ext Trip B CB2 TARA
IB< Start CB2 Trip OutputC CB2 TARB

Module 11 Module 14
IC< Start CB2 Ext Trip C CB2TARC
AR Initiation CB2 1-pole / 3- pole trip
AR Trip Test A CB2 Ext Trip3ph CB2 TMEM1Ph
AR Trip Test B CB2 Trip AR MemA CB2TMEM2/3 Ph
AR Trip Test C CB2 Trip AR MemB CB2 TMEM3Ph
Any Trip CB2 Trip AR MemC
ResPRMem
Test Autoreclose AR Trip Test A
InitAR
Init APh AR Test AR Trip Test B
Module 12 AR Trip Test C Trip Inputs A FltMem2 P
Init BPh AR Test Trip Test
Init CPh AR Test AR Trip Test 3Ph Ext Fault Aph FltMem3 P
Init 3P AR Test Trip Inputs B

Ext Fault BPh
Module 15
Trip Inputs C Fault Memory
Ext Fault CPh
AR Start
V03393-2 ResPRMem
108 P841B-TM-EN-1.1
CB2 Ext Trip A AR Start Single Pole Shot Seq Counter= 0

CB2 Ext Trip B CB1 AR Init Three Pole Shot Seq Counter= 1
CB2 Ext Trip C CB1 ARIP CB1 AR Init Seq Counter= 2
CB2 Ext Trip 3ph ARIP CB2 AR Init Seq Counter= 3
CB1 Ext Trip A Module 18 Seq Counter= 4
CB1LARIP ARIP
Sequence Counter
CB1 Ext Trip B CB1FARIP AR Start Seq Counter> 4
CB1 Ext Trip C 1P Dtime Seq Counter>Set
CB1 Ext Trip 3ph Seq Counter= 1 SCIncrement
Inhibit AR LastShot
ProtRe_Op
CB1 LO Alarm
CB1 NoAR ARIP CB1 AR 1p InProg
CB1 ARIP ResetL -F CB2 AR 1p InProg
AR Start ProtRe_Op LeaderSPAR
Set CB1 Close Module 16
CB1 AR In Progress TMEM1Ph CB1LSPAR
CB1 Closed 3 ph CB2TMEM1 PH CB2LSPAR
CB2 ARIP
CB1L 3PAR CB1FSPAR
Leader CB1 CB2L 3PAR CB2FSPAR
Follower CB1 CB1F3PAR
InitAR CB2F3PAR
Module 19
TMEM2/3 Ph CB1 LARIP 1-phase AR Cycle Selection
TMEM1 Ph CB1FARIP
CB1Op2 /3P CB2 LARIP
CB1 L3PAROK CB2FARIP
CB1F3PAROK CB1 LSPAROK
CB1ARSucc CB2 LSPAROK
CBARCancel CB1FSPAROK
CB1OPAny CB2FSPAROK
CB1LSPAR
CB2 Ext Trip A CB2 AR Init
CB2LSPAR
CB2 Ext Trip B CB2 ARIP
CB2 Ext Trip C CB2LARIP Discrim Time Evolve 3Ph
CB2 Ext Trip 3ph CB2FARIP 1P Dtime CB1 Failed AR
Inhibit AR Seq Counter= 1 CB2 Failed AR
CB2 LO Alarm CB1 AR Lockout ProtRe_Op
CB2 NoAR CB2 AR Lockout EvolveLock
CB2 ARIP CB1 Closed 3 ph ResetL-F
AR Start CB2 Closed 3 ph
Set CB2 Close Module 20
CB1 ARIP
Evolving Fault
CB2 Closed 3 ph CB2 ARIP
Module 17
Leader CB2 CB2 AR In Progress
TMemAny
Follower CB2
TARAny
InitAR ProtRe_Op
CB2TMEM2/3Ph LastShot
CB2TMEM1Ph SetCB1 Cl
CB2OP2/3 P SetCB2 Cl
CB2 L3PAROK
CB2F3PAROK
CB2ARSucc
CBARCancel
CB2OPAny
V03393-3
P841B-TM-EN-1.1 109
Evolve 3Ph CB1 AR 3p InProg 3P AR DT Shot 1 OK Time 3P
CB1LARIP CB2 AR 3p InProg 3P AR DT Shot 2 3P DTime1
CB1 L3PAROK CB1L3 PAR 3P AR DT Shot 3 3P DTime2
TMEM3 P CB2L3 PAR 3P AR DT Shot 4 3P DTime3
CB1OP2/3 P CB1F3PAR DTOK CB1L 3P 3P DTime4
TMemAny CB2F 3PAR DTOK CB2L 3P 3P Dead Time IP
DTOK All CB1 3P DTime

CB1LSPAROK
Module 25 CB2 3P DTime
CB2LARIP AR Start
3-phase AR Dead Time
CB2 L3PAROK Module 21 Seq Counter= 1 3PDTCOMP
3-phase AR cycle selection
CB2TMEM3P Seq Counter= 2 CB13PDTComp
CB2OP2/3 P Seq Counter= 3 CB23PDTComp
CB2LSPAROK Seq Counter= 4
CB1FARIP CB1 L3PAR
CB1F3PAROK CB2 L3PAR
CB1FSPAROK 3PDTCOMP
CB2FARIP
CB2F3PAROK BF if LFail Cls En CB1 Follower
CB2FSPAROK AR Start En CB2 Follower
Control CloseCB1
DT Start by Prot DTOK All
CB1 AR Lockout
3PDTStart WhenLD DTOK CB1L 1P
CB1 Closed 3 ph
DTStart by CB Op DTOK CB1L 3P
CB1 Close Fail
Num CBs DTOK CB2L 1P
Control CloseCB2 Module 27
AR Start DTOK CB2L 3P Follower CB AR Enable
CB2 AR Lockout
OK Time 3P DeadLineLockout CB2 Close Fail
ARIP CB2 Closed 3 ph
CB1 AR Init
CB1FSPAR
CB2 AR Init
Module 22 CB1 F3PAR
Dead Line
Dead Time Start Enable CB2FSPAR
CB1 AR 1p InProg
CB2 F3PAR
CB2 AR 1p InProg
CB1 Open 3 ph Dynamic F/L 1PF TComp
CB2 Open 3 ph Follower Time 1P Follower Time
OKTimeSP En CB1 Follower CB1SPFTComp

CB1OP1P En CB2 Follower CB2SPFTComp
CB1OPAny 1PF TComp
CB2OP1P Seq Counter= 1
CB2OPAny AR Start
Module 28
DT Start by Prot 1P Dtime CB1LFRC Follower 1- phase CB AR Time
1 Pole Dead Time CB2LFRC

OKTimeSP
CB1 OP1P
DTOK CB1L 1P CB1SPDTComp
CB2 OP1P
DTOK CB2L 1P CB2SPDTComp
CB1FSPAR
Seq Counter= 1
Module 24 CB2FSPAR
DTOK All
1-phase AR Dead Time CB1OP2 /3P
AR Start
CB2OP2 /3P
CB1 LSPAR
CB2 LSPAR
CB1OP2/3 P
CB2OP2/3 P
V03393-4
110 P841B-TM-EN-1.1
Dynamic F /L 3PF TComp Set CB1 Close SetCB1SPCl

Follower Time 3P Follower Time Set CB2 Close SetCB13 PCl
CB1 open 3 ph CB13PFTComp CB1L SCOK SetCB2SPCl
CB2 open 3 ph CB23PFTComp CB2L SCOK SetCB23 PCl
En CB1 Follower CB1 Fast SCOK
En CB2 Follower CB2 Fast SCOK
3PF TComp OK Time 3P

Module 29
AR Start Follower 3-phase CB AR Time CB1F SCOK
CB2F SCOK Module 34
CB1FSPAR Prepare Reclaim Initiation
CB2FSPAR CB1SPDTComp
CB1F3PAR CB1SPFTComp
CB2F3PAR CB13PDTComp
CB1LFRC CB13 PFTComp
CB2LFRC CB2SPDTComp
CB2SPFTComp
Any Trip Set CB1 Close
CB23PDTComp
CB1 AR Lockout Auto Close CB1 CB23 PFTComp
CB1 Healthy CB1 Control
CB1 Open 3 ph Set CB2 Close Dynamic F/L 1P Reclaim TComp
CB1L SCOK Auto Close CB2 Close Pulse Time 1P Reclaim Time
CB1 Fast SCOK CB2 Control SPAR ReclaimTime 3 P Reclaim TComp
OK Time 3P 3PAR ReclaimTime 3P Reclaim Time
CB1F SCOK Auto Close CB1 CBARCancel

ARIP Auto Close CB2
CB1 ARIP 1P Reclaim Time
CB1 Closed 3 ph 3P Reclaim Time
CB2 AR Lockout CB1 Closed 3 ph
CB2 Healthy CB2 Closed 3 ph
CB2 Open 3 ph CB1 ARIP
CB2L SCOK CB2 ARIP Module 35
CB2 Fast SCOK Reclaim Time
SetCB 1SPCl
CB2F SCOK SetCB 2SPCl
CB2 ARIP
Module 32 & 33 SetCB13 PCl
CB2 Closed 3 ph CB Autoclose
SetCB23 PCl
CB1SPDTComp CB1 FARIP
CB1OP1P CB2 FARIP
CB1L3 PAR CB1LARIP
CB13 PDTComp CB2LARIP
CB1FSPAR CB1LFRC
CB1SPFTComp CB2LFRC
CB1F3PAR LeaderSPAR
CB13 PFTComp ProtRe_Op
ProtRe_ Op
CB2SPDTComp
CB2OP1P
CB2L3 PAR
CB23 PDTComp
CB2FSPAR
CB2SPFTComp
CB2F3PAR
CB23 PFTComp
V03393-5
P841B-TM-EN-1.1 111
1P Reclaim TComp CB1 Succ 1P AR CB Healthy Time AR CB1 Unhealthy

3P Reclaim TComp CB1 Succ 3P AR Check Sync Time AR CB1 No C/S
CB1 Closed 3 ph CB2 Succ 1P AR OK Time 3P AR CB2 Unhealthy
CB2 Closed 3 ph CB2 Succ 3P AR CB1 Fast SCOK AR CB2 No C/S
SetCB1SPCl CB1 ARSucc CB1 Healthy

SetCB13 PCl CB2 ARSucc CB1 AR Lockout
CB1OP1P Module 36 CB1 Closed 3 ph
Successful AR Signals
CB1OP2/3 P CB1L SCOK
ResCB1ARSucc CB1F SCOK
SetCB2SPCl CB2 Fast SCOK
SetCB23 PCl CB2 Healthy
CB2OP1P CB2 AR Lockout
Module 39 & 40
CB2OP2/3 P CB2 Closed 3 ph CB Healthy and System Check
Timers
ResCB2ARSucc CB2L SCOK
CB2F SCOK
Res AROK by UI ResCB1ARSucc
Reset AROK Ind ResCB2ARSucc CB1 L3PAR
Res AROK by NoAR CB1SPDTComp
Res AROK by Ext CB1SPFTComp
Res AROK by Tdly CB13PDTComp
AROK Reset Time CB13 PFTComp
Num CBs CB2 L3PAR

Module 37 & 38 CB2SPDTComp
AR Start
AR Reset Successful CB2SPFTComp
Ext Rst CB1 AROK
CB23PDTComp
Ext Rst CB2 AROK
CB23 PFTComp
CB1OPAny
CB Control by Control TripCB1
CB2OPAny
Trip Pulse Time CB1 Trip Fail
CB1ARSucc
CB2ARSucc Man Close Delay CB1 Close inProg
ARDisabled Close Pulse Time Control CloseCB1

CB Healthy Time CB1 Close Fail
Reset CB Shots CB1 Total Shots Counter Check Sync Time ManCB1 Unhealthy
Set CB1 Close CB1 Successful SPAR HMI Trip NoCS CB1ManClose
CB1 Succ 1P AR Shot 1 Counter
HMI Close
CB1 Successful 3PAR
CB1 Succ 3P AR Shot 1 Counter Init Trip CB1
Seq Counter= 1 CB1 Successful 3PAR Init close CB1
Seq Counter= 2 Shot 2 Counter
CB1 Successful 3PAR CB1 Arip
Seq Counter= 3
Shot 3 Counter Auto Close CB1
Seq Counter= 4 CB1 Successful 3PAR
Shot 4 Counter Rst CB1 CloseDly
CB1 Arip
Any Trip
CB1 AR Lockout CB1 Failed Counter Module 43
Module 41 & 42 Control TripCB1 CB Control (CB1)
Ext Rst CB1Shots AR Shot Counters
CB2 Total Shots Counter CB1 Ext Trip3Ph
CB2 Arip
CB2 Successful SPAR CB1 Ext Trip A
CB2 AR Lockout Shot 1 Counter CB1 Ext Trip B
Ext Rst CB2Shots CB2 Successful 3PAR CB1 Ext Trip C
Set CB2 Close Shot 1 Counter
CB2 Successful 3PAR CB1 Open 3 ph
CB2 Succ 1P AR
Shot 2 Counter CB1 Open A ph
CB2 Succ 3P AR CB2 Successful 3PAR
CB1 Open B ph
Shot 3 Counter
CB2 Successful 3PAR CB1 Open C ph
Shot 4 Counter CB1 Closed 3 ph
CB2 Failed Counter CB1 Closed A ph
CB1 Closed B ph
CB1 Closed C ph
CB1 Healthy
V03393-6 CB1 Man SCOK
112 P841B-TM-EN-1.1
CB Control by Control TripCB2 CB2L SC ClsNoDly CB2 Fast SCOK

Trip Pulse Time CB2 Trip Fail CB2L SC CS1 CB2L SCOK
Man Close Delay CB2 Close inProg CB2L SC CS2
Close Pulse Time Control CloseCB2 CB2L SC DLLB
CB Healthy Time CB2 Close Fail CB2L SC LLDB
Check Sync Time ManCB2 Unhealthy CB2L SC DLDB
HMI Trip NoCS CB2ManClose CB2L SC Shot 1
HMI Close CB2L SC all

Module 46
CB2 CS1 OK 3 Phase AR System Check
Init Trip CB2 Leader(CB2)
Init close CB2 CB2 CS2 OK
CB2 ARIP Dead Line
Auto Close CB2 Live Bus 2
Rst CB2 CloseDly Live Line
Any Trip Dead Bus 2

Module 44
Control TripCB2 Dead Line
CB Control (CB2)
CB2 Ext Trip 3Ph Seq Counter= 1
CB2 Ext Trip A CB2 Ext CS OK
CB2 Ext Trip B CB1 Fast SCOK

CB2 Ext Trip C CB1F SC CS1 CB1F SCOK
CB2 Open 3 ph CB1F SC CS2
CB2 Open A ph CB1F SC DLLB
CB2 Open B ph CB1F SC LLDB
CB2 Open C ph CB1F SC DLDB
CB2 Closed 3 ph CB1F SC Shot 1
CB2 Closed A ph CB1F SC all Module 47
CB2 Closed B ph 3 Phase AR System Check
CB1 CS1 OK Follower (CB1)
CB2 Closed C ph
CB1 CS2 OK
CB2 Healthy
Live Bus 1
CB2 Man SCOK
Live Line
CB1L SC ClsNoDly CB1 Fast SCOK Dead Bus 1
CB1L SC CS1 CB1L SCOK Dead Line
CB1L SC CS2 Seq Counter= 1
CB1L SC DLLB CB1 Ext CS OK
CB1L SC LLDB
CB2 Fast SCOK
CB1L SC DLDB
CB2F SC CS1 CB2F SCOK
CB1L SC Shot 1
CB2F SC CS2
CB1L SC all Module 45
3 Phase AR System Check CB2F SC DLLB
CB1 CS1 OK Leader( CB1)
CB2F SC LLDB
CB1 CS2 OK CB2F SC DLDB
Live Bus 1 CB2F SC Shot 1
Live Line CB2F SC all Module 48
Dead Bus1 3 Phase AR System Check
CB2 CS1 OK Follower (CB2)
Dead Line
CB2 CS2 OK
Seq Counter= 1
Live Bus 2
CB1 Ext CS OK
Live Line
Dead Bus 2
Dead Line
Seq Counter= 1
V03393-7 CB2 Ext CS OK
P841B-TM-EN-1.1 113
CB1M SC CS1 CB1 Man SCOK Multi Phase AR CB1 AR Lockout

CB1M SC CS2 CB2 Man SCOK BF if LFail Cls BARCB1
CB1M SC DLLB Num CBs
CB1M SC LLDB Trip Pulse Time
CB1M SC DLDB CB1 Close Fail
CB1M SC required CB2 AR Lockout
CB2M SC CS1 CB1 Fail Pr Trip
CB2M SC CS2 CB2 Fail Pr Trip
CB2M SC DLLB Block CB1 AR
CB2M SC LLDB AR CB1 Unhealthy
CB2M SC DLDB AR In Service
CB2M SC required AR CB1 No C/S
Module 51 & 52
CB Manual Close System Check
CB1 CS1 OK Evolve 3Ph
CB1 CS2 OK CB1 In Service
CB2 CS1 OK CB2 In Service
CB2 CS2 OK Seq Counter>Set
Live Bus 1 CB1 Status Alm
Live Bus 2 Set CB1 Close
Live Line Set CB2 Close
Dead Bus1 CB1 AR Init
Dead Bus2 CB1 ARIP Module 55
Autoreclose Lockout
Dead Line FltMem2 P (CB1)
CB1 Ext CS OK FltMem3 P
CB2 Ext CS OK CB2LFRC
Trip Pulse Time CB1 Fail Pr Trip CB1 FARIP
CB2 Fail Pr Trip CB1 OPAny

CB1 Open 3 ph
ProtRe_Op
CB1 Closed 3 ph
LastShot
CB2 Open 3 ph
EvolveLock
CB2 Closed 3 ph Module 53 & 54
CB Trip Time Monitor ProtARBlock
TARA TMEM1Ph
TARB TMEM2/3Ph
TARC CB1L3 PAROK
TAR2 /3Ph CB1F3PAROK
TMEM2/3 Ph CB1LSPAROK
CB1 FSPAROK
CB1LARIP
CB1 FARIP
CB2 OPAny
Invalid_ AR_Mode
DeadLineLockout
V03393-8 ResCB1Lo
114 P841B-TM-EN-1.1
Multi Phase AR CB2 AR Lockout Res LO by CB IS ResCB1Lo

BF if LFail Cls BARCB2 Res LO by UI ResCB2Lo
Num CBs Reset CB1 LO
Trip Pulse Time Reset CB2 LO
CB2 Close Fail Res LO by NoAR
CB1 AR Lockout Res LO by ExtDDB
CB1 Fail Pr Trip Res LO by TDelay
CB2 Fail Pr Trip LO Reset Time

Module 57 & 58
Block CB2 AR Num CBs Reset CB Lockout
AR CB2 Unhealthy Rst CB1 Lockout

AR In Service Rst CB2 Lockout
AR CB2 No C/S CB1 AR Lockout
Evolve 3Ph CB2 AR Lockout
CB1 In Service CB1CRLo
CB2 In Service CB2CRLo
Seq Counter>Set ARDisabled
CB2 Status Alm
Set CB1 Close System Checks Live Line
Set CB2 Close VAN Dead line

VBN Live Bus 1
CB2 AR Init
VCN Dead Bus 1
CB2 ARIP Module 56
Autoreclose Lockout VAB
VBC Live Bus 2
FltMem2P (CB2)
VCA Dead Bus 2
FltMem3P VBus
CB2LFRC MCB/VTS Module 59
CB2FARIP MCB/VTS CB1 CS System Checks Voltage Monitor
CB2OPAny MCB/VTS CB2 CS
ProtRe_ Op Inhibit LL
LastShot Inhibit DL
EvolveLock Inhibit LB1
ProtARBlock Inhibit LB2
TMEM1 Ph Inhibit DB1
TMEM2/3 Ph Inhibit DB2
CB2 L3PAROK
CB2F3PAROK
CB2LSPAROK
CB2FSPAROK
CB2LARIP
CB2FARIP
CB2OPAny
Invalid_AR_Mode
DeadLineLockout
ResCB2Lo
V03393-9
P841B-TM-EN-1.1 115
Sys checks CB1 SChksInactiveCB1 CB1 AR Lockout Pole Discrep CB1

CB1 CS1 Status CB1 CS1 SlipF > CB2 AR Lockout Pole Discrep CB2
CB1 CS2 Status CB1 CS1 SlipF < CB1 LO Alarm
VAN CB1 CS2 SlipF > CB2 LO Alarm
VBN CB1 CS2 SlipF < Pol Disc CB1 Ext
VCN
CS Vline> Pol Disc CB2 Ext
VAB
VAB
VBC CS Vbus> CB1 AR 1p InProg Module 62
VCA CS Vline< CB2 AR 1p InProg Pole Discrepancy
VBus
VBus1 CS Vbus< CB1 Open A ph
MCB/VTS CB1 CS CB1 CS1 Vl>Vb CB1 Open B ph
MCB/VTS CB1 CS1 Vl<Vb CB1 Open C ph
VTS Fast Block CB1 CS1 Fl>Fb CB2 Open A ph
Module 60
F out of Range Check Sync Signals CB1 CS1 Fl<Fb CB2 Open B ph
CB1 CS1 Enabled (CB1)
CB1 CS1 AngHigh+ CB2 Open C ph
CB1 CS2 Enabled CB1 CS1 AngHigh-
CB1Tripping Mode CB1 Trip OutputA
CB1 CS2 Fl>Fb
CB2Tripping Mode CB1 Trip OutputB
CB1 CS2 Fl<Fb
Trip Inputs A CB1 Trip OutputC
CB1 CS2 AngHigh+
Trip Inputs B CB2 Trip OutputA
CB1 CS2 AngHigh-
Trip Inputs C CB2 Trip OutputB
CB1 CS AngRotACW
AR Force CB1 3P CB2 Trip OutputC
CB1 CS AngRotCW
AR Force CB2 3P Module 63 CB1 Trip 3ph
CB1 CS2 Vl>Vb
CB Trip Conversion CB2 Trip 3ph
CB1 CS2 Vl<Vb Force 3PTrip CB1
Force 3PTrip CB2 Any Trip
CB1 CS1 OK
CB1 Trip I/P 3Ph 2/3 Ph Fault
CB1 CS2 OK
CB2 Trip I/P 3Ph 3 Ph Fault
Sys checks CB2 SChksInactiveCB2 Pole Dead A
CB2 CS1 Status CB2 CS1 SlipF > Pole Dead B
CB2 CS2 Status CB2 CS1 SlipF < Pole Dead C
VAN
VAN CB2 CS2 SlipF >
VBN CB2 CS2 SlipF <
VCN
CS Vbus2>
VAB
VBC CS Vbus2<
VCA CB2 CS1 Vl>Vb
VBus1
VBus CB2 CS1 Vl<Vb
MCB/VTS CB2 CS CB2 CS1 Fl>Fb
MCB/VTS CB2 CS1 Fl<Fb
Module 61
VTS Fast Block Check Sync Signals CB2 CS1 AngHigh+
F out of Range (CB2 ) CB2 CS1 AngHigh-
CB2 CS1 Enabled CB2 CS2 Fl>Fb
CB2 CS2 Enabled CB2 CS2 Fl<Fb
CB2 CS2 AngHigh+
CB2 CS2 AngHigh-
CB2 CS AngRotACW
CB2 CS AngRotCW
CB2 CS2 Vl>Vb
CB2 CS2 Vl<Vb
CB2 CS1 OK
V03393-10 CB2 CS2 OK
4.2 AUTORECLOSE INTERNAL SIGNALS

The following table lists all the internal signals used in the CB control and Autoreclose logic system:
Signal Name Source Destination Description
3PDTCOMP 3-phase AR Dead Time (25) 3-phase AR Dead Time (25) Three phase dead time complete
Reset CB Lockout (57)
Force 3-phase Trip (10)
ARDisabled AR Enable (5) Overall autoreclosing disabled
CB1-pole / 3-pole trip (13)
AR Reset Successful (37)
BARCB1 Autoreclose Lockout (55) Leader/Follower (7) Block Autoreclose for CB1
116 P841B-TM-EN-1.1

BARCB2 Autoreclose Lockout (55) Leader/Follower (7) Block Autoreclose for CB2
CB Autoclose (32)
Three-pole Autoreclose dead time is
CB13PDTComp 3-phase AR Dead Time (25) Prepare Reclaim Initiation (34)
complete for CB1
CB Healthy and System Check Timers (39)
CB Autoclose (32)
Follower 3-phase CB AR Three-pole Autoreclose follower time is
CB13PFTComp Prepare Reclaim Initiation (34)
Time (29) complete for CB1
CB1ARSucc Successful AR Signals (36) Autoreclose successful for CB1
CB1 AR In Progress (16)
Autoreclose Lockout (55) Autoreclose in progress for CB1 acting as
CB1FARIP CB1 AR In Progress (16)
Reclaim Time (35) follower
Autoreclose Lockout (55) Autoreclose in progress for CB1 acting as
CB1LARIP CB1 AR In Progress (16)
Reclaim Time (35) leader
Dead Time Start Enable (22)
Follower 1-phase CB AR Time (28)
CB1OP1P CB Open (3) CB1 is open on 1 phase
CB Autoclose (32)
Successful AR Signals (36)
3-phase AR cycle selection (21)
CB1OP2/3P CB Open (3) CB1 is open on 2 or 3 phases
CB1OPAny CB Open (3) Autoreclose Lockout (55) CB1 is open on 1, 2 or 3 phases
CB1 is OK for single-phase autoreclosure
CB1SPOK
(either as leader or follower)
CB1CRLo CB In Service (4) Reset CB Lockout (57) Reset CB1 lockout
3-phase AR cycle selection Follower 3-phase CB AR Time (29) Three-phase Autoreclose is active for CB1
CB1F3PAR
(21) CB Autoclose (32) as follower
CB1 is OK to perform three-phase
CB1F3PAROK AR Modes Enable (9) 3-phase AR cycle selection (21)
Autoreclose as follower
Autoreclose Lockout (55)
Follower CB AR Enable (27
1-phase AR Cycle Selection Follower 1-phase CB AR Time (28) Single-phase Autoreclose is in progress for
CB1FSPAR
(19) Follower 3-phase CB AR Time (29) CB1 as follower
CB Autoclose (32)
Force 3-phase Trip (10), 1-phase AR Cycle
Selection (19) CB1 is OK to perform single-phase
CB1FSPAROK AR Modes Enable (9)
3-phase AR cycle selection (21) Autoreclose as follower
1-phase AR Cycle Selection (19)
3-phase AR cycle selection 3-phase AR Dead Time (25) Three-phase Autoreclose is active for CB1
CB1L3PAR
(21) CB Autoclose (32) (CB1 as leader)
CB1 is OK to perform three-phase
CB1L3PAROK AR Modes Enable (9) 3-phase AR cycle selection (21),
Autoreclose (as leader)
Leader/Follower
Logic 1 & 2 (7)
Leader/Follower
CB1LFRC Follower 1-phase CB AR Time (28) CB1 failed to reclose (as leader)
Logic 1 & 2 (7)
Reclaim Time (35)
P841B-TM-EN-1.1 117

1-phase AR Cycle Selection 1-phase AR Cycle Selection (19) Single-phase Autoreclose is in progress for
CB1LSPAR
(19) 1-phase AR Dead Time (24) CB1 (as leader)
AR Modes Enable (9), Force 3-phase Trip
(10)
CB1 is OK to perform single-phase
CB1LSPAROK AR Modes Enable (9) 1-phase AR Cycle Selection (19)
Autoreclose (as leader)
1-phase AR Dead Time (24)
CB Autoclose (32)
CB1SPDTComp 1-phase AR Dead Time (24) CB1 single-phase dead time is complete
Prepare Reclaim Initiation (34)
CB Autoclose (32), Prepare Reclaim
Follower 1-phase CB AR
CB1SPFTComp Initiation (34) CB1 single-phase follower time is complete
Time (28)
CB2 three-phase Autoreclose dead time is
CB23PDTComp 3-phase AR Dead Time (25)
complete
Follower 3-phase CB AR CB2 three-phase Autoreclose time is
CB23PFTComp
Time (29) complete
CB2 is OK for three-phase Autoreclose as
CB23POK
leader or follower
CB2ARSucc CB2 AR In Progress (17) Autoreclose successful for CB2
Autoreclose is in progress for CB2 as
CB2FARIP CB2 AR In Progress (17) 3-phase AR cycle selection (21)
follower
Reclaim Time (35)
CB2LARIP CB2 AR In Progress (17) 3-phase AR cycle selection (21) Autoreclose is in progress for CB2 as leader
Reclaim Time (35)
CB2OP1P CB Open (3) CB2 is open on 1 phase
CB2OP2/3P CB Open (3) CB2 is open on 2 or 3 phases
CB2OpAny CB Open (3) Dead Time Start Enable (22) CB2 is open on 1, 2 or 3 phases
CB2 is OK for single-phase Autoreclose as
CB2SPOK
leader or follower
A 2-phase or 3-phase trip has initiated
CB2TAR2/3Ph CB2 1-pole / 3-pole trip (14)
Autoreclose for CB2
An A-phase trip has initiated Autoreclose
CB2TARA CB2 1-pole / 3-pole trip (14) CB1-pole / 3-pole trip (13)
for CB2
A B-phase trip has initiated Autoreclose for
CB2TARB CB2 1-pole / 3-pole trip (14) CB1-pole / 3-pole trip (13)
CB2
A C-phase trip has initiated Autoreclose for
CB2TARC CB2 1-pole / 3-pole trip (14) CB1-pole / 3-pole trip (13)
CB2
1-phase AR Cycle Selection (19) A single-phase trip initiated Autoreclose for
CB2TMEM1Ph CB2 1-pole / 3-pole trip (14)
CB2 AR In Progress (17) CB2
A 2-phase or 3-phase trip initiated
CB2TMEM2/3Ph CB2 1-pole / 3-pole trip (14) CB2 AR In Progress (17)
Autoreclose for CB2
CB2TMEM3Ph CB2 1-pole / 3-pole trip (14) A 3-phase trip initiated Autoreclose for CB2
118 P841B-TM-EN-1.1

CB2CRLo CB In Service (4) Reset lockout for CB2
Three-phase Autoreclose is in progress for
CB2F3PAR Follower CB AR Enable (27)
CB2 as a follower
CB2 AR In Progress (17) CB2 is OK to perform three-phase
CB2F3PAROK AR Modes Enable (9)
3-phase AR cycle selection (21) Autoreclose as follower
Follower CB AR Enable (27)
1-phase AR Cycle Selection Single-phase Autoreclose is in progress for
CB2FSPAR Follower 1-phase CB AR Time (28)
(19) CB2 as follower
CB2FSPAROK AR Modes Enable (9) 1-phase AR Cycle Selection (19)
Autoreclose as follower
3-phase AR cycle selection Three-phase Autoreclose is in progress for
CB2L3PAR 1-phase AR Cycle Selection (19)
(21) CB2 as leader
CB2 AR In Progress (17) CB2 is OK to perform three-phase
CB2L3PAROK AR Modes Enable (9)
3-phase AR cycle selection (21) Autoreclose as leader
Leader/Follower (7)
Leader/Follower
CB2LFRC Follower 3-phase CB AR Time (29) CB2 failed to reclose as leader
Logic 1 & 2 (7)
Reclaim Time (35)
AR Modes Enable (9)
1-phase AR Cycle Selection Single-phase Autoreclose is in progress for
CB2LSPAR 1-phase AR Cycle Selection (19)
(19) CB2 as leader
AR Modes Enable (9)
CB2LSPAROK AR Modes Enable (9) 1-phase AR Cycle Selection (19)
Autoreclose as leader
CB2SPDTComp 1-phase AR Dead Time (24) CB2 single-phase dead time is complete
Follower 1-phase CB AR
CB2SPFTComp CB2 single-phase follower time is complete
Time (28)
Signal to force the auto-reclose sequence
DeadLineLockout Dead Time Start Enable (22) Autoreclose Lockout (55)
to lockout
Enable dead time for three-phase
ENABLE CB13PDT
Autoreclose for CB1
Enable dead time for single-phase
ENABLE CB1SPDT
Autoreclose for CB1
Enable dead time for three-phase
ENABLE CB23PDT
Autoreclose for CB2
Enable dead time for single-phase
ENABLE CB2SPDT
Autoreclose for CB2
Lockout for 2nd trip after the "Discrim
EvolveLock Evolving Fault (20) Autoreclose Lockout (55)
Time" has expired
Signal from the frequency tracking logic
F Out of Range Check Sync Signals (60) indicating that the measured power system
frequency is outside the operational range
A signal to indicate that the initiating fault
FltMem2P Fault Memory (15) Autoreclose Lockout (55)
involved 2 phases
A signal to indicate that the initiating fault
FltMem3P Fault Memory (15) Autoreclose Lockout (55)
involved 3 phases
Leader/Follower (7) The follower circuit breaker is Ok for three-
Foll3PAROK AR Modes Enable (9)
AR Modes Enable (9) phase Autoreclose
P841B-TM-EN-1.1 119

The follower circuit breaker is Ok for single-
FollSPAROK AR Modes Enable (9) Leader/Follower (7)
phase Autoreclose
AR Initiation (11)
CB1-pole / 3-pole trip (13)
Internally derived signal to initiate
InitAR AR Initiation (11) CB2 1-pole / 3-pole trip (14)
Autoreclose (external triggers not included)
An invalid state is being indicated by the
Invalid_AR_Mode AR Modes Enable (9) Autoreclose Lockout (55) logic that uses opto-inputs to determine
the Autoreclose mode.
Evolving Fault (20) Idicates tha the Autoreclose sequence has
LastShot Sequence Counter (18)
Autoreclose Lockout (55) reached the last shot
The dead time for single pole Autoreclose is
OKTimeSP 1-phase AR Dead Time (24) Dead Time Start Enable (22)
OK
Leader/Follower CB
PrefLCB1 Leader/Follower (7) CB1 is the preferred leader
Selection (6)
Leader/Follower CB
PrefLCB2 Leader/Follower (7) CB2 is the preferred leader
Selection (6)
Signal to block Autoreclose for selected
ProtARBlock AR Initiation (11) Autoreclose Lockout (55)
host protection elements
Sequence Counter (18) Signal to indicate that further protection
ProtRe_Op Evolving Fault (20)
1-phase AR Cycle Selection (19) operation has occurred during Autoreclose
Evolving Fault (20)
Successful AR Signals (36) Reset the indication of successful
ResCB1ARSucc Successful AR Signals (36)
AR Reset Successful (37) Autoreclose for CB1
ResCB1Lo Reset CB Lockout (57) Autoreclose Lockout (55) Reset the indication of lockout for CB1
Reset the indication of successful
ResCB2ARSucc
Autoreclose for CB2
ResCB2Lo Reset the indication of lockout for CB2
Leader/Follower (7) Used to reset the allocation of leader/
ResetL-F Evolving Fault (20)
1-phase AR Cycle Selection (19) follower functionality
CB2 1-pole / 3-pole trip (14) Reset the signal that indicates the faulted
ResPRMem CB1-pole / 3-pole trip (13)
Fault Memory (15) phases that initiated the Autoreclose
SCIncrement Sequence Counter (18) Increment the sequence counter
SCCountoveqShots Sequence counter has exceeded setting
Leader/Follower
SetLCB1 Leader/Follower (7) CB1 has been selected as leader
Logic 1 & 2 (7)
Leader/Follower
SetLCB2 Leader/Follower (7) CB2 has been selected as leader
Logic 1 & 2 (7)
Prepare Reclaim Initiation Reclaim Time (35)
SetCB13PCl Three-phase close command to CB1
(34) Successful AR Signals (36)
Prepare Reclaim Initiation Reclaim Time (35)
SetCB1SPCl Single-phase close command to CB1
(34) Successful AR Signals (36)
SetCB23PCl Reclaim Time (35) Three-phase close command to CB2
SetCB2SPCl Reclaim Time (35) Single-phase close command to CB2
SPDTComp Single-phase dead time complete
CB1-pole / 3-pole trip (13), A 2-phase or 3-phase trip has initiated
TAR2/3Ph CB Trip Time Monitor (53)
CB2 1-pole / 3-pole trip (14) Autoreclose for CB1 (as leader)
120 P841B-TM-EN-1.1

TARA CB1-pole / 3-pole trip (13) CB Trip Time Monitor (53) An A-phase trip has initiated Autoreclose
TARAny CB1-pole / 3-pole trip (13) CB1-pole / 3-pole trip (13) Any trip has initiated Autoreclose
Evolving Fault (20)
TARB CB1-pole / 3-pole trip (13) CB Trip Time Monitor (53) A B-phase trip has initiated Autoreclose
TARC CB1-pole / 3-pole trip (13) CB Trip Time Monitor (53) A C-phase trip has initiated Autoreclose
Signal to remember that Autoreclose was
TMEM1Ph CB1-pole / 3-pole trip (13) CB1 AR In Progress (16)
initiated by a single-phase fault
CB Trip Time Monitor (53) Signal to remember that Autoreclose was
TMEM2/3Ph CB1-pole / 3-pole trip (13) Autoreclose Lockout (55) initiated by a 2-phase fault or a 3-phase
CB1 AR In Progress (16) fault
Signal to remember that Autoreclose was
TMEM3Ph CB1-pole / 3-pole trip (13)
initiated by a 3-phase fault
Evolving Fault (20) Signal to remember that Autoreclose was
TMemAny CB1-pole / 3-pole trip (13)
3-phase AR cycle selection (21) initiated by an AnyTrip
4.3 AUTORECLOSE DDB SIGNALS

The following table lists all the DDB signals used in the CB control and Autoreclose logic system:
DDB Signal Name DDB Signal Number Source Module (Module Number) Destination Module (Module Number.)
Sequence Counter (18)
1P DTime 1554 1-phase AR Dead Time (24)
Evolving Fault (20)
1P Follower Time 1446 Follower 1-phase CB AR Time (28)
1P Reclaim TComp 1568 Reclaim Time (35) Successful AR Signals (36)
1P Reclaim Time 1567 Reclaim Time (35) Reclaim Time (35)
1PF TComp 1561 Follower 1-phase CB AR Time (28) Follower 1-phase CB AR Time (28)
2/3 Ph Fault 527 CB Trip Conversion (63)
3 Ph Fault 528 CB Trip Conversion (63)
3P Dead Time IP 853 3-phase AR Dead Time (25)
3P DTime1 1556 3-phase AR Dead Time (25)
3P Follower Time 1447 Follower 3-phase CB AR Time (29)
3P Reclaim TComp 1570 Reclaim Time (35) Successful AR Signals (36)
3P Reclaim Time 1569 Reclaim Time (35) Reclaim Time (35)
3PF TComp 1562 Follower 3-phase CB AR Time (29) Follower 1-phase CB AR Time (29)
AR Initiation (11)
CB1 Autoclose (32)
Any Trip 522 CB Trip Conversion (63) CB2 Autoclose (33)
CB Control (43)
CB2 Control (44)
AR CB1 No C/S 308 CB Healthy and System Check Timers (39) Autoreclose Lockout (55)
AR CB1 Unhealthy 307 CB Healthy and System Check Timers (39) Autoreclose Lockout (55)
Leader Follower Logic (7)
P841B-TM-EN-1.1 121
AR CB2 No C/S 330 CB2 Healthy and System Check Timers (40) CB2 Autoreclose Lockout (56)
AR CB2 Unhealthy 329 CB2 Healthy and System Check Timers (40) CB2 Autoreclose Lockout (56)
AR Enable 1384 AR Enable (5)
AR Enable (5)
AR Enable CB1 1609
AR Modes Enable (9)
AR Enable (5)
AR OK (8)
AR Enable CB2 1605
AR Modes Enable (9)
AR Force CB1 3P 858 Force 3-phase Trip (10) CB Trip Conversion (63)
AR Force CB2 3P 1485 Force 3-phase Trip (10) CB Trip Conversion (63)
AR Modes Enable (9)
AR In Service 1385 AR Enable (5)
CB2 Autoreclose Lockout (56)
AR Mode 1P 1497 AR Modes Enable (9)
AR Mode 3P 1498 AR Modes Enable (9)
AR OFF Pulse 1383 AR Enable (5)
AR On Pulse 1382 AR Enable (5)
Fault Memory (15)
AR Start 1541 CB1 AR In Progress (16)
CB2 AR Reset Successful (38)
AR Trip Test 3ph 576 Trip Test (12)
AR Trip Test A 577 Trip Test (12) AR Initiation (11)
AR Trip Test B 578 Trip Test (12) AR Initiation (11)
AR Trip Test C 579 Trip Test (12) AR Initiation (11)
1-phase AR Cycle Selection (19),
1-pole / 3-pole trip (13)
ARIP 1542 CB1 AR In Progress (16) Dead Time Start Enable (22)
CB1 Autoclose (32)
CB2 Autoclose (33)
Reclaim Time (35)
Auto Close CB1 854 CB1 Autoclose (32)
CB Control (43)
122 P841B-TM-EN-1.1
Reclaim Time (35)
Auto Close CB2 1448 CB2 Autoclose (33)
CB2 Control (44)
Block CB1 AR 448 Autoreclose Lockout (55)
Block CB2 AR 1421 CB2 Autoreclose Lockout (56)
CB1 3P Dtime 1560 3-phase AR Dead Time (25)
CB1 AR 1p InProg 845 1-phase AR Cycle Selection (19),
Pole Discrepancy (62)
CB1 AR 3p InProg 844 3-phase AR Cycle Selection (21)
CB1 AR Init 1543 CB1 AR In Progress (16) Dead Time Start Enable (22)
CB In Service (4)
Evolving Fault (20)
CB1 Autoclose (32)
CB1 AR Lockout 306 Autoreclose Lockout (55)
AR Shot Counters (41)
Reset CB Lockout (57)
CB In Service (4)
Evolving Fault (20)
CB1 Autoclose (32)
CB1 ARIP 1544 CB1 AR In Progress (16)
Reclaim Time (35)
CB Control (43)
CB1Aux 3ph(52-A) 420 CB1 State Monitor (1)
CB1Aux 3ph(52-B) 424 CB1 State Monitor (1)
CB1Aux A(52-A) 421 CB1 State Monitor (1)
CB1Aux A(52-B) 425 CB1 State Monitor (1)
CB1Aux B(52-A) 422 CB1 State Monitor (1)
CB1Aux B(52-B) 426 CB1 State Monitor (1)
CB1Aux C(52-A) 423 CB1 State Monitor (1)
CB1Aux C(52-B) 427 CB1 State Monitor (1)
CB1 Close Fail 303 CB Control (43) Leader Follower Logic (7)
CB1 Close inProg 842 CB Control (43)
P841B-TM-EN-1.1 123
CB In Service (4)
CB1 Autoclose (32)
Evolving Fault (20)
CB1 Closed 3 ph 907 CB State Monitor (1)
Reclaim Time (35)
CB Control (43)
CB Trip Time Monitor (53)
CB1 Closed A ph 908 CB State Monitor (1) CB Control (43)
CB1 Closed B ph 909 CB State Monitor (1) CB Control (43)
CB1 Closed C ph 910 CB State Monitor (1) CB Control (43)
CB1 Control 1566 CB1 Autoclose (32)
CB1 CS AngRotACW 1594 Check Sync Signals (60)
CB1 CS AngRotCW 1595 Check Sync Signals (60)
CB1 CS1 AngHigh- 1593 Check Sync Signals (60)
CB1 CS1 AngHigh+ 1592 Check Sync Signals (60)
CB1 CS1 Enabled 881 Check Sync Signals (60)
CB1 CS1 FL>FB 1590 Check Sync Signals (60)
3 Phase AR System Check (45)
CB1 CS1 OK 883 Check Sync Signals (60)
CB Manual Close System Check (51)
CB1 CS1 SlipF< 1579 Check Sync Signals (60)
CB1 CS1 SlipF> 1578 Check Sync Signals (60)
CB1 CS1 VL<VB 1588 Check Sync Signals (60)
CB1 CS1 VL>VB 1586 Check Sync Signals (60)
CB1 CS2 AngHigh- 1496 Check Sync Signals (60)
CB1 CS2 AngHigh+ 1495 Check Sync Signals (60)
CB1 CS2 Enabled 882 Check Sync Signals (60)
CB1 CS2 FL<FB 1494 Check Sync Signals (60)
CB1 CS2 FL>FB 1493 Check Sync Signals (60)
CB1 CS2 OK 884 Check Sync Signals (60)
CB1 CS2 SlipF< 1465 Check Sync Signals (60)
CB1 CS2 SlipF> 1464 Check Sync Signals (60)
CB1 CS2 VL<VB 1589 Check Sync Signals (60)
CB1 CS2 VL>VB 1587 Check Sync Signals (60)
CB1 Ext CS OK 900
CB1 1-pole / 3-pole trip (13),
CB1 Ext Trip A 535 CB1 AR In Progress (16),
CB Control (43)
CB1 Ext Trip B 536 CB1 AR In Progress (16),
CB Control (43)
124 P841B-TM-EN-1.1
CB1 Ext Trip C 537 CB1 AR In Progress (16),
CB Control (43)
CB1 Ext Trip3ph 534 CB1 AR In Progress (16),
CB Control (43)
CB1 Fail Pr Trip 1575 CB Trip Time Monitor (53)
CB1 Failed AR 1550 Evolving Fault (20)
CB1 Autoclose (32)
3 Phase AR System Check Leader (45)
CB1 Fast SCOK 1572 Prepare Reclaim Initiation (34)
3 Phase AR System Check Follower (47)
CB1 Autoclose (32)
CB1 Healthy 436 CB Healthy and System Check Timers (39)
CB Control (43)
CB1 In Service 1526 CB In Service (4)
CB1 LO Alarm 860
CB1 Man SCOK 1574 Manual Close System Check (51) CB Control (43)
Leader Follower Logic (8) CB1 AR In Progress (16)
CB1 NoAR 1528
Leader Follower Logic (7) Leader Follower Logic (7)
CB Open (3)
CB1 Open 3 ph 903 CB State Monitor (1)
CB1 Autoclose (32)
CB Control (43)
CB Trip Time Monitor (53)
CB Open (3)
CB1 Open A ph 904 CB State Monitor (1) CB Control (43)
Pole Discrepancy
CB Open (3)
CB1 Open B ph 905 CB State Monitor (1) CB Control (43)
CB Open (3)
CB1 Open C ph 906 CB State Monitor (1) CB Control (43)
CB1 Status Alarm 301 CB State Monitor (1) Autoreclose Lockout (55)
CB1 Succ 1P AR 1571 Successful AR Signals (36) AR Shot Counters (41)
CB1 Succ 3P AR 852 Successful AR Signals (36) AR Shot Counters (41)
CB1 Trip 3ph 526 CB Trip Conversion (63)
CB1 Trip AR MemA 1535 CB1 1-pole / 3-pole Trip (13) CB1 1-pole / 3-pole Trip (13)
CB1 Trip AR MemB 1536 CB1 1-pole / 3-pole Trip (13) CB1 1-pole / 3-pole Trip (13)
CB1 Trip AR MemC 1537 CB1 1-pole / 3-pole Trip (13) CB1 1-pole / 3-pole Trip (13)
CB1 Trip Fail 302 CB Control (43)
CB1 Trip IP 3Ph 529 CB Trip Conversion (63)
CB1 Trip Output A 523 CB Trip Conversion (63) CB1 1-pole / 3-pole trip (13)
P841B-TM-EN-1.1 125
CB1 Trip Output B 524 CB Trip Conversion (63) CB1 1-pole / 3-pole trip (13)
CB1 Trip Output C 525 CB Trip Conversion (63) CB1 1-pole / 3-pole trip (13)
CB1 Autoclose (32)
CB1F SCOK 1491 3 Phase AR System Check (45) Prepare Reclaim Initiation (34)
CB1 Autoclose (32)
CB1L SCOK 1573 3 Phase AR System Check (45) Prepare Reclaim Initiation (34)
CB2 3P Dtime 1444 3-phase AR Dead Time (25)
CB2 AR Init 1434 CB2 AR In Progress (17) Dead Time Start Enable (22)
CB In Service (4)
Evolving Fault (20)
CB2 Autoclose (33)
CB2 AR Lockout 328 CB2 Autoreclose Lockout (56)
CB2 Healthy and System Check Timers (40)
CB2 AR Shot Counters (42)
Reset CB2 Lockout (58)
CB In Service (4)
Evolving Fault (20)
CB2 Autoclose (33)
CB2 ARIP 1435 CB2 AR In Progress (17) CB2 AR In Progress (17)
Reclaim Time (35)
CB2 Control (44)
CB2 Aux3ph(52-A) 428 CB2 State Monitor (2)
CB2 Aux3ph(52-B) 432 CB2 State Monitor (2)
CB2 Aux A(52-A) 429 CB2 State Monitor (2)
CB2 Aux A(52-B) 433 CB2 State Monitor (2)
CB2 Aux B(52-A) 430 CB2 State Monitor (2)
CB2 Aux B(52-B) 434 CB2 State Monitor (2)
CB2 Aux C(52-A) 431 CB2 State Monitor (2)
CB2 Aux C(52-B) 435 CB2 State Monitor (2)
CB2 Close Fail 325 CB Control (44) Leader Follower Logic (7
Follower CB AR Enable (27))
CB2 Close inProg 1453 CB Control (44)
126 P841B-TM-EN-1.1
CB In Service (4)
CB2 Autoclose (33)
Evolving Fault (20)
CB2 Closed 3 ph 915 CB2 State Monitor (1)
Reclaim Time (35)
CB Control (44)
CB2 Trip Time Monitor (54)
CB2 Closed A ph 916 CB2 State Monitor (2) CB Control (44)
CB2 Closed B ph 917 CB2 State Monitor (2) CB Control (44)
CB2 Closed C ph 918 CB2 State Monitor (2) CB Control (44)
CB2 Control 1450 CB2 Autoclose (33)
CB2 CS AngRotACW 1482 CB2 Check Sync Signals (61)
CB2 CS AngRotCW 1483 CB2 Check Sync Signals (61)
CB2 CS1 AngHigh- 1479 CB2 Check Sync Signals (61)
CB2 CS1 AngHigh+ 1478 CB2 Check Sync Signals (61)
CB2 CS1 Enabled 1426 CB2 Check Sync Signals (61)
CB2 CS1 Fl<FB 1476 CB2 Check Sync Signals (61)
CB2 CS1 Fl>FB 1474 CB2 Check Sync Signals (61)
3 Phase AR System Check Leader CB2 (46)
CB2 CS1 OK 1577 CB2 Check Sync Signals (61) 3 Phase AR System Check Follower CB2 (48)
CB2 Manual Close System Check (52)
CB2 CS1 SlipF< 1467 CB2 Check Sync Signals (61)
CB2 CS1 SlipF> 1466 CB2 Check Sync Signals (61)
CB2 CS1 VL<VB 1472 CB2 Check Sync Signals (61)
CB2 CS1 VL>VB 1470 CB2 Check Sync Signals (61)
CB2 CS2 AngHigh- 1481 CB2 Check Sync Signals (61)
CB2 CS2 AngHigh+ 1480 CB2 Check Sync Signals (61)
CB2 CS2 Enabled 1427 CB2 Check Sync Signals (61)
CB2 CS2 FL<FB 1476 CB2 Check Sync Signals (61)
CB2 CS2 FL>FB 1475 CB2 Check Sync Signals (61)
CB2 CS2 OK 1463 CB2 Check Sync Signals (61) 3 Phase AR System Check Follower CB2 (48)
CB2 CS2 SlipF< 1469 CB2 Check Sync Signals (61)
CB2 CS2 SlipF> 1468 CB2 Check Sync Signals (61)
CB2 CS2 VL<VB 1473 CB2 Check Sync Signals (61)
CB2 CS2 VL>VB 1471 CB2 Check Sync Signals (61)
CB2 Ext CS OK 901 3 Phase AR System Check Follower CB2 (48)
CB2 1-pole / 3-pole trip (14)
CB2 Ext Trip A 539
CB Control (44)
P841B-TM-EN-1.1 127
CB2 Ext Trip B 540
CB Control (44)
CB2 Ext Trip C 541
CB Control (44)
CB2 Ext Trip3ph 538
CB Control (44)
CB2 Fail Pr Trip 1459 CB2 Trip Time Monitor (54)
CB2 Failed AR 1441 Evolving Fault (20)
3 Phase AR System Check Leader CB2 (46) CB2 Autoclose (33)
CB2 Fast SCOK 1454
3 Phase AR System Check Follower CB2 (48) CB2 Healthy and System Check Timers (40)
CB Autoclose (32)
CB2 Healthy 437 CB2 Healthy and System Check Timers (40)
CB Control (44)
CB2 In Service 1428 CB In Service (4)
CB2 Lead 1408 Leader/Follower CB Selection (6)
CB2 LO Alarm 1599
CB2 Man SCOK 1458 CB2 Manual Close System Check (52) CB Control (44)
Leader Follower Logic (8) CB2 AR In Progress (17)
CB2 NoAR 1429
Leader Follower Logic (7) Leader Follower Logic (7)
CB Open (3)
CB2 Open 3 ph 911 CB2 State Monitor (2)
CB2 Autoclose (33)
CB Control (44)
CB2 Trip Time Monitor (54)
CB Open (3)
CB2 Open A ph 912 CB2 State Monitor (2) CB Control (44)
CB Open (3)
CB2 Open B ph 913 CB2 State Monitor (2) CB Control (44)
CB Open (3)
CB2 Open C ph 914 CB2 State Monitor (2) CB Control (44)
CB2 Status Alm 323 CB2 State Monitor (2) CB2 Autoreclose Lockout (56)
CB2 Succ 1P AR 1451 Successful AR Signals (36) CB2 AR Shot Counters (42)
CB2 Succ 3P AR 1452 Successful AR Signals (36) CB2 AR Shot Counters (42)
CB2 Trip 3ph 1600 CB Trip Conversion (63)
CB2 Trip AR MemA 1499 CB2 1-pole / 3-pole Trip (13) CB2 1-pole / 3-pole Trip (13)
128 P841B-TM-EN-1.1
CB2 Trip AR MemB 1500 CB2 1-pole / 3-pole Trip (13) CB2 1-pole / 3-pole Trip (13)
CB2 Trip AR MemC 1501 CB2 1-pole / 3-pole Trip (13) CB2 1-pole / 3-pole Trip (13)
CB2 Trip Fail 324 CB Control (44)
CB2 Trip IP 3Ph 1608 CB Trip Conversion (63)
CB2 Trip Output A 1601 CB Trip Conversion (63) CB2 1-pole / 3-pole trip (13)
CB2 Trip Output B 1602 CB Trip Conversion (63) CB2 1-pole / 3-pole trip (13)
CB2 Trip Output C 1603 CB Trip Conversion (63) CB2 1-pole / 3-pole trip (13)
CB2 Autoclose (33)
CB2F SCOK 1456 3 Phase AR System Check Follower CB2 (48) Prepare Reclaim Initiation (34)
CB2 Autoclose (33)
CB2L SCOK 1455 3 Phase AR System Check Leader CB2 (46) Prepare Reclaim Initiation (34)
Control CloseCB1 839 CB Control (43) Follower CB AR Enable (27)
Control CloseCB2 841 CB Control (44) Follower CB AR Enable (27)
Control TripCB1 838 CB Control (43) CB Control (43)
Control TripCB2 840 CB Control (44) CB2 Control (44)
CS VBus1> 1583 Check Sync Signals (60)
CS VBus1< 1582 Check Sync Signals (60)
CS VBus2< 1585 CB2 Check Sync Signals (61)
CS VBus2> 1584 CB2 Check Sync Signals (61)
CS VLine< 1580 Check Sync Signals (60)
CS VLine> 1581 Check Sync Signals (60)
Dead Bus 1 887 System Checks Voltage Monitor (59)
3 Phase AR System Check CB2 (46)
Dead Bus 2 1462 System Checks Voltage Monitor (59)
Dead Line 889 System Checks Voltage Monitor (59) 3 Phase AR System Check (47)
DTOK All 1551 Dead Time Start Enable (22)
DTOK CB1L 1P 1552 Dead Time Start Enable (22) 1-phase AR Dead Time (24)
En CB1 Follower 1488 Follower CB AR Enable (27)
En CB2 Follower 1455 Follower CB AR Enable (27)
Evolve 3Ph 1547 Evolving Fault (20) Autoreclose Lockout (55)
P841B-TM-EN-1.1 129
Ext Fault Aph 1508 Fault Memory (15)
Ext Fault BPh 1509 Fault Memory (15)
Ext Fault CPh 1510 Fault Memory (15)
Ext Rst CB1 AROK 1517 AR Reset Successful (37)
Ext Rst CB1Shots 1518 AR Shot Counters (41)
Ext Rst CB2 AROK 1417 AR Reset Successful (37)
Ext Rst CB2Shots 1418 CB2 AR Shot Counters (42)
Check Sync Signals (60)
F out of Range 319
CB2 Check Sync Signals (61)
Foll AR Mode 1P 1409 AR Modes Enable (9)
Foll AR Mode 3P 1410 AR Modes Enable (9)
Follower CB1 1432 Leader Follower Logic (7) CB1 AR In Progress (16)
Follower CB2 1433 Leader Follower Logic (7) CB2 AR In Progress (17)
Force 3PTrip CB1 533 CB Trip Conversion (63)
Force 3PTrip CB2 1604 CB Trip Conversion (63)
IA< Start 864 AR Initiation (11)
IB< Start 865 AR Initiation (11)
IC< Start 866 AR Initiation (11)
Force 3-phase Trip (10) CB1 AR In Progress (16), CB2
Inhibit AR 1420
AR In Progress (17)
Inhibit DB1 1525 System Checks Voltage Monitor (59)
Inhibit DB2 1425 System Checks Voltage Monitor (59)
Inhibit DL 1523 System Checks Voltage Monitor (59)
Inhibit LB1 1524 System Checks Voltage Monitor (59)
Inhibit LB2 1424 System Checks Voltage Monitor (59)
Inhibit LL 1522 System Checks Voltage Monitor (59)
Init 3P AR Test 1507 Trip Test (12)
Init APh AR Test 1504 Trip Test (12)
Init BPh AR Test 1505 Trip Test (12)
Init Close CB1 440 CB Control (43)
Init Close CB2 442 CB2 Control (44)
Init CPh AR Test 1506 Trip Test (12)
Init Trip CB1 439 CB Control (43)
Init Trip CB2 441 Init Trip CB2
Invalid AR Mode 331 AR Modes Enable (9)
Leader CB1 1530 Leader Follower Logic (7)
AR Modes Enable (9)
Leader CB2 1431 Leader Follower Logic (7)
AR Modes Enable (9)
Live Bus 1 886 System Checks Voltage Monitor (59) 3 Phase AR System Check (47)
130 P841B-TM-EN-1.1
Live Bus 2 1461 System Checks Voltage Monitor (59) 3 Phase AR System Check CB2 (48)
Live Line 888 System Checks Voltage Monitor (59)
ManCB1 Unhealthy 304 CB Control (43)
ManCB2 Unhealthy 326 CB Control (44)
System Checks Voltage Monitor (59)
MCB/VTS 438 Check Sync Signals (60)
MCB/VTS CB1 CS 1521
MCB/VTS CB2 CS 1423
NoCS CB1ManClose 305 CB Control (43)
NoCS CB2ManClose 327 CB Control (44)
CB1 Autoclose (32)
CB2 Autoclose (33)
OK Time 3P 1555 3-phase AR Dead Time (25)
Pole Dead A 892 CB Trip Conversion (63)
Pole Dead B 893 CB Trip Conversion (63)
Pole Dead C 894 CB Trip Conversion (63)
Pole Disc. CB1 Ext 451 Pole Discrepancy (62)
Pole Disc. CB2 Ext 1606 Pole Discrepancy (62)
Pole Discrep. CB1 699 Pole Discrepancy (62)
Pole Discrep. CB2 1607 Pole Discrepancy (62)
Rst CB1 CloseDly 443 CB Control (43)
Rst CB2 CloseDly 1419 CB2 Control (44)
Rst CB1 Lockout 446 Reset CB Lockout (57)
Rst CB2 Lockout 1420 Reset CB2 Lockout (58)
SChksInactiveCB1 880 Check Sync Signals (60)
SChksInactiveCB2 1484 CB2 Check Sync Signals (61)
Seq Counter = 0 846 Sequence Counter (18) AR Modes Enable (9)
P841B-TM-EN-1.1 131
AR Modes Enable (9)
Evolving Fault (20)
Seq Counter = 1 847 Sequence Counter (18) Follower 1-phase CB AR Time (28)
Seq Counter = 2 848 Sequence Counter (18)
Seq Counter > 4 851 Sequence Counter (18)
Autoreclose Lockout (55
Seq Counter>Set 1546 Sequence Counter (18)
CB2 Autoreclose Lockout (56))
Set CB1 Close 1565 CB1 Autoclose (32) AR Shot Counters (41)
Set CB2 Close 1449 CB2 Autoclose (33) CB2 AR Shot Counters (42)
Fault Memory (15)
Trip Inputs A 530
CB Trip Conversion (63)
Fault Memory (15)
Trip Inputs B 531
Fault Memory (15)
Trip Inputs C 532
VTS Fast Block 832
132 P841B-TM-EN-1.1
5 LOGIC MODULES
This section contains a complete set of logic diagrams, which will help to explain the Autoreclose function. Most of
the logic diagrams shown are logic modules that comprise the overall Autoreclose system. Some of the diagrams
shown are not directly related to Autoreclose functionality, however, they may use some inputs are produce
outputs that are used by the Autoreclose system. These diagrams are shown in this section for the sake of
completeness.
5.1 CIRCUIT BREAKER STATUS MONITOR

The Circuit Breaker State Monitor logic is part of the Monitoring and Control functionality and is fully described in
that chapter. The logic diagram is repeated in this section because some of the outputs of this logic module are
used as inputs to some of the Autoreclose logic modules.
P841B-TM-EN-1.1 133
5.1.1 CB STATE MONITOR

420
CB1 Aux 3ph(52-A)
&
424
CB1 Aux 3ph(52-B)
& 1 907
1 CB1 Closed 3 ph
XOR
&
CB1 Status Input

&
52A 3 pole
52B 3 pole
52A & 52B 3 pole & 1 903
1 CB1 Open 3 ph
&
&
421
CB1 Aux A(52-A)
&
425 908
CB1 Aux A(52-B) 1 CB1 Closed A ph
& 1
XOR
&
&
CB1 Status Input

&
52A 1 pole
52B 1 pole 904
1 CB1 Open A ph
52A & 52B 1 pole & 1
&
&
&
422 909
CB1 Aux B(52-A) 1 CB1 Closed B ph
CB1 Aux B(52-B) 426
905
Phase B 1 CB1 Open B ph
CB1 Status Input
(Same logic as phase A )
52A 1 pole
52B 1 pole
52A & 52B 1 pole
423 910
CB1 Aux C(52-A) 1 CB1 Closed C ph
CB1 Aux C(52-B) 427
906
Phase C 1 CB1 Open C ph
CB1 Status Input
52A 1 pole
52B 1 pole 301
1 CB1 Status Alm
52A & 52B 1 pole
V01265 CB1 Status Time
Figure 48: CB State logic diagram (Module 1)
5.2 CIRCUIT BREAKER OPEN LOGIC

The Circuit Breaker Open logic module produces internal signals indicating the open status of one or more phases.
These signals are used by some of the Autoreclose logic modules.
134 P841B-TM-EN-1.1
5.2.1 CIRCUIT BREAKER OPEN LOGIC DIAGRAM

904
CB1 Open A ph
905
CB1 Open B ph 1 CB1Op1P
906
CB1 Open C ph
1 CB1OpAny
903
CB1 Open 3 ph
1 CB1 Op2/3P
³2
912
CB2 Open A ph
913
CB2 Open B ph 1 CB2Op1P
914
CB2 Open C ph
1 CB2OpAny
911
CB2 Open 3 ph
1 CB2 Op2/3P
³2
V03390
Figure 49: Circuit Breaker Open logic diagram (Module 3)
5.3 CIRCUIT BREAKER IN SERVICE LOGIC

For Autoreclose to proceed, a circuit breaker has to be in service when the Autoreclose is initiated. A circuit breaker
is considered to be in service if it has been closed for more than the CB IS Time setting.
For applications with fast-acting circuit breaker auxiliary switches, a time delay setting CB IS Memory Time is
provided. This is used to ensure correct operation if a delay between the circuit breaker tripping and recognition by
the protection, is expected.
When an Autoreclose cycle starts, the “in service” signal for a circuit breaker stays set until the Autoreclose cycle
finishes.
The circuit breaker “in service” signal resets if the circuit breaker opens, or if the corresponding Autoreclose in
progress (ARIP) signal resets.
P841B-TM-EN-1.1 135
5.3.1 CIRCUIT BREAKER IN SERVICE LOGIC DIAGRAM
CB1 AR Lockout CBIST

& CB1 CRLO
0
Num CBs
CB1 Only
1 CBIST
Both CB 1&CB2 &
CBISMT & S
Q CB1 In Service
CB1 Closed 3 ph R
Logic 1 1
CB1 ARIP
CB2 AR Lockout CBIST

& CB2 CRLO
0
Num CBs
CB2 Only
1 CBIST
Both CB 1&CB2 &
CBISMT & S
Q CB2 In Service
CB2 Closed 3 ph R
Logic 1 1
CB2 ARIP
V03303
Figure 50: CB In Service logic diagram (Module 4)
5.4 AUTORECLOSE ENABLE LOGIC

The Autoreclose function must be enabled in the CONFIGURATION column before it can be brought into service. It
can be brought into service by:
● using an opto-input mapped to the AR Enable DDB signal
● pulsing the DDB signal AR On Pulse (use AR Off Pulse to bring it out of service)
● programming a function key on the HMI.
● if applicable, using IEC 60870-5-103 communications
Further validation signals are also required to switch on Autoreclose. These are the DDB signals AR Enable CB1
and AR Enable CB2. Once Autoreclose is in service, the AR In Service DDB signal is asserted and the AR Status cell
in the CB CONTROL column is set accordingly.
5.4.1 AUTORECLOSE ENABLE LOGIC DIAGRAM
Auto-Reclose
Enable
& AR DISABLED
HMI Comand
IEC 60870 Comand 1385 AR In Service

Autoreclose
Status
1382 Default = ON 1
AR On Pulse
1383
AR OFF Pulse
1384
AR Enable
1609
AR Enable CB1 *
1
1605
AR Enable CB2 *
*Defaults to High if not mapped in PSL
V03301
Figure 51: Autoreclose Enable logic diagram (Module 5)
5.5 AUTORECLOSE LEADER/FOLLOWER

You can select either CB1 or CB2 to be the leader, with CB2 or CB1 as the follower respectively.
136 P841B-TM-EN-1.1
5.5.1 LEADER/FOLLOWER CB SELECTION LOGIC DIAGRAM
Leader Select By
Menu
&
Select Leader
1 Pref LCB1
CB1
CB2
&
Leader Select By
Opto
&
1408 1 Pref LCB2
CB2 Lead
&
Leader Select By
Control
&
CB2 Lead
Set
Num CBs &

Both CB 1&CB2
CB1 Only
CB2 Only
V03306
Figure 52: Leader/Follower CB Selection Logic Diagram (Module 6)
P841B-TM-EN-1.1 137
5.5.2 LEADER FOLLOWER LOGIC DIAGRAM

1530
Leader CB1
&
CB1 Close Fail
303 1 CB1 LFRC
307 1 &
AR CB1 Unhealthy
1542
ARIP
Leader CB2 1431
&
CB2 Close Fail 325 1 CB2 LFRC
329 1 &
AR CB2 Unhealthy
ARIP 1542
Reset L -F 1 & S
0.1s Q
R 1 SET LCB1
Pref LCB1
&
1429
CB2 NoAR
0.1 &
1544
CB1 ARIP
0 1
&
& S
Pref LCB2 Q
R 1 SET LCB2
&
CB1 NoAR 1528
0.1 &
1435
CB2 ARIP
0 1
&
1385
AR in Service
AR Enable CB 1 1609
1526 1528
CB1 in Service & CB1 NoAR
CB1 AR Lockout 306
BAR CB1
ARIP 1542 &
1 S 1530
& Q Leader CB1
Set LCB1 R
&
Reset L -F
0 .1s
Foll SPAROK &

1 1
Foll 3 PAROK
1431 &
Leader CB2
1 & 1432 Follower CB1
CB2 LFRC
1385
AR in Service
AR Enable CB 2 1605
1428 1429
CB2 in Service & CB2 NoAR
328
CB2 AR Lockout
BAR CB2
ARIP 1542 &
1 S 1431
& R
Q Leader CB2
Set LCB2
&
Reset L -F
0. 1s
&
1
Foll SPAROK
1
Foll 3 PAROK &
1530 1433
Leader CB1 & Follower CB2
1
CB1 LFRC V03307
Figure 53: Leader/Follower logic diagram (Module 7 & 8)
138 P841B-TM-EN-1.1
5.6 AUTORECLOSE MODES

The device can provide Single-phase and/or Three-phase Autoreclose. The Autoreclose mode is configured by the
AR Mode setting in the AUTORECLOSE column. You can choose from:
● Single-phase (AR 1P)
● Three-phase (AR 3P)
● Single-phase and Three-phase (AR 1/3P)
● Controlled by commands from DDB signals that must be mapped to opto-isolated inputs in the PSL (AR
Opto).
Single-phase Autoreclosing is permitted only for the first shot of an Autoreclose cycle. In a multi-shot Autoreclose
cycle the second and subsequent trips will always be three-phase.
For multi-phase faults, you can use the Multi Phase AR setting in the AUTORECLOSE column to configure the
following options:
● Allow Autoreclose for all fault types (Allow Autoclose)
● Block Autoreclose for 2-phase and 3-phase faults (BAR 2 and 3 ph)
● Block Autoreclose for 3-phase faults (BAR 3 Phase)
5.6.1 SINGLE-PHASE AND THREE-PHASE AUTORECLOSE

This section applies to dual-CB devices. Where there are signals and settings for each of the two circuit breakers,
only the first CB (CB1) is shown, to improve clarity and save repetition. Where settings and signals include "CB1",
there is a "CB2" equivalent.
Single-phase Autoreclose Only

If single-phase Autoreclose is enabled, the logic allows only a single shot Autoreclose. For a single-phase fault, the
single phase dead timer SP AR Dead Time starts, and the DDB signal CB1 AR 1p Inprog is asserted, which indicates
that single-phase Autoreclose is in progress. In this case, for a multi-phase fault the logic triggers a three-phase
trip and goes to lockout.
Three-phase Autoreclose Only

During three-phase Autoreclose, for any fault, the three-phase dead timers: 3P AR DT Shot 1, 3P AR DT Shot 2, 3P
AR DT Shot 3 and 3P AR DT Shot 4 are started and the DDB signal is CB1 AR 3p InProg is asserted, which indicates
that three-phase Autoreclose is in progress.
If three-phase only Autoreclose is enabled, the logic forces a three-phase trip by setting the DDB signal AR Force
CB1 3P for any single-phase fault.
Single-phase and Three-phase Autoreclose

With single-phase and three-phase Autoreclose enabled then, if the first fault is a single-phase fault the single-
phase dead time SP AR Dead Time is started and the single-phase Autoreclose in progress signal is asserted. If the
first fault is a multi-phase fault the three phase dead timer 3P AR DT Shot 1 is started and the three-phase
Autoreclose in progress signal is asserted. If set to allow more than one reclose (AR Shots > 1) then any subsequent
faults are converted to three-phase trips by setting the force three-pole tripping signal. The three-phase dead
times 3P AR DT Shot 2, 3P AR DT Shot 3 and 3P AR DT Shot 4 (Dead Times 2, 3, 4) are started for the 2nd, 3rd and
4th trips (shots) respectively. The DDB signal CB1 AR 3p InProg is asserted. If a single-phase fault evolves to a
multi-phase fault during the single-phase dead time (SP AR Dead Time), single-phase Autoreclose is stopped. The
single-phase Autoreclose in progress signal is reset, the three-phase Autoreclose in progress signal is set, and the
three-phase dead timer 3P AR DT Shot 1 is started.
P841B-TM-EN-1.1 139
5.6.2 AUTORECLOSE MODES ENABLE LOGIC DIAGRAM

1385
AR in Service
& * If not mapped in PSL, AR Enable
Num CBs & CB1 and AR Enable CB 2 default to
CB1 only high
&
CB2 only & When Leader/Follower AR mode is
Both CB 1&CB2
& set via opto -inputs, there are 7
1609
AR Enable CB1 invalid combinations. This logic
1 &
AR Enable CB2 1605 detects these combinations and on
a trip forces both CB 1 and CB2 to
AR Mode lockout.
1 &
AR 1 P
AR 1/ 3P 1P 3P 1P 3P
AR 3 P 1 0 0 0 1
AR Opto 0 0 1 0
&
1497
0 0 1 1
AR Mode 1P
0 1 1 0
1498 & 0 1 1 1
AR Mode 3P
1 0 1 1
&
Lead /Foll ARMode 1 1 1 1 0
L 1P, F 1 P
L 1P, F 3 P
&
L 3P, F 3 P 1
L 1/3P, F 1 /3P
L 1/3P , F 3P
& Foll SPAROK
AR Opto 1
& Foll3 PAROK

1
1497
&
AR Mode 1P Invalid AR Mode
1498 & 5s
AR Mode 3P 331
See Note Invalid AR Mode
1409 & 0
Foll AR Mode 1 P
1410
&
Foll AR Mode 3 P
Seq Counter = 0 846

847 1
Seq Counter = 1 & CB1LSPAROK
1530
Leader CB 1 1
1609
&
AR Enable CB1
& CB2LSPAROK
1
&
Leader CB 2 1431
1 CB1L 3PAROK
1605 &
AR Enable CB2
& 1 CB2L 3PAROK
846
Seq Counter = 0
847 1
Seq Counter = 1
AR Enable CB1 1609
& CB1 FSPAROK
&
Foll CB1
CB2L SPAROK
& CB1F3PAROK
Fol SPAROK
1605
AR Enable CB2 & CB2 FSPAROK
&
Foll CB2
CB1L SPAROK
& CB2F3PAROK
Foll 3 PAROK
V03310
Figure 54: Autoreclose Modes Enable logic diagram (Module 9)
140 P841B-TM-EN-1.1
5.7 AR FORCE THREE-PHASE TRIP LOGIC

Following single-phase tripping, while the Autoreclose cycle is in progress, and upon resetting of the protection
elements, tripping switches to three-phase.
Any protection operations that occur for subsequent faults while the Autoreclose cycle remains in progress will be
tripped three-phase.
5.7.1 FORCE THREE-PHASE TRIP LOGIC DIAGRAM
CB1 L SPAROK
1
CB1 F SPAROK
1554
CB1 ARIP
&
TARANY
847 &
Seq Counter = 1
1
Seq Counter = 2 848 &
1 858
849
& AR Force CB1 3P
Seq Counter = 3
Seq Counter = 4 850
306
CB1 AR Lockout
307
AR CB1 Unhealthy
1420
Inhibit AR
CB2Tripping Mode
3 Pole
&
1 and 3 pole
1431
Leader CB2
CB21 L SPAROK
1
CB2 F SPAROK
1435
CB2 ARIP
&
TARANY
847 &
Seq Counter = 1
1
Seq Counter = 2 848 &
1 1485
849 & AR Force CB2 3P
Seq Counter = 3
850
Seq Counter = 4
CB2 AR Lockout 328
329
AR CB2 Unhealthy
1420
Inhibit AR
CB1Tripping Mode
3 Pole
&
1 and 3 pole
1530
Leader CB1
1585
AR In Service
NUM CBs
1
CB1 Only
Both CB1 &CB2
1
CB2 Only
V03314
Figure 55: Force three-phase trip logic diagram (Module 10)
P841B-TM-EN-1.1 141
5.8 AUTORECLOSE INITIATION LOGIC

Autoreclose initiation starts Autoreclose for a circuit breaker only if Autoreclose is enabled for the circuit breaker,
and the circuit breaker is in service. When an Autoreclose cycle is started, Autoreclose in progress (ARIP) is
indicated. The indication remains until the end of the cycle. The end of the cycle is signified by successful
Autoreclose, or by lockout.
Autoreclose cycles can be initiated by:
● Protection functions internal to the product
● A Trip Test feature
● External protection equipment
● Evolving fault combinations
Internal Protection Functions

Many of the protection functions in the product can be programmed to initiate or block Autoreclose. The
associated settings are found in the Autoreclose column and the available options are No Action, Initiate
AR, or Block AR. If set to Block AR operation of the protection function blocks the Autoreclose function and
forces a lockout.
Trip Test Feature

The Test Autoreclose command cell in the COMMISSION TESTS column can be used to initiate an Autoreclose
cycle. Each option provides a 100 ms pulse output. There is also a ‘No Operation’ option to exit the command field
without initiating a test.
External Protection Equipment

Protection operation from a different device can be used to initiate Autoreclose via PSL. By default these external
trip input signals are mapped to initiate Autoreclose. These inputs are not mapped to the trip outputs. With
appropriate mapping in the PSL, however, the external device can use this product to trip connected circuit
breakers.
Evolving Fault Combinations

The Autoreclose function would normally be initiated by a single condition (such as a single-phase fault). If,
however, the system conditions evolve such that other conditions that could initiate Autoreclose, then the
dynamics of the Autoreclose logic need to adapt. For example, if a single-phase fault evolves into a multi-phase
fault, then the operation of the Autorecloser must consequently adapt. To achieve this signals are generated to
indicate conditions such as evolving faults, re-operation of protection, combinations of initiation by internal
protection, external protection, or test features, which control the Autoreclose sequencing.
Records of initiating conditions are stored and used to control the sequencing. Initiation can be from a protection
function integrated in the product, from external protection and internal sources such as the Autoreclose test
function. Initiation can be further qualified by the phases causing the initiation. These conditions are stored in
signals that generally feature “MEM”- memory, or “AR” – Autoreclose, in the signal name.
142 P841B-TM-EN-1.1
5.8.1 AUTORECLOSE INITIATION LOGIC DIAGRAM
Protection function 1 Trip
Block AR
Initiate AR 1 Prot AR Block
Protection function n Trip
Block AR 1 S
Q
Initiate AR R 1 INIT AR
864
IA< Start &
1
865
IB< Start
866
IC< Start
577
AR Trip Test A
1
578 &
AR Trip Test B
579
AR Trip Test C
522
Any Trip
V03315
Figure 56: Autoreclose Initiation logic diagram (Module 11)
5.8.2 AUTORECLOSE TRIP TEST LOGIC DIAGRAM

1504
Init APh AR Test
1 577
1 AR Trip Test A
1505
Init BPh AR Test
1 578
1 AR Trip Test B
1506
Init CPh AR Test
1 579
1 AR Trip Test C
1507
Init 3P AR Test 576
1 AR Trip Test 3Ph
Test Autoreclose
No Operation
Trip Pole A
Trip Pole B
Trip Pole C
Trip 3 Pole
V03304
Figure 57: Autoreclose Trip Test logic diagram (Module 12)
P841B-TM-EN-1.1 143
5.8.3 EXTERNAL TRIP LOGIC DIAGRAM FOR CB1
CB2 TARA
CB2 TARB 1
CB2 TARC
Num CBs
CB1 only ≥
TAR2/ 3PH
CB2 only 1 2
Both CB1 &CB2
1 TARANY
Init AR
523
&
CB1 Trip OutputA 1 TARA
535 S
CB1 Ext Trip A 1535
Q CB1 Trip AR MemA
Init AR R
524
&
CB1 Trip OutputB 1 TARB
CB1 Ext Trip B 536 S 1536

Q CB1 Trip AR MemB
Init AR R
525
&
CB1 Trip OutputC 1 TARC
537
CB1 Ext Trip C S 1537
Q CB1 Trip AR MemC
CB1 Ext Trip3 ph 534 R
1542 0.01
ARIP
0.1
&
1 RESPRMEM
1 0.2
AR Disabled & S
0 Q
R
1
TARANY
1499
CB2 Trip AR MemA
1500
CB2 Trip AR MemB 1
1 TMEMANY
1501
CB2 Trip AR MemC
CB1 Trip AR MemA 1535
1536
CB1 Trip AR MemB 1
1537
CB1 Trip AR MemC
=
TMEM1Ph
1
≥
TMEM2 /3Ph
2
& TMEM3Ph
V03318
Figure 58: Autoreclose initiation by internal single and three phase trip or external trip for CB1 (Module 13)
Note:
For single-phase Autoreclose, these signals must be mapped as shown in the default PSL scheme.
144 P841B-TM-EN-1.1
5.8.4 EXTERNAL TRIP LOGIC DIAGRAM FOR CB2
Num CBs
CB1 only ≥
CB2 TAR2/3PH
CB2 only 1 2
Both CB1 &CB2
Init AR
&
CB2 Trip OutputA 1 CB2 TARA
CB2 Ext Trip A S

Q CB2 Trip AR MemA
Init AR R
&
CB2 Trip OutputB 1 CB2 TARB
CB2 Ext Trip B S

Q CB2 Trip AR MemB
Init AR R
&
CB2 Trip OutputC 1 CB2 TARC
CB2 Ext Trip C S

Q CB2 Trip AR MemC
CB2 Ext Trip3 ph R
RESPRMEM
CB2 Trip AR MemA

=
CB2 Trip AR MemB CB2 TMEM1Ph
1
CB2 Trip AR MemC
≥
CB2 TMEM2/3 Ph
2
& CB2 TMEM3Ph

V03325
Figure 59: Autoreclose initiation by internal single and three phase trip or external trip for CB2 (Module 14)
Note:
For single-phase Autoreclose, these signals must be mapped as shown in the default PSL scheme.
P841B-TM-EN-1.1 145
5.8.5 PROTECTION REOPERATION AND EVOLVING FAULT LOGIC DIAGRAM
TMEMANY 0
&
0.02 &
1 Prot ReOp
TARANY
&
& RESETL-F
Discrim Time
t
1554 &
1P DTime 0
Prot ReOp & Evolve Lock
847
Seq Counter = 1
576
& Evolve 3Ph
0
LastShot & S
0.02 Q 1550
306
R & CB1 Failed AR
CB1 AR Lockout
328 1
CB2 AR Lockout
Set CB1 CL
907 0 1
CB1 Closed 3 ph &
0.02
1544
CB1 ARIP
Set CB2 CL & 1441

CB2 Failed AR
915 0 1
CB2 Closed 3 ph &
0.02
1544
CB2 ARIP
V03332
Figure 60: Protection Reoperation and Evolving Fault logic diagram (Module 20)
5.8.6 FAULT MEMORY LOGIC DIAGRAM
Trip Inputs A
1
Ext Fault APh & S
Q =
R FLTMEM 2P
Trip Inputs B 2
1
Ext Fault BPh & S
Q
R & FLTMEM 3P
Trip Inputs C
1
Ext Fault CPh & S
Q
R
AR Start
RESPRMEM
V03320
Figure 61: Fault Memory logic diagram (Module 15)
5.9 AUTORECLOSE IN PROGRESS

The AR In Progress module produces various signals to indicate to other modules and functions that an
Autoreclose operation is currently in progress.
146 P841B-TM-EN-1.1
5.9.1 AUTORECLOSE IN PROGRESS LOGIC DIAGRAM FOR CB1
CB2 Ext Trip A
CB2 Ext Trip B 1 AR Start
CB2 Ext Trip C
CB2 Ext Trip3 ph
Init AR
CB1 Ext Trip A 1

CB1 Ext Trip B
CB1 Ext Trip C
CB1 Ext Trip3 ph
TMEM2 /3Ph
1
TMEM1Ph &
& & CB1 AR Init
CB1 Op2/3 P
CB1L3 PAROK S
Q CB1 ARIP
1 R
CB1 F3 PAROK
1 ARIP
Inhibit AR 1
CB1 LO Alarm
CB1 NoAR
CB1 ARSUCC
CBARCancel
0.02
CB1 OpAny
0 &
CB1 ARIP 1
AR Start &
Set CB1 Close
&
CB1 Closed 3 ph
CB2 ARIP
& CB1 LARIP
Leader CB1
1
& CB1 FARIP
Follower CB1
V03322
Figure 62: Autoreclose In Progress logic diagram for CB1 (Module 16)
P841B-TM-EN-1.1 147
5.9.2 AUTORECLOSE IN PROGRESS LOGIC DIAGRAM FOR CB2
Init AR
CB2 Ext Trip A 1

CB2 Ext Trip B
CB2 Ext Trip C
CB2 Ext Trip 3ph
CB2 TMEM2/3 Ph
1
CB2 TMEM1Ph &
& & CB2 AR Init
CB2 Op2/3 P
CB2L3 PAROK S
1 Q CB2 ARIP
CB2 F3 PAROK R
Inhibit AR 1
CB2 LO Alarm
CB2 NoAR
CB2 ARSUCC
CBARCancel
0.02
CB2 OpAny
0 &
CB2 ARIP 1
AR Start &
Set CB2 Close
&
CB2 Closed 3 ph
& CB2 LARIP

Leader CB2
1
& CB2 FARIP
Follower CB2
V03324
Figure 63: Autoreclose In Progress logic diagram for CB2 (Module 17)
5.10 SEQUENCE COUNTER

The Autoreclose logic includes a counter for counting the number of Autoreclose shots. This is referred to as the
sequence counter. The sequence counter has a value of zero if Autoreclose is not in progress. Following a trip, and
subsequent Autoreclose initiation, the sequence counter is incremented. The counter provides output signals
indicating how many initiation events have occurred in any Autoreclose cycle. These signals are available as user
indications and are used in the logic to select the appropriate dead times or, for a persistent fault, force a lockout.
It is possible to skip the first Autoreclose attempt by enabling the AR Skip Shot 1 setting. If this is set, the sequence
counter will skip the first Autoreclose attempt (Shot 1) and move to the second (Shot 2) immediately upon
Autoreclose initiation. Each time the protection trips the sequence counter is incremented by 1. The Autoreclose
logic compares the sequence counter value to the number of Autoreclose shots setting AR Shots. If the counter
value exceeds this setting then the Autoreclose is locked out. If Autoreclose is successful, the sequence counter
resets to zero.
148 P841B-TM-EN-1.1
5.10.1 AUTORECLOSE SEQUENCE COUNTER LOGIC DIAGRAM
CB1 AR Init
1
CB2 AR Init &
1
ARIP &
AR Start
&
1P Dtime
&
Seq Counter = 1
Seq Counter = 0
Increment on rising edge Seq Counter = 1
Reset on falling edge Seq Counter = 2
Single Pole Shot Seq Counter = 3

Sequence Counter
Three Pole Shot Seq Counter = 4
Seq Counter > 4
Seq Counter >Set
& S
Prot Re-op Q LastShot
R
V03327
Figure 64: Autoreclose Sequence Counter logic diagram (Module 18)
5.11 AUTORECLOSE CYCLE SELECTION

The Autoreclose cycle selection logic is responsible for determining whether the Autoreclose will start as single-
phase or three-phase.
P841B-TM-EN-1.1 149
5.11.1 SINGLE PHASE AUTORECLOSE CYCLE SELECTION LOGIC DIAGRAM
ARIP S
Q LeaderSPAR
1 R
CB1 L 3 PAR
CB2 L 3 PAR
RESETL-F 1
CB1 L ARIP
& S
CB1 L SPAROK Q CB1 L SPAR
R
TMEM1PH
1
CB1 L 3 PAR
CB2 L ARIP
& S
Q CB2 L SPAR
CB2 L SPAROK R
CB2 TMEM1 PH
1
CB2 L 3 PAR 1 CB1 AR 1 p InProg
CB1F ARIP
& S
CB2L SPAR Q CB1F SPAR
R
CB1F SPAROK
TMEM1PH
CB1F 3PAR
1 1 CB2 AR 1 p InProg
CB2L 3PAR
CB2F ARIP
& S
CB1L SPAR Q CB2F SPAR
R
CB2F SPAROK
CB2 TMEM1 PH
CB2F 3PAR
1
CB1L 3PAR
V03330
Figure 65: Single-phase Autoreclose Cycle Selection logic diagram (Module 19)
150 P841B-TM-EN-1.1
5.11.2 3-PHASE AUTORECLOSE CYCLE SELECTION
CB1L ARIP
& S
CB1 L3 PAROK Q CB1L 3PAR
R
Evolve 3Ph
TMEM3P 1
CB1 OP2 /3P
TMEM ANY
&
CB1 L SPAROK 1 CB1 AR 3 p InProg
CB2L ARIP
& S
CB2L 3PAROK Q CB2L 3PAR
R
CB2 TMEM 3 P
1
CB2 OP 2 /3P
1 CB2 AR 3 p InProg
&
CB2L SPAROK
CB1F ARIP
& S
Q CB1F3PAR
CB1 F 3 PAROK R
1
CB1 OP 2 /3P
&
CB1F SPAROK
CB2F ARIP
& S
Q CB2F 3PAR
CB2 F 3 PAROK R
1
CB2 OP 2 /3P
&
CB2F SPAROK
V03335
Figure 66: Three-phase Autoreclose Cycle Selection logic diagram (Module 21)
5.12 DEAD TIME CONTROL

Once an Autoreclose cycle has started, the conditions to enable the dead time to run are determined by the menu
settings, the circuit breaker status, the protection status, the nature of the AR cycle (single-phase or three-phase),
and the opto-isolated inputs from external sources.
Three settings are involved in controlling the dead time start:
● DT Start by Prot
● 3PDTStart WhenLD
● DTStart by CB Op
The DT Start by Prot determines how the protection action will initiate a dead time. The setting is always visible
and has three options Protection Reset, Protection Op (protection operation), and Disable which
should be selected if you don’t want protection action to start the dead time. These options set the basic
conditions for starting the dead time.
Selecting protection operation to start the dead time can, optionally, be qualified by a check that the line is dead.
Selecting protection reset to start the dead time can, optionally, be qualified by a check, that the circuit breaker is
open (DTStart by CB Op) before starting the dead time. For three-phase tripping applications, there is a further
option to check that the line is dead (3PDTStart WhenLD) before starting the dead time.
P841B-TM-EN-1.1 151
If DT Start by Prot is disabled, the circuit breaker must be open for the dead time to start. For three-phase tripping
applications, there is an option to check that the line is dead (3PDTStart WhenLD) before starting the dead time. To
check that the line is dead, set 3PDTStart WhenLD to enabled. To check that the circuit breaker is open, set
DTStart by CB Op to Enabled.
5.12.1 DEAD TIME START ENABLE LOGIC DIAGRAM
DT Start by Prot
Disable
1
Protection Reset & DTOK All
&
Protection Op
AR Start
Dead Line Time
OKTimeSP &
S
Q
OK Time 3P 1 R & S t
Q DeadLineLockout
ARIP R 0
CB1 AR Init 0 1
1
CB2 AR Init 0.02
Dead Line
1
3 PDTStart WhenLD
&
Enabled
Disabled
DT Start by Prot
Protection Reset
1
Disable &
CB1 AR 1 p InProg
CB2 AR 1 p InProg &
&
DTStart by CB Op
Disabled
1
Enabled
1 DTOK CB1L 1P
CB1OP1 P &
CB2OPAny
1
1 DTOK CB1L 3P
CB1 Open 3 ph &
CB2 Open 3 ph
1
1 DTOK CB2L 1P
CB2OP1 P &
CB1OPAny
1
1 DTOK CB2L 3P
CB2 Open 3 ph &
CB1 Open 3 ph
1
Num CBs
CB1 Only
CB2 Only
V03338
Figure 67: Dead time Start Enable logic diagram (Module 22)
152 P841B-TM-EN-1.1
5.12.2 SINGLE-PHASE LEADER DEAD TIME LOGIC DIAGRAM
CB1LSPAR
&
DTOK CB1L 1P 1
& S
CB2LSPAR Q
& R & OKTimeSP
DTOK CB2L 1P
Seq Counter = 1
DTOK All
AR Start
1
DT Start by Prot
&
Protection Reset
CB1LSPAR
1
CB2LSPAR
CB1OP2/ 3P
&
CB2OP2/ 3P
Logic 1
&
CB1LSPAR 1
Logic 1
&
CB2LSPAR
t
0
1 Pole Dead Time
CB1LSPAR &
1 1P DTime
& CB1SPDTCOMP
CB2LSPAR &
& CB2SPDTCOMP
V03343
Figure 68: Single-phase Leader Dead Time logic diagram (Module 24)
P841B-TM-EN-1.1 153
5.12.3 3-PHASE LEADER DEAD TIME LOGIC DIAGRAM
CB1L 3PAR
&
DTOK CB1L 3P
1
CB2L 3PAR
&
DTOK CB2L 3P
& S
DTOK All Q
R & OK Time 3P
3PDTCOMP
DT Start by Prot &

Protection Reset 1
AR Start
CB1L 3PAR
1
CB2L 3PAR Logic 1
&
1
Logic 1
&
3P AR DT Shot 1
t 1 3PDTCOMP
&
Seq Counter = 1 0
& 3P DTime1
3P AR DT Shot 2
t
&
Seq Counter = 2 0
& 3P DTime2
3P AR DT Shot 3
t
&
Seq Counter = 3 0
& 3P DTime3
3P AR DT Shot 4
t
&
Seq Counter = 4 0
& 3P DTime4
1 3P Dead Time IP
3PDTCOMP
CB1L 3PAR & CB1 3 P DTime
& CB13 PDTCOMP
CB2L 3PAR & CB2 3 P DTime
& CB23 PDTCOMP

V03341
Figure 69: Three-phase Leader CB Dead Time logic diagram (Module 25)
154 P841B-TM-EN-1.1
5.12.4 FOLLOWER ENABLE LOGIC DIAGRAM
Control CloseCB1
& S
CB2 F SPAR Q
1 RD & En CB 2 Follower
CB2F 3PAR
CB2 Closed 3 ph 1
CB2 Close Fail
AR Start
BF if LFail Cls
Disabled
&
1
CB1 AR Lockout
CB1 Closed 3 ph
Logic 1
&
CB2 F SPAR 1
Logic 1
&
CB2F 3PAR
Control CloseCB2
& S
CB2 F SPAR Q
1 RD & En CB1 Follower
CB2F 3PAR
CB1 Closed 3 ph
1
CB1 Close Fail
AR Start
BF if LFail Cls
Disabled
&
1
CB2 AR Lockout
CB2 Closed 3 ph
Logic 1
&
CB1 F SPAR 1
Logic 1
&
CB1F 3PAR
V03346
Figure 70: Follower Enable logic diagram (Module 27)
P841B-TM-EN-1.1 155
5.12.5 SINGLE-PHASE FOLLOWER TIMING LOGIC DIAGRAM
Dynamic F/L
Enabled
&
CB1 LFRC
1
CB2 LFRC
CB1OP1 P
CB1FSPAR &
1
En CB 1 Follower
&
1PF TComp 1 1PF TComp
CB2OP1 P & S
Q
R
CB2FSPAR
En CB 2 Follower
Seq Counter = 1
1 t
AR Start
0
CB1FSPAR
1
CB2FSPAR
CB1OP2/ 3P
&
CB2OP2/ 3P
Follower Time
CB1FSPAR &
1 1 P Follower Time
& CB1SPFTCOMP
CB2FSPAR &
& CB2SPFTCOMP
V03347
Figure 71: Single-phase Follower CB timing logic diagram (Module 28)
156 P841B-TM-EN-1.1
5.12.6 THREE-PHASE FOLLOWER TIMING LOGIC DIAGRAM
Dynamic F/L
Enabled
&
CB1 LFRC
1
CB2 LFRC
CB1 open 3 ph
CB1F3PAR &
1
En CB 1 Follower
&
3PF TComp 1 3PF TComp
CB2 open 3 ph & S

Q
R
CB2F3PAR
En CB 2 Follower
1 t
AR Start
0
CB1FSPAR
1
CB2FSPAR
Follower Time
CB1F3PAR &
1 3 P Follower Time
& CB13 PFTCOMP
CB2F3PAR &
& CB23 PFTCOMP
V03348
Figure 72: Three-phase Follower CB timing logic diagram (Module 29)
5.13 CIRCUIT BREAKER AUTOCLOSE

Autoclose logic takes effect when dead times have expired.
The Autoclose logic checks that all necessary conditions are satisfied before issuing an Autoclose command to the
circuit breaker control scheme.
Before a circuit breaker can be closed, it must be healthy (sufficient energy to close, and if necessary re-trip) and it
must not be in a lockout condition.
For three-phase Autoreclose, the circuit breaker must be open on all three phases and the appropriate system
check conditions must be met. For single-phase Autoreclose, the circuit breaker must be open on that phase.
The Autoclose command is a pulse lasting 100 milliseconds. Another command (Set CB Close) to set the circuit
breaker to close is asserted as well as the Autoclose command. This signal will remain set either until the end of
the Autoreclose cycle, or until the next protection operation. These commands are used to initiate the Reclaim
Time logic and the Autoreclose Shot Counter logic.
P841B-TM-EN-1.1 157
5.13.1 CIRCUIT BREAKER AUTOCLOSE LOGIC DIAGRAM

522
Any Trip
306
CB1 AR Lockout &
&
CB1 Healthy 436 If the DDB signal CB1 Healthy is not mapped in PSL , it defaults to
High.
CB1SPDTComp
CB1OP1P &
CB1L3PAR
903
CB1 Open 3 ph
CB13PDTComp
1573 &
CB1 L SCOK 1
CB1 Fast SCOK 1572
1555
&
OK Time 3P
CB1FSPAR &
CB1SPFTComp
CB1F3PAR 1
&
CB13PFTComp
1491
CB1F SCOK
1562
Set CB1 Close
306 & S
CB1 AR Lockout Logic 1 Q 854
Auto Close CB1
R
ProtRe_Op
0.1s
1542
1
ARIP
1544
CB1 ARIP
1566
907 & CB1 Control
CB1 Closed 3 ph
522
Any Trip
328
CB2 AR Lockout &
&
CB2 Healthy 437
CB2SPDTComp If the DDB signal CB2 Healthy is not mapped in PSL , it defaults to
High.
CB2OP1P &
CB2L3PAR
911
CB2 Open 3 ph
CB23PDTComp
1455 &
CB2 L SCOK 1
1454
CB2 Fast SCOK
1555 &
OK Time 3P
CB2FSPAR &
CB2SPFTComp
CB2F3PAR 1
&
CB23PFTComp
1456
CB2F SCOK
1449
Set CB2 Close
328 & S
CB2 AR Lockout Logic 1 Q
1448
Auto Close CB2
R
ProtRe_Op
0.1s
1542 1
ARIP
1435
CB2 ARIP
1450
915
& CB2 Control
CB2 Closed 3 ph
V03350
Figure 73: Circuit Breaker Autoclose Logic Diagram (Modules 32 & 33)
5.14 RECLAIM TIME

If the protection operates again before the reclaim time has expired, the corresponding sequence counter is
incremented. At the same time, any “dead time complete” (….DTCOMP) signals are reset and the logic is prepared
158 P841B-TM-EN-1.1
for the next dead time to start when conditions are suitable. The operation also resets the signal that would set the
circuit breaker to close, and stops and resets the reclaim timer. The reclaim time starts again if the signal to set a
circuit breaker to close goes high following completion of a dead time in a subsequent Autoreclose cycle.
If the circuit breaker is closed and has not tripped again when the reclaim time expires, signals are generated to
indicate successful Autoreclose. These signals increment the relevant circuit breaker successful Autoreclose shot
counters and reset the relevant Autoreclose in progress signal.
The “successful Autoreclose” signals generated from the logic can be reset by various commands and settings
options available under CB CONTROL menu settings as follows:
If Res AROK by UI is set to Enabled, all the signals can be reset by user interface command Reset AROK Ind from
the CB CONTROL menu.
If Res AROK by NoAR is set to Enabled, the signals for each circuit breaker can be reset by temporarily
generating an Autoreclose disabled signal according to the logic shown.
If Res AROK by Ext is set to Enabled, the signals can be reset by activation of an external input signal
appropriately mapped in the PSL.
If Res AROK by TDly is set to Enabled, the signals are automatically reset after a time delay set in AROK Reset
Time.
5.14.1 PREPARE RECLAIM INITIATION LOGIC DIAGRAM
CB1SPDTComp
1
CB1 SPFTComp & S
1565
Q SETCB1SPCl
Set CB1 Close R
CB13 PDTComp
1573
&
CB1 L SCOK
1572
CB1 Fast SCOK &
1555 & 1 S
OK Time 3P Q SETCB13 PCl
R
CB13PFTComp
1491 &
CB1F SCOK
CB2SPDTComp
1
CB2 SPFTComp & S
1449
Q SETCB2SPCl
Set CB2 Close R
CB23 PDTComp
1455
&
CB2 L SCOK
1454
CB2 Fast SCOK & S
1555 & 1
OK Time 3P Q SETCB23 PCl
R
CB23PFTComp
1456 &
CB2F SCOK
V03353
Figure 74: Prepare Reclaim Initiation logic diagram (Module 34)
P841B-TM-EN-1.1 159
5.14.2 RECLAIM TIME LOGIC DIAGRAM
SETCB 1SPCL
CB2FARIP
SETCB 2SPCL 1
SPAR ReclaimTime
SETCB 23PCL
Logic 1
CB1LARIP
854
Auto Close CB1 & t 1568
& 1P Reclaim TComp
Auto Close CB2 1448 1 0
CB1FARIP
SETCB 1SPCL 1
1567
SETCB 13PCL & 1P Reclaim Time
SETCB 2SPCL &

CB2LARIP
CB2LFRC
&
SETCB 1SPCL 1
&
CB1LFRC
&
SETCB 2SPCL 1
&
CB2LFRC &
&
SETCB 13PCL
&
CB1LFRC 1
&
SETCB 23PCL
Dynamic F/L
Enabled
&
LeaderSPAR
SETCB 13PCL
CB2FARIP 3PAR ReclaimTime

1
SETCB 23PCL Logic 1
CB1LARIP t 1570
854
& 3P Reclaim TComp
Auto Close CB1 & 1 0
1448
Auto Close CB2
CB1FARIP 1569
1 & 3P Reclaim Time
SETCB 13PCL
SETCB 2SPCL &

CB2LARIP
Close Pulse Time
1567
1P Reclaim Time t
1569
1
3P Reclaim Time 0
&
Prot Re-op & CBARCancel
907
CB1 Closed 3 ph
1544
&
CB1 ARIP
915
CB2 Closed 3 ph 1
1435
&
CB2 ARIP
V03356
Figure 75: Reclaim Time logic diagram (Module 35)
160 P841B-TM-EN-1.1
5.14.3 SUCCESFUL AUTORECLOSE SIGNALS LOGIC DIAGRAM

1570
3P Reclaim TComp
1568
1
1P Reclaim TComp & S 1571
Q CB1 Succ 1P AR
RD
SetCB1SPCl 0
&
CB1OP1P 0.02S
907 & S
CB1 Closed 3 ph Q
R
ResCB1ARSucc 1 CB1ARSucc
1570
3P Reclaim TComp
1568
1
Q CB1 Succ 3P AR
RD
SetCB13PCl 0
&
CB1OP2/3P 0.02S
907 & S
CB1 Closed 3 ph Q
R
3P Reclaim TComp 1570
1568
1
Q CB2 Succ 1P AR
RD
SetCB2SPCl 0
&
CB2OP1P 0.02S
915 & S
CB2 Closed 3 ph Q
R
ResCB2ARSucc 1 CB2ARSucc
1570
3P Reclaim TComp
1568
1
Q CB2 Succ 3P AR
RD
SetCB23PCl 0
&
CB2OP2/3P 0.02S
915 & S
CB2 Closed 3 ph Q
R
1
V03359
Figure 76: Successful Autoreclose Signals logic diagram (Module 36)
P841B-TM-EN-1.1 161
5.14.4 AUTORECLOSE RESET SUCCESSFUL INDICATION LOGIC DIAGRAM
CB1OPAny
1541 1
AR Start
1 ResCB1 ARSucc
Res AROK by UI
Enabled
&
Reset AROK Ind
Yes
Res AROK by NoAR

Enabled
&
ARDisabled
1
Num CBs
CB1 Only
1517
Ext Rst CB1 AROK
&
Res AROK by Ext
Enabled
Res AROK by TDly

Enabled
&
AROK Reset Time
t
CB1 ARSucc
0
CB2OPAny
1541
1
AR Start
1 ResCB2 ARSucc
Res AROK by UI
Enabled
&
Reset AROK Ind
Yes
Res AROK by NoAR

Enabled
&
ARDisabled
1
Num CBs
CB1 Only
1417
Ext Rst CB2 AROK
&
Res AROK by Ext
Enabled
Res AROK by TDly

Enabled
&
AROK Reset Time
t
CB2 ARSucc
0 V03362
Figure 77: Autoreclose Reset Successful Indication logic diagram (Modules 37 & 38)
5.15 CB HEALTHY AND SYSTEM CHECK TIMERS

This logic provides signals to cancel Autoreclose if the circuit breaker is not healthy (for example low gas pressure)
or system check conditions are not satisfied (for example required line & bus voltage conditions) when the scheme
is ready to close the circuit breaker.
At the completion of a dead time, the logic starts an Autoreclose healthy timer. If a circuit breaker healthy signal
becomes high before the Autoreclose healthy time is complete, the timer stops and, if all other relevant circuit
breaker closing conditions are satisfied, the scheme issues a circuit breaker Autoclose signal. If the circuit breaker
healthy signal stays low, then, at the end of the Autoreclose healthy time, a circuit breaker unhealthy alarm is
raised. This forces the Autoreclose sequence to be cancelled.
Additionally, at the completion of any three-phase dead time, the logic starts an Autoreclose check synchronism
timer. If the circuit breaker synchronism-check OK signal goes high before the time is complete, the timer stops
and, if all other relevant circuit breaker closing conditions are satisfied, the scheme issues a circuit breaker
162 P841B-TM-EN-1.1
Autoclose signal. If the circuit breaker synchronism-check OK signal stays low, then when the Autoreclose check
synchronism timer expires, an alarm is set to inform that the check synchronism is not satisfied and cancels the
Autoreclose cycle.
5.15.1 CB HEALTHY AND SYSTEM CHECK TIMERS LOGIC DIAGRAM
CB Healthy Time
CB1L 3PAR
1555
OK Time 3P 1
1572
CB1 Fast SCOK
CB1SPDTComp
1
CB1 SPFTComp & S t 307
Q AR CB1 Unhealthy
RD 0
CB13 PDTComp
CB13PFTComp
CB1 Healthy 436
306
CB1 AR Lockout 1
907
CB1 Closed 3 Ph
Check Sync Time
CB13 PDTComp
1573
1 S
CB1 L SCOK Q t 308
RD 1 AR CB1 No C/S
0
306
CB1 AR Lockout
907 1
CB1 Closed 3 Ph
CB13PFTComp
1491
1 S Note : If the DDB signal CB1 Healthy is not mapped in PSL , it defaults to High .
CB1F SCOK Q
RD
306
CB1 AR Lockout
907
1
CB1 Closed 3 Ph
CB Healthy Time
CB2L 3PAR
1555
OK Time 3P 1
1454
CB2 Fast SCOK
CB2SPDTComp
1
CB2 SPFTComp & S t 329
Q AR CB2 Unhealthy
RD 0
CB23 PDTComp
CB23PFTComp
437
CB2 Healthy
328
CB2 AR Lockout 1
915
CB2 Closed 3 Ph
Check Sync Time
CB23 PDTComp
1455
1 S
CB2 L SCOK Q t 330
RD 1 AR CB2 No C/S
0
328
CB2 AR Lockout
915 1
CB2 Closed 3 Ph
CB23PFTComp
1456 1 S Note : If the DDB signal CB2 Healthy is not mapped in PSL , it defaults to High .
CB2F SCOK Q
RD
328
CB2 AR Lockout
915
1
CB2 Closed 3 Ph V03364
Figure 78: Circuit Breaker Healthy and System Check Timers Healthy logic diagram (Module 39)
5.16 AUTORECLOSE SHOT COUNTERS

A number of counters are provided to enable analysis of circuit breaker Autoreclose history. The counters are
stored in non-volatile memory, so that the data is maintained even in the event of a failure of the auxiliary supply.
P841B-TM-EN-1.1 163
The counter values are accessible through the CB CONTROL column. The counters can be reset manually, or by
activation of an input appropriately mapped in the PSL.
The logic provides the following summary information for each circuit breaker
● Overall total number of shots (Number of Autoreclose attempts)
● Number of successful 1st shot single-phase Autoreclose sequences
● Number of successful 1st shot three-phase Autoreclose sequences
● Number of successful 2nd shot three-phase Autoreclose sequences
● Number of successful 3rd shot three-phase Autoreclose sequences
● Number of successful 4th shot three-phase Autoreclose sequences
● Number of failed Autoreclose cycles which forced a circuit breaker to lockout
164 P841B-TM-EN-1.1
5.16.1 AUTORECLOSE SHOT COUNTERS LOGIC DIAGRAM
1565
Set CB1 Close Increment
CB1 Total Shots Counter
Reset
1571
CB1 Succ 1P AR Increment
CB1 Successful SPAR Shot 1 Counter
852 Reset
CB1 Succ 3P AR
847 & Increment

Seq Counter = 1 CB1 Successful 3PAR Shot 1 Counter
Reset
& Increment
848
Reset
849
& Increment
Reset
850
& Increment
Reset
1544
0
CB1 Arip
0.02 & Increment
CB1 Failed AR Counter
Reset
306
CB1 AR Lockout
1518
Ext Rst CB1Shots
1
Reset CB Shots
Yes
1449
Set CB2 Close Increment
CB2 Total Shots Counter
Reset
1451
CB2 Succ 1P AR Increment
CB2 Successful SPAR Shot 1 Counter
1452 Reset
CB2 Succ 3P AR
847 & Increment

Reset
& Increment
848
Reset
849
& Increment
Reset
850 & Increment

Reset
1435
0
CB2 Arip
0.02 & Increment
CB2 Failed AR Counter
Reset
328
CB2 AR Lockout
1418
Ext Rst CB2Shots
1
Reset CB Shots
Yes V03367
Figure 79: Autoreclose Shot Counters logic diagram (Modules 41 & 42)
P841B-TM-EN-1.1 165
5.17 CIRCUIT BREAKER CONTROL
5.17.1 CB CONTROL LOGIC DIAGRAM
CB Control by
Opto
Note : If the DDB signal CB1 Healthy or CB2 Healthy is not mapped in PSL , it
Opto +Local defaults to High .
1
Opto+Remote
Opto+Rem+Local
Trip Pulse Time
838
HMI Trip Control TripCB1
1
& S t
439
& Q 302
Init Trip CB1 RD 0 & CB1 Trip Fail
440 &
Init close CB1 Man Close Delay Close Pulse Time
1 842
CB1 Close inProg
HMI Close
& S t
CB1 ARIP 1544 Q 839
RD 0 & Control CloseCB1
854
1 S t
Auto Close CB1 Q
RD 0
443
Rst CB1 CloseDly
522 303
Any Trip & CB1 Close Fail
1
838
Control TripCB1
534
CB1 Ext Trip3ph 1
1
535
CB1 Ext Trip A
536
CB1 Ext Trip B
537
CB1 Ext Trip C
1 1
903
CB1 Open 3 ph
1
904
CB1 Open A ph
905
CB1 Open B ph &
906
CB1 Open C ph
907
CB1 Closed 3 ph
1
908
CB1 Closed A ph
CB1 Closed B ph 909

1 CB Healthy Time
910
CB1 Closed C ph
t 304
436
& ManCB1 Unhealthy
CB1 Healthy 0
Check Sync Time
t 305
1574
& NoCS CB1ManClose
CB1 Man SCOK 0
V03370
Figure 80: CB1 Control Logic (Module 43)
166 P841B-TM-EN-1.1
CB Control by
Opto
Opto +Local Note: If the DDB signal CB 1 Healthy, or CB2 healthy is not mapped in PSL , it defaults to
1 High.
Opto+Remote
Opto+Rem+Local
Trip Pulse Time
840
1
& S t
441
& Q 324
442 &
1 1453
CB2 Close inProg
HMI Close
& S t
CB2 ARIP 1435 Q 841
1448
1 S t
Auto Close CB2 Q
RD 0
1419
Rst CB2 CloseDly
522 325
1
840
Control TripCB2
538
CB2 Ext Trip3ph 1
1
539
CB2 Ext Trip A
540
CB2 Ext Trip B
541
CB2 Ext Trip C
1 1
911
CB2 Open 3 ph
912
CB2 Open A ph
913
CB2 Open B ph &
914
CB2 Open C ph
915
CB2 Closed 3 ph
1
916
CB2 Closed A ph
CB2 Closed B ph 917

1 CB Healthy Time
918
CB2 Closed C ph
t 326
437
& ManCB2 Unhealthy
CB2 Healthy 0
Check Sync Time
t 327
1458
& NoCS CB2ManClose
CB2 Man SCOK 0
V03344
5.18 CIRCUIT BREAKER TRIP TIME MONITORING

The circuit breaker trip time monitoring logic checks for correct circuit breaker tripping following the issue of a
protection trip signal. When the protection trip signal is issued, a timer controlled by the Trip Pulse Time setting in
the CB CONTROL column is started.
If the circuit breaker trips correctly the timer resets. If Autoreclose is enabled and the timer resets, the cycle
continues. If the circuit breaker fails to trip correctly within the set time, the Autoreclose cycle is forced to lock out
and a signal is issued indicating that the circuit breaker failed to trip in response to the protection operation.
P841B-TM-EN-1.1 167
5.18.1 CB TRIP TIME MONITORING LOGIC DIAGRAM
Trip Pulse Time
TAR2/3Ph S t
Q 1575
RD 0 1 CB1 Fail Pr Trip
903
& S
CB1 Open 3 Ph Q
RD
907
CB1 Closed 3 Ph
Trip Pulse Time
TARA
& S
TMEM2 /3Ph Q t
RD 1
0
903 & S
CB1 Open 3 Ph Q
RD
907
CB1 Closed 3 Ph 1
TARB
& S
TMEM2 /3Ph Q
RD
903
& S
CB1 Open 3 Ph Q
RD
907
CB1 Closed 3 Ph 1
TARC
& S
TMEM2 /3Ph Q
RD
903 & S
CB1 Open 3 Ph Q
RD
907
CB1 Closed 3 Ph 1
Trip Pulse Time
TAR2/3Ph S t
Q 1459
RD 0 1 CB2 Fail Pr Trip
911 & S
CB2 Open 3 Ph Q
RD
915
CB2 Closed 3 Ph
Trip Pulse Time
TARA
& S
TMEM2 /3Ph Q t
RD 1
0
911 & S
CB2 Open 3 Ph Q
RD
915
CB2 Closed 3 Ph 1
TARB
& S
TMEM2 /3Ph Q
RD
911
& S
CB2 Open 3 Ph Q
RD
915
CB2 Closed 3 Ph 1
TARC
& S
TMEM2 /3Ph Q
RD
911 & S
CB2 Open 3 Ph Q
RD
915
CB2 Closed 3 Ph 1
V03377
Figure 82: Circuit Breaker Trip Time Monitoring logic diagram (Modules 53 & 54)
168 P841B-TM-EN-1.1
5.19 AUTORECLOSE LOCKOUT

A number of events will cause Autoreclose lockout. If this happens an Autoreclose lockout alarm is raised. In this
condition, Autoreclose cannot be initiated until the corresponding lockout has been reset.
The following events force Autoreclose lockout:
● Protection operation during reclaim time. Following the final Autoreclose attempt, if the protection operates
during the reclaim time, the AR cycle goes to AR lockout and the Autoreclose function is disabled until the
AR lockout condition is reset.
● Persistent fault. A fault is considered persistent if the protection re-operates after the last permitted shot.
● Block Autoreclose. If the block Autoreclose DDB is asserted whilst Autoreclose is in progress, the cycle goes
to lockout.
● Protection function selection. Setting ‘Block AR’ against a particular protection function in the AUTORECLOSE
column means that operation of the protection will block Autoreclose and force lockout.
● Circuit breaker failure to close. If a circuit breaker fails to close Autoreclose is blocked and forced to lockout.
● Circuit breaker remains open at the end of the reclaim time. An Autoreclose lockout is forced if the circuit
breaker is open at the end of the reclaim time.
● Circuit breaker fails to close when the close command is issued.
● Circuit breaker fails to trip correctly.
● Three-phase dead time started by ‘line dead’ violation. If the line does not go dead within the Dead Line
Time setting, the logic forces the Autoreclose sequence to lockout. Determination of when to start the timer
is made in the 3PDTStart WhenLD setting.
● Block Follower if Leader fails to close is set. If the setting BF if Lfail Cls in the AUTORECLOSE column is set to
Enable, the active Follower circuit breaker will lockout if the Leader circuit breaker fails to reclose.
● Leader/Follower invalid selection using opto-isolated input. If the Leader/Follower Autoreclose mode in the
AUTORECLOSE settings is set to be selected using the opto-isolated inputs, then if the logic detects an invalid
Autoreclose mode combination, it forces both circuit breakers to lockout if a trip occurs.
P841B-TM-EN-1.1 169
5.19.1 CB LOCKOUT LOGIC DIAGRAM
FLTMEM3P
&
Multi Phase AR
BAR 3 Phase
1
BAR 2 and 3 ph
&
FLTMEM2P
303
CB1 Close Fail
BF if LFail Cls
& 306
CB1 AR Lockout
Enabled
CB2 LFRC
& 1385
CB1 FARIP AR In Service
&
CB2 AR Lockout 328
Num CBs & S
Q
1575 Both CB 1&CB2 R
CB1 Fail Pr Trip 1
CB1 Only
CB1OpAny
1544
CB1 ARIP & RESCB1LO
Block CB1 AR 448 &
307
AR CB1 Unhealthy
308
AR CB1 No C/S
1547 S
Evolve 3Ph
Q
PROTRE-OP R
LastShot &
1544
CB1 ARIP
EVOLVELOCK & 1 BARCB1
ProtARBlock
1526
CB1 In Service
&
TMEM2 /3Ph
CB1L3 PAROK 0
1
CB1 F3 PAROK 0.02s
1526
CB1 In Service
&
TMEM1Ph
CB1 LSPAROK 0 Note: This diagram shows the logic for CB 1 only. The logic for CB2 follows the same
1 principles and is not repeated .
CB1 FSPAROK 0.02s
1546
Seq Counter >Set
301
CB1 Status Alm
CB1 LARIP Trip Pulse Time

1
CB1 FARIP
Set CB1 Close 1565 t

&
Set CB2 Close 1449 0
CB2OpAny
1428
&
CB2 In Service
1526
CB1 In Service
&
Num CBs
&
Both CB1 &CB2
CB2 Fail Pr Trip 1459
InvalidAR Mode
&
1543
CB1 AR Init
1544 1
CB1 ARIP
DeadLineLockout V03380
Figure 83: CB1 Lockout Logic Diagram (Module 55)
170 P841B-TM-EN-1.1
FltMem3P
&
Multi Phase AR
BAR 3 Phase
1
BAR 2 and 3 ph
&
FltMem2P
325
CB2 Close Fail
BF if LFail Cls
& 328
CB2 AR Lockout
Enabled
CB1 LFRC
& 1385
CB2FARIP AR In Service
&
CB1 AR Lockout 306
Num CBs & S
Q
1459 Both CB 1&CB2 R
CB2 Fail Pr Trip 1
CB1 Only
CB2OpAny
1435
CB2 ARIP & ResCB2Lo
Block CB2 AR 1421 &
329
AR CB2 Unhealthy
330
AR CB2 No C/S
1547 S
Evolve 3Ph
Q
ProtRe_Op R
LastShot &
1435
CB2 ARIP
EvolveLock & 1 BARCB2
ProtARBlock
1428
CB2 In Service
&
TMEM2 /3Ph
CB2L3PAROK 0
1
CB2 F3 PAROK 0.02s
1428
CB2 In Service
&
TMEM1Ph
CB2LSPAROK 0
1
CB2FSPAROK 0.02s
1546
Seq Counter >Set
323
CB2 Status Alm
CB2 LARIP Trip Pulse Time

1
CB2FARIP
Set CB2 Close 1449 t

&
Set CB1 Close 1565 0
CB1OpAny
1526
&
CB1 In Service
1428
CB2 In Service
&
Num CBs
&
Both CB1 &CB2
CB1 Fail Pr Trip 1575
Invalid_AR_Mode
&
1434
CB2 AR Init
1435 1
CB2 ARIP
DeadLineLockout V03403
Figure 84: CB2 Lockout Logic Diagram (Module 56)
5.20 RESET CIRCUIT BREAKER LOCKOUT

Lockout conditions caused by the circuit breaker condition monitoring functions can be reset according to the
condition of the Rst CB mon LO by setting found in the CB CONTROL column. There are two options; CB Close
and User interface.
P841B-TM-EN-1.1 171
If set to CB Close, a timer setting, CB mon LO RstDly, becomes visible. When the circuit breaker closes, the CB
mon LO RstDly time starts. The lockout is reset when the timer expires.
If set to User Interface then a command, CB mon LO reset, becomes visible. This command can be used to
reset the lockout from a user interface.
An Autoreclose lockout generates an Autoreclose lockout alarm. Autoreclose lockout conditions can be reset by
various commands and setting options found under the CB CONTROL column.
If Res LO by CB IS is set to Enabled, a lockout is reset if the circuit breaker is successfully closed manually. For
this, the circuit breaker must remain closed long enough so that it enters the “In Service” state.
If Res LO by UI is set to Enabled, the circuit breaker lockout can be reset from a user interface using the reset
circuit breaker lockout command in the CB CONTROL column.
If Res LO by NoAR is set to Enabled, the circuit breaker lockout can be reset by temporarily generating an AR
disabled signal.
If Res LO by TDelay is set to Enabled, the circuit breaker lockout is automatically reset after a time delay set in
the LO Reset Time setting.
If Res LO by ExtDDB is Enabled, the circuit breaker lockout can be reset by activation of an external input
mapped in the PSL to the relevant reset lockout DDB signal.
172 P841B-TM-EN-1.1
5.20.1 RESET CB LOCKOUT LOGIC DIAGRAM
Res LO by CB IS
Enabled
&
CB1CRLo
Res LO by UI
Enabled
&
Reset CB1 LO
Yes
Res LO by NoAR
Enabled
& 1 ResCB1Lo
ARDisabled
1
Num CBs
CB2 Only
Res LO by ExtDDB
Enabled
&
446
Rst CB1 Lockout
Res LO by TDelay
Enabled
&
LO Reset Time
306
t
CB1 AR Lockout
0
Res LO by CB IS
Enabled
&
CB2CRLo
Res LO by UI
Enabled
&
Reset CB2 LO
Yes
Res LO by NoAR
Enabled
& 1 ResCB2Lo
ARDisabled
1
Num CBs
CB2 Only
Res LO by ExtDDB
Enabled
&
1422
Rst CB2 Lockout
Res LO by TDelay
Enabled
&
LO Reset Time
328
t
CB2 AR Lockout
0
V03383
Figure 85: Reset Circuit Breaker Lockout Logic Diagram (Modules 57 & 58)
5.21 POLE DISCREPANCY

In a three-pole CB, certain combinations of poles open and closed are indicative of a problem. The Pole
Discrepancy Logic combines an indication of a Pole Discrepancy condition from the CB Monitoring logic with
signals from the internal Autoreclose logic to produce a combined Pole Discrepancy indication for the CB.
P841B-TM-EN-1.1 173
5.21.1 POLE DISCREPANCY LOGIC DIAGRAM

306
CB1 AR Lockout
1 0.04 699
CB1 LO Alarm 860 & Pole Discrep CB1
0
451
Pol Disc CB1 Ext
845 &
CB1 AR 1 p InProg
904
CB1 Open A ph
1
905
CB1 Open B ph
906
CB1 Open C ph
&
328
CB2 AR Lockout
1 0.04 1607
CB2 LO Alarm 1599 & Pole Discrep CB2
0
1606
Pol Disc CB2 Ext
855 &
CB2 AR 1 p InProg
912
CB2 Open A ph
1
913
CB2 Open B ph
914
CB2 Open C ph
&
V03385
Figure 86: Pole Discrepancy Logic Diagram (Module 62)
5.22 CIRCUIT BREAKER TRIP CONVERSION

Circuit breakers should only trip single-pole or three-pole. The trip conversion logic ensures that the tripping is
either single-pole or three-pole. The trip conversion logic ensures that all conditions that should cause three-pole
tripping do so. Indication of the number of phases that caused tripping is provided.
174 P841B-TM-EN-1.1
5.22.1 CB TRIP CONVERSION LOGIC DIAGRAM

530
Trip Inputs A
1 S 523
Q CB1 Trip OutputA
R
531
Trip Inputs B
1 S 524
Q CB1 Trip OutputB
R
532
Trip Inputs C
1 S 525
Q CB1 Trip OutputC
R
CB1Tripping Mode 1
&
3 Pole 1 S 526
Q CB1 Trip 3ph
858 R
AR Force CB1 3P 1
533
Force 3PTrip CB1
529
CB1 Trip I/P 3Ph
530
Trip Inputs A
1 S 1601
Q CB2 Trip OutputA
R
531
Trip Inputs B
1 S 1602
Q CB2 Trip OutputB
R
532
Trip Inputs C
1 S
1603
Q CB2 Trip OutputC
1 R
CB2Tripping Mode &
3 Pole 1 S 1600
Q CB2 Trip 3ph
1485 R
AR Force CB2 3P 1
Force 3PTrip CB2 1604
1608
CB2 Trip I/P 3Ph
Dwell
522
1 Any Trip
530 100 ms
Trip Inputs A
531
Trip Inputs B
≥ S
Trip Inputs C 532 2 Q
527
2/3 Ph Fault
R
892
Pole Dead A &
1 S 528
Q 3 Ph Fault
R
893
& 1
Pole Dead B 1
&
894 1
Pole Dead C
&
V03387
Figure 87: Circuit Breaker Trip Conversion Logic Diagram (Module 63)
5.23 MONITOR CHECKS FOR CB CLOSURE

For single-phase Autoreclose neither voltage nor synchronisation checks are needed as synchronising power
should be flowing in the two healthy phases. For three-phase Autorelcose, for the first shot (and only the first shot),
you can choose to attempt reclosure without performing a synchronisation check. The setting to permit
Autoreclose without checking synchronising conditions is CB SC Shot 1.
Otherwise, synchronising checks on voltages, relative frequencies, and relative phase angles are needed to ensure
that sympathetic conditions exist before CB closure is attempted.
The following diagrams detail the Monitor Checks for CB closure.
P841B-TM-EN-1.1 175
5.23.1 VOLTAGE MONITOR FOR CB CLOSURE
System Checks
Enabled
VAN 888
Live Line & Live Line
VBN
VCN 889
Select Dead Line & Dead line
VAB
VBC 886
Live Bus 1 & Live Bus 1
VCA
VBus1 Dead Bus 1 & 887

Dead Bus 1
VBus 2
1461
MCB/VTS 438
1521 1462
MCB/VTS CB1 CS Dead Bus 2 & Dead Bus 2
1423
MCB/VTS CB2 CS
Voltage Monitors
1522 1
Inhibit LL
1523 1
Inhibit DL
1524 1
Inhibit LB 1
1525
1
Inhibit DB 1
1424 1
Inhibit LB 2
1425 1
Inhibit DB 2
V 01258
Figure 88: Voltage Monitor for CB Closure (Module 59)
176 P841B-TM-EN-1.1
5.23.2 CHECK SYNCHRONISATION MONITOR FOR CB CLOSURE
Sys checks CB 1
880
Disabled SChksInactiveCB 1
Enabled
CS1 Criteria OK
VAN &
VBN CS2 Criteria OK
&
VCN
Select CB1 CS1 SlipF> 1578
VAB & CB1 CS1 SlipF>
VBC CB1 CS1 SlipF< 1579

& CB1 CS1 SlipF<
VCA CB1 CS2 SlipF> 1464
& CB1 CS2 SlipF>
VBus1
CB1 CS2 SlipF< 1465
& CB1 CS2 SlipF<
CS Vline> 1581
& CS Vline>
CS Vbus1> 1583
& CS Vbus1>
CS Vline< 1580
& CS Vline<
Check Synchronisation Function
CS Vbus1< 1582
& CS Vbus<
CB1 CS1 Vl>Vb 1586
& CB1 CS1 Vl> Vb
CB1 CS1 Vl<Vb 1588
& CB1 CS1 Vl< Vb
CB1 CS1 Fl>Fb 1590
& CB1 CS1 Fl>Fb
CB1 CS1 Fl<Fb 1591
& CB1 CS1 Fl<Fb
CB1 CS1 AngHigh+ 1592
& CB1 CS1 AngHigh+
CB1 CS1 AngHigh- 1593
& CB1 CS1 AngHigh-
CB1 CS2 Fl>Fb 1493
& CB1 CS2 Fl>Fb
CB1 CS2 Fl<Fb 1494
& CB1 CS2 Fl<Fb
& CB1 CS2 AngHigh+
& CB1 CS2 AngHigh-
CB1 CS AngRotACW 1594
& CB1 CS AngRotACW
1521
MCB/VTS CB CS CB1 CS AngRotCW 1595
438 & CB1 CS AngRotCW
MCB/VTS
832 CB1 CS2 Vl>Vb 1587
VTS Fast Block & CB1 CS2 Vl> Vb
1
319
F out of Range CB1 CS2 Vl<Vb 1589
& CB1 CS2 Vl< Vb
CB1 CS1 Status
883
Enabled & CB1 CS1 OK
881
CB1 CS1 Enabled
CB1 CS2 Status
884
882
CB1 CS2 Enabled V01260
Figure 89: Check Synchronisation Monitor for CB1 closure (Module 60)
P841B-TM-EN-1.1 177
Sys checks CB 2
1484
Enabled
CS1 Criteria OK
VAN &
VBN CS1 Criteria OK

&
VCN

& CB2 CS1 SlipF<
& CB2 CS2 SlipF>
VBus2
CB2 CS2 SlipF< 1469
& CB2 CS2 SlipF<
&
CS Vbus2> 1585
& CS Vbus2>
&
CS Vbus2<
1584
& CS Vbus2<
CB2 CS1 Vl>Vb 1470
& CB2 CS1 Vl> Vb
CB2 CS1 Vl<Vb 1472
& CB2 CS1 Vl< Vb
CB2 CS1 Fl>Fb 1474
& CB2 CS1 Fl>Fb
CB2 CS1 Fl<Fb 1476
& CB2 CS1 Fl<Fb
& CB2 CS1 AngHigh+
& CB2 CS1 AngHigh-
CB2 CS2 Fl>Fb 1475
& CB2 CS2 Fl>Fb
CB2 CS2 Fl<Fb 1477
& CB2 CS2 Fl<Fb
& CB2 CS2 AngHigh+
& CB2 CS2 AngHigh-
& CB2 CS AngRotACW
1521
MCB/VTS
832 CB2 CS2 Vl>Vb 1471
1
319
& CB2 CS2 Vl< Vb
CB2 CS1 Status
1577
1426
CB2 CS1 Enabled
CB2 CS2 Status
884
1427
5.24 SYNCHRONISATION CHECKS FOR CB CLOSURE

Logical checking of the outputs from the CB closure monitors is performed to generate signals to indicate that it is
OK to close circuit breakers.
Signals are provided to indicate that manual CB closure conditions are OK (CB Man SCOK), as are signals to
indicate that automatic CB closure conditions are OK (CB SCOK and CB Fast SCOK). The CB Fast SCOK signal
allows CB autoreclosure without waiting for the Dead Time to expire.
178 P841B-TM-EN-1.1
For single-phase Autoreclose no voltage or synchronism check is required as synchronising power is flowing in the
two healthy phases. Three-phase Autoreclose can be performed without checking that voltages are in
synchronism for the first shot (and only the first shot). The settings to permit Autoreclose without checking voltage
synchronism on the first shot are:
● CB1L SC Shot 1 for circuit breaker 1 as a leader,
● CB1F SC Shot 1 for circuit breaker 1 as a follower,
● CB2L SC Shot 1 for circuit breaker 2 as a leader,
● CB2L SC Shot 1 for circuit breaker 2 as a follower.
When the circuit breaker has closed, the Autoreclose function asserts a DDB signal Set CB1 Close, which indicates
that an attempt has been made to close the circuit breaker. At this point, the Reclaim Time starts. If the circuit
breaker remains closed after the reclaim timer expires, the Autoreclose cycle is complete, and signals are
generated to indicate that Autoreclose was successful. These are:
● CB1 Succ 1P AR (Single-phase Autoreclose CB1)
● CB2 Succ 1P AR (Single-phase Autoreclose CB2)
● CB1 Succ 3P AR (Three-phase Autoreclose CB1)
● CB2 Succ 3P AR (Three-phase Autoreclose CB2)
These signals increment the relevant circuit breaker successful Autoreclose shot counters, as well as resetting the
Autoreclose in progress signal.
The relevant circuit breaker successful Autoreclose shot counters are:
● CB1 SUCC SPAR (Single-phase Autoreclose CB1)
● CB1 SUCC 3PAR Shot1 (Three-phase Autoreclose CB1, Shot 1)
● CB2 SUCC SPAR (Single-phase Autoreclose CB2)
P841B-TM-EN-1.1 179
5.24.1 THREE-PHASE AUTORECLOSE LEADER CHECK LOGIC DIAGRAM
CB1L SC ClsNoDly
Enabled 1572
& CB1 Fast SCOK
CB1 L SC CS1
Enabled 1
&
883
CB1 CS1 OK
CB1 L SC CS2
Enabled
&
884
CB1 CS2 OK
CB1L SC DLLB
Enabled
889 &
Dead Line
886
Live Bus 1
CB1L SC LLDB
Enabled
1573
888 & 1 CB1 L SCOK
Live Line
887
Dead Bus 1
CB1L SC DLDB
Enabled
889
&
Dead Line
887 Note: If the DDB signal CB1 Ext CS OK is not mapped in PSL , it defaults to High .
Dead Bus 1
CB1L SC Shot 1
Disabled
&
847
Seq Counter = 1
CB1L SC all
Disabled
&
900
CB1 Ext CS OK V03373
Figure 91: Three-phase AR System Check logic diagram for CB1 as leader (Module 45)
180 P841B-TM-EN-1.1
CB2L SC ClsNoDly
Enabled 1454
& CB2 Fast SCOK
CB2 L SC CS1
Enabled 1
&
1577
CB2 CS1 OK
CB2 L SC CS2
Enabled
&
1463
CB2 CS2 OK
CB2L SC DLLB
Enabled
889 &
Dead Line
1461
Live Bus 2
CB2L SC LLDB
Enabled
1455
888 & 1 CB2 L SCOK
Live Line
887
Dead Bus 1
CB2L SC DLDB
Enabled
889
&
Dead Line
1462
Dead Bus 2
CB2L SC Shot 1 Note: If the DDB signal CB2 Ext CS OK is not mapped in PSL , it defaults to
High.
Disabled
&
847
Seq Counter = 1
CB2L SC all
Disabled
&
901
Figure 92: Three-phase AR System Check logic diagram for CB2 as leader (Module 46)
P841B-TM-EN-1.1 181
5.24.2 THREE-PHASE AUTORECLOSE FOLLOWER CHECK LOGIC DIAGRAM
&
CB1F SC CS1
Enabled 1
&
883
CB1 CS1 OK
CB1F SC CS2
Enabled
&
884
CB1 CS2 OK
CB1F SC DLLB
Enabled
889 &
Dead Line
886
Live Bus 1
CB1F SC LLDB
Enabled
1491
888
& 1 CB1F SCOK
Live Line
Dead Bus 1 887
CB1 F SC DLDB
Enabled
889 &
Dead Line
Dead Bus 1 887 Note: If the DDB signal CB1 Ext CS OK is not mapped in PSL , it
defaults to High .
CB1 F SC Shot 1
Disabled
&
847
Seq Counter = 1
CB1F SC all
Disabled
&
900
Figure 93: Three-phase AR System Check logic d for CB1 as follower (Module 47)
182 P841B-TM-EN-1.1
&
CB2F SC CS1
Enabled 1
&
1577
CB2 CS1 OK
CB2F SC CS2
Enabled
&
1463
CB2 CS2 OK
CB2F SC DLLB
Enabled
889 &
Dead Line
1461
Live Bus 2
CB2F SC LLDB
Enabled
1456
888
& 1 CB2F SCOK
Live Line
Dead Bus 1 887
CB2 F SC DLDB
Enabled
889 &
Dead Line
Dead Bus 2 1462 Note: If the DDB signal CB2 Ext CS OK is not mapped in PSL , it
defaults to High .
CB2 F SC Shot 1
Disabled
&
847
Seq Counter = 1
CB2F SC all
Disabled
&
901
Figure 94: Three-phase AR System Check logic diagram for CB2 as follower (Module 48)
P841B-TM-EN-1.1 183
5.24.3 CB MANUAL CLOSE SYSTEM CHECK LOGIC DIAGRAM
CB1 M SC CS1
Enabled
&
883
CB1 CS1 OK
CB1 M SC CS2
Enabled
&
884
CB1 CS2 OK
CB1M SC DLLB
Enabled
889
&
Dead Line
886
Live Bus 1
CB1M SC LLDB
Enabled
1574
888 & 1 CB1 Man SCOK
Live Line
887
Dead Bus 1
CB1 M SC DLDB
Enabled Note : If the DDB signal CB1 Ext CS OK is not mapped in PSL , it
& defaults to High .
889
Dead Line
Dead Bus 1 887
CB1M SC required
Disabled
&
900
CB1 Ext CS OK
CB2 M SC CS1
Enabled
&
1577
CB2 CS1 OK
CB2 M SC CS2
Enabled
&
1463
CB2 CS2 OK
CB2M SC DLLB
Enabled
889 &
Dead Line
1461
Live Bus 2
CB2M SC LLDB
Enabled
1458
888 & 1 CB2 Man SCOK
Live Line
1462
Dead Bus 2
CB2 M SC DLDB
Enabled
889
&
Dead Line Note: If the DDB signal CB2 Ext CS OK is not mapped in PSL , it
defaults to High .
1462
Dead Bus 2
CB2M SC required
Disabled
&
901
Figure 95: CB Manual Close System Check Logic Diagram (Modules 51 & 52)
184 P841B-TM-EN-1.1
6 SETTING GUIDELINES
6.1 DE-IONISING TIME GUIDANCE

The de-ionisation time of a fault arc depends on several factors such as circuit voltage, conductor spacing, fault
current and duration, atmospheric conditions, wind speed and capacitive coupling from adjacent conductors. For
this reason it is difficult to estimate the de-ionisation time. Circuit voltage is, generally the most significant factor
and experience tells us that typical minimum de-ionising times for a three-phase fault are as follows:
● 66 kV: 100 ms
● 110 kV: 150 ms
● 132 kV: 170 ms
● 220 kV: 280 ms
● 275 kV: 300 ms
● 400 kV: 500 ms
Where single-pole high speed Autoreclose is used, the capacitive current induced between the healthy phases and
the faulty phase tends to maintain the arc. This significantly increases the de-ionisation time and hence required
dead time.
Single-pole Autoreclose is generally only used at transmission voltages. A typical de-ionisation time at 220 kV may
be as high as 560 ms.
6.2 DEAD TIMER SETTING GUIDELINES

High speed Autoreclose may need to maintain stability on a network with two or more power sources. For high
speed Autoreclose the system disturbance time should be minimised by using fast protection (typically <30 ms)
and fast circuit breakers (typically <60 ms). For stability between two sources a system dead time of ≤300 ms may
typically be required.
The minimum system dead time (considering just the circuit breaker) is the trip mechanism reset time plus the
circuit breaker closing time.
The Autoreclose minimum dead time settings are governed primarily by two factors:
● Time taken for de-ionisation of the fault path
● Circuit breaker characteristics
It is essential that the protection fully resets during the dead time, so that correct time discrimination will be
maintained after Autoreclose onto a fault. For high speed Autoreclose instantaneous reset of protection is
required.
For highly interconnected systems synchronism is unlikely to be lost by the tripping out of a single line. Here the
best policy may be to adopt longer dead times, to allow time for power swings resulting from the fault to settle.
6.2.1 EXAMPLE DEAD TIME CALCULATION

The following circuit breaker and system characteristics can be used for the minimum dead time calculation:
● a) Circuit breaker Operating time (Trip coil energized to Arc interruption): 50 ms
● b) Circuit breaker Opening + Reset time (Trip coil energized to trip mechanism reset): 200 ms
● c) Protection reset time: < 80 ms
● d) Circuit breaker Closing time (Close command to Contacts make): 85 ms
● e) De-ionisation time (280 ms for 3-phase, or 560 ms for 1-phase)
Three-phase de-ionisation time for 220 kV line is typically 280 ms.
The minimum Autoreclose dead time setting is therefore the greater of:
(a) + (c) = 50 ms + 80 ms = 130 ms, to allow protection reset
P841B-TM-EN-1.1 185
(a) + (e) - (d) = 50 ms + 280 ms - 85 ms = 245 ms, to allow de-ionising

In practice a few additional cycles would be added to allow for tolerances, so Dead Time 1 could be set to 300 ms
or greater. The overall system dead time is found by adding (d) to the chosen settings then subtracting (a). This
gives 335 ms.
A typical de-ionising time value for single-phase trip on a 220 kV line is 560 ms, so the 1 Pole Dead Time could be
chosen as 600 ms or greater. The overall system dead time is found by adding (d) to the chosen settings then
subtracting (a). This gives 635 ms.
6.3 RECLAIM TIME SETTING GUIDELINES

Several factors influence the choice of the reclaim timer, such as:
● Fault incidence/Past experience: Small reclaim times may be required where there is a high incidence of
recurrent lightning strikes to prevent unnecessary lockout for transient faults.
● Spring charging time: For high speed Autoreclose the reclaim time may be set longer than the spring
charging time. A minimum reclaim time of more than 5s may be needed to allow the circuit breaker time to
recover after a trip and close before it can perform another trip-close-trip cycle. This time will depend on the
duty (rating) of the circuit breaker. For delayed Autoreclose this may not be needed as the dead time can be
extended by an extra circuit breaker healthy check / Autoreclose Inhibit Time window time if there is
insufficient energy in the circuit breaker.
● Switchgear Maintenance: Excessive operation resulting from short reclaim times can mean shorter
maintenance intervals.
When used in conjunction with distance protection, the Reclaim Time setting is generally set greater than the zone
2 delay.
6.4 AUTORECLOSE SHOT COUNTERS

In dual circuit breaker applications, the two circuit breakers are normally arranged to reclose sequentially with one
designated the Leader circuit breaker reclosing after a set dead time. If the Leader circuit breaker remains closed
after the dead time, the second circuit breaker referred to as the Follower recloses after a further delay, the
Follower Time.
The Follower Time is provided to prevent un-necessary operation of the Follower circuit breaker. The Follower Time
should be set sufficiently long as to avoid an un-necessary closure of the Follower circuit breaker where conditions
are such that it would be required to trip again.
After expiry of the dead time, the Leader circuit breaker will attempt Autoreclose. The minimum value of the
Follower time should allow sufficient time for the Autoreclose of the Leader circuit breaker to be considered
successful.
An extreme case may be where instantaneous protection is only provided by distance elements and where
Autoreclose is onto a dead line with a persistent fault at the remote end of the line.
Local end protection (Time delayed Back up protection, like distance Z2 element) may detect this fault after a time
delay (typically > 200 ms). In addition to the delays associated with the back-up protection (typically >200 ms), time
must be allowed for the Leader circuit breaker to re-trip (50 - 100 ms), and a safety margin needs to be added so
that a minimum Follower time could be around 500 ms.
If the Autoreclose of the Leader circuit breaker is successful, the Follower circuit breaker can be allowed to
Autoreclose. Delaying the Autoreclose of the Follower circuit breaker will allow any transients to decay before the
switching. If the transient decay figure is known, it can be used to determine a minimum Follower Time value. The
larger of the two values can then be used as the minimum Follower Time.
186 P841B-TM-EN-1.1
Note:
The Follower circuit breaker should only be reclosed if the system is healthy. In a dual circuit breaker scheme where the
system is healthy, the Follower circuit breaker acts more like a bus coupler. In this case there is no need for fast switching and
a time delay in excess of 1s is often appropriate. The default Follower time in this product is chosen as 5 s and this can
comfortably be applied to most applications.
P841B-TM-EN-1.1 187
188 P841B-TM-EN-1.1
CHAPTER 7
CB FAIL PROTECTION
Chapter 7 - CB Fail Protection P841B
190 P841B-TM-EN-1.1
P841B Chapter 7 - CB Fail Protection
1 CHAPTER OVERVIEW
The device provides a Circuit Breaker Fail Protection function. This chapter describes the operation of this function
including the principles, logic diagrams and applications.
Chapter Overview 191
Circuit Breaker Fail Protection 192
Circuit Breaker Fail Implementation 193
Circuit Breaker Fail Logic 195
Application Notes 199
P841B-TM-EN-1.1 191
2 CIRCUIT BREAKER FAIL PROTECTION

When a fault occurs, one or more protection devices will operate and issue a trip command to the relevant circuit
breakers. Operation of the circuit breaker is essential to isolate the fault and prevent, or at least limit, damage to
the power system. For transmission and sub-transmission systems, slow fault clearance can also threaten system
stability.
For these reasons, it is common practice to install Circuit Breaker Failure protection (CBF). CBF protection monitors
the circuit breaker and establishes whether it has opened within a reasonable time. If the fault current has not
been interrupted following a set time delay from circuit breaker trip initiation, the CBF protection will operate,
whereby the upstream circuit breakers are back-tripped to ensure that the fault is isolated.
CBF operation can also reset all start output contacts, ensuring that any blocks asserted on upstream protection
are removed.
192 P841B-TM-EN-1.1
3 CIRCUIT BREAKER FAIL IMPLEMENTATION

Circuit Breaker Failure Protection is implemented in the CB FAIL & P.DEAD column of the relevant settings group.
3.1 CIRCUIT BREAKER FAIL TIMERS

The circuit breaker failure protection incorporates two timers, CB Fail 1 Timer and CB Fail 2 Timer, allowing
configuration for the following scenarios:
● Simple CBF, where only CB Fail 1 Timer is enabled. For any protection trip, the CB Fail 1 Timer is started, and
normally reset when the circuit breaker opens to isolate the fault. If breaker opening is not detected, the CB
Fail 1 Timer times out and closes an output contact assigned to breaker fail (using the programmable
scheme logic). This contact is used to back-trip upstream switchgear, generally tripping all infeeds
connected to the same busbar section.
● A retripping scheme, plus delayed back-tripping. Here, CB Fail 1 Timer is used to issue a trip command to a
second trip circuit of the same circuit breaker. This requires the circuit breaker to have duplicate circuit
breaker trip coils. This mechanism is known as retripping. If retripping fails to open the circuit breaker, a
back-trip may be issued following an additional time delay. The back-trip uses CB Fail 2 Timer, which was
also started at the instant of the initial protection element trip.
You can configure the CBF elements CB Fail 1 Timer and CBF Fail 2 Timer to operate for trips triggered by
protection elements within the device. Alternatively you can use an external protection trip by allocating one of the
opto-inputs to the External Trip DDB signal in the PSL.
You can reset the CBF from a breaker open indication (from the pole dead logic) or from a protection reset. In these
cases resetting is only allowed if the undercurrent elements have also been reset. The resetting mechanism is
determined by the settings Volt Prot Reset and Ext Prot Reset.
The resetting options are summarised in the following table:
Initiation (Menu Selectable) CB Fail Timer Reset Mechanism
The resetting mechanism is fixed (e.g. 50/51/46/21/87)
Current based protection
IA< operates AND IB< operates AND IC< operates AND IN< operates
The resetting mechanism is fixed.
Sensitive Earth Fault element
ISEF< Operates
Three options are available:
● All I< and IN< elements operate
Non-current based protection (e.g. 27/59/81/32L)
● Protection element reset AND all I< and IN< elements operate
● CB open (all 3 poles) AND all I< and IN< elements operate
Three options are available.
● All I< and IN< elements operate
External protection
● External trip reset AND all I< and IN< elements operate
● CB open (all 3 poles) AND all I< and IN< elements operate
3.2 ZERO CROSSING DETECTION

When there is a fault and the circuit breaker interrupts the CT primary current, the flux in the CT core decays to a
residual level. This decaying flux introduces a decaying DC current in the CT secondary circuit known as
subsidence current. The closer the CT is to its saturation point, the higher the subsidence current.
The time constant of this subsidence current depends on the CT secondary circuit time constant and it is generally
long. If the protection clears the fault, the CB Fail function should reset fast to avoid maloperation due to the
subsidence current. To compensate for this the device includes a zero-crossing detection algorithm, which ensures
that the CB Fail re-trip and back-trip signals are not asserted while subsidence current is flowing. If all the samples
within half a cycle are greater than or smaller than 0 A (10 mS for a 50 Hz system), then zero crossing detection is
asserted, thereby blocking the operation of the CB Fail function. The zero-crossing detection algorithm is used
P841B-TM-EN-1.1 193
after the circuit breaker in the primary system has opened ensuring that the only current flowing in the AC
secondary circuit is the subsidence current.
194 P841B-TM-EN-1.1
4 CIRCUIT BREAKER FAIL LOGIC
4.1 CIRCUIT BREAKER FAIL LOGIC - PART 1
WI Prot Reset
Enabled
ExtTrip Only Ini

Enabled
&
642
Aid1 WI Trip 3Ph &
1
652
Aid2 WI Trip 3Ph 1 WIINFEEDA
&
637
Aid 1 WI Trip A &
1
647
Aid 2 WI Trip A 1 WIINFEEDB
&
638
Aid 1 WI Trip B &
1
648
Aid 2 WI Trip B 1 WIINFEEDC
&
639
Aid 1 WI Trip C &
1
649
Aid 2 WI Trip C
Note: This part is not relevant for non -distance models
ExtTrip Only Ini

Enabled
& S
CurrentProtSEFTrip Q TripStateSEF
RD
ISEF<FastUndercurrent
ZCDStateA
ZCDStateB
ZCD function
ZCDStateC
ZCDStateSEF
V00729
Figure 96: Circuit Breaker Fail logic - part 1
P841B-TM-EN-1.1 195
CB1 Ext Trip A 535

S
4 Q TripStateExtACB1
1 RD
3
1
CB1 Ext Prot Rst
2 I< Only
&
CB Open & I<
904
CB1 Open A ph 1 Prot Reset & I<
&
Prot Reset OR I<
0 Rst OR CBOp & I<
IA<FastUndercurrent
4
LatchATripResetIncompCB1
2
&
1
&
0
Logic 0
V00740
Note:
This diagram shows only phase-A for the first CB (CB1) of a dual-CB device. The diagrams for phases B and C and for the
second CB (CB2) follow the same principle and are not repeated here.
196 P841B-TM-EN-1.1
WIINFEEDA
TripStateExtA 1 TripStateACB1
ExtTrip Only Ini

Enabled
& S
AnyTripPhaseA Q
RD
IA<FastUndercurrent
CB1 Ext Trip 3ph 534

S
4 Q
1 1
RD
3
1
CB1 Ext Prot Rst
2 I< Only
&
CB Open & I<
CB1 Open 3 ph 534
1 1 Prot Reset& I<
904
&
CB1 Open A ph Prot Reset OR I<
905 0 Rst OR CBOp & I<

CB1 Open B ph &
CB1 Open C ph 906
4
Latch3PhTripResetIncompCB1
2
&
IA<FastUndercurrent
IB<FastUndercurrent & 1
&
IC<FastUndercurrent
0
ExtTrip Only Ini 0
Enabled
874 & S
CBF Non I Trip
2 Q
&
RD
890
All Poles Dead
1 1
892 &
Pole Dead A CB1 Ext Prot Rst
893
0 I< Only
Pole Dead B &
CB Open & I<
894
Pole Dead C Prot Reset& I<
Prot Reset OR I<
IA<FastUndercurrent Rst OR CBOp & I<
IB<FastUndercurrent &
2
&
IC<FastUndercurrent LatchNonITripResetIncompCB1
1
&
0
Logic 0
V00741
Note:
This diagram shows only first CB (CB1) of a dual-CB device. The diagrams for the second CB (CB2) follow the same principle
and are not repeated here..
P841B-TM-EN-1.1 197
From phase B equivalent

LatchATripResetIncomp From phase C equivalent 834
1 CB1 Fail1 Trip
Latch3PhTripResetIncomp 1
298
1 CB1 Fail Alarm
LatchNonITripResetIncomp
835
1 CB1 Fail2 Trip
CB1 ZCD State A
WI INFEED A
1
TripStateA CB1
& & 1672
t 1 CB1 Fail1 Trip A
CB1 Fail1 Status
0
Enabled
CB1 Fail1 Timer

1
& 1675
TripStateA t 1 CB1 Fail2 Trip A
&
0
CB1 Fail2 Status
Enabled
CB1 Fail2 Timer
ZCD StateSEF
1
TripStateSEF
& &
t
CB1 Fail1 Status
0
Enabled
CB1 Fail1 Timer

1
&
TripStateSEF t
&
0
CB1 Fail2 Status
Enabled
CB1 Fail2 Timer
V00742
Note:
This diagram shows only phase-A for the first CB (CB1) of a dual-CB device. The diagrams for phases B and C and for the
second CB (CB2) follow the same principle and are not repeated here.
198 P841B-TM-EN-1.1
5 APPLICATION NOTES
5.1 RESET MECHANISMS FOR CB FAIL TIMERS

It is common practise to use low set undercurrent elements to indicate that circuit breaker poles have interrupted
the fault or load current. This covers the following situations:
● Where circuit breaker auxiliary contacts are defective, or cannot be relied on to definitely indicate that the
breaker has tripped.
● Where a circuit breaker has started to open but has become jammed. This may result in continued arcing at
the primary contacts, with an additional arcing resistance in the fault current path. Should this resistance
severely limit fault current, the initiating protection element may reset. Therefore, reset of the element may
not give a reliable indication that the circuit breaker has opened fully.
For any protection function requiring current to operate, the device uses operation of undercurrent elements to
detect that the necessary circuit breaker poles have tripped and reset the CB fail timers. However, the
undercurrent elements may not be reliable methods of resetting CBF in all applications. For example:
● Where non-current operated protection, such as under/overvoltage or under/overfrequency, derives
measurements from a line connected voltage transformer. Here, I< only gives a reliable reset method if the
protected circuit would always have load current flowing. In this case, detecting drop-off of the initiating
protection element might be a more reliable method.
● Where non-current operated protection, such as under/overvoltage or under/overfrequency, derives
measurements from a busbar connected voltage transformer. Again using I< would rely on the feeder
normally being loaded. Also, tripping the circuit breaker may not remove the initiating condition from the
busbar, and so drop-off of the protection element may not occur. In such cases, the position of the circuit
breaker auxiliary contacts may give the best reset method.
5.2 SETTING GUIDELINES (CB FAIL TIMER)

The following timing chart shows the CB Fail timing during normal and CB Fail operation. The maximum clearing
time should be less than the critical clearing time which is determined by a stability study. The CB Fail back-up trip
time delay considers the maximum CB clearing time, the CB Fail reset time plus a safety margin. Typical CB
clearing times are 1.5 or 3 cycles. The CB Fail reset time should be short enough to avoid CB Fail back-trip during
normal operation. Phase and ground undercurrent elements must be asserted for the CB Fail to reset. The
assertion of the undercurrent elements might be delayed due to the subsidence current that might be flowing
through the secondary AC circuit.
P841B-TM-EN-1.1 199
CBF resets:
1. Undercurrent element asserts
2. Undercurrent element asserts and the
breaker status indicates an open position
3. Protection resets and the undercurrent
Fault occurs element asserts
CBF Safety
Protection Maximum breaker reset margin
Normal operating time clearing time time time
operation
t
Protection Local Bks clearing

Breaker failure operating time CBF back-up trip time delay time
operation
Local 86 Remote CB
operating clearing time
time
Maximum fault clearing time
V00693 Fault occurs
Figure 100: CB Fail timing
The following examples consider direct tripping of a 2-cycle circuit breaker. Typical timer settings to use are as
follows:
Typical Delay For 2 Cycle Circuit
CB Fail Reset Mechanism tBF Time Delay
Breaker
CB interrupting time + element reset time (max.) + error in tBF
Initiating element reset 50 + 50 + 10 + 50 = 160 ms
timer + safety margin
CB auxiliary contacts opening/ closing time (max.) + error in tBF
CB open 50 + 10 + 50 = 110 ms
timer + safety margin
CB interrupting time + undercurrent element (max.) + safety
Undercurrent elements 50 + 25 + 50 = 125 ms
margin operating time
Note:
All CB Fail resetting involves the operation of the undercurrent elements. Where element resetting or CB open resetting is
used, the undercurrent time setting should still be used if this proves to be the worst case.
Where auxiliary tripping relays are used, an additional 10-15 ms must be added to allow for trip relay operation.
5.3 SETTING GUIDELINES (UNDERCURRENT)

The phase undercurrent settings (I<) must be set less than load current to ensure that I< operation correctly
indicates that the circuit breaker pole is open. A typical setting for overhead line or cable circuits is 20%In. Settings
of 5% of In are common for generator CB Fail.
The earth fault undercurrent elements must be set less than the respective trip. For example:
IN< = (IN> trip)/2
200 P841B-TM-EN-1.1
CHAPTER 8
CURRENT PROTECTION FUNCTIONS

Chapter 8 - Current Protection Functions P841B
202 P841B-TM-EN-1.1
P841B Chapter 8 - Current Protection Functions
1 CHAPTER OVERVIEW
The primary purpose of this product is not overcurrent protection. It does however provide a range of current
protection functions to be used as backup protection. This chapter assumes you are familiar with overcurrent
protection principles and does not provide detailed information here. If you require further information about
general overcurrent protection principles, please refer either to General Electric's NPAG publication, earlier
incarnations of this technical manual, or one of our technical manuals from our P40 Agile Modular distribution
range of products such as the P14x.
Phase Fault Overcurrent Protection 204
Negative Sequence Overcurrent Protection 207
Earth Fault Protection 210
Sensitive Earth Fault Protection 215
High Impedance REF 220
Thermal Overload Protection 222
Broken Conductor Protection 226
P841B-TM-EN-1.1 203
2 PHASE FAULT OVERCURRENT PROTECTION

Phase fault overcurrent protection is provided as a form of back-up protection that could be:
● Permanently disabled
● Permanently enabled
● Enabled only in case of VT fuse/MCB failure
● Enabled only in case of protection communication channel failure
● Enabled if VT fuse/MCB or protection communication channel fail
● Enabled if VT fuse/MCB and protection communication channel fail
In addition, each stage may be disabled by a DDB signal.

It should be noted that phase overcurrent protection is phase segregated, but the operation of any phase is
mapped to 3 phase tripping in the default PSL.
The VTS element of the IED can be selected to either block the directional element or simply remove the directional
control.
2.1 POC IMPLEMENTATION

Phase Overcurrent Protection is configured in the OVERCURRENT column of the relevant settings group.
The product provides four stages of three-phase overcurrent protection, each with independent time delay
characteristics. The settings are independent for each stage, but for each stage, the settings apply to all phases.
Stages 1 and 2 provide a choice of operate and reset characteristics, where you can select between:
● A range of IDMT (Inverse Definite Minimum Time) curves based on IEC and IEEE standards
● A range of programmable user-defined curves
● DT (Definite Time) characteristic
This is achieved using the cells:

● I>(n) Function for the overcurrent operate characteristic
● I>(n) Reset Char for the overcurrent reset characteristic
● I>(n) Usr Rst Char for the reset characteristic for user-defined curves
where (n) is the number of the stage.

The IDMT-equipped stages, (1 and 2) also provide a Timer Hold facility. This is configured using the cells I>(n)
tReset, where (n) is the number of the stage. This does not apply to IEEE curves.
Stages 3 and 4 have definite time characteristics only.
2.2 DIRECTIONAL ELEMENT

If fault current can flow in both directions through a protected location, you will need to use a directional
overcurrent element to determine the direction of the fault. Once the direction has been determined the device
can decide whether to allow tripping or to block tripping. To determine the direction of a phase overcurrent fault,
the device must compare the phase angle of the fault current with that of a known reference quantity. The phase
angle of this known reference quantity must be independent of the faulted phase. Typically this will be the line
voltage between the other two phases.
The phase fault elements of the IEDs are internally polarized by the quadrature phase-phase voltages, as shown in
the table below:
Phase of protection Operate current Polarizing voltage
A Phase IA VBC
204 P841B-TM-EN-1.1
Phase of protection Operate current Polarizing voltage

B Phase IB VCA
C Phase IC VAB
Under system fault conditions, the fault current vector lags its nominal phase voltage by an angle depending on
the system X/R ratio. The IED must therefore operate with maximum sensitivity for currents lying in this region. This
is achieved by using the IED characteristic angle (RCA). This is the is the angle by which the current applied to the
IED must be displaced from the voltage applied to the IED to obtain maximum sensitivity.
The device provides a setting I> Char Angle, which is set globally for all overcurrent stages. It is possible to set
characteristic angles anywhere in the range –95° to +95°.
A directional check is performed based on the following criteria:
Directional forward
-90° < (angle(I) - angle(V) - RCA) < 90°
Directional reverse
-90° > (angle(I) - angle(V) - RCA) > 90°
For close up three-phase faults, all three voltages will collapse to zero and no healthy phase voltages will be
present. For this reason, the device includes a synchronous polarisation feature that stores the pre-fault voltage
information and continues to apply this to the directional overcurrent elements for a time period of 3.2 seconds.
This ensures that either instantaneous or time-delayed directional overcurrent elements will be allowed to operate,
even with a three-phase voltage collapse.
P841B-TM-EN-1.1 205
2.3 POC LOGIC

762
IA I>1 Start A
I>1 Current Set 656

& & I>1 Trip A
VBC
I>1 Direction
Directional
VTS Fast Block 832 check Timer Settings
I> Blocking &
VTS Blocks I>1
763
I>1 Start B
IB
I>1 Current Set 657

& & I>1 Trip B
VCA
I>1 Direction
Directional
I> Blocking &
VTS Blocks I>1
764
I>1 Start C
IC
I>1 Current Set 658

& & I >1 Trip C
VAB 761
I>1 Direction
Directional 1 I>1 Start

655
I> Blocking &
1 I>1 Trip
VTS Blocks I>1
401
I>1 Timer Block
Note: For the purpose of clarity , this diagram shows the first
relevant stage number for each signal and setting name .
V00735
Figure 101: Phase Overcurrent Protection logic diagram
206 P841B-TM-EN-1.1
3 NEGATIVE SEQUENCE OVERCURRENT PROTECTION

When applying standard phase overcurrent protection, the overcurrent elements must be set significantly higher
than the maximum load current. This limits the element’s sensitivity. Most protection schemes also use an earth
fault element operating from residual current, which improves sensitivity for earth faults. However, certain faults
may arise which can remain undetected by such schemes. Negative Phase Sequence Overcurrent elements can
help in such cases.
Any unbalanced fault condition will produce a negative sequence current component. Therefore, a negative phase
sequence overcurrent element can be used for both phase-to-phase and phase-to-earth faults. Negative Phase
Sequence Overcurrent protection offers the following advantages:
● Negative phase sequence overcurrent elements are more sensitive to resistive phase-to-phase faults,
where phase overcurrent elements may not operate.
● In certain applications, residual current may not be detected by an earth fault element due to the system
configuration. For example, an earth fault element applied on the delta side of a delta-star transformer is
unable to detect earth faults on the star side. However, negative sequence current will be present on both
sides of the transformer for any fault condition, irrespective of the transformer configuration. Therefore, a
negative phase sequence overcurrent element may be used to provide time-delayed back-up protection for
any uncleared asymmetrical faults downstream.
3.1 NEGATIVE SEQUENCE OVERCURRENT PROTECTION IMPLEMENTATION

Negative Sequence Overcurrent Protection is implemented in the NEG SEQ O/C column of the relevant settings
group.
The product provides four stages of negative sequence overcurrent protection with independent time delay
characteristics.
Stages 1, 2 provide a choice of operate and reset characteristics, where you can select between:
● A range of standard IDMT (Inverse Definite Minimum Time) curves
● DT (Definite Time)
This is achieved using the cells

● I2>(n) Function for the overcurrent operate characteristic
● I2>(n) Reset Char for the overcurrent reset characteristic
The IDMT-capable stages, (1 and 2) also provide a Timer Hold. This is configured using the cells I2>(n) tReset, where
(n) is the number of the stage. This is not applicable for curves based on the IEEE standard.

Where negative phase sequence current may flow in either direction, directional control should be used.
Directionality is achieved by comparing the angle between the negative phase sequence voltage and the negative
phase sequence current. A directional element is available for all of the negative sequence overcurrent stages.
This is found in the I2> Direction cell for the relevant stage. It can be set to non-directional, directional forward, or
directional reverse.
A suitable characteristic angle setting (I2> Char Angle) is chosen to provide optimum performance. This setting
should be set equal to the phase angle of the negative sequence current with respect to the inverted negative
sequence voltage (–V2), in order to be at the centre of the directional characteristic.
P841B-TM-EN-1.1 207
3.3 NPSOC LOGIC
567 I2>1 Start

I2
IDMT/DT
I2>1 Current Set 571
& & & I2>1 trip
928
CTS Block
562
I2 > Inhibit
I2 >1 Direction
V2
Directional
I2> V2pol Set
check
833
VTS Slow block
I 2> VTS Blocking &
VTS Blocks I2 >1
563
I2>1 Tmr Blk
Note : For the purpose of clarity , this diagram shows the first
V 00736
Figure 102: Negative Phase Sequence Overcurrent Protection logic diagram
3.4 APPLICATION NOTES
3.4.1 SETTING GUIDELINES (CURRENT THRESHOLD)

A negative phase sequence element can be connected in the primary supply to the transformer and set as
sensitively as required to protect for secondary phase-to-earth or phase-to-phase faults. This function will also
provide better protection than the phase overcurrent function for internal transformer faults. The NPS overcurrent
protection should be set to coordinate with the low-side phase and earth elements for phase-to-earth and phase-
to-phase faults.
The current pick-up threshold must be set higher than the negative phase sequence current due to the maximum
normal load imbalance. This can be set practically at the commissioning stage, making use of the measurement
function to display the standing negative phase sequence current. The setting should be at least 20% above this
figure.
Where the negative phase sequence element needs to operate for specific uncleared asymmetric faults, a precise
threshold setting would have to be based on an individual fault analysis for that particular system due to the
complexities involved. However, to ensure operation of the protection, the current pick-up setting must be set
approximately 20% below the lowest calculated negative phase sequence fault current contribution to a specific
remote fault condition.
3.4.2 SETTING GUIDELINES (TIME DELAY)

Correct setting of the time delay for this function is vital. You should also be very aware that this element is applied
primarily to provide back-up protection to other protection devices or to provide an alarm. It would therefore
normally have a long time delay.
The time delay set must be greater than the operating time of any other protection device (at minimum fault level)
that may respond to unbalanced faults such as phase overcurrent elements and earth fault elements.
3.4.3 SETTING GUIDELINES (DIRECTIONAL ELEMENT)

Where negative phase sequence current may flow in either direction through an IED location, such as parallel lines
or ring main systems, directional control of the element should be employed (VT models only).
208 P841B-TM-EN-1.1
Directionality is achieved by comparing the angle between the negative phase sequence voltage and the negative
phase sequence current and the element may be selected to operate in either the forward or reverse direction. A
suitable relay characteristic angle setting (I2> Char Angle) is chosen to provide optimum performance. This setting
should be set equal to the phase angle of the negative sequence current with respect to the inverted negative
sequence voltage (–V2), in order to be at the centre of the directional characteristic.
The angle that occurs between V2 and I2 under fault conditions is directly dependent on the negative sequence
source impedance of the system. However, typical settings for the element are as follows:
● For a transmission system the relay characteristic angle (RCA) should be set equal to –60°
● For a distribution system the relay characteristic angle (RCA) should be set equal to –45°
For the negative phase sequence directional elements to operate, the device must detect a polarising voltage
above a minimum threshold, I2> V2pol Set. This must be set in excess of any steady state negative phase
sequence voltage. This may be determined during the commissioning stage by viewing the negative phase
sequence measurements in the device.
P841B-TM-EN-1.1 209
4 EARTH FAULT PROTECTION

Earth faults are overcurrent faults where the fault current flows to earth. Earth faults are the most common type of
fault.
Earth faults can be measured directly from the system by means of:
● A separate current Transformer (CT) located in a power system earth connection
● A separate Core Balance Current Transformer (CBCT), usually connected to the SEF transformer input
● A residual connection of the three line CTs, where the Earth faults can be derived mathematically by
summing the three measured phase currents.
Depending on the device model, it will provide one or more of the above means for Earth fault protection.
4.1 EARTH FAULT PROTECTION IMPLEMENTATION

Earth fault protection is implemented in the EARTH FAULT column of the relevant settings group. The element uses
quantities derived internally from summing the three-phase currents.
The product provides four stages of Earth Fault protection with independent time delay characteristics, for each
EARTH FAULT column.
Stages 1 and 2 provide a choice of operate and reset characteristics, where you can select between:
● A range of IDMT (Inverse Definite Minimum Time) curves
This is achieved using the cells:

● IN>(n) Function for the overcurrent operate characteristics
● IN>(n) Reset Char for the overcurrent reset characteristic

Stages 1 and 2 provide a Timer Hold facility. This is configured using the cells IN>(n) tReset
Stages 3 and 4 can have definite time characteristics only.
Earth fault Overcurrent IN> can be set to:
● Permanently disabled
● Permanently enabled
● Enabled only if VT fuse/MCB fails
● Enabled only if protection communication channel fails
● Enabled if VT fuse/MCB or protection communication channel fail
● Enabled if VT fuse/MCB and protection communication channel fail
Each stage can be individually inhibited with a DDB signal Inhibit IN>(n), where n is the stage number.
4.2 IDG CURVE

The IDG curve is commonly used for time delayed earth fault protection in the Swedish market. This curve is
available in stage 1 of the Earth Fault protection.
The IDG curve is represented by the following equation:
 I 
top = 5.8 − 1.35 log e  
 IN > Setting 
where:
210 P841B-TM-EN-1.1
top is the operating time

I is the measured current
IN> Setting is an adjustable setting, which defines the start point of the characteristic
Note:
Although the start point of the characteristic is defined by the "ΙN>" setting, the actual current threshold is a different setting
called "IDG Ιs". The "IDG Ιs" setting is set as a multiple of "ΙN>".
Note:
When using an IDG Operate characteristic, DT is always used with a value of zero for the Rest characteristic.
An additional setting "IDG Time" is also used to set the minimum operating time at high levels of fault current.
10
8 IDGIsIsSetting
IDG SettingRange
Range
time (seconds)
(seconds)
6
Operating time
5
Operating
3
IDG Time
IDG Time Setting
Setting Range
Range
2
0
1 10 100
I/IN>
V00611
Figure 103: IDG Characteristic

If Earth fault current can flow in both directions through a protected location, you will need to use a directional
overcurrent element to determine the direction of the fault. Typical systems that require such protection are
parallel feeders and ring main systems.
A directional element is available for all of the Earth Fault stages. These are found in the direction setting cells for
the relevant stage. They can be set to non-directional, directional forward, or directional reverse.
Directional control can be blocked by the VTS element if required.
For standard earth fault protection, two options are available for polarisation; Residual Voltage (zero sequence) or
Negative Sequence.
4.3.1 RESIDUAL VOLTAGE POLARISATION

With earth fault protection, the polarising signal needs to be representative of the earth fault condition. As residual
voltage is generated during earth fault conditions, this quantity is commonly used to polarise directional earth
fault elements. This is known as Zero Sequence Voltage polarisation, Residual Voltage polarisation or Neutral
Displacement Voltage (NVD) polarisation.
P841B-TM-EN-1.1 211
Small levels of residual voltage could be present under normal system conditions due to system imbalances, VT
inaccuracies, device tolerances etc. For this reason, the device includes a user settable threshold (IN> VNPol set),
which must be exceeded in order for the DEF function to become operational. The residual voltage measurement
provided in the MEASUREMENTS 1 column of the menu may assist in determining the required threshold setting
during the commissioning stage, as this will indicate the level of standing residual voltage present.
Note:
Residual voltage is nominally 180° out of phase with residual current. Consequently, the DEF elements are polarised from the
"-Vres" quantity. This 180° phase shift is automatically introduced within the device.
The directional criteria with residual voltage polarisation is given below:

● Directional forward: -90° < (angle(IN) - angle(VN + 180°) - RCA) < 90°
● Directional reverse : -90° > (angle(IN) - angle(VN + 180°) - RCA) > 90°
4.3.2 NEGATIVE SEQUENCE POLARISATION

In some applications, the use of residual voltage polarisation may be not possible to achieve, or at the very least,
problematic. For example, a suitable type of VT may be unavailable, or an HV/EHV parallel line application may
present problems with zero sequence mutual coupling.
In such situations, the problem may be solved by using Negative Phase Sequence (NPS) quantities for polarisation.
This method determines the fault direction by comparing the NPS voltage with the NPS current. The operating
quantity, however, is still residual current.
This can be used for both the derived and measured standard earth fault elements. It requires a suitable voltage
and current threshold to be set in cells IN> V2pol set and IN> I2pol set respectively.
Negative phase sequence polarising is not recommended for impedance earthed systems regardless of the type
of VT feeding the relay. This is due to the reduced earth fault current limiting the voltage drop across the negative
sequence source impedance to negligible levels. If this voltage is less than 0.5 volts the device will stop providing
directionalisation.
The directional criteria with negative sequence polarisation is given below:
● Directional forward: -90° < (angle(I2) - angle(V2 + 180°) - RCA) < 90°
● Directional reverse : -90° > (angle(I2) - angle(V2 + 180°) - RCA) > 90°
212 P841B-TM-EN-1.1
4.4 EARTH FAULT PROTECTION LOGIC
777 IN>1 Start

IN
IDMT/ DT
IN>1 Current Set 671
& & & IN>1 Trip
CTS Block 928
467
Inhibit IN >1
IN>1 Directional
VN
IN> VNpol Set
IN Directional
check
Low Current
Residual voltage polarisation
833
VTS Slow Block
IN> Blocking &
VTS Blocks IN>1
405
IN>1 Timer Blk
V2
IN> V2pol Set
I2
IN> I2pol Set
Negative Sequence Polarisation

Note: For the purpose of clarity, this diagram shows the first
V00737
Figure 104: Earth Fault Protection logic diagram
4.5.1 RESIDUAL VOLTAGE POLARISATION SETTING GUIDELINES

It is possible that small levels of residual voltage will be present under normal system conditions due to system
imbalances, VT inaccuracies, IED tolerances etc. Hence, the IED includes a user settable threshold (IN> VNPol Set)
which must be exceeded in order for the DEF function to be operational. In practice, the typical zero sequence
voltage on a healthy system can be as high as 1% (i.e. 3% residual), and the VT error could be 1% per phase. A
setting between 1% and 4% is therefore typical. The residual voltage measurement may assist in determining the
required threshold setting during commissioning, as this will indicate the level of standing residual voltage present.
4.5.2 SETTING GUIDELINES (DIRECTIONAL ELEMENT)

With directional earth faults, the residual current under fault conditions lies at an angle lagging the polarising
voltage. Hence, negative RCA settings are required for DEF applications. This is set in the cell I> Char Angle in the
relevant earth fault menu.
P841B-TM-EN-1.1 213
We recommend the following RCA settings:

● Resistance earthed systems: 0°
● Distribution systems (solidly earthed): -45°
● Transmission systems (solidly earthed): -60°
214 P841B-TM-EN-1.1
5 SENSITIVE EARTH FAULT PROTECTION

With some earth faults, the fault current flowing to earth is limited by either intentional resistance (as is the case
with some HV systems) or unintentional resistance (e.g. in very dry conditions and where the substrate is high
resistance, such as sand or rock).
To provide protection in such cases, it is necessary to provide an earth fault protection system with a setting that is
considerably lower than for normal line protection. Such sensitivity cannot be provided with conventional CTs,
therefore the SEF input would normally be fed from a core balance current transformer (CBCT) mounted around
the three phases of the feeder cable. The SEF transformer should be a special measurement class transformer.
5.1 SEF PROTECTION IMPLEMENTATION

The product provides four stages of SEF protection with independent time delay characteristics.
Stages 1, 2 provide a choice of operate and reset characteristics, where you can select between:
● A range of IDMT (Inverse Definite Minimum Time) curves
This is achieved using the cells

● ISEF>(n) Function for the overcurrent operate characteristic
● ISEF>(n) Reset Chr for the overcurrent reset characteristic

Stages 1 and 2 also provide a Timer Hold facility. This is configured using the cells ISEF>(n) tReset.
Each stage can be individually inhibited with a DDB signal Inhibit ISEF>(n), where n is the stage number.
5.2 EPATR B CURVE

The EPATR B curve is commonly used for time-delayed Sensitive Earth Fault protection in certain markets. This
curve is only available in the Sensitive Earth Fault protection stages 1 and 2. It is based on primary current settings,
employing a SEF CT ratio of 100:1 A.
The EPATR_B curve has 3 separate segments defined in terms of the primary current. It is defined as follows:
Segment Primary Current Range Based on 100A:1A CT Ratio Current/Time Characteristic
1 ISEF = 0.5A to 6.0A t = 432 x TMS/ISEF 0.655 secs
2 ISEF = 6.0A to 200A t = 800 x TMS/ISEF secs
3 ISEF above 200A t = 4 x TMS secs
where TMS (time multiplier setting) is 0.025 - 1.2 in steps of 0.025.
P841B-TM-EN-1.1 215
EPATR Curve
1000
100
Time in Secs
10
1
0.1 1 10 100 1000
Current in Primary A (CT Ratio 100A/1A)
V00616
Figure 105: EPATR B characteristic shown for TMS = 1.0
5.3 SENSITIVE EARTH FAULT PROTECTION LOGIC
777 IN>1 Start

IN
IDMT/ DT
ISEF>1 Current 671
& & & IN>1 Trip
CTS Block 928
1724
Inhibit ISEF>1
ISEF>1 Direction
VN
ISEF> VNpol Set
IN Directional
check
Low Current
Residual voltage polarisation
833
VTS Slow Block
ISEF> Blocking &
VTS Blocks IN>1
409
ISEF>1 Timer Blk
ISEF> Blocking
AR Blks ISEF>3 *
Note: For the purpose of clarity , this diagram shows the first
V00738 * Stages 3 and 4 only relevant stage number for each signal and setting name .
Figure 106: Sensitive Earth Fault Protection logic diagram
216 P841B-TM-EN-1.1
5.4.1 INSULATED SYSTEMS

When insulated systems are used, it is not possible to detect faults using standard earth fault protection. It is
possible to use a residual overvoltage device to achieve this, but even with this method full discrimination is not
possible. Fully discriminative earth fault protection on this type of system can only be achieved by using a SEF
(Sensitive Earth Fault) element. This type of protection detects the resultant imbalance in the system charging
currents that occurs under earth fault conditions. A core balanced CT must be used for this application. This
eliminates the possibility of spill current that may arise from slight mismatches between residually connected line
CTs. It also enables a much lower CT ratio to be applied, thereby allowing the required protection sensitivity to be
more easily achieved.
The following diagram shows an insulated system with a C-phase fault.
Ia1
Ib1
IR1
jXc1
IH1
Ia2
Ib2
IR2
jXc2
IH2
Ia3
Ib3
IH1 + IH2 + IH3
IR3
jXc3
IR3 = IH1 + IH2 + IH3 - IH3 IH3 IH1 + IH2

IR3 = IH1 + IH2
E00627
Figure 107: Current distribution in an insulated system with C phase fault
The protection elements on the healthy feeder see the charging current imbalance for their own feeder. The
protection element on the faulted feeder, however, sees the charging current from the rest of the system (IH1 and
IH2 in this case). Its own feeder's charging current (IH3) is cancelled out.
With reference to the associated vector diagram, it can be seen that the C-phase to earth fault causes the
voltages on the healthy phases to rise by a factor of √3. The A-phase charging current (Ia1), leads the resultant A
phase voltage by 90°. Likewise, the B-phase charging current leads the resultant Vb by 90°.
P841B-TM-EN-1.1 217
Vaf
Restrain
Vapf
IR1
Ib1
Operate
Ia1
Vbf
Vcpf Vbpf
Vres
(= 3Vo)
An RCA setting of ±90º shifts the

“centre of the characteristic” to here IR3 = (IH1 + IH2)
E00628
Figure 108: Phasor diagrams for insulated system with C phase fault
The current imbalance detected by a core balanced current transformer on the healthy feeders is the vector
addition of Ia1 and Ib1. This gives a residual current which lags the polariing voltage (–3Vo) by 90°. As the healthy
phase voltages have risen by a factor of Ö3, the charging currents on these phases are also Ö3 times larger than
their steady state values. Therefore, the magnitude of the residual current IR1, is equal to 3 times the steady state
per phase charging current.
The phasor diagram indicates that the residual currents on the healthy and faulted feeders (IR1 and IR3
respectively) are in anti-phase. A directional element (if available) could therefore be used to provide discriminative
earth fault protection.
If the polarising is shifted through +90°, the residual current seen by the relay on the faulted feeder will lie within
the operate region of the directional characteristic and the current on the healthy feeders will fall within the
restrain region.
The required characteristic angle setting for the SEF element when applied to insulated systems, is +90°. This is for
the case when the protection is connected such that its direction of current flow for operation is from the source
busbar towards the feeder. If the forward direction for operation were set such that it is from the feeder into the
busbar, then a –90° RCA would be required.
Note:
Discrimination can be provided without the need for directional control. This can only be achieved, however, if it is possible to
set the IED in excess of the charging current of the protected feeder and below the charging current for the rest of the system.
5.4.2 SETTING GUIDELINES (INSULATED SYSTEMS)

The residual current on the faulted feeder is equal to the sum of the charging currents flowing from the rest of the
system. Further, the addition of the two healthy phase charging currents on each feeder gives a total charging
current which has a magnitude of three times the per phase value. Therefore, the total imbalance current is equal
to three times the per phase charging current of the rest of the system. A typical setting may therefore be in the
order of 30% of this value, i.e. equal to the per phase charging current of the remaining system. Practically though,
the required setting may well be determined on site, where suitable settings can be adopted based on practically
obtained results.
When using a core-balanced transformer, care must be taken in the positioning of the CT with respect to the
earthing of the cable sheath:
218 P841B-TM-EN-1.1
Cable gland
Cable box
Cable gland/shealth
earth connection
“Incorrect”
No operation
SEF
“Correct”
Operation
SEF
E00614
Figure 109: Positioning of core balance current transformers
If the cable sheath is terminated at the cable gland and directly earthed at that point, a cable fault (from phase to
sheath) will not result in any unbalanced current in the core balance CT. Therefore, prior to earthing, the
connection must be brought back through the CBCT and earthed on the feeder side. This then ensures correct
relay operation during earth fault conditions.
P841B-TM-EN-1.1 219
6 HIGH IMPEDANCE REF

The device provides a high impedance restricted earth fault protection function. An external resistor is required to
provide stability in the presence of saturated line current transformers. Current transformer supervision signals do
not block the high impedance REF protection. The appropriate logic must be configured in PSL to block the high
impedance REF when any of the above signals is asserted.
6.1 HIGH IMPEDANCE REF PRINCIPLE

This scheme is very sensitive and can protect against low levels of fault current, typical of winding faults.
High Impedance REF protection is based on the differential principle. It works on the circulating current principle as
shown in the following diagram.
Healthy CT Saturated CT
Protected
circuit
A-G
Zm1 Zm2
I = Is + IF
RCT1 RCT2
I IF
RL1 IS RL3
Vs RST
R
RL2 RL4
V00671
Figure 110: High Impedance REF principle
When subjected to heavy through faults the line current transformer may enter saturation unevenly, resulting in
imbalance. To ensure stability under these conditions a series connected external resistor is required, so that most
of the unbalanced current will flow through the saturated CT. As a result, the current flowing through the device
will be less than the setting, therefore maintaining stability during external faults.
Voltage across REF element Vs = IF (RCT2 + RL3 + RL4)
Stabilising resistor RST = Vs/Is –RR
where:
● IF = maximum secondary through fault current
● RR = device burden
● RCT = CT secondary winding resistance
● RL2 and RL3 = Resistances of leads from the device to the current transformer
● RST = Stabilising resistor
High Impedance REF can be used for either delta windings or star windings in both solidly grounded and
resistance grounded systems. The connection to a modern IED are as follows:
220 P841B-TM-EN-1.1
Phase A
Phase A
Phase B
Phase B
Phase C
Phase C
I Phase A
I Phase B
I Phase C
RSTAB I Neutral
I Neutral RSTAB
IED IED
Connecting IED to star winding for High Connecting IED to delta winding for High
Impedance REF Impedance REF
V00680
Figure 111: High Impedance REF Connection
P841B-TM-EN-1.1 221
7 THERMAL OVERLOAD PROTECTION

The heat generated within an item of plant is the resistive loss. The thermal time characteristic is therefore based
on the equation I2Rt. Over-temperature conditions occur when currents in excess of their maximum rating are
allowed to flow for a period of time.
Temperature changes during heating follow exponential time constants. The device provides two characteristics
for thermal overload protection; a single time constant characteristic and a dual time constant characteristic. You
select these according to the application.
7.1 SINGLE TIME CONSTANT CHARACTERISTIC

This characteristic is used to protect cables, dry type transformers and capacitor banks.
The single constant thermal characteristic is given by the equation:
 I 2 − ( KI FLC )2 
t = −τ log  
 I 2 − I p2 
e  
where:
● t = time to trip, following application of the overload current I
● t = heating and cooling time constant of the protected plant
● I = largest phase current
● IFLC full load current rating (the Thermal Trip setting)
● K = a constant with the value of 1.05
● Ip = steady state pre-loading before application of the overload
7.2 DUAL TIME CONSTANT CHARACTERISTIC

This characteristic is used to protect equipment such as oil-filled transformers with natural air cooling. The thermal
model is similar to that with the single time constant, except that two timer constants must be set.
For marginal overloading, heat will flow from the windings into the bulk of the insulating oil. Therefore, at low
current, the replica curve is dominated by the long time constant for the oil. This provides protection against a
general rise in oil temperature.
For severe overloading, heat accumulates in the transformer windings, with little opportunity for dissipation into
the surrounding insulating oil. Therefore at high current levels, the replica curve is dominated by the short time
constant for the windings. This provides protection against hot spots developing within the transformer windings.
Overall, the dual time constant characteristic serves to protect the winding insulation from ageing and to minimise
gas production by overheated oil. Note however that the thermal model does not compensate for the effects of
ambient temperature change.
The dual time constant thermal characteristic is given by the equation:
( − t / τ1 ) ( −t / τ 2 )
 I 2 − ( KI FLC )2 
0.4e + 0.6e = 2 2

 I − I p 
where:
● t1 = heating and cooling time constant of the transformer windings
● t2 = heating and cooling time constant of the insulating oil
222 P841B-TM-EN-1.1
7.3 THERMAL OVERLOAD PROTECTION IMPLEMENTATION

The device incorporates a current-based thermal characteristic, using RMS load current to model heating and
cooling of the protected plant. The element can be set with both alarm and trip stages.
Thermal Overload Protection is implemented in the THERMAL OVERLOAD column of the relevant settings group.
This column contains the settings for the characteristic type, the alarm and trip thresholds and the time constants.
7.4 THERMAL OVERLOAD PROTECTION LOGIC
IA
IB Max RMS
Thermal State
IC
Thermal Trip
680
Thermal Trip
Characteristic Thermal trip
Disabled Thermal threshold
Single Calculation
Dual
Time Constant 1
Time Constant 2
445
Reset Thermal
785
Thermal Alarm
Thermal Alarm
V00630
Figure 112: Thermal overload protection logic diagram
The magnitudes of the three phase input currents are compared and the largest magnitude is taken as the input
to the thermal overload function. If this current exceeds the thermal trip threshold setting a start condition is
asserted.
The Start signal is applied to the chosen thermal characteristic module, which has three outputs signals; alarm trip
and thermal state measurement. The thermal state measurement is made available in one of the MEASUREMENTS
columns.
The thermal state can be reset by either an opto-input (if assigned to this function using the programmable
scheme logic) or the HMI panel menu.
7.5.1 SETTING GUIDELINES FOR DUAL TIME CONSTANT CHARACTERISTIC

The easiest way of solving the dual time constant thermal equation is to express the current in terms of time and
to use a spreadsheet to calculate the current for a series of increasing operating times using the following
equation, then plotting a graph.
0.4 I p 2 .e( − t /τ 1) + 0.6 I p 2 .e( − t /τ 2) − k 2 .I FLC 2

I=
0.4e( − t / + 0.6e( − t /τ 2) − 1
τ 1)
P841B-TM-EN-1.1 223
Figures based
on equation
E00728
Figure 113: Spreadsheet calculation for dual time constant thermal characteristic
100000
10000 Time constant 1 = 5 mins

Operating Time (seconds)
Time constant 2 = 120 mins

Pre-overload current = 0.9 pu
Thermal setting = 1 Amp
1000
100
10
1
1 10
Current as a Multiple of Thermal Setting
V00629
Figure 114: Dual time constant thermal characteristic
The current setting is calculated as:

Thermal Trip = Permissible continuous loading of the transformer item/CT ratio.
For an oil-filled transformer with rating 400 to 1600 kVA, the approximate time constants are:
● t1 = 5 minutes
● t2 = 120 minutes
An alarm can be raised on reaching a thermal state corresponding to a percentage of the trip threshold. A typical
setting might be "Thermal Alarm" = 70% of thermal capacity.
224 P841B-TM-EN-1.1
Note:
The thermal time constants given in the above tables are typical only. Reference should always be made to the plant
manufacturer for accurate information.
7.5.2 SETTING GUIDELINES FOR SINGLE TIME CONSTANT CHARACTERISTIC

The time to trip varies depending on the load current carried before application of the overload, i.e. whether the
overload was applied from hot or cold.
The thermal time constant characteristic may be rewritten as:
θ − θ p 
e( − t / τ ) =  
e 
θ −1 
where:
● θ = thermal state = I2/K2IFLC2
● θp = pre-fault thermal state = Ip2/K2IFLC2
● Ip is the pre-fault thermal state

● IFLC is the full load current
Note:
A current of 105%Is (KIFLC) has to be applied for several time constants to cause a thermal state measurement of 100%.
The current setting is calculated as:

Thermal Trip = Permissible continuous loading of the plant item/CT ratio.
The following tables show the approximate time constant in minutes, for different cable rated voltages with
various conductor cross-sectional areas, and other plant equipment.
Area mm2 6 - 11 kV 22 kV 33 kV 66 kV
25 – 50 10 minutes 15 minutes 40 minutes –
70 – 120 15 minutes 25 minutes 40 minutes 60 minutes
150 25 minutes 40 minutes 40 minutes 60 minutes
Plant type Time Constant (Minutes)

Dry-type transformer <400 kVA 40
Dry-type transformers 400 – 800 kVA 60 - 90
Air-core Reactors 40
Capacitor Banks 10
Overhead Lines with cross section > 100 mm2 10

Overhead Lines 10
Busbars 60
P841B-TM-EN-1.1 225
8 BROKEN CONDUCTOR PROTECTION

One type of unbalanced fault is the 'Series' or 'Open Circuit' fault. This type of fault can arise from, among other
things, broken conductors. Series faults do not cause an increase in phase current and so cannot be detected by
overcurrent protection. However, they do produce an imbalance, resulting in negative phase sequence current,
which can be detected.
It is possible to apply a negative phase sequence overcurrent element to detect broken conductors. However, on a
lightly loaded line, the negative sequence current resulting from a series fault condition may be very close to, or
less than, the full load steady state imbalance arising from CT errors and load imbalances, making it very difficult
to distinguish. A regular negative sequence element would therefore not work at low load levels. To overcome this,
the device incorporates a special Broken Conductor protection element.
The Broken Conductor element measures the ratio of negative to positive phase sequence current (I2/I1). This ratio
is approximately constant with variations in load current, therefore making it more sensitive to series faults than
standard negative sequence protection.
8.1 BROKEN CONDUCTOR PROTECTION IMPLEMENTATION

Broken Conductor protection is implemented in the BROKEN CONDUCTOR column of the relevant settings group.
This column contains the settings to enable the function, for the pickup threshold and the time delay.
8.2 BROKEN CONDUCTOR PROTECTION LOGIC

The ratio of I2/I1 is calculated and compared with the threshold setting. If the threshold is exceeded, the delay
timer is initiated. The CTS block signal is used to block the operation of the delay timer.
I2/I1
DT 679
I 2/I1 Setting & Broken Wire Trip
I2
Low Current
928
CTS Block
V00739
Figure 115: Broken conductor logic
8.3.1 SETTING GUIDELINES

For a broken conductor affecting a single point earthed power system, there will be little zero sequence current
flow and the ratio of I2/I1 that flows in the protected circuit will approach 100%. In the case of a multiple earthed
power system (assuming equal impedance’s in each sequence network), the ratio I2/I1 will be 50%.
In practise, the levels of standing negative phase sequence current present on the system govern this minimum
setting. This can be determined from a system study, or by making use of the measurement facilities at the
commissioning stage. If the latter method is adopted, it is important to take the measurements during maximum
system load conditions, to ensure that all single-phase loads are accounted for.
226 P841B-TM-EN-1.1
Note:
A minimum value of 8% negative phase sequence current is required for successful operation.
Since sensitive settings have been employed, we can expect that the element will operate for any unbalanced
condition occurring on the system (for example, during a single pole autoreclose cycle). For this reason, a long time
delay is necessary to ensure co-ordination with other protection devices. A 60 second time delay setting may be
typical.
The following example was recorded by an IED during commissioning:
Ifull load = 500A
I2 = 50A
therefore the quiescent I2/I1 ratio = 0.1
To allow for tolerances and load variations a setting of 20% of this value may be typical: Therefore set:
I2/I1 = 0.2
In a double circuit (parallel line) application, using a 40% setting will ensure that the broken conductor protection
will operate only for the circuit that is affected. A setting of 0.4 results in no pick-up for the parallel healthy circuit.
Set I2/I1 Time Delay = 60 s to allow adequate time for short circuit fault clearance by time delayed protections.
P841B-TM-EN-1.1 227
228 P841B-TM-EN-1.1
CHAPTER 9
VOLTAGE PROTECTION FUNCTIONS

Chapter 9 - Voltage Protection Functions P841B
230 P841B-TM-EN-1.1
P841B Chapter 9 - Voltage Protection Functions
1 CHAPTER OVERVIEW
The device provides a wide range of voltage protection functions. This chapter describes the operation of these
functions including the principles, logic diagrams and applications.
Undervoltage Protection 232
Overvoltage Protection 235
Compensated Overvoltage 238
Residual Overvoltage Protection 239
P841B-TM-EN-1.1 231
2 UNDERVOLTAGE PROTECTION
Undervoltage conditions may occur on a power system for a variety of reasons, some of which are outlined below:
● Undervoltage conditions can be related to increased loads, whereby the supply voltage will decrease in
magnitude. This situation would normally be rectified by voltage regulating equipment such as AVRs (Auto
Voltage Regulators) or On Load Tap Changers. However, failure of this equipment to bring the system
voltage back within permitted limits leaves the system with an undervoltage condition, which must be
cleared.
● If the regulating equipment is unsuccessful in restoring healthy system voltage, then tripping by means of
an undervoltage element is required.
● Faults occurring on the power system result in a reduction in voltage of the faulty phases. The proportion by
which the voltage decreases is dependent on the type of fault, method of system earthing and its location.
Consequently, co-ordination with other voltage and current-based protection devices is essential in order to
achieve correct discrimination.
● Complete loss of busbar voltage. This may occur due to fault conditions present on the incomer or busbar
itself, resulting in total isolation of the incoming power supply. For this condition, it may be necessary to
isolate each of the outgoing circuits, such that when supply voltage is restored, the load is not connected.
Therefore, the automatic tripping of a feeder on detection of complete loss of voltage may be required. This
can be achieved by a three-phase undervoltage element.
● Where outgoing feeders from a busbar are supplying induction motor loads, excessive dips in the supply
may cause the connected motors to stall, and should be tripped for voltage reductions that last longer than
a pre-determined time.
2.1 UNDERVOLTAGE PROTECTION IMPLEMENTATION

Undervoltage Protection is implemented in the VOLT PROTECTION column of the relevant settings group. The
Undervoltage parameters are contained within the sub-heading UNDERVOLTAGE.
The product provides two stages of Undervoltage protection with independent time delay characteristics.
Stage 1 provides a choice of operate characteristics, where you can select between:
● An IDMT characteristic
You set this using the V<1 Function setting.

The IDMT characteristic is defined by the following formula:
t = K/( M-1)
where:
● K = Time multiplier setting
● t = Operating time in seconds
● M = Measured voltage / IED setting voltage (V<(n) Voltage Set)
The undervoltage stages can be configured either as phase-to-neutral or phase-to-phase voltages in the V<
Measur't Mode cell.
There is no Timer Hold facility for Undervoltage.
Stage 2 can have definite time characteristics only. This is set in the V<2 Status cell.
Outputs are available for single or three-phase conditions via the V< Operate Mode cell for each stage.
232 P841B-TM-EN-1.1
2.2 UNDERVOLTAGE PROTECTION LOGIC

V< Measur't Mode
V<1 Start A/A B
V<1 Voltage Set & V<1 Trip A/ AB
V< Hysteresis
V<1 Time Delay
V<1 Start B/B C

V< Measur't Mode
& V<1 Trip B/ BC
V<1 Voltage Set
V< Hysteresis
V<1 Time Delay V<1 Start C/CA
V< Measur't Mode & V<1 Trip C/CA
1
&
V<1 Voltage Set
1 V<1 Start
V< Hysteresis &
&
V<1 Time Delay
1
&
V<1 Timer Block 1 V<1 Trip
&
V< Operate Mode &
Any Phase
Three Phase
Notes: This diagram does not show all stages. Other stages follow similar
principles.
V00 829
VTS Fast Block only applies for directional models.
Figure 116: Undervoltage - single and three phase tripping mode (single stage)
The Undervoltage protection function detects when the voltage magnitude for a certain stage falls short of a set
threshold. If this happens a Start signal, signifying the "Start of protection", is produced. This Start signal can be
blocked by the VTS Fast Block signal and an All Poles Dead signal. This Start signal is applied to the timer module
to produce the Trip signal, which can be blocked by the undervoltage timer block signal (V<(n) Timer Block). For
each stage, there are three Phase undervoltage detection modules, one for each phase. The three Start signals
from each of these phases are OR'd together to create a 3-phase Start signal (V<(n) Start), which can be be
activated when any of the three phases start (Any Phase), or when all three phases start (Three Phase), depending
on the chosen V< Operate Mode setting.
The outputs of the timer modules are the trip signals which are used to drive the tripping output relay. These
tripping signals are also OR'd together to create a 3-phase Trip signal, which are also controlled by the V< Operate
Mode setting.
If any one of the above signals is low, or goes low before the timer has counted out, the timer module is inhibited
(effectively reset) until the blocking signal goes high.
In some cases, we do not want the undervoltage element to trip; for example, when the protected feeder is de-
energised, or the circuit breaker is opened, an undervoltage condition would obviously be detected, but we would
not want to start protection. To cater for this, an All Poles Dead signal blocks the Start signal for each phase. This
is controlled by the V<Poledead Inh cell, which is included for each of the stages. If the cell is enabled, the relevant
stage will be blocked by the integrated pole dead logic. This logic produces an output when it detects either an
open circuit breaker via auxiliary contacts feeding the opto-inputs or it detects a combination of both
undercurrent and undervoltage on any one phase.
P841B-TM-EN-1.1 233
Voltage drop-off threshold, defined as a percentage of set voltage, may be adjusted via the V< Hysteresis setting.
For example, where the V<Hysteresis default setting is 2, relay pick-up will be at set voltage and drop-off will be at
102% of set voltage.
2.3.1 UNDERVOLTAGE SETTING GUIDELINES

In most applications, undervoltage protection is not required to operate during system earth fault conditions. If this
is the case you should select phase-to-phase voltage measurement, as this quantity is less affected by single-
phase voltage dips due to earth faults.
The voltage threshold setting for the undervoltage protection should be set at some value below the voltage
excursions that may be expected under normal system operating conditions. This threshold is dependent on the
system in question but typical healthy system voltage excursions may be in the order of 10% of nominal value.
The same applies to the time setting. The required time delay is dependent on the time for which the system is able
to withstand a reduced voltage.
If motor loads are connected, then a typical time setting may be in the order of 0.5 seconds.
234 P841B-TM-EN-1.1
3 OVERVOLTAGE PROTECTION
Overvoltage conditions are generally related to loss of load conditions, whereby the supply voltage increases in
magnitude. This situation would normally be rectified by voltage regulating equipment such as AVRs (Auto Voltage
Regulators) or On Load Tap Changers. However, failure of this equipment to bring the system voltage back within
permitted limits leaves the system with an overvoltage condition which must be cleared.
Note:
During earth fault conditions on a power system there may be an increase in the healthy phase voltages. Ideally, the system
should be designed to withstand such overvoltages for a defined period of time.
3.1 OVERVOLTAGE PROTECTION IMPLEMENTATION

Overvoltage Protection is implemented in the VOLT PROTECTION column of the relevant settings group. The
Overvoltage parameters are contained within the sub-heading OVERVOLTAGE.
The product provides two stages of overvoltage protection with independent time delay characteristics.
You set this using the V>1 Function setting.

t = K/( M - 1)
where:
● M = Measured voltage setting voltage (V>(n) Voltage Set)
The overvoltage stages can be configured either as phase-to-neutral or phase-to-phase voltages in the V>
Measur't Mode cell.
There is no Timer Hold facility for Overvoltage.
Stage 2 can have definite time characteristics only. This is set in the V>2 Status cell.
Outputs are available for single or three-phase conditions via the V> Operate Mode cell for each stage.
P841B-TM-EN-1.1 235
3.2 OVERVOLTAGE PROTECTION LOGIC

V> Measur't Mode
V>1 Start A/A B
V>1 Voltage Set & V>1 Trip A/ AB
V> Hysteresis
V>1 Time Delay
V>1 Start B/B C

V> Measur't Mode
& V>1 Trip B/ BC
V>1 Voltage Set
V> Hysteresis
V>1 Time Delay V>1 Start C/CA
V> Measur't Mode & V>1 Trip C/CA
1
&
V>1 Voltage Set
1 V>1 Start
V> Hysteresis &
&
V>1 Time Delay
1
&
V>1 Timer Block 1 V>1 Trip
&
V> Operate Mode &
Any Phase
Three Phase
Notes: This diagram does not show all stages. Other stages follow similar
principles.
V00 828
VTS Fast Block only applies for directional models.
Figure 117: Overvoltage - single and three phase tripping mode (single stage)
The Overvoltage protection function detects when the voltage magnitude for a certain stage exceeds a set
threshold. If this happens a Start signal, signifying the "Start of protection", is produced. This Start signal can be
blocked by the VTS Fast Block signal. This start signal is applied to the timer module to produce the Trip signal,
which can be blocked by the overvoltage timer block signal (V>(n) Timer Block). For each stage, there are three
Phase overvoltage detection modules, one for each phase. The three Start signals from each of these phases are
OR'd together to create a 3-phase Start signal (V>(n) Start), which can then be activated when any of the three
phases start (Any Phase), or when all three phases start (Three Phase), depending on the chosen V> Operate Mode
setting.
The outputs of the timer modules are the trip signals which are used to drive the tripping output relay. These
tripping signals are also OR'd together to create a 3-phase Trip signal, which are also controlled by the V> Operate
Mode setting.
If any one of the above signals is low, or goes low before the timer has counted out, the timer module is inhibited
(effectively reset) until the blocking signal goes high.
Voltage drop-off threshold, defined as a percentage of set voltage, may be adjusted via the V> Hysteresis setting.
For example, where the V>Hysteresis default setting is 2, relay pick-up will be at set voltage and drop-off will be at
98% of set voltage.
236 P841B-TM-EN-1.1
3.3.1 OVERVOLTAGE SETTING GUIDELINES

The provision of multiple stages and their respective operating characteristics allows for a number of possible
applications:
● Definite Time can be used for both stages to provide the required alarm and trip stages.
● Use of the IDMT characteristic allows grading of the time delay according to the severity of the overvoltage.
As the voltage settings for both of the stages are independent, the second stage could then be set lower
than the first to provide a time-delayed alarm stage.
● If only one stage of overvoltage protection is required, or if the element is required to provide an alarm only,
the remaining stage may be disabled.
This type of protection must be co-ordinated with any other overvoltage devices at other locations on the system.
P841B-TM-EN-1.1 237
4 COMPENSATED OVERVOLTAGE
The Compensated Overvoltage function calculates the positive sequence voltage at the remote terminal using the
positive sequence local current and voltage and the line impedance and susceptance. This can be used on long
transmission lines where Ferranti Overvoltages can develop under remote circuit breaker open conditions.
The Compensated overvoltage protection function can be set in the VOLT PROTECTION column under the sub
heading COMP OVERVOLTAGE. The remote voltage is calculated using line impedance settings and the line
charging admittance in the LINE PARAMETERS column.
The IED uses the [A,B,C,D] transmission line equivalent model given the following parameters:
● Total Impedance Z = zÐq ohms
● Total Susceptance Y = yÐ-90°
● Line Length l
The remote voltage is calculated using the following equations:
Vr   D − C  Vs 
 = × 
Ir
   − BA   Is 
where
● Vr is the voltage at the receiving end
● Ir is the current at the receiving end
● Vs is the measured voltage at the sending end
● Is is the measured current at the sending end
● A= D = cosh(y.l)
● B = Zc.sinh(y.l)
● C = Yc.sinh(y.l)
● y.l = Ö(Z.Y)
● Zc = 1/Yc = Ö(Z/Y)
● Y = total line capacitive charging susceptance
● Zc = characteristic impedance of the line (surge impedance)
There are two stages to provide both alarm and trip stages where required. Both stages can be set independently.
Stage 1 can be set to IDMT, DT or Disabled, in the V1>1 Cmp Funct cell. Stage 2 is DT only and is enabled or
disabled in the V1>2 Cmp Status cell.
The IDMT characteristic on the first stage is defined by the following formula:
t = K/(M - 1)
where:
● t =Operating time in seconds
● M = Remote Calculated voltage / IED setting voltage
Voltage drop-off threshold, defined as a percentage of set voltage, may be adjusted via the Cp V Hysteresis
setting. For example, where the Cp V Hysteresis default setting is 2, relay pick-up will be at set voltage and drop-
off will be at 98% of set voltage.
238 P841B-TM-EN-1.1
5 RESIDUAL OVERVOLTAGE PROTECTION

On a healthy three-phase power system, the sum of the three-phase to earth voltages is nominally zero, as it is the
vector sum of three balanced vectors displaced from each other by 120°. However, when an earth fault occurs on
the primary system, this balance is upset and a residual voltage is produced. This condition causes a rise in the
neutral voltage with respect to earth. Consequently this type of protection is also commonly referred to as 'Neutral
Voltage Displacement' or NVD for short.
This residual voltage may be derived (from the phase voltages) or measured (from a measurement class open
delta VT). Derived values will normally only be used where the model does not support measured functionality (a
dedicated measurement class VT). If a measurement class VT is used to produce a measured Residual Voltage, it
cannot be used for other features such as Check Synchronisation.
This offers an alternative means of earth fault detection, which does not require any measurement of current. This
may be particularly advantageous in high impedance earthed or insulated systems, where the provision of core
balanced current transformers on each feeder may be either impractical, or uneconomic, or for providing earth
fault protection for devices with no current transformers.
5.1 RESIDUAL OVERVOLTAGE PROTECTION IMPLEMENTATION

Residual Overvoltage Protection is implemented in the RESIDUAL O/V NVD column of the relevant settings group.
Some applications require more than one stage. For example an insulated system may require an alarm stage and
a trip stage. It is common in such a case for the system to be designed to withstand the associated healthy phase
overvoltages for a number of hours following an earth fault. In such applications, an alarm is generated soon after
the condition is detected, which serves to indicate the presence of an earth fault on the system. This gives time for
system operators to locate and isolate the fault. The second stage of the protection can issue a trip signal if the
fault condition persists.
The product provides two stages of Residual Overvoltage protection with independent time delay characteristics.

t = K/( M - 1)
where:
● K= Time multiplier setting
● M = Derived residual voltage setting voltage (VN> Voltage Set)
You set this using the VN>1 Function setting.

Stage 1 also provides a Timer Hold facility.
Stage 2 can have definite time characteristics only. This is set in the VN>2 status cell
The device derives the residual voltage internally from the three-phase voltage inputs supplied from either a 5-limb
VT or three single-phase VTs. These types of VT design provide a path for the residual flux and consequently permit
the device to derive the required residual voltage. In addition, the primary star point of the VT must be earthed.
Three-limb VTs have no path for residual flux and are therefore unsuitable for this type of protection.
P841B-TM-EN-1.1 239
5.2 RESIDUAL OVERVOLTAGE LOGIC
804
VN>1 Start
VN
VN>1 Voltage Set & 700
& IDMT/DT VN>1 Trip
832
VTS Fast Block
418
VN>1 Timer Blk
V00802
Figure 118: Residual Overvoltage logic
The Residual Overvoltage module (VN>) is a level detector that detects when the voltage magnitude exceeds a set
threshold, for each stage. When this happens, the comparator output produces a Start signal (VN>(n) Start), which
signifies the "Start of protection". This can be blocked by a VTS Fast block signal. This Start signal is applied to the
timer module. The output of the timer module is the VN> (n) Trip signal which is used to drive the tripping output
relay.
5.3.1 CALCULATION FOR SOLIDLY EARTHED SYSTEMS

Consider a Phase-A to Earth fault on a simple radial system.
240 P841B-TM-EN-1.1
E S IED F
ZS ZL
VA
VA
VC VB VC VB VC VB
VA VRES
VRES
VA
VB VB VB
VC VC VC
VRES = ZS0
X3E
2ZS1 + ZS0 + 2ZL1 + ZL0
E00800
Figure 119: Residual voltage for a solidly earthed system
As can be seen from the above diagram, the residual voltage measured on a solidly earthed system is solely
dependent on the ratio of source impedance behind the protection to the line impedance in front of the protection,
up to the point of fault. For a remote fault far away, the ZS/ZL: ratio will be small, resulting in a correspondingly
small residual voltage. Therefore, the protection only operates for faults up to a certain distance along the system.
The maximum distance depends on the device setting.
5.3.2 CALCULATION FOR IMPEDANCE EARTHED SYSTEMS

Consider a Phase-A to Earth fault on a simple radial system.
P841B-TM-EN-1.1 241
E S IED F
ZS ZL
N
ZE
VA - G
S R VA - G
G,F G,F
G,F
VC - G VC - G VC - G
VB - G VB - G VB - G
VRES VRES VRES
VB - G VB - G VB - G
VA - G VA - G
VC - G VC - G VC - G
ZS0 + 3ZE
VRES = X3E
2ZS1 + ZS0 + 2ZL1 + ZL0 + 3Z
E
E00801
Figure 120: Residual voltage for an impedance earthed system
An impedance earthed system will always generate a relatively large degree of residual voltage, as the zero
sequence source impedance now includes the earthing impedance. It follows then that the residual voltage
generated by an earth fault on an insulated system will be the highest possible value (3 x phase-neutral voltage),
as the zero sequence source impedance is infinite.

The voltage setting applied to the elements is dependent on the magnitude of residual voltage that is expected to
occur during the earth fault condition. This in turn is dependent on the method of system earthing employed.
Also, you must ensure that the protection setting is set above any standing level of residual voltage that is present
on the system.
242 P841B-TM-EN-1.1
CHAPTER 10
FREQUENCY PROTECTION FUNCTIONS

Chapter 10 - Frequency Protection Functions P841B
244 P841B-TM-EN-1.1
P841B Chapter 10 - Frequency Protection Functions
1 CHAPTER OVERVIEW
The device provides a range of frequency protection functions. This chapter describes the operation of these
functions including the principles, logic diagrams and applications.
Frequency Protection 246
Independent R.O.C.O.F Protection 249
P841B-TM-EN-1.1 245
2 FREQUENCY PROTECTION
Power generation and utilisation needs to be well balanced in any industrial, distribution or transmission network.
These electrical networks are dynamic entities, with continually varying loads and supplies, which are continually
affecting the system frequency. Increased loading reduces the system frequency and generation needs to be
increased to maintain the frequency of the supply. Conversely decreased loading increases the system frequency
and generation needs to be reduced. Sudden fluctuations in load can cause rapid changes in frequency, which
need to be dealt with quickly.
Unless corrective measures are taken at the appropriate time, frequency decay can go beyond the point of no
return and cause widespread network collapse, which has dire consequences.
Normally, generators are rated for a particular band of frequency. Operation outside this band can cause
mechanical damage to the turbine blades. Protection against such contingencies is required when frequency does
not improve even after load shedding steps have been taken. This type of protection can be used for operator
alarms or turbine trips in case of severe frequency decay.
Clearly a range of methods is required to ensure system frequency stability. The frequency protection in this device
provides both underfrequency and overfrequency protection.
Frequency Protection is implemented in the FREQ PROTECTION column of the relevant settings group.
2.1 UNDERFREQUENCY PROTECTION

A reduced system frequency implies that the net load is in excess of the available generation. Such a condition can
arise, when an interconnected system splits, and the load left connected to one of the subsystems is in excess of
the capacity of the generators in that particular subsystem. Industrial plants that are dependent on utilities to
supply part of their loads will experience underfrequency conditions when the incoming lines are lost.
Many types of industrial loads have limited tolerances on the operating frequency and running speeds (e.g.
synchronous motors). Sustained underfrequency has implications on the stability of the system, whereby any
subsequent disturbance may damage equipment and even lead to blackouts. It is therefore essential to provide
protection for underfrequency conditions.
2.1.1 UNDERFREQUENCY PROTECTION IMPLEMENTATION

Simple underfrequency Protection is configured in the FREQ PROTECTION column of the relevant settings group.
The device provides 4 stages of underfrequency protection. The function uses the following settings (shown for
stage 1 only - other stages follow the same principles).
● F<1 Status: enables or disables underfrequency protection for the relevant stage
● F<1 Setting: defines the frequency pickup setting
● F<1 Time Delay: sets the time delay
246 P841B-TM-EN-1.1
2.1.2 UNDERFREQUENCY PROTECTION LOGIC
Freq 1155
Averaging F<1 Start
DT
1161
F<1 Setting & F<1 Trip
F<1 Status
Enabled
890
All Poles Dead
1
Freq Not Found 1370
1149
F<1 Timer Block
V00861
Figure 121: Underfrequency logic (single stage)
If the frequency is below the setting and not blocked the DT timer is started. If the frequency cannot be
determined, the function is blocked.
2.1.3 APPLICATION NOTES
2.1.3.1 SETTING GUIDELINES

In order to minimise the effects of underfrequency, a multi-stage load shedding scheme may be used with the
plant loads prioritised and grouped. During an underfrequency condition, the load groups are disconnected
sequentially, with the highest priority group being the last one to be disconnected.
The effectiveness of each load shedding stage depends on the proportion of power deficiency it represents. If the
load shedding stage is too small compared with the prevailing generation deficiency, then there may be no
improvement in the frequency. This should be taken into account when forming the load groups.
Time delays should be sufficient to override any transient dips in frequency, as well as to provide time for the
frequency controls in the system to respond. These should not be excessive as this could jeopardize system
stability. Time delay settings of 5 - 20 s are typical.
The protection function should be set so that declared frequency-time limits for the generating set are not
infringed. Typically, a 10% underfrequency condition should be continuously sustainable.
2.2 OVERFREQUENCY PROTECTION

An increased system frequency arises when the mechanical power input to a generator exceeds the electrical
power output. This could happen, for instance, when there is a sudden loss of load due to tripping of an outgoing
feeder from the plant to a load centre. Under such conditions, the governor would normally respond quickly to
obtain a balance between the mechanical input and electrical output, thereby restoring normal frequency.
Overfrequency protection is required as a backup to cater for cases where the reaction of the control equipment is
too slow.
2.2.1 OVERFREQUENCY PROTECTION IMPLEMENTATION

Simple overfrequency Protection is configured in the FREQ PROTECTION column of the relevant settings group.
The device provides 2 stages of overfrequency protection. The function uses the following settings (shown for
stage 1 only - other stages follow the same principles).
● F>1 Status: enables or disables underfrequency protection for the relevant stage
● F>1 Setting: defines the frequency pickup setting
● F>1 Time Delay: sets the time delay
P841B-TM-EN-1.1 247
2.2.2 OVERFREQUENCY PROTECTION LOGIC
1159
Freq Averaging F>1 Start
DT
1165
F>1 Setting & F>1 Trip
F>1 Status
Enabled
890
All Poles Dead
1
Freq Not Found 1370
1153
F>1 Timer Block
V00862
Figure 122: Overfrequency logic (single stage)
If the frequency is above the setting and not blocked, the DT timer is started and after this has timed out, the trip is
produced. If the frequency cannot be determined, the function is blocked.
2.2.3 APPLICATION NOTES
2.2.3.1 SETTING GUIDELINES

Following changes on the network caused by faults or other operational requirements, it is possible that various
subsystems will be formed within the power network. It is likely that these subsystems will suffer from a
generation/load imbalance. The "islands" where generation exceeds the existing load will be subject to
overfrequency conditions. Severe over frequency conditions may be unacceptable to many industrial loads, since
running speeds of motors will be affected. The overfrequency element can be suitably set to sense this
contingency.
248 P841B-TM-EN-1.1
3 INDEPENDENT R.O.C.O.F PROTECTION

Where there are very large loads, imbalances may occur that result in rapid decline in system frequency. The
situation could be so bad that shedding one or two stages of load is unlikely to stop this rapid frequency decline. In
such a situation, standard underfrequency protection will normally have to be supplemented with protection that
responds to the rate of change of frequency. An element is therefore required which identifies the high rate of
decline of frequency, and adapts the load shedding scheme accordingly.
Such protection can identify frequency variations occurring close to nominal frequency thereby providing early
warning of a developing frequency problem. The element can also be used as an alarm to warn operators of
unusually high system frequency variations.
3.1 INDEPENENT R.O.C.O.F PROTECTION IMPLEMENTATION

The device provides four independent stages of protection. Each stage can respond to either rising or falling
frequency conditions. This depends on whether the frequency threshold is set above or below the system nominal
frequency. For example, if the frequency threshold is set above nominal frequency, the rate of change of frequency
setting is considered as positive and the element will operate for rising frequency conditions. If the frequency
threshold is set below nominal frequency, the setting is considered as negative and the element will operate for
falling frequency conditions.
The function uses the following settings (shown for stage 1 only - other stages follow the same principles).
● df/dt Avg.Cycles calculates the rate of change of frequency over a fixed period of several cycles.
● df/dt>1 Status: determines whether the stage is for falling or rising frequency conditions
● df/dt>1 Setting: defines the rate of change of frequency pickup setting
● df/dt>1 Time: sets the time delay
● df/dt>1 Dir'n: sets the direction of change you wish to check (positive, negative, or both)
In addition, start, trip and timer block DDB signals are available for each stage, as well as an inhibit signal to inhibit
all four stages.
3.2 INDEPENDENT R.O.C.O.F PROTECTION LOGIC

df /dt>1 Status
Enabled
Frequency 597
V df/dt df/dt >1 Start
determination
& 601
df /dt Avg . Cycles 1 df /dt>1 Trip
-1
df /dt>1 Setting × & df/dt >1 Time
df /dt>1 Dir’n 1
Positive
Both
1
Negative
1370
Freq Not Found
1368
Freq High 1
Freq Low 1369
V00869
Figure 123: Rate of change of frequency logic (single stage)
P841B-TM-EN-1.1 249
250 P841B-TM-EN-1.1
CHAPTER 11
CURRENT TRANSFORMER REQUIREMENTS

Chapter 11 - Current Transformer Requirements P841B
252 P841B-TM-EN-1.1
P841B Chapter 11 - Current Transformer Requirements
1 CHAPTER OVERVIEW

Recommended CT Classes 254
Current Differential Requirements 255
Determining Vk for IEEE C-class CT 256
Worked Examples 257
P841B-TM-EN-1.1 253
2 RECOMMENDED CT CLASSES
You can use Class X current transformers with a knee point voltage greater or equal to that calculated. You can
also use class 5P protection CT. These have a knee-point voltage equivalent, which can be approximated from the
following calculations:
Vk = (VA ´ ALF)/In + (RCT ´ ALF ´ In)
where:
● Vk = Knee-point voltage
● VA = Voltampere burden rating
● ALF = Accuracy limit factor
● In = CT nominal secondary current
● RCT = CT resistance
254 P841B-TM-EN-1.1
3 CURRENT DIFFERENTIAL REQUIREMENTS

We strongly recommend class X or class 5P Current Transformers. The CT knee point voltage should comply with
the minimum requirements of the formulae shown below:
Vk ³ KIn(RCT + 2RL)
where:
● Vk = Required IEC knee point voltage
● K = Dimensioning factor
● In = CT nominal secondary current
● RCT = CT resistance
● RL = One-way lead impedance from CT to relay
● K is a constant depending on the maximum value of through fault current for stability (If), and the Primary
system X/R ratio
Determination of K with transient bias disabled

For IEDs with the settings: Is1 = 20%, Is2 = 2In, k1 = 30%, k2 = 150% and for (If ´ X/R) £ 1000 (2-end applications):
K must have the value 65 or as calculated by: K = 40 + (0.07(If ´ X/R)), whichever the highest.
For higher (If ´ X/R) up to 2600, K = 107
For IEDs with the settings: Is1 = 20%, Is2 = 2In, k1 = 30%, k2 = 100% and for (If ´ X/R) £ 600 (3-end applications):
K must have the value 65 or as calculated by: K = 40 + (0.35(If ´ X/R))
For higher (If ´ X/R) up to 2600, K = 256
Determination of K with transient bias enabled

For IEDs with the settings: Is1 = 20%, Is2 = 2 In, k1 = 30%, k2 = 150% (2-end applications):
K = (1.42If + 53.7)(6.06E-03 ´ X/R + 0.515)
For IEDs with the settings: Is1 = 20%, Is2 = 2 In, k1 = 30%, k2 = 100% (3-end applications):
K = (7.47 ´ If + 77.8)(8.19E-03 ´ X/R + 0.345)
This is valid for If £ 50 pu and X/R £ 80
P841B-TM-EN-1.1 255
4 DETERMINING VK FOR IEEE C-CLASS CT

Where IEEE standards are used to specify CTs, the C class voltage rating can be checked to determine the
equivalent Vk (knee point voltage according to IEC).
The equivalence formula is:
Vk = 1.05(C rating in volts) + 100RCT
256 P841B-TM-EN-1.1
5 WORKED EXAMPLES
The power system and the line parameters used in these examples are as follows:
● Single circuit operation between Green Valley and Blue River
● System voltage = 230 kV
● System frequency = 50 Hz
● System grounding = solid
● CT ratio = 1200/1
● Line length = 100 km
● Line positive sequence impedance Z1 = 0.089 + j 0.476 ohm per km
● Bus fault level = 40 kA
● Primary time constant = 120 ms
Important notes to be considered

● For calculating the CT requirements, the bus bar short time symmetrical fault rating should be considered
as the bus fault level.
● If only indicative X/R ratios are available, the circuit breaker’s DC breaking capacity is used to derive the
primary time constant and therefore the primary system X/R. It is derived from the circuit breaker
manufacturer’s practical primary time constants. These vary between 50 ms (66 kV and 132 kV breakers)
and 120 ms (220 kV and 400 kV breakers). 150 ms is a practical figure for generator circuit breakers.
5.1 OVERCURRENT ELEMENTS
Phase Elements
VK ³ 0.5ICP (RCT + RL + Rrp)
Ground Elements
VK ³ 0.5ICN (RCT + 2RL + Rrp + Rrn)
5.2 OVERCURRENT ELEMENTS

VK ³ 0.5ICN (RCT + 2RL + Rrn)
P841B-TM-EN-1.1 257
258 P841B-TM-EN-1.1
CHAPTER 12
MONITORING AND CONTROL

Chapter 12 - Monitoring and Control P841B
260 P841B-TM-EN-1.1
P841B Chapter 12 - Monitoring and Control
1 CHAPTER OVERVIEW
As well as providing a range of protection functions, the product includes comprehensive monitoring and control
functionality.
Event Records 262
Disturbance Recorder 266
Measurements 267
CB Condition Monitoring 268
CB State Monitoring 279
Circuit Breaker Control 281
Pole Dead Function 287
System Checks 288
P841B-TM-EN-1.1 261
2 EVENT RECORDS
General Electric devices record events in an event log. This allows you to establish the sequence of events that led
up to a particular situation. For example, a change in a digital input signal or protection element output signal
would cause an event record to be created and stored in the event log. This could be used to analyse how a
particular power system condition was caused. These events are stored in the IED's non-volatile memory. Each
event is time tagged.
The event records can be displayed on an IED's front panel but it is easier to view them through the settings
application software. This can extract the events log from the device and store it as a single .evt file for analysis on
a PC.
The event records are detailed in the VIEW RECORDS column. The first event (0) is always the latest event. After
selecting the required event, you can scroll through the menus to obtain further details.
If viewing the event with the settings application software, simply open the extracted event file. All the events are
displayed chronologically. Each event is summarised with a time stamp (obtained from the Time & Date cell) and a
short description relating to the event (obtained from the Event Text cell. You can expand the details of the event
by clicking on the + icon to the left of the time stamp.
The following table shows the correlation between the fields in the setting application software's event viewer and
the cells in the menu database.
Field in Event Viewer Equivalent cell in menu DB Cell reference User settable?
Left hand column header VIEW RECORDS ® Time & Date 01 03 No
Right hand column header VIEW RECORDS ® Event Text 01 04 No
Description SYSTEM DATA ® Description 00 04 Yes
Plant reference SYSTEM DATA ® Plant Reference 00 05 Yes
Model number SYSTEM DATA ® Model Number 00 06 No
Address Displays the Courier address relating to the event N/A No
Event type VIEW RECORDS ® Menu Cell Ref 01 02 No
Event Value VIEW RECORDS ® Event Value 01 05 No
Evt Unique Id VIEW RECORDS ® Evt Unique ID 01 FE No
The Select Event setting allows access to individual event records, with the latest event stored at position 0. This
setting also defines the maximum number of records available.
In addition to the event log, there are two logs which contain duplicates of the last 5 maintenance records and the
last 5 fault records. The purpose of this is to provide convenient access to the most recent fault and maintenance
events.
2.1 EVENT TYPES

There are several different types of event:
● Opto-input events (Change of state of opto-input)
● Contact events (Change of state of output relay contact)
● Alarm events
● Fault record events
● Standard events
● Security events
262 P841B-TM-EN-1.1
Standard events are further sub-categorised internally to include different pieces of information. These are:
● Protection events (starts and trips)
● Maintenance record events
● Platform events
Note:
The first event in the list (event 0) is the most recent event to have occurred.
2.1.1 OPTO-INPUT EVENTS

If one or more of the opto-inputs has changed state since the last time the protection algorithm ran (which runs at
several times per cycle), a new event is created, which logs the logic states of all opto-inputs. You can tell which
opto-input has changed state by comparing the new event with the previous one.
The description of this event type, as shown in the Event Text cell is always Logic Inputs # where # is the
batch number of the opto-inputs. This is '1', for the first batch of opto-inputs and '2' for the second batch of opto-
inputs (if applicable).
The event value shown in the Event Value cell for this type of event is a binary string. This shows the logical states
of the opto-inputs, where the Least Significant Bit (LSB), on the right corresponds to the first opto-input Input L1.
The same information is also shown in the Opto I/P Status cell in the SYSTEM DATA column. This information is
updated continuously, whereas the information in the event log is a snapshot at the time when the event was
created.
2.1.2 CONTACT EVENTS

If one or more of the output relays (also known as output contacts) has changed state since the last time the
protection algorithm ran (which runs at several times per cycle), a new event is created, which logs the logic states
of all output relays. You can tell which output relay has changed state by comparing the new event with the
previous one.
The description of this event type, as shown in the Event Text cell is always Output Contacts # where # is the
batch number of the output relay contacts. This is '1', for the first batch of output contacts and '2' for the second
batch of output contacts (if applicable).
The event value shown in the Event Value cell for this type of event is a binary string. This shows the logical states
of the output relays, where the LSB (on the right) corresponds to the first output contact Output R1.
The same information is also shown in the Relay O/P Status cell in the SYSTEM DATA column. This information is
created.
2.1.3 ALARM EVENTS

The IED monitors itself on power up and continually thereafter. If it notices any problems, it will register an alarm
event.
The description of this event type, as shown in the Event Text cell is cell dependent on the type of alarm and will be
one of those shown in the following tables, followed by OFF or ON.
The event value shown in the Event Value cell for this type of event is a 32 bit binary string. There are one or more
banks 32 bit registers, depending on the device model. These contain all the alarm types and their logic states (ON
or OFF).
The same information is also shown in the Alarm Status (n) cells in the SYSTEM DATA column. This information is
created.
P841B-TM-EN-1.1 263
2.1.4 FAULT RECORD EVENTS

An event record is created for every fault the IED detects. This is also known as a fault record.
The event type description shown in the Event Text cell for this type of event is always Fault Recorded.
The IED contains a separate register containing the latest fault records. This provides a convenient way of viewing
the latest fault records and saves searching through the event log. You access these fault records using the Select
Fault setting, where fault number 0 is the latest fault.
A fault record is triggered by the Fault REC TRIG signal DDB, which is assigned in the PSL. The fault recorder
records the values of all parameters associated with the fault for the duration of the fault. These parameters are
stored in separate Courier cells, which become visible depending on the type of fault.
The fault recorder stops recording only when:
The Start signal is reset AND the undercurrent is ON OR the Trip signal is reset, as shown below:
Start signal resets

& Fault recorder stops recording
Undercurrent is ON
1
Trip signal resets
Fault recorder trigger
V01234
Figure 124: Fault recorder stop conditions
The event is logged as soon as the fault recorder stops. The time stamp assigned to the fault corresponds to the
start of the fault. The timestamp assigned to the fault record event corresponds to the time when the fault
recorder stops.
Note:
We recommend that you do not set the triggering contact to latching. This is because if you use a latching contact, the fault
record would not be generated until the contact has been fully reset.
2.1.5 MAINTENANCE EVENTS

Internal failures detected by the self-test procedures are logged as maintenance records. Maintenance records are
special types of standard events.
The event type description shown in the Event Text cell for this type of event is always Maint Recorded.
The Event Value cell also provides a unique binary code.
The IED contains a separate register containing the latest maintenance records. This provides a convenient way of
viewing the latest maintenance records and saves searching through the event log. You access these fault records
using the Select Maint setting.
The maintenance record has a number of extra menu cells relating to the maintenance event. These parameters
are Maint Text, Maint Type and Maint Data. They contain details about the maintenance event selected with the
Select Maint cell.
2.1.6 PROTECTION EVENTS

The IED logs protection starts and trips as individual events. Protection events are special types of standard events.
The event type description shown in the Event Text cell for this type of event is dependent on the protection event
that occurred. Each time a protection event occurs, a DDB signal changes state. It is the name of this DDB signal
followed by 'ON' or 'OFF' that appears in the Event Text cell.
264 P841B-TM-EN-1.1
The Event Value cell for this type of event is a 32 bit binary string representing the state of the relevant DDB
signals. These binary strings can also be viewed in the COMMISSION TESTS column in the relevant DDB batch cells.
Not all DDB signals can generate an event. Those that can are listed in the RECORD CONTROL column. In this
column, you can set which DDBs generate events.
2.1.7 SECURITY EVENTS

An event record is generated each time a setting that requires an access level is executed.
The event type description shown in the Event Text cell displays the type of change.
2.1.8 PLATFORM EVENTS

Platform events are special types of standard events.
The event type description shown in the Event Text cell displays the type of change.
P841B-TM-EN-1.1 265
3 DISTURBANCE RECORDER
The disturbance recorder feature allows you to record selected current and voltage inputs to the protection
elements, together with selected digital signals. The digital signals may be inputs, outputs, or internal DDB signals.
The disturbance records can be extracted using the disturbance record viewer in the settings application software.
The disturbance record file can also be stored in the COMTRADE format. This allows the use of other packages to
view the recorded data.
The integral disturbance recorder has an area of memory specifically set aside for storing disturbance records. The
number of records that can be stored is dependent on the recording duration. The minimum duration is 0.1 s and
the maximum duration is 10.5 s.
When the available memory is exhausted, the oldest records are overwritten by the newest ones.
Each disturbance record consists of a number of analogue data channels and digital data channels. The relevant
CT and VT ratios for the analogue channels are also extracted to enable scaling to primary quantities.
The fault recording times are set by a combination of the Duration and Trigger Position cells. The Duration cell
sets the overall recording time and the Trigger Position cell sets the trigger point as a percentage of the duration.
For example, the default settings show that the overall recording time is set to 1.5 s with the trigger point being at
33.3% of this, giving 0.5 s pre-fault and 1 s post fault recording times.
With the Trigger Mode set to Single, if further triggers occurs whilst a recording is taking place, the recorder will
ignore the trigger. However, with the Trigger Mode set to Extended, the post trigger timer will be reset to zero,
extending the recording time.
You can select any of the IED's analogue inputs as analogue channels to be recorded. You can also map any of the
opto-inputs output contacts to the digital channels. In addition, you may also map a number of DDB signals such
as Starts and LEDs to digital channels.
You may choose any of the digital channels to trigger the disturbance recorder on either a low to high or a high to
low transition, via the Input Trigger cell. The default settings are such that any dedicated trip output contacts will
trigger the recorder.
It is not possible to view the disturbance records locally via the front panel LCD. You must extract these using
suitable setting application software such as MiCOM S1 Agile.
266 P841B-TM-EN-1.1
4 MEASUREMENTS
4.1 MEASURED QUANTITIES

The device measures directly and calculates a number of system quantities, which are updated every second. You
can view these values in the relevant MEASUREMENT columns or with the Measurement Viewer in the settings
application software. Depending on the model, the device may measure and display some or more of the following
quantities:
● Measured and calculated analogue current and voltage values
● Power and energy quantities
● Peak, fixed and rolling demand values
● Frequency measurements
● Thermal measurements
● Teleprotection channel measurements
4.2 MEASUREMENT SETUP

You can define the way measurements are set up and displayed using the MEASURE'T SETUP column and the
measurements are shown in the relevant MEASUREMENTS tables.
4.3 FAULT LOCATOR

Some models provide fault location functionality. It is possible to identify the fault location by measuring the fault
voltage and current magnitude and phases and presenting this information to a Fault Locator function. The fault
locator is triggered whenever a fault record is generated, and the subsequent fault location data is included as
part of the fault record. This information is also displayed in the Fault Location cell in the VIEW RECORDS column.
This cell will display the fault location in metres, miles ohms or percentage, depending on the chosen units in the
Fault Location cell of the MEASURE'T SETUP column.
The Fault Locator uses pre-fault and post-fault analogue input signals to calculate the fault location. The result is
included it in the fault record. The pre-fault and post-fault voltages are also presented in the fault record.
When applied to parallel circuits, mutual flux coupling can alter the impedance seen by the fault locator. The
coupling contains positive, negative and zero sequence components. In practise the positive and negative
sequence coupling is insignificant. The effect on the fault locator of the zero sequence mutual coupling can be
eliminated using the mutual compensation feature provided.
4.4 OPTO-INPUT TIME STAMPING

Each opto-input sample is time stamped within a tolerance of +/- 1 ms with respect to the Real Time Clock. These
time stamps are used for the opto event logs and for the disturbance recording. The device needs to be
synchronised accurately to an external clock source such as an IRIG-B signal or a master clock signal provided in
the relevant data protocol.
For both the filtered and unfiltered opto-inputs, the time stamp of an opto-input change event is the sampling time
at which the change of state occurred. If multiple opto-inputs change state at the same sampling interval, these
state changes are reported as a single event.
P841B-TM-EN-1.1 267
5 CB CONDITION MONITORING
The device records various statistics related to each circuit breaker trip operation, allowing an accurate
assessment of the circuit breaker condition to be determined. These statistics are available in the CB CONDITION
column. The menu cells are register values only and cannot be set directly. They may be reset, however, during
maintenance. The statistics monitored are:
● Total Current Broken: A register stores the total amount of current that the CB has broken is stored in an
accumulator, giving at any time a measure of the total amount of current that the CB has broken since the
value was last reset.
● Number of CB operations: A counter registers the number of CB trips that have been performed for each
phase, giving at any time the total number of trips that the CB has performed since the value was last reset.
● CB Operate Time: A register stores the total amount of time the CB has transitioned from closed to open is
stored in an accumulator, giving at any time a measure of the total time that the CB has spent tripping since
the values was last reset.
● Excessive Fault Frequency: A counter registers the number of CB trips that have been performed for all
phases, giving at any time the total number of trips performed since the value was last reset.
These statistics are available in the CB CONDITION column. The menu cells are register values only and cannot be
set directly. They may be reset, however, during maintenance.
Note:
When in Commissioning test mode the CB condition monitoring registers are not updated.
Circuit breaker lockout, can be caused by the following circuit breaker condition monitoring functions:
● Maintenance lockout
● Excessive fault frequency lockout
● Broken current lockout
If the circuit breaker is locked out, the logic generates a lockout alarm
268 P841B-TM-EN-1.1
5.1 BROKEN CURRENT ACCUMULATOR

CB1PhaseACurrent
Set Set CB1 Cumulative IA broken In
Reset
CB1PhaseBCurrent
Set Set CB1 Cumulative IB broken In
Reset
CB1PhaseCCurrent
Set Set CB 1 Cumulative IC broken In
526
CB1 Trip 3ph t Reset
534
1
CB1 Ext Trip3 ph 0
523 Note: Broken current totals not incremented when device is in test mode
CB1 Trip OutputA t 1
535 1
CB1 Ext Trip A 0
524
CB1 Trip OutputB t 1
536 1
CB1 Ext Trip B 0
525
CB1 Trip OutputC t 1
537
1
CB1 Ext Trip C 0
Reset CB Data
447
1
Reset CB Data
CB2PhaseACurrent
Set Set CB2 Cumulative IA broken In
Reset
CB2PhaseBCurrent
Set Set CB2 Cumulative IB broken In
Reset
CB2PhaseCCurrent
Set Set CB 2 Cumulative IC broken In
1600
CB2 Trip 3ph t Reset
538
1
CB2 Ext Trip3 ph 0
CB2 Trip OutputA 1601

t 1 Note: Broken current totals not incremented when device is in test mode
539
1
CB2 Ext Trip A 0
1602
CB2 Trip OutputB t 1
540
1
CB2 Ext Trip B 0
1603
CB2 Trip OutputC t 1
541 1
CB2 Ext Trip C 0
Reset CB Data Note: All timers have 1 cycle pickup delay

447 1
Reset CB Data
V01273
Figure 125: Broken Current Accumulator logic diagram
P841B-TM-EN-1.1 269
5.2 CB TRIP COUNTER

526
Déc 3ph DJ1
534
1
Déc. ext 3ph DJ1
523
Sortie Déc A DJ1 1 Incrément
535 1 DJ1 Compteur de
Déc. ext A DJ1
déclenchement Phase A
Réinit
524
Sortie Déc B DJ1 1 Incrément
Déc. ext B DJ1
déclenchement Phase B
Réinit
525
Sortie Déc C DJ1 1 Incrément
Déc. ext C DJ1
déclenchement Phase C
Réinit
RAZ Infos DJ1
447
1
RAZ Infos DJ1
1600
Déc 3ph DJ2
538
1
Déc. ext 3ph DJ2
1601
Sortie Déc A DJ2 1 Incrément
Déc.2 Extern A
déclenchement Phase A
Réinit
1602
Sortie Déc B DJ2 1 Incrément
Déc.2 Extern B
déclenchement Phase B
Réinit
1603
Sortie Déc C DJ2 1 Incrément
Déc.2 Extern C
déclenchement Phase C
Réinit
RAZ Infos DJ2
1597
1
RAZ Données DJ2
V01277
Figure 126: CB Trip Counter logic diagram
270 P841B-TM-EN-1.1
5.3 CB OPERATING TIME ACCUMULATOR

526
CB1 Trip 3ph
534
1 Note: CB operating time not accumulated when device is in test mode
CB1 Ext Trip3 ph
523
CB1 Trip OutputA 1 Start
CB1 Ext Trip A 535 CB1 operating time phase A Increment

Stop CB1OpTimePhA Counter
IA < fixed threshold Reset
1
Pole Dead A 892
524
CB1 Trip OutputB 1 Start
CB1 Ext Trip B 536 CB1 operating time phase B Increment

Stop CB1OpTimePhB Counter
IB < fixed threshold Reset
1
893
Pole Dead B
525
CB1 Trip OutputC 1 Start
CB1 Ext Trip C 537 CB1 operating time phase C Increment

Stop CB1 OpTimePhC Counter
IC < fixed threshold Reset
1
894
Pole Dead C
Reset CB1 Data

447
1
Rst CB1 Data
1600
CB2 Trip 3ph
538 1
CB2 Ext Trip3 ph
1601
CB2 Trip OutputA 1 Start
CB2 Ext Trip A 539 CB2 operating time phase A Increment

Stop CB2OpTimePhA Counter
IA < fixed threshold Reset
1
892
Pole Dead A
1602
CB2 Trip OutputB 1 Start
CB2 Ext Trip B 540 CB2 operating time phase B Increment

Stop CB2OpTimePhB Counter
IB < fixed threshold Reset
1
Pole Dead B 893
1603
CB2 Trip OutputC 1 Start
CB2 Ext Trip C 541 CB2 operating time phase C Increment

Stop CB2 OpTimePhC Counter
IC < fixed threshold Reset
1
894
Pole Dead C
Reset CB2 Data

1597 1
Rst CB2 Data
V01275
Figure 127: Operating Time Accumulator
P841B-TM-EN-1.1 271
5.4 EXCESSIVE FAULT FREQUENCY COUNTER

CB1 Trip 3ph
1
CB1 Ext Trip3 ph 1 Increment
CB1 Trip OutputA CB1 Excessive Fault Frequency Counter
1 Reset
CB1 Ext Trip A
CB1 Trip OutputB

1 S t
CB1 Ext Trip B Q
R 0 1
CB1 Trip OutputC
1
CB1 Ext Trip C
CB1 LO Alarm
CB1FltFreqTime
CB2 Trip 3ph

1
CB2 Ext Trip3 ph 1 Increment
CB2 Trip OutputA CB2 Excessive Fault Frequency Counter
1 Reset
CB2 Ext Trip A
CB2 Trip OutputB

1 S t
CB2 Ext Trip B Q
R 0 1
CB2 Trip OutputC
1
CB2 Ext Trip C
CB2 LO Alarm
CB2FltFreqTime
V01279
Figure 128: Excessive Fault Frequency logic diagram
272 P841B-TM-EN-1.1
5.5 RESET LOCKOUT ALARM

CB mon LO reset
Yes
1 Reset CB1 Lockout Alarm
Clear Alarms
CB1 Failed to Trip S

Q
R t
CB1 Open 3 ph &
0
CB1 LO Alarm
CB1 Closed 3 ph
1
CB1 Closed A ph
CB1 Closed B ph &
CB1 Closed C ph
Rst CB mon LO by
CB Close
CB mon LO RstDly
CB mon LO reset
Yes
1 Reset CB2 Lockout Alarm
Clear Alarms
CB2 Failed to Trip S

Q t
R &
CB2 Open 3 ph 0
CB2 LO Alarm
CB2 Closed 3 ph
1
CB2 Closed A ph
CB2 Closed B ph &
CB2 Closed C ph
Rst CB mon LO by
CB Close
CB mon LO RstDly
V01281
Figure 129: Reset Lockout Alarm logic diagram
P841B-TM-EN-1.1 273
5.6 CB CONDITION MONITORING LOGIC

CB1 I^ Maint
Alarm Enabled
&
Greatest broken current total & CB1 I^ Maint
S
CB1 I^ Maint Q
R 1 CB1 Monitor Alm
CB1 I^ Lockout
Alarm Enabled
& CB1 I^ Lockout
CB1 I^ Lockout
No.CB1 Ops Maint

Alarm Enabled
&
Max no. of CB operations & No.CB1 Ops Maint
S
No.CB1 Ops Maint Q
R
No.CB1 Ops Lock
Alarm Enabled
& No.CB1 Ops Lock
No.CB1 Ops Lock
&
1 CB1 Pre-Lockout
-1
CB1FltFreqLock
Alarm Enabled
& S
Fault frequency count Q CB1 FaultFreqLock
R
CB1FltFreqCount
&
-1 1 CB1 Mon LO Alarm
CB1 Time Maint
Alarm Enabled
&
Greatest CB operate time & CB1 Time Maint
S
CB1 Time Maint Q
R
CB1 Time Lockout
Alarm Enabled
& CB1 Time Lockout
CB1 Time Lockout
Clear Alarms 1
Reset CB1 Data

Yes 1
Rst CB1 Data

S
Q CB1 LO Alarm
Reset CB1 Lockout Alarm R
Control CB1 Unhealthy

CB1 Control no Check Synch
CB1 failed to trip
CB1 failed to close V01283
Figure 130: CB1 Condition Monitoring logic diagram
274 P841B-TM-EN-1.1
CB2 I^ Maint
Alarm Enabled
&
Greatest broken current total & CB2 I^ Maint
S
CB2 I^ Maint Q
R 1 CB2 Monitor Alm
CB2 I^ Lockout
Alarm Enabled
& CB2 I^ Lockout
CB2 I^ Lockout
No.CB2 Ops Maint

Alarm Enabled
&
Max no . of CB operations & No.CB2 Ops Maint
S
No.CB2 Ops Maint Q
R
No.CB2 Ops Lock
Alarm Enabled
& No.CB2 Ops Lock
No.CB2 Ops Lock
&
1 CB2 Pre-Lockout
-1
CB2FltFreqLock
Alarm Enabled
& S
Fault frequency count
Q CB2 FaultFreqLock
R
CB2FltFreqCount
&
-1 1 CB2 Mon LO Alarm
CB2 Time Maint
Alarm Enabled
&
Greatest CB operate time & CB2 Time Maint
S
CB2 Time Maint Q
R
CB2 Time Lockout
Alarm Enabled
& CB2 Time Lockout
CB2 Time Lockout
Clear Alarms 1
Reset CB2 Data

Yes 1
Rst CB2 Data

S
Q CB2 LO Alarm
Reset CB2 Lockout Alarm R
Control CB2 Unhealthy

CB2 Control no Check Synch
CB2 failed to trip
CB2 failed to close V01284
Figure 131: CB2 Condition Monitoring logic diagram
5.7 RESET CIRCUIT BREAKER LOCKOUT

Lockout conditions caused by the circuit breaker condition monitoring functions can be reset according to the
condition of the Rst CB mon LO by setting found in the CB CONTROL column. There are two options; CB Close
and User interface.
If set to CB Close, a timer setting, CB mon LO RstDly, becomes visible. When the circuit breaker closes, the CB
mon LO RstDly time starts. The lockout is reset when the timer expires.
If set to User Interface then a command, CB mon LO reset, becomes visible. This command can be used to
reset the lockout from a user interface.
An Autoreclose lockout generates an Autoreclose lockout alarm. Autoreclose lockout conditions can be reset by
various commands and setting options found under the CB CONTROL column.
P841B-TM-EN-1.1 275
If Res LO by CB IS is set to Enabled, a lockout is reset if the circuit breaker is successfully closed manually. For
this, the circuit breaker must remain closed long enough so that it enters the “In Service” state.
If Res LO by UI is set to Enabled, the circuit breaker lockout can be reset from a user interface using the reset
circuit breaker lockout command in the CB CONTROL column.
If Res LO by NoAR is set to Enabled, the circuit breaker lockout can be reset by temporarily generating an AR
disabled signal.
If Res LO by TDelay is set to Enabled, the circuit breaker lockout is automatically reset after a time delay set in
the LO Reset Time setting.
If Res LO by ExtDDB is Enabled, the circuit breaker lockout can be reset by activation of an external input
mapped in the PSL to the relevant reset lockout DDB signal.
276 P841B-TM-EN-1.1
5.7.1 RESET CB LOCKOUT LOGIC DIAGRAM
Res LO by CB IS
Enabled
&
CB1CRLo
Res LO by UI
Enabled
&
Reset CB1 LO
Yes
Res LO by NoAR
Enabled
& 1 ResCB1Lo
ARDisabled
1
Num CBs
CB2 Only
Res LO by ExtDDB
Enabled
&
446
Rst CB1 Lockout
Res LO by TDelay
Enabled
&
LO Reset Time
306
t
CB1 AR Lockout
0
Res LO by CB IS
Enabled
&
CB2CRLo
Res LO by UI
Enabled
&
Reset CB2 LO
Yes
Res LO by NoAR
Enabled
& 1 ResCB2Lo
ARDisabled
1
Num CBs
CB2 Only
Res LO by ExtDDB
Enabled
&
1422
Rst CB2 Lockout
Res LO by TDelay
Enabled
&
LO Reset Time
328
t
CB2 AR Lockout
0
V03383
Figure 132: Reset Circuit Breaker Lockout Logic Diagram (Modules 57 & 58)
5.8.1 SETTING THE THRESHOLDS FOR THE TOTAL BROKEN CURRENT

Where power lines use oil circuit breakers (OCBs), changing of the oil accounts for a significant proportion of the
switchgear maintenance costs. Often, oil changes are performed after a fixed number of CB fault operations.
However, this may result in premature maintenance where fault currents tend to be low, because oil degradation
may be slower than would normally be expected. The Total Current Accumulator (I^ counter) cumulatively stores
the total value of the current broken by the circuit breaker providing a more accurate assessment of the circuit
breaker condition.
P841B-TM-EN-1.1 277
The dielectric withstand of the oil generally decreases as a function of I2t, where ‘I’ is the broken fault current and
‘t’ is the arcing time within the interrupter tank. The arcing time cannot be determined accurately, but is generally
dependent on the type of circuit breaker being used. Instead, you set a factor (Broken I^) with a value between 1
and 2, depending on the circuit breaker.
Most circuit breakers would have this value set to '2', but for some types of circuit breaker, especially those
operating on higher voltage systems, a value of 2 may be too high. In such applications Broken I^ may be set
lower, typically 1.4 or 1.5.
The setting range for Broken I^ is variable between 1.0 and 2.0 in 0.1 steps.
Note:
Any maintenance program must be fully compliant with the switchgear manufacturer’s instructions.
5.8.2 SETTING THE THRESHOLDS FOR THE NUMBER OF OPERATIONS

Every circuit breaker operation results in some degree of wear for its components. Therefore routine maintenance,
such as oiling of mechanisms, may be based on the number of operations. Suitable setting of the maintenance
threshold will allow an alarm to be raised, indicating when preventative maintenance is due. Should maintenance
not be carried out, the device can be set to lockout the autoreclose function on reaching a second operations
threshold (No. CB ops Lock). This prevents further reclosure when the circuit breaker has not been maintained to
the standard demanded by the switchgear manufacturer’s maintenance instructions.
Some circuit breakers, such as oil circuit breakers (OCBs) can only perform a certain number of fault interruptions
before requiring maintenance attention. This is because each fault interruption causes carbonising of the oil,
degrading its dielectric properties. The maintenance alarm threshold (setting No. CB Ops Maint) may be set to
indicate the requirement for oil dielectric testing, or for more comprehensive maintenance. Again, the lockout
threshold No. CB Ops Lock may be set to disable autoreclosure when repeated further fault interruptions could
not be guaranteed. This minimises the risk of oil fires or explosion.
5.8.3 SETTING THE THRESHOLDS FOR THE OPERATING TIME

Slow CB operation indicates the need for mechanism maintenance. Alarm and lockout thresholds (CB Time Maint
and CB Time Lockout) are provided to enforce this. They can be set in the range of 5 to 500 ms. This time relates to
the interrupting time of the circuit breaker.
5.8.4 SETTING THE THRESHOLDS FOR EXCESSSIVE FAULT FREQUENCY

Persistent faults will generally cause autoreclose lockout, with subsequent maintenance attention. Intermittent
faults such as clashing vegetation may repeat outside of any reclaim time, and the common cause might never be
investigated. For this reason it is possible to set a frequent operations counter, which allows the number of
operations Fault Freq Count over a set time period Fault Freq Time to be monitored. A separate alarm and lockout
threshold can be set.
278 P841B-TM-EN-1.1
6 CB STATE MONITORING
CB State monitoring is used to verify the open or closed state of a circuit breaker. Most circuit breakers have
auxiliary contacts through which they transmit their status (open or closed) to control equipment such as IEDs.
These auxiliary contacts are known as:
● 52A for contacts that follow the state of the CB
● 52B for contacts that are in opposition to the state of the CB
This device can be set to monitor both of these types of circuit breaker state indication. If the state is unknown for
some reason, an alarm can be raised.
Some CBs provide both sets of contacts. If this is the case, these contacts will normally be in opposite states.
Should both sets of contacts be open, this would indicate one of the following conditions:
● Auxiliary contacts/wiring defective
● Circuit Breaker (CB) is defective
● CB is in isolated position
Should both sets of contacts be closed, only one of the following two conditions would apply:
● Auxiliary contacts/wiring defective
● Circuit Breaker (CB) is defective
If any of the above conditions exist, an alarm will be issued after a 5 s time delay. An output contact can be
assigned to this function via the programmable scheme logic (PSL). The time delay is set to avoid unwanted
operation during normal switching duties.
In the CB CONTROL column there is a setting called CB Status Input. This cell can be set at one of the following
four options:
● None
● 52A
● 52B
● Both 52A and 52B
Where None is selected no CB status is available. Where only 52A is used on its own then the device will assume a
52B signal opposite to the 52A signal. Circuit breaker status information will be available in this case but no
discrepancy alarm will be available. The above is also true where only a 52B is used. If both 52A and 52B are used
then status information will be available and in addition a discrepancy alarm will be possible, according to the
following table:
Auxiliary Contact Position CB State Detected Action
52A 52B
Open Closed Breaker open Circuit breaker healthy
Closed Open Breaker closed Circuit breaker healthy
Alarm raised if the condition persists for greater than
Closed Closed CB failure
5s
Alarm raised if the condition persists for greater than
Open Open State unknown
5s
P841B-TM-EN-1.1 279
6.1 CB STATE MONITOR

420
CB1 Aux 3ph(52-A)
&
424
CB1 Aux 3ph(52-B)
& 1 907
1 CB1 Closed 3 ph
XOR
&
CB1 Status Input

&
52A 3 pole
52B 3 pole
52A & 52B 3 pole & 1 903
1 CB1 Open 3 ph
&
&
421
CB1 Aux A(52-A)
&
425 908
CB1 Aux A(52-B) 1 CB1 Closed A ph
& 1
XOR
&
&
CB1 Status Input

&
52A 1 pole
52B 1 pole 904
1 CB1 Open A ph
52A & 52B 1 pole & 1
&
&
&
422 909
CB1 Aux B(52-A) 1 CB1 Closed B ph
CB1 Aux B(52-B) 426
905
Phase B 1 CB1 Open B ph
CB1 Status Input
52A 1 pole
52B 1 pole
52A & 52B 1 pole
423 910
CB1 Aux C(52-A) 1 CB1 Closed C ph
CB1 Aux C(52-B) 427
906
Phase C 1 CB1 Open C ph
CB1 Status Input
52A 1 pole
52B 1 pole 301
1 CB1 Status Alm
52A & 52B 1 pole
V01265 CB1 Status Time
Figure 133: CB State logic diagram (Module 1)
280 P841B-TM-EN-1.1
7 CIRCUIT BREAKER CONTROL

Although some circuit breakers do not provide auxiliary contacts, most provide auxiliary contacts to reflect the
state of the circuit breaker. These are:
● CBs with 52A contacts (where the auxiliary contact follows the state of the CB)
● CBs with 52B contacts (where the auxiliary contact is in the opposite state from the state of the CB)
● CBs with both 52A and 52B contacts
Circuit Breaker control is only possible if the circuit breaker in question provides auxiliary contacts. The CB Status
Input cell in the CB CONTROL column must be set to the type of circuit breaker. If no CB auxiliary contacts are
available then this cell should be set to None, and no CB control will be possible.
For local control, the CB control by cell should be set accordingly.
The output contact can be set to operate following a time delay defined by the setting Man Close Delay. One
reason for this delay is to give personnel time to safely move away from the circuit breaker following a CB close
command.
The control close cycle can be cancelled at any time before the output contact operates by any appropriate trip
signal, or by activating the Reset Close Dly DDB signal.
The length of the trip and close control pulses can be set via the Trip Pulse Time and Close Pulse Time settings
respectively. These should be set long enough to ensure the breaker has completed its open or close cycle before
the pulse has elapsed.
If an attempt to close the breaker is being made, and a protection trip signal is generated, the protection trip
command overrides the close command.
The Reset Lockout by setting is used to enable or disable the resetting of lockout automatically from a manual
close after the time set by Man Close RstDly.
If the CB fails to respond to the control command (indicated by no change in the state of CB Status inputs) an
alarm is generated after the relevant trip or close pulses have expired. These alarms can be viewed on the LCD
display, remotely, or can be assigned to output contacts using the programmable scheme logic (PSL).
Note:
The CB Healthy Time and Sys Check time set under this menu section are applicable to manual circuit breaker operations
only. These settings are duplicated in the AUTORECLOSE menu for autoreclose applications.
The Lockout Reset and Reset Lockout by settings are applicable to CB Lockouts associated with manual circuit
breaker closure, CB Condition monitoring (Number of circuit breaker operations, for example) and autoreclose
lockouts.
The device includes the following options for control of a single circuit breaker:
● The IED menu (local control)
● The Hotkeys (local control)
● The function keys (local control)
● The opto-inputs (local control)
● SCADA communication (remote control)
7.1 CB CONTROL USING THE IED MENU

You can control manual trips and closes with the CB Trip/Close command in the SYSTEM DATA column. This can be
set to No Operation, Trip, or Close accordingly.
P841B-TM-EN-1.1 281
For this to work you have to set the CB control by cell to option 1 Local, option 3 Local + Remote, option 5
Opto+Local, or option 7 Opto+Local+Remote in the CB CONTROL column.
7.2 CB CONTROL USING THE HOTKEYS

The hotkeys allow you to manually trip and close the CB without the need to enter the SYSTEM DATA column. For
this to work you have to set the CB control by cell to option 1 Local, option 3 Local+Remote, option 5 Opto
+Local, or option 7 Opto+Local+Remote in the CB CONTROL column.
CB control using the hotkey is achieved by pressing the right-hand button directly below LCD screen. This button is
only enabled if:
● The CB Control by setting is set to one of the options where local control is possible (option 1,3,5, or 7)
● The CB Status Input is set to '52A', '52B', or 'Both 52A and 52B'
If the CB is currently closed, the command text on the bottom right of the LCD screen will read Trip. Conversely, if
the CB is currently open, the command text will read Close.
If you execute a Trip, a screen with the CB status will be displayed once the command has been completed. If
you execute a Close, a screen with a timing bar will appear while the command is being executed. This screen
also gives you the option to cancel or restart the close procedure. The time delay is determined by the Man Close
Delay setting in the CB CONTROL menu. When the command has been executed, a screen confirming the present
status of the circuit breaker is displayed. You are then prompted to select the next appropriate command or exit.
If no keys are pressed for a period of 5 seconds while waiting for the command confirmation, the device will revert
to showing the CB Status. If no key presses are made for a period of 25 seconds while displaying the CB status
screen, the device will revert to the default screen.
To avoid accidental operation of the trip and close functionality, the hotkey CB control commands are disabled for
10 seconds after exiting the hotkey menu.
The hotkey functionality is summarised graphically below:
Default Display
HOTKEY CB CTRL
Hotkey Menu
CB closed CB open
<CB STATUS> EXECUTE <CB STATUS> EXECUTE EXECUTE CLOSE

CLOSED CB TRIP OPEN CB CLOSE 30 secs
TRIP EXIT CONFIRM CANCEL EXIT CLOSE CANCEL CONFIRM CANCEL RESTART
E01209
Figure 134: Hotkey menu navigation
7.3 CB CONTROL USING THE FUNCTION KEYS

For most models, you can also use the function keys to allow direct control of the circuit breaker. This has the
advantage over hotkeys, that the LEDs associated with the function keys can indicate the status of the CB. The
282 P841B-TM-EN-1.1
default PSL is set up such that Function key 2 initiates a trip and Function key 3 initiates a close. For this to work
you have to set the CB control by cell to option 5 Opto+Local, or option 7 Opto+Local+Remote in the CB
CONTROL column.
As shown below, function keys 2 and 3 have already been assigned to CB control in the default PSL.
Function Key 2 Init Trip CB
Non- FnKey LED2 Red

Latching FnKey LED2 Grn
Function Key 3 Init Close CB
1 Non- FnKey LED3 Red

Close in Prog
Latching FnKey LED3 Grn
V01245
Figure 135: Default function key PSL
The programmable function key LEDs have been mapped such that they will indicate yellow whilst the keys are
activated.
Note:
Not all models provide function keys.
7.4 CB CONTROL USING THE OPTO-INPUTS

Certain applications may require the use of push buttons or other external signals to control the various CB control
operations. It is possible to connect such push buttons and signals to opto-inputs and map these to the relevant
DDB signals.
For this to work, you have to set the CB control by cell to option 4 opto, option 5 Opto+Local, option 6 Opto
+Remote, or option 7 Opto+Local+Remote in the CB CONTROL column.
7.5 REMOTE CB CONTROL

Remote CB control can be achieved by setting the CB Trip/Close cell in the SYSTEM DATA column to trip or close by
using a command over a communication link.
For this to work, you have to set the CB control by cell to option 2 Remote, option 3 Local+Remote, option 6
Opto+remote, or option 7 Opto+Local+Remote in the CB CONTROL column.
We recommend that you allocate separate relay output contacts for remote CB control and protection tripping.
This allows you to select the control outputs using a simple local/remote selector switch as shown below. Where
this feature is not required the same output contact(s) can be used for both protection and remote tripping.
P841B-TM-EN-1.1 283
Protection Trip
Trip
Remote
Control
Trip Close
Remote
Control
Close
Local
Remote
Trip Close
E01207
Figure 136: Remote Control of Circuit Breaker
7.6 CB HEALTHY CHECK

A CB Healthy check is available if required. This facility accepts an input to one of the opto-inputs to indicate that
the breaker is capable of closing (e.g. that it is fully charged). A time delay can be set with the setting CB Healthy
Time. If the CB does not indicate a healthy condition within the time period following a Close command, the device
will lockout and alarm.
7.7 SYNCHRONISATION CHECK

Where the check synchronism function is set, this can be enabled to supervise manual circuit breaker Close
commands. A circuit breaker Close command will only be issued if the Check Synchronisation criteria are satisfied.
A time delay can be set with the setting Sys Check time. If the Check Synchronisation criteria are not satisfied
within the time period following a Close command the device will lockout and alarm.
7.8 CB CONTROL AR IMPLICATIONS

An Auto Close CB signal from the Auto-close logic bypasses the Man Close Delay time, and the CB Close output
operates immediately to close the circuit breaker.
If Autoreclose is used it may be desirable to block its operation when performing a manual close. In general, the
majority of faults following a manual closure are permanent faults and it is undesirable to allow automatic
reclosure.
To ensure that Autoreclose is not initiated for a manual circuit breaker closure on to a pre-existing fault, the CB IS
Time (circuit breaker in service time) setting in the AUTORECLOSE menu should be set for the desired time window.
This setting ensures that Autoreclose initiation is inhibited for a period equal to setting CB IS Time following a
manual circuit breaker closure. If a protection operation occurs during the inhibit period, Autoreclose is not
initiated.
284 P841B-TM-EN-1.1
Following manual circuit breaker closure, if either a single phase or a three phase fault occur, the circuit breaker is
tripped three phase, but Autoreclose is not locked out for this condition.
7.9 CB CONTROL LOGIC DIAGRAM

CB Control by
Opto
Note : If the DDB signal CB1 Healthy or CB2 Healthy is not mapped in PSL , it
Opto +Local defaults to High .
1
Opto+Remote
Opto+Rem+Local
Trip Pulse Time
838
1
& S t
439
& Q 302
440 &
1 842
CB1 Close inProg
HMI Close
& S t
CB1 ARIP 1544 Q 839
854
1 S t
Auto Close CB1 Q
RD 0
443
Rst CB1 CloseDly
522 303
1
838
Control TripCB1
534
CB1 Ext Trip3ph 1
1
535
CB1 Ext Trip A
536
CB1 Ext Trip B
537
CB1 Ext Trip C
1 1
903
CB1 Open 3 ph
1
904
CB1 Open A ph
905
CB1 Open B ph &
906
CB1 Open C ph
907
CB1 Closed 3 ph
1
908
CB1 Closed A ph
CB1 Closed B ph 909

1 CB Healthy Time
910
CB1 Closed C ph
t 304
436
& ManCB1 Unhealthy
CB1 Healthy 0
Check Sync Time
t 305
1574
& NoCS CB1ManClose
CB1 Man SCOK 0
V03370
P841B-TM-EN-1.1 285
CB Control by
Opto
Opto +Local Note: If the DDB signal CB 1 Healthy, or CB2 healthy is not mapped in PSL , it defaults to
1 High.
Opto+Remote
Opto+Rem+Local
Trip Pulse Time
840
1
& S t
441
& Q 324
442 &
1 1453
CB2 Close inProg
HMI Close
& S t
CB2 ARIP 1435 Q 841
1448
1 S t
Auto Close CB2 Q
RD 0
1419
Rst CB2 CloseDly
522 325
1
840
Control TripCB2
538
CB2 Ext Trip3ph 1
1
539
CB2 Ext Trip A
540
CB2 Ext Trip B
541
CB2 Ext Trip C
1 1
911
CB2 Open 3 ph
912
CB2 Open A ph
913
CB2 Open B ph &
914
CB2 Open C ph
915
CB2 Closed 3 ph
1
916
CB2 Closed A ph
CB2 Closed B ph 917

1 CB Healthy Time
918
CB2 Closed C ph
t 326
437
& ManCB2 Unhealthy
CB2 Healthy 0
Check Sync Time
t 327
1458
& NoCS CB2ManClose
CB2 Man SCOK 0
V03344
286 P841B-TM-EN-1.1
8 POLE DEAD FUNCTION

The Pole Dead Logic is used to determine and indicate that one or more phases of the line are not energised. A
Pole Dead condition is determined either by measuring:
● the line currents and/or voltages, or
● by monitoring the status of the circuit breaker auxiliary contacts, as shown by dedicated DDB signals.
It can also be used to block operation of underfrequency and undervoltage elements where applicable.
8.1 POLE DEAD LOGIC

IA 20 ms
I< Current Set &

1 Pole Dead A
VA
V<
CB1 Open A ph
&
CB2 Open A ph
IB 20 ms
I< Current Set &

1 Pole Dead B
VB
V<
CB1 Open B ph
&
CB2 Open B ph
IC 20 ms
I< Current Set &

1 Pole Dead C
VC
1 Any Pole Dead

V<
VTS Slow Block

& All Poles Dead
CB1 Open C ph
&
CB2 Open C ph
CB1 Open 3 ph
&
CB2 Open 3 ph
V01269
Figure 139: Pole Dead logic
If both the line current and voltage values fall below a certain threshold, or a CB Open condition is asserted from
the state control logic, the device initiates a Pole Dead condition. The current and voltage thresholds can be set
with the I< Current Set and the V< settings respectively, in the CBFAIL&P.DEAD column.
If one or more poles are dead, the device indicates which phase is dead and asserts the Any Pole Dead DDB
signal. If all phases are dead the Any Pole Dead signal is accompanied by the All Poles Dead signal.
If the VT fails, a VTS Slow Block signal is taken from the VTS logic to block the Pole Dead indications that would be
generated by the undervoltage and undercurrent thresholds.
P841B-TM-EN-1.1 287
9 SYSTEM CHECKS
In some situations it is possible for both "bus" and "line" sides of a circuit breaker to be live when a circuit breaker is
open - for example at the ends of a feeder that has a power source at each end. Therefore, it is normally necessary
to check that the network conditions on both sides are suitable, before closing the circuit breaker. This applies to
both manual circuit breaker closing and autoreclosing. If a circuit breaker is closed when the line and bus voltages
are both live, with a large phase angle, frequency or magnitude difference between them, the system could be
subjected to an unacceptable shock, resulting in loss of stability, and possible damage to connected machines.
The System Checks functionality involves monitoring the voltages on both sides of a circuit breaker, and if both
sides are live, performing a synchronisation check to determine whether any differences in voltage magnitude,
phase angle or frequency are within permitted limits.
The pre-closing system conditions for a given circuit breaker depend on the system configuration, and for
autoreclosing, on the selected autoreclose program. For example, on a feeder with delayed autoreclosing, the
circuit breakers at the two line ends are normally arranged to close at different times. The first line end to close
usually has a live bus and a dead line immediately before reclosing. The second line end circuit breaker now sees a
live bus and a live line.
If there is a parallel connection between the ends of the tripped feeder the frequencies will be the same, but any
increased impedance could cause the phase angle between the two voltages to increase. Therefore just before
closing the second circuit breaker, it may be necessary to perform a synchronisation check, to ensure that the
phase angle between the two voltages has not increased to a level that would cause unacceptable shock to the
system when the circuit breaker closes.
If there are no parallel interconnections between the ends of the tripped feeder, the two systems could lose
synchronism altogether and the frequency at one end could "slip" relative to the other end. In this situation, the
second line end would require a synchronism check comprising both phase angle and slip frequency checks.
If the second line-end busbar has no power source other than the feeder that has tripped; the circuit breaker will
see a live line and dead bus assuming the first circuit breaker has re-closed. When the second line end circuit
breaker closes the bus will charge from the live line (dead bus charge).
9.1 SYSTEM CHECKS IMPLEMENTATION

The System Checks function provides Live/Dead Voltage Monitoring, two stages of Check Synchronisation and
System Split indication.
The System Checks function is enabled or disabled by the System Checks setting in the CONFIGURATION column. If
System Checks is disabled, the SYSTEM CHECKS menu becomes invisible, and a SysChks Inactive DDB signal is
set.
The system Checks functionality can also be enabled or disabled individually for each circuit breaker by the
System Checks CB1 and System Checks CB2 settings in the SYSTEM CHECKS column. For the Systems Checks
functionality to be enabled, both the System Checks setting in the CONFIGURATION column AND the relevant
setting (System Checks CB1 and/or System Checks CB2) in the SYSTEM CHECKS column must be enabled. For the
System Checks functionality to be disabled, either the System Checks setting in the CONFIGURATION column OR
the relevant setting (System Checks CB1 and/or System Checks CB2) in the SYSTEM CHECKS column must be be
enabled. In the latter case, the SysChks Inactive DDB signal is set.
9.1.1 VT CONNECTIONS
The device provides inputs for a three-phase "Main VT" and at least one single-phase VT for check synchronisation.
Depending on the primary system arrangement, the Main VT may be located on either the line-side of the busbar-
side of the circuit breaker, with the Check Sync VT on the other. Normally, the Main VT is located on the line-side (as
per the default setting), but this is not always the case. For this reason, a setting is provided where you can define
this. This is the Main VT Location setting, which is found in the CT AND VT RATIOS column.
288 P841B-TM-EN-1.1
The Check Sync VT may be connected to one of the phase-to-phase voltages or phase-to-neutral voltages. This
needs to be defined using the CS Input setting in the CT AND VT RATIOS column. Options are, A-B, B-C, C-A, A-N, B-
N, or C-N.
9.1.2 VOLTAGE MONITORING

The settings in the VOLTAGE MONITORS sub-heading in the SYSTEM CHECKS column allow you to define the
threshold at which a voltage is considered live, and a threshold at which the voltage is considered dead. These
thresholds apply to both line and bus sides. If the measured voltage falls below the Dead Voltage setting, a DDB
signal is generated (Dead Bus, or Dead Line, depending on which side is being measured). If the measured voltage
exceeds the Live Voltage setting, a DDB signal is generated (Live Bus, or Live Line, depending on which side is
being measured).
9.1.3 CHECK SYNCHRONISATION

The device provides two stages of Check Synchronisation. The first stage (CS1) is intended for use in synchronous
systems. This means, where the frequencies and phase angles of both sides are compared and if the difference is
within set limits, the circuit breaker is allowed to close. The second stage (CS2) is similar to stage, but has an
additional adaptive setting. The second stage CS2 is intended for use in asynchronous systems, i.e. where the two
sides are out of synchronism and one frequency is slipping continuously with respect to another. If the closing time
of the circuit breaker is known, the CB Close command can be issued at a definite point in the cycle such that the
CB closes at the point when both sides are in phase.
In situations where it is possible for the voltages on either side of a circuit breaker to be either synchronous or
asynchronous, both CS1 and CS2 can be enabled to provide a CB Close signal if either set of permitted closing
conditions is satisfied.
Each stage can also be set to inhibit circuit breaker closing if selected blocking conditions such as overvoltage,
undervoltage or excessive voltage magnitude difference are detected. CS2 requires the phase angle difference to
be decreasing in magnitude before permitting the circuit breaker to close. CS2 has an optional “Adaptive” closing
feature, which issues the permissive close signal when the predicted phase angle difference immediately prior to
the instant of circuit breaker main contacts closing (i.e. after CB Close time) is as close as practicable to zero.
Slip frequency is the rate of change of phase between each side of the circuit breaker, which is measured by the
difference between the voltage signals on either side of the circuit breaker.
Having two system synchronism check stages available allows the circuit breaker closing to be enabled under
different system conditions (for example, low slip / moderate phase angle, or moderate slip / small phase angle).
The settings specific to Check Synchronisation are found under the sub-heading CHECK SYNC in the SYSTEM
CHECKS column. The only difference between the CS1 settings and the CS2 settings is that CS2 has settings for
predictive closure of each CB (CB1 CS2 Adaptive and CB2 CS2 Adaptive).
9.1.4 CHECK SYNCRONISATION VECTOR DIAGRAM

The following vector diagram represents the conditions for the System Check functionality. The Dead Volts setting
is represented as a circle around the origin whose radius is equal to the maximum voltage magnitude, whereby
the voltage can be considered dead. The nominal line voltage magnitude is represented by a circle around the
origin whose radius is equal to the nominal line voltage magnitude. The minimum voltage magnitude at which the
system can be considered as Live, is the magnitude difference between the bus and line voltages.
P841B-TM-EN-1.1 289
0º
Check Sync
Stage 2 Limits
Check Sync
Stage 1 Limits
V
BUS
Live Volts
Rotating
Vector
Nomical
Volts
V LINE
Dead Volts
±180º
System Split
E01204 Limits
Figure 140: Check Synchronisation vector diagram
290 P841B-TM-EN-1.1
9.2 VOLTAGE MONITOR FOR CB CLOSURE

System Checks
Enabled
VAN 888
Live Line & Live Line
VBN
VCN 889
Select Dead Line & Dead line
VAB
VBC 886
VCA
VBus1 Dead Bus 1 & 887

Dead Bus 1
VBus 2
1461
MCB/VTS 438
1521 1462
MCB/VTS CB1 CS Dead Bus 2 & Dead Bus 2
1423
MCB/VTS CB2 CS
Voltage Monitors
1522 1
Inhibit LL
1523 1
Inhibit DL
1524 1
Inhibit LB 1
1525
1
Inhibit DB 1
1424 1
Inhibit LB 2
1425 1
Inhibit DB 2
V 01258
Figure 141: Voltage Monitor for CB Closure (Module 59)
P841B-TM-EN-1.1 291
9.3 CHECK SYNCHRONISATION MONITOR FOR CB CLOSURE

Sys checks CB 1
880
Enabled
CS1 Criteria OK
VAN &
VBN CS2 Criteria OK
&
VCN

& CB1 CS1 SlipF<
& CB1 CS2 SlipF>
VBus1
CB1 CS2 SlipF< 1465
& CB1 CS2 SlipF<
CS Vline> 1581
& CS Vline>
CS Vbus1> 1583
& CS Vbus1>
CS Vline< 1580
& CS Vline<
CS Vbus1< 1582
& CS Vbus<
CB1 CS1 Vl>Vb 1586
& CB1 CS1 Vl> Vb
CB1 CS1 Vl<Vb 1588
& CB1 CS1 Vl< Vb
CB1 CS1 Fl>Fb 1590
& CB1 CS1 Fl>Fb
CB1 CS1 Fl<Fb 1591
& CB1 CS1 Fl<Fb
& CB1 CS1 AngHigh+
& CB1 CS1 AngHigh-
CB1 CS2 Fl>Fb 1493
& CB1 CS2 Fl>Fb
CB1 CS2 Fl<Fb 1494
& CB1 CS2 Fl<Fb
& CB1 CS2 AngHigh+
& CB1 CS2 AngHigh-
& CB1 CS AngRotACW
1521
MCB/VTS
832 CB1 CS2 Vl>Vb 1587
1
319
& CB1 CS2 Vl< Vb
CB1 CS1 Status
883
881
CB1 CS1 Enabled
CB1 CS2 Status
884
882
292 P841B-TM-EN-1.1
Sys checks CB 2
1484
Enabled
CS1 Criteria OK
VAN &
VBN CS1 Criteria OK

&
VCN

& CB2 CS1 SlipF<
& CB2 CS2 SlipF>
VBus2
CB2 CS2 SlipF< 1469
& CB2 CS2 SlipF<
&
CS Vbus2> 1585
& CS Vbus2>
&
CS Vbus2<
1584
& CS Vbus2<
CB2 CS1 Vl>Vb 1470
& CB2 CS1 Vl> Vb
CB2 CS1 Vl<Vb 1472
& CB2 CS1 Vl< Vb
CB2 CS1 Fl>Fb 1474
& CB2 CS1 Fl>Fb
CB2 CS1 Fl<Fb 1476
& CB2 CS1 Fl<Fb
& CB2 CS1 AngHigh+
& CB2 CS1 AngHigh-
CB2 CS2 Fl>Fb 1475
& CB2 CS2 Fl>Fb
CB2 CS2 Fl<Fb 1477
& CB2 CS2 Fl<Fb
& CB2 CS2 AngHigh+
& CB2 CS2 AngHigh-
& CB2 CS AngRotACW
1521
MCB/VTS
832 CB2 CS2 Vl>Vb 1471
1
319
& CB2 CS2 Vl< Vb
CB2 CS1 Status
1577
1426
CB2 CS1 Enabled
CB2 CS2 Status
884
1427
P841B-TM-EN-1.1 293
9.4 SYSTEM CHECK PSL
SysChks Inactive
Check Sync 1 OK
Check Sync 2 OK
Live Line Man Check Synch

&
Dead Bus 1 AR Sys Checks
&
Dead Line
&
Live Bus
V02028
Figure 144: System Check PSL
9.5.1 PREDICTIVE CLOSURE OF CIRCUIT BREAKERS

The CB1 CS2 Adaptive and CB1 CS2 Adaptive settings compensate for the time taken to close the CB. When set to
provide CB Close Time compensation, a predictive approach is used to close the circuit breaker ensuring that
closing occurs at close to 0º therefore minimising the impact to the power system. The actual closing angle is
subject to the constraints of the existing product architecture, i.e. the protection task runs twice per power system
cycle, based on frequency tracking over the frequency range of 40 Hz to 65 Hz.
9.5.2 VOLTAGE AND PHASE ANGLE CORRECTION

For the Check Synchronisation function, the device needs to convert measured secondary voltages into primary
voltages. In some applications, VTs either side of the circuit breaker may have different VT Ratios. In such cases, a
magnitude correction factor is required.
There are some applications where the main VT is on the HV side of a transformer and the Check Sync VT is on the
LV side, or vice-versa. If the vector group of the transformer is not "0", the voltages are not in phase, so phase
correction is also necessary.
The correction factors are as follows and are located in the CT AND VT RATIOS column:
● C/S V kSM, where kSM is the voltage correction factor.
● C/S Phase kSA, where kSA is the angle correction factor.
Assuming C/S input setting is A-N, then:
The line and bus voltage magnitudes are matched if Va sec = Vcs sec x C/S V kSA
The line and bus voltage angles are matched if ÐVa sec = ÐVcs sec + C/S Phase kSA
The following application scenarios show where the voltage and angular correction factors are applied to match
different VT ratios:
CS Correction
Physical Ratios (ph-N Values) Setting Ratios
Factors
Scenario Main VT Ratio (ph-
Main VT Ratio CS VT Ratio CS VT Ratio
ph) Always kSM kSA
Pri (kV) Sec (V) Pri (kV) Sec (V) Pri (kV) Sec (V) Pri (kV) Sec (V)
1 220/√3 110/√3 132/√3 100/√3 220 110 132 100 1.1 30º
294 P841B-TM-EN-1.1
2 220/√3 110/√3 220/√3 110 220 110 127 110 0.577 0º

3 220/√3 110/√3 220/√3 110/3 220 110 381 110 1.732 0º
P841B-TM-EN-1.1 295
296 P841B-TM-EN-1.1
CHAPTER 13
SUPERVISION
Chapter 13 - Supervision P841B
298 P841B-TM-EN-1.1
P841B Chapter 13 - Supervision
1 CHAPTER OVERVIEW
This chapter describes the supervison functions.
Voltage Transformer Supervision 300
Current Transformer Supervision 304
Trip Circuit Supervision 306
P841B-TM-EN-1.1 299
2 VOLTAGE TRANSFORMER SUPERVISION

The Voltage Transformer Supervision (VTS) function is used to detect failure of the AC voltage inputs to the
protection. This may be caused by voltage transformer faults, overloading, or faults on the wiring, which usually
results in one or more of the voltage transformer fuses blowing.
If there is a failure of the AC voltage input, the IED could misinterpret this as a failure of the actual phase voltages
on the power system, which could result in unnecessary tripping of a circuit breaker.
The VTS logic is designed to prevent such a situation by detecting voltage input failures, which are NOT caused by
power system phase voltage failure, and automatically blocking associated voltage dependent protection
elements. A time-delayed alarm output is available to warn of a VTS condition.
The following scenarios are possible with respect to the failure of the VT inputs.
● Loss of one or two-phase voltages
● Loss of all three-phase voltages under load conditions
● Absence of three-phase voltages upon line energisation
2.1 LOSS OF ONE OR TWO PHASE VOLTAGES

If the power system voltages are healthy, no Negative Phase Sequence (NPS) current will be present. If however,
one or two of the AC voltage inputs are missing, there will be Negative Phase Sequence voltage present, even if the
actual power system phase voltages are healthy. VTS works by detecting Negative Phase Sequence (NPS) voltage
without the presence of Negative Phase Sequence current. So if there is NPS voltage present, but no NPS current,
it is certain that there is a problem with the voltage transformers and a VTS block should be applied to voltage
dependent protection functions to prevent maloperation. The use of negative sequence quantities ensures correct
operation even where three-limb or V-connected VTs are used.
The Negative Sequence VTS Element is blocked by the Any Pole Dead DDB signal during SP AR Dead Time. The
resetting of the blocking signal is delayed by 240 ms after an Any Pole Dead condition disappears.
2.2 LOSS OF ALL THREE PHASE VOLTAGES

If all three voltage inputs are lost, there will be no Negative Phase Sequence quantities present, but the device will
see that there is no voltage input. If this is caused by a power system failure, there will be a step change in the
phase currents. However, if this is not caused by a power system failure, there will be no change in any of the
phase currents. So if there is no measured voltage on any of the three phases and there is no change in any of the
phase currents, this indicates that there is a problem with the voltage transformers and a VTS block should be
applied to voltage dependent protection functions to prevent maloperation.
To avoid blocking VTS due to changing load condition, the superimposed current signal can only prevent operation
of the VTS during the time window of 40 ms following the voltage collapse.
2.3 ABSENCE OF ALL THREE PHASE VOLTAGES ON LINE ENERGISATION

On line energisation there should be a change in the phase currents as a result of loading or line charging current.
Under this condition we need an alternative method of detecting three-phase VT failure.
If there is no measured voltage on all three phases during line energisation, two conditions might apply:
● A three-phase VT failure
● A close-up three-phase fault.
The first condition would require VTS to block the voltage-dependent functions.
In the second condition, voltage dependent functions should not be blocked, as tripping is required.
To differentiate between these two conditions an overcurrent level detector is used (VTS I> Inhibit). This prevents a
VTS block from being issued in case of a genuine fault. This overcurrent level detector is only enabled for 240 ms
300 P841B-TM-EN-1.1
following line energization (based on an All Poles Dead signal drop off). It must still be set in excess of any non-
fault based currents on line energisation (load, line charging current, transformer inrush current if applicable), but
below the level of current produced by a close-up three-phase fault.
If the line is closed where a three-phase VT failure is present, the overcurrent detector will not operate and a VTS
block will be applied. Closing onto a three-phase fault will result in operation of the overcurrent detector and
prevent a VTS block being applied.
2.4 VTS IMPLEMENTATION

VTS is implemented in the SUPERVISION column of the relevant settings group.
The following settings are relevant for VT Supervision:
● VTS Mode: determines the mode of operation (Measured + MCB, Measured Only, MCB Only)
● VTS Status: determines whether the VTS Operate output will be a blocking output or an alarm indication
only
● VTS Reset Mode: determines whether the Reset is to be manual or automatic
● VTS Time Delay: determines the operating time delay
● VTS I> Inhibit: inhibits VTS operation in the case of a phase overcurrent fault
● VTS I2> Inhibit: inhibits VTS operation in the case of a negative sequence overcurrent fault
For faults with I2 less than the setting VTS I2 Inhibit, VTS will be active and block the associated functions if
sufficient V2 is measured. VTS is only enabled during a live line condition (as indicated by the pole dead logic) to
prevent operation under dead system conditions.
Thresholds
The negative sequence thresholds used by the element are:
● V2 = 10 V (fixed)
● I2 = 0.05 to 0.5 In settable (default 0.05 In).
The phase voltage level detectors are:

● Drop off = 10 V (fixed)
● Pickup = 30 V (fixed)
The sensitivity of the superimposed current elements is fixed at 0.1 In.
Fuse Fail
The device includes a setting (VT Connected ) in the CT AND VT RATIOS column, which determines whether there
are voltage transformers connected to it. If set to Yes, this setting has no effect.
If set to No it causes the VTS logic to set the VTS Slow Block and VTS Fast Block DDBs, but not raise any alarms. It
also disables the VTS function. This prevents the pole dead logic working incorrectly if there is no voltage or
current. It also blocks the distance, under voltage and other voltage-dependant functions. However, it does not
affect the CB open part of the logic.
A VTS condition can be raised by a mini circuit breaker (MCB) status input, by internal logic using IED
measurement, or both. The setting VTS Mode is used to select the method of indicating VT failure.
P841B-TM-EN-1.1 301
2.5 VTS LOGIC
& 1
All Poles Dead

IA
240ms
VTS I> Inhibit

IB &
1
VTS I> Inhibit
IC
VTS I> Inhibit
VA
VTS Time Delay

Hardcoded threshold
VB
1 t
Hardcoded threshold 1 & S
0 Q
VC R 1
& VTS Slow Block
Hardcoded threshold
Delt a IA 40m s
& S 1 & VTS Fast Block

Hardcoded threshold Q
R
Delt a IB
1
Hardcoded threshold 1
Delt a IC
Hardcoded threshold
&
V2
Hardcoded threshold & & S

Q
I2
R
I2>1 Current Set &

Any Volt age
dependent function
VTS Reset Mode
Manual &
1
Auto
MCB/VTS
VTS Status
Indicat ion
Blocking
20ms 1 S 1 VT Fail Alarm
Any Pole Dead & Q
240ms 0 R
&
VTS Acc Ind
5
Cycl e
1½
½ Cycl e
Cycl e
VT Fast Block 1 Block Distance
&
All Poles Dead ½
Cycl e V01261
Figure 145: VTS logic
302 P841B-TM-EN-1.1
The IED may respond as follows, on operation of any VTS element:

● VTS set to provide alarm indication only
● Optional blocking of voltage-dependent protection elements
● Optional conversion of directional overcurrent elements to non-directional protection (by setting the
relevant current protection status cells to Enabled VTS. In this case, the directional setting cells are
automatically set to non-directional.)
The VTS I> Inhibit or VTS I2> Inhibit elements are used to override a VTS block if a fault occurs that could trigger
the VTS logic. However, once the VTS block is set, subsequent system faults must not override the block. Therefore
the VTS block is latched after a settable time delay (VTS Time Delay). Once the signal has latched, there are two
methods of resetting. The first is manually using the front panel HMI, or remote communications (if the VTS
condition has been removed). The second is in Auto mode, by restoring the 3 phase voltages above the phase level
detector settings mentioned previously.
VTS Status can be set to Disabled, Blocking or Indication. If VTS Status is set to Blocking, a VTS
condition will block operation of the relevant protection elements. In this case, a VTS indication is given after the
VTS Time Delay has expired. If it is set to Indication, their is a risk of maloperation because protection
elements are not blocked. In this case the VTS indication is given before the VTS Time Delay expires, if a trip signal
is given (in this case a signal from the VTS acceleration logic is used as an input).
This scheme also operates correctly under very low load or even no load conditions. To achieve this, it uses a
combination of time delayed signals derived from the DDB signals VTS Fast Block and All Poles Dead, to generate
the distance blocking DDB signal called VTS Blk Distance.
Note:
All non-distance voltage-dependent elements are blocked by the VTS Fast Block DDB.
If a miniature circuit breaker (MCB) is used to protect the voltage transformer output circuits, MCB auxiliary
contacts can be used to indicate a three-phase output disconnection. It is possible for the VTS logic to operate
correctly without this input, but this facility has been provided to maintain compatibility with some practises.
Energising an opto-isolated input assigned to the MCB/VTS provides the necessary block.
The VTS function is inhibited if:
● An All Poles Dead DDB signal is present
● Any phase overcurrent condition exists
● A Negative Phase Sequence current exists
● If the phase current changes over the period of 1 cycle
P841B-TM-EN-1.1 303
3 CURRENT TRANSFORMER SUPERVISION

The Current Transformer Supervision function (CTS) is used to detect failure of the AC current inputs to the
protection. This may be caused by internal current transformer faults, overloading, or faults on the wiring. If there
is a failure of the AC current input, the protection could misinterpret this as a failure of the actual phase currents
on the power system, which could result in maloperation. Also, interruption in the AC current circuits can cause
dangerous CT secondary voltages to be generated.
3.1 CTS IMPLEMENTATION

If the power system currents are healthy, no zero sequence voltage are derived. However, if one or more of the AC
current inputs are missing, a zero sequence current would be derived, even if the actual power system phase
currents are healthy. Standard CTS works by detecting a derived zero sequence current where there is no
corresponding derived zero sequence voltage.
The voltage transformer connection used must be able to refer zero sequence voltages from the primary to the
secondary side. Therefore, this element should only be enabled where the VT is of a five-limb construction, or
comprises three single-phase units with the primary star point earthed.
The CTS function is implemented in the SUPERVISION column of the relevant settings group, under the sub-heading
CT SUPERVISION.
The following settings are relevant for CT Supervision:
● CTS Status: to disable or enable CTS
● CTS VN< Inhibit: inhibits CTS if the zero sequence voltage exceeds this setting
● CTS IN> Set: determines the level of zero sequence current
● CTS Time Delay: determines the operating time delay
304 P841B-TM-EN-1.1
3.2 STANDARD CTS LOGIC

CTS Time Delay
IN2
& Pickup S
CTS IN> Set
Q CT1 Fail Alarm
VN & R
CTS VN< Inhibit 1

& CTS Block
Inhibit CTS
1
Disable CTS
CTS Status 1
In indication mode , timer is set to 20 ms
Indication
Restrain
CTS Reset Mode

Manual
Auto
CTS Time Delay
IN2
& Pickup S
CTS IN> Set
Q CT2 Fail Alarm
VN & R
CTS VN< Inhibit
Inhibit CTS
1
Disable CTS
CTS Status 1
In indication mode , timer is set to 20 ms
Indication
CTS Reset Mode

Manual
Auto V01270
Figure 146: Standard CTS
3.3 CTS BLOCKING

Both the standard and differential CTS methods block protection elements operating from derived quantities, such
as Broken conductor, derived earth fault and negative sequence overcurrent. Measured quantities such as DEF
can be selectively blocked by designing an appropriate PSL scheme.
Differential CTS can be used to restrain the differential protection if required.

The residual voltage setting, CTS VN< Inhibit and the residual current setting, CTS IN> Set, should be set to avoid
unwanted operation during healthy system conditions. For example:
● CTS VN< Inhibit should be set to 120% of the maximum steady state residual voltage.
● CTS IN> Set will typically be set below minimum load current.
● CTS Time Delay is generally set to 5 seconds.
Where the magnitude of residual voltage during an earth fault is unpredictable, the element can be disabled to
prevent protection elements being blocked during fault conditions.
P841B-TM-EN-1.1 305
4 TRIP CIRCUIT SUPERVISION

In most protection schemes, the trip circuit extends beyond the IED enclosure and passes through components
such as links, relay contacts, auxiliary switches and other terminal boards. Such complex arrangements may
require dedicated schemes for their supervision.
There are two distinctly separate parts to the trip circuit; the trip path, and the trip coil. The trip path is the path
between the IED enclosure and the CB cubicle. This path contains ancillary components such as cables, fuses and
connectors. A break in this path is possible, so it is desirable to supervise this trip path and to raise an alarm if a
break should appear in this path.
The trip coil itself is also part of the overall trip circuit, and it is also possible for the trip coil to develop an open-
circuit fault.
This product supports a number of trip circuit supervision (TCS) schemes.
4.1 TRIP CIRCUIT SUPERVISION SCHEME 1

This scheme provides supervision of the trip coil with the CB open or closed, however, it does not provide
supervision of the trip path whilst the breaker is open. The CB status can be monitored when a self-reset trip
contact is used. However, this scheme is incompatible with latched trip contacts, as a latched contact will short out
the opto-input for a time exceeding the recommended Delayed Drop-off (DDO) timer setting of 400 ms, and
therefore does not support CB status monitoring. If you require CB status monitoring, further opto-inputs must be
used.
Note:
A 52a CB auxiliary contact follows the CB position. A 52b auxiliary contact is the opposite.
+ve
Trip Output Relay 52A Trip coil

Trip path
Blocking diode
52B
R1 Opto-input Circuit Breaker

V01214 -ve
Figure 147: TCS Scheme 1
When the CB is closed, supervision current passes through the opto-input, blocking diode and trip coil. When the
CB is open, supervision current flows through the opto-input and into the trip coil via the 52b auxiliary contact.
This means that Trip Coil supervision is provided when the CB is either closed or open, however Trip Path
supervision is only provided when the CB is closed. No supervision of the trip path is provided whilst the CB is open
(pre-closing supervision). Any fault in the trip path will only be detected on CB closing, after a 400 ms delay.
4.1.1 RESISTOR VALUES

The supervision current is a lot less than the current required by the trip coil to trip a CB. The opto-input limits this
supervision current to less than 10 mA. If the opto-input were to be short-circuited however, it could be possible for
the supervision current to reach a level that could trip the CB. For this reason, a resistor R1 is often used to limit the
current in the event of a short-circuited opto-input. This limits the current to less than 60mA. The table below
shows the appropriate resistor value and voltage setting for this scheme.
Trip Circuit Voltage Opto Voltage Setting with R1 Fitted Resistor R1 (ohms)
48/54 24/27 1.2k
306 P841B-TM-EN-1.1
Trip Circuit Voltage Opto Voltage Setting with R1 Fitted Resistor R1 (ohms)
110/125 48/54 2.7k
220/250 110/125 5.2k
Warning:
This Scheme is not compatible with Trip Circuit voltages of less than 48 V.
4.1.2 PSL FOR TCS SCHEME 1
0 0
Opto Input dropoff Straight *Output Relay
400 0
50
& pickup Latching LED
0
User Alarm
*NC stands for Normally Closed. V01217
Figure 148: PSL for TCS Scheme 1
The opto-input can be used to drive a Normally Closed Output Relay, which in turn can be used to drive alarm
equipment. The signal can also be inverted to drive a latching programmable LED and a user alarm DDB signal.
The DDO timer operates as soon as the opto-input is energised, but will take 400 ms to drop off/reset in the event
of a trip circuit failure. The 400 ms delay prevents a false alarm due to voltage dips caused by faults in other
circuits or during normal tripping operation when the opto-input is shorted by a self-reset trip contact. When the
timer is operated the NC (normally closed) output relay opens and the LED and user alarms are reset.
The 50 ms delay on pick-up timer prevents false LED and user alarm indications during the power up time,
following a voltage supply interruption.

This scheme provides supervision of the trip coil with the breaker open or closed but does not provide pre-closing
supervision of the trip path. However, using two opto-inputs allows the IED to correctly monitor the circuit breaker
status since they are connected in series with the CB auxiliary contacts. This is achieved by assigning one opto-
input to the 52a contact and another opto-input to the 52b contact. Provided the CB Status setting in the CB
CONTROL column is set to Both 52A and 52B, the IED will correctly monitor the status of the breaker. This
scheme is also fully compatible with latched contacts as the supervision current will be maintained through the
52b contact when the trip contact is closed.
+ve
Trip Output Relay Trip coil

Trip path 52A
52B
R1 Opto-input 1
Circuit Breaker
-ve
R2 Opto-input 2
V01215
P841B-TM-EN-1.1 307
When the breaker is closed, supervision current passes through opto input 1 and the trip coil. When the breaker is
open current flows through opto input 2 and the trip coil. No supervision of the trip path is provided whilst the
breaker is open. Any fault in the trip path will only be detected on CB closing, after a 400 ms delay.

Optional resistors R1 and R2 can be added to prevent tripping of the CB if either opto-input is shorted. The table
below shows the appropriate resistor value and voltage setting for this scheme.
Trip Circuit Voltage Opto Voltage Setting with R1 Fitted Resistor R1 and R2 (ohms)
48/54 24/27 1.2k
110/125 48/54 2.7k
220/250 110/125 5.2k
Warning:
Opto Input 1 CB Aux 3ph(52 -A)
0 0
1 dropoff straight *Output Relay
400 0
Opto Input 2 CB Aux 3ph(52 -B)
50
0
User Alarm
In TCS scheme 2, both opto-inputs must be low before a trip circuit fail alarm is given.

TCS Scheme 3 is designed to provide supervision of the trip coil with the breaker open or closed. It provides pre-
closing supervision of the trip path. Since only one opto-input is used, this scheme is not compatible with latched
trip contacts. If you require CB status monitoring, further opto-inputs must be used.
+ve
R3
Output Relay Trip coil
Trip path 52A
R2
52B
Opto-input R1 Circuit Breaker

-ve
V01216
When the CB is closed, supervision current passes through the opto-input, resistor R2 and the trip coil. When the
CB is open, current flows through the opto-input, resistors R1 and R2 (in parallel), resistor R3 and the trip coil. The
308 P841B-TM-EN-1.1
supervision current is maintained through the trip path with the breaker in either state, therefore providing pre-
closing supervision.

Resistors R1 and R2 are used to prevent false tripping, if the opto-input is accidentally shorted. However, unlike the
other two schemes. This scheme is dependent upon the position and value of these resistors. Removing them
would result in incomplete trip circuit monitoring. The table below shows the resistor values and voltage settings
required for satisfactory operation.
Opto Voltage Setting with R1
Trip Circuit Voltage Resistor R1 & R2 (ohms) Resistor R3 (ohms)
Fitted
48/54 24/27 1.2k 600
110/250 48/54 2.7k 1.2k
220/250 110/125 5.0k 2.5k
Warning:
0 0
Opto Input dropoff Straight *Output Relay
400 0
50
0
User Alarm
P841B-TM-EN-1.1 309
310 P841B-TM-EN-1.1
CHAPTER 14
DIGITAL I/O AND PSL CONFIGURATION

Chapter 14 - Digital I/O and PSL Configuration P841B
312 P841B-TM-EN-1.1
P841B Chapter 14 - Digital I/O and PSL Configuration
1 CHAPTER OVERVIEW
This chapter introduces the PSL (Programmable Scheme Logic) Editor, and describes the configuration of the digital
inputs and outputs. It provides an outline of scheme logic concepts and the PSL Editor. This is followed by details
about allocation of the digital inputs and outputs, which require the use of the PSL Editor. A separate "Settings
Application Software" document is available that gives a comprehensive description of the PSL, but enough
information is provided in this chapter to allow you to allocate the principal digital inputs and outputs.
Configuring Digital Inputs and Outputs 314
Scheme Logic 315
Configuring the Opto-Inputs 317
Assigning the Output Relays 318
Fixed Function LEDs 319
Configuring Programmable LEDs 320
Function Keys 322
Control Inputs 323
P841B-TM-EN-1.1 313
2 CONFIGURING DIGITAL INPUTS AND OUTPUTS

Configuration of the digital inputs and outputs in this product is very flexible. You can use a combination of
settings and programmable logic to customise them to your application. You can access some of the settings
using the keypad on the front panel, but you will need a computer running the settings application software to fully
interrogate and configure the properties of the digital inputs and outputs.
The settings application software includes an application called the PSL Editor (Programmable Scheme Logic
Editor). The PSL Editor lets you allocate inputs and outputs according to your specific application. It also allows you
to apply attributes to some of the signals such as a drop-off delay for an output contact.
In this product, digital inputs and outputs that are configurable are:
● Optically isolated digital inputs (opto-inputs). These can be used to monitor the status of associated plant.
● Output relays. These can be used for purposes such as initiating the tripping of circuit breakers, providing
alarm signals, etc..
● Programmable LEDs. The number and colour of the programmable LEDs varies according to the particular
product being applied.
● Function keys and associated LED indications. These are not provided on all products, but where they are,
each function key has an associated tri-colour LED.
● IEC 61850 GOOSE inputs and outputs. These are only provided on products that have been specified for
connection to an IEC61850 system, and the details of the GOOSE are presented in the documentation on
IEC61850.
314 P841B-TM-EN-1.1
3 SCHEME LOGIC
The product is supplied with pre-loaded Fixed Scheme Logic (FSL) and Programmable Scheme Logic (PSL).
The Scheme Logic is a functional module within the IED, through which all mapping of inputs to outputs is handled.
The scheme logic can be split into two parts; the Fixed Scheme Logic (FSL) and the Programmable Scheme Logic
(PSL). It is built around a concept called the digital data bus (DDB). The DDB encompasses all of the digital signals
(DDBs) which are used in the FSL and PSL. The DDBs included digital inputs, outputs, and internal signals.
The FSL is logic that has been hard-coded in the product. It is fundamental to correct interaction between various
protection and/or control elements. It is fixed and cannot be changed.
The PSL gives you a facility to develop custom schemes to suit your application if the factory-programmed default
PSL schemes do not meet your needs. Default PSL schemes are programmed before the product leaves the
factory. These default PSL schemes have been designed to suit typical applications and if these schemes suit your
requirements, you do not need to take any action. However, if you want to change the input-output mappings, or
to implement custom scheme logic, you can change these, or create new PSL schemes using the PSL editor.
The PSL consists of components such as logic gates and timers, which combine and condition DDB signals.
The logic gates can be programmed to perform a range of different logic functions. The number of inputs to a logic
gate are not limited. The timers can be used either to create a programmable delay or to condition the logic
outputs. Output contacts and programmable LEDs have dedicated conditioners.
The PSL logic is event driven. Only the part of the PSL logic that is affected by the particular input change that has
occurred is processed. This minimises the amount of processing time used by the PSL ensuring industry leading
performance.
The following diagram shows how the scheme logic interacts with the rest of the IED.
Energising quantities Protection functions Fixed LEDs

SL outputs
SL inputs
Opto-inputs Programmable LEDs

PSL and FSL
Function keys Output relays

Goose outputs
Control inputs
Goose inputs
Control input Ethernet

module processing module
V02011
Figure 153: Scheme Logic Interfaces
P841B-TM-EN-1.1 315
3.1 PSL EDITOR

The Programmable Scheme Logic (PSL) is a module of programmable logic gates and timers in the IED, which can
be used to create customised logic to qualify how the product manages its response to system conditions. The
IED's digital inputs are combined with internally generated digital signals using logic gates, timers, and
conditioners. The resultant signals are then mapped to digital outputs signals including output relays and LEDs.
The PSL Editor is a tool in the settings application software that allows you to create and edit scheme logic
diagrams. You can use the default scheme logic which has been designed to suit most applications, but if it does
not suit your application you can change it. If you create a different scheme logic with the software, you need to
upload it to the device to apply it.
3.2 PSL SCHEMES

Your product is shipped with default scheme files. These can be used without modification for most applications, or
you can choose to use them as a starting point to design your own scheme. You can also create a new scheme
from scratch. To create a new scheme, or to modify an existing scheme, you will need to launch the settings
application software. You then need to open an existing PSL file, or create a new one, for the particular product
that you are using, and then open a PSL file. If you want to create a new PSL file, you should select File then New
then Blank scheme... This action opens a default file appropriate for the device in question, but deletes the
diagram components from the default file to leave an empty diagram with configuration information loaded. To
open an existing file, or a default file, simply double-click on it.
3.3 PSL SCHEME VERSION CONTROL

To help you keep track of the PSL loaded into products, a version control feature is included. The user interface
contains a PSL DATA column, which can be used to track PSL modifications. A total of 12 cells are contained in the
PSL DATA column; 3 for each setting group.
Grp(n) PSL Ref: When downloading a PSL scheme to an IED, you will be prompted to enter the relevant group
number and a reference identifier. The first 32 characters of the reference identifier are displayed in this cell. The
horizontal cursor keys can scroll through the 32 characters as the LCD display only displays 16 characters.
Example:
Grp(n) PSL Ref
Date/time: This cell displays the date and time when the PSL scheme was downloaded to the IED.
Example:
18 Nov 2002
08:59:32.047
Grp(n) PSL ID: This cell displays a unique ID number for the downloaded PSL scheme.
Example:
Grp(n) PSL ID
ID - 2062813232
316 P841B-TM-EN-1.1
4 CONFIGURING THE OPTO-INPUTS

The number of optically isolated status inputs (opto-inputs) depends on the specific model supplied. The use of the
inputs will depend on the application, and their allocation is defined in the programmable scheme logic (PSL). In
addition to the PSL assignment, you also need to specify the expected input voltage. Generally, all opto-inputs will
share the same input voltage range, but if different voltage ranges are being used, this device can accommodate
them.
In the OPTO CONFIG column there is a global nominal voltage setting. If all opto-inputs are going to be energised
from the same voltage range, you select the appropriate value in the setting. If you select Custom in the setting,
then the cells Opto Input 1, Opto Input 2, etc. become visible. You use these cells to set the voltage ranges for
each individual opto-input.
Within the OPTO CONFIG column there are also settings to control the filtering applied to the inputs, as well as the
pick-up/drop-off characteristic.
The filter control setting provides a bit string with a bit associated with all opto-inputs. Setting the bit to ‘1’ means
that a half-cycle filter is applied to the inputs. This helps to prevent incorrect operation in the event of power
system frequency interference on the wiring. Setting the field to ‘0’ removes the filter and provides for faster
operation.
The Characteristic setting is a single setting that applies to all the opto-inputs. It is used to set the pick-up/drop-
off ratios of the input signals. As standard it is set to 80% pick-up and 60% drop-off, but you can change it to other
available thresholds if that suits your operational requirements.
P841B-TM-EN-1.1 317
5 ASSIGNING THE OUTPUT RELAYS

Relay contact action is controlled using the PSL. DDB signals are mapped in the PSL and drive the output relays.
The driving of an output relay is controlled by means of a relay output conditioner. Several choices are available for
how output relay contacts are conditioned. For example, you can choose whether operation of an output relay
contact is latched, has delay on pick-up, or has a delay on drop-off. You make this choice in the Contact
Properties window associated with the output relay conditioner.
To map an output relay in the PSL you should use the Contact Conditioner button in the toolbar to import it. You
then condition it according to your needs. The output of the conditioner respects the attributes you have assigned.
The toolbar button for a Contact Conditioner looks like this:
The PSL contribution that it delivers looks like this:
Note:
Contact Conditioners are only available if they have not all been used. In some default PSL schemes, all Contact Conditioners
might have been used. If that is the case, and you want to use them for something else, you will need to re-assign them.
On the toolbar there is another button associated with the relay outputs. The button looks like this:
This is the "Contact Signal" button. It allows you to put replica instances of a conditioned output relay into the PSL,
preventing you having to make cross-page connections which might detract from the clarity of the scheme.
318 P841B-TM-EN-1.1
6 FIXED FUNCTION LEDS

Four fixed-function LEDs on the left-hand side of the front panel indicate the following conditions.
● Trip (Red) switches ON when the IED issues a trip signal. It is reset when the associated fault record is
cleared from the front display. Also the trip LED can be configured as self-resetting.
● Alarm (Yellow) flashes when the IED registers an alarm. This may be triggered by a fault, event or
maintenance record. The LED flashes until the alarms have been accepted (read), then changes to
constantly ON. When the alarms are cleared, the LED switches OFF.
● Out of service (Yellow) is ON when the IED's functions are unavailable.
● Healthy (Green) is ON when the IED is in correct working order, and should be ON at all times. It goes OFF if
the unit’s self-tests show there is an error in the hardware or software. The state of the healthy LED is
reflected by the watchdog contacts at the back of the unit.
6.1 TRIP LED LOGIC

When a trip occurs, the trip LED is illuminated. It is possible to reset this with a number of ways:
● Directly with a reset command (by pressing the Clear Key)
● With a reset logic input
● With self-resetting logic
You enable the automatic self-resetting with the Sys Fn Links cell in the SYSTEM DATA column. A '0' disables self
resetting and a '1' enables self resetting.
The reset occurs when the circuit is reclosed and the Any Pole Dead signal has been reset for three seconds
providing the Any Start signal is inactive. The reset is prevented if the Any Start signal is active after the breaker
closes.
The Trip LED logic is as follows:
Any Trip S
Q Trip LED Trigger
Reset R
1
Reset Relays/LED
Sys Fn Links
Trip LED S/Reset
3s
&
Any Pole Dead
Any Start
V01211
Figure 154: Trip LED logic
P841B-TM-EN-1.1 319
7 CONFIGURING PROGRAMMABLE LEDS

There are three types of programmable LED signals which vary according to the model being used. These are:
● Single-colour programmable LED. These are red when illuminated.
● Tri-colour programmable LED. These can be illuminated red, green, or amber.
● Tri-colour programmable LED associated with a Function Key. These can be illuminated red, green, or
amber.
DDB signals are mapped in the PSL and used to illuminate the LEDs. For single-coloured programmable LEDs there
is one DDB signal per LED. For tri-coloured LEDs there are two DDB signals associated with the LED. Asserting LED
# Grn will illuminate the LED green. Asserting LED # Red will illuminate the LED red. Asserting both DDB signals will
illuminate the LED amber.
The illumination of an LED is controlled by means of a conditioner. Using the conditioner, you can decide whether
the LEDs reflect the real-time state of the DDB signals, or whether illumination is latched pending user intervention.
To map an LED in the PSL you should use the LED Conditioner button in the toolbar to import it. You then condition
it according to your needs. The output(s) of the conditioner respect the attribute you have assigned.
The toolbar button for a tri-colour LED looks like this:
The PSL contribution that it delivers looks like this:
The toolbar button for a single-colour LED looks like this:
The PSL contribution that it delivers looks like this.
Note:
LED Conditioners are only available if they have not all been used up, and in some default PSL schemes they might be. If that
is the case and you want to use them for something else, you will need to re-assign them.
On the toolbar there is another button associated with the LEDs. For a tri-coloured LED the button looks like this:
For a single-colour LED it looks like this:
It is the "LED Signal" button. It allows you to put replica instances of a conditioned LED into the PSL, preventing you
having to make cross-page connections which might detract from the clarity of the scheme.
320 P841B-TM-EN-1.1
Note:
All LED DDB signals are always shown in the PSL Editor. However, the actual number of LEDs depends on the device
hardware. For example, if a small 20TE device has only 4 programmable LEDs, LEDs 5-8 will not take effect even if they are
mapped in the PSL.
P841B-TM-EN-1.1 321
8 FUNCTION KEYS
For most models, a number of programmable function keys are available. This allows you to assign function keys
to control functionality via the programmable scheme logic (PSL). Each function key is associated with a
programmable tri-colour LED, which you can program to give the desired indication on activation of the function
key.
These function keys can be used to trigger any function that they are connected to as part of the PSL. The function
key commands are found in the FUNCTION KEYS column.
Each function key is associated with a DDB signal as shown in the DDB table. You can map these DDB signals to
any function available in the PSL.
The Fn Key Status cell displays the status (energised or de-energised) of the function keys by means of a binary
string, where each bit represents a function key starting with bit 0 for function key 1.
Each function key has three settings associated with it, as shown:
● Fn Key (n), which enables or disables the function key
● Fn Key (n) Mode, which allows you to configure the key as toggled or normal
● Fn Key (n) label, which allows you to define the function key text that is displayed
The Fn Key (n) cell is used to enable (unlock) or disable (unlock) the function key signals in PSL. The Lock setting has
been provided to prevent further activation on subsequent key presses. This allows function keys that are set to
Toggled mode and their DDB signal active ‘high’, to be locked in their active state therefore preventing any
further key presses from deactivating the associated function. Locking a function key that is set to the “Normal”
mode causes the associated DDB signals to be permanently off. This safety feature prevents any inadvertent
function key presses from activating or deactivating critical functions.
When the Fn Key (n) Mode cell is set to Toggle, the function key DDB signal output will remain in the set state
until a reset command is given. In the Normal mode, the function key DDB signal will remain energised for as long
as the function key is pressed and will then reset automatically. In this mode, a minimum pulse duration can be
programmed by adding a minimum pulse timer to the function key DDB output signal.
The Fn Key Label cell makes it possible to change the text associated with each individual function key. This text
will be displayed when a function key is accessed in the function key menu, or it can be displayed in the PSL.
The status of all function keys are recorded in non-volatile memory. In case of auxiliary supply interruption their
status will be maintained.
Note:
All function key DDB signals are always shown in the PSL Editor. However, the actual number of function keys depends on the
device hardware. For example, if a small 20TE device has no function keys, the function key DDBs mapped in the PSL will not
take effect.
322 P841B-TM-EN-1.1
9 CONTROL INPUTS
The control inputs are software switches, which can be set or reset locally or remotely. These inputs can be used to
trigger any PSL function to which they are connected. There are three setting columns associated with the control
inputs: CONTROL INPUTS, CTRL I/P CONFIG and CTRL I/P LABELS. These are listed in the Settings and Records
appendix at the end of this manual.
P841B-TM-EN-1.1 323
324 P841B-TM-EN-1.1
CHAPTER 15
ELECTRICAL TELEPROTECTION
Chapter 15 - Electrical Teleprotection P841B
326 P841B-TM-EN-1.1
P841B Chapter 15 - Electrical Teleprotection
1 CHAPTER OVERVIEW
Introduction 328
Teleprotection Scheme Principles 329
Implementation 330
Configuration 331
Connecting to Electrical InterMiCOM 333
Application Notes 334
P841B-TM-EN-1.1 327
2 INTRODUCTION
Electrical Teleprotection is an optional feature that uses communications links to create protection schemes. It can
be used to replace hard wiring between dedicated relay output contacts and digital input circuits. Two products
equipped with electrical teleprotection can connect and exchange commands using a communication link. It is
typically used to implement teleprotection schemes.
Using full duplex communications, eight binary command signals can be sent in each direction between
connected products. The communication connection complies with the EIA(RS)232 standard. Ports may be
connected directly, or using modems. Alternatively EIA(RS)232 converters can be used for connecting to other
media such as optical fibres.
Communications statistics and diagnostics enable you to monitor the integrity of the communications link, and a
loopback feature is available to help with testing.
328 P841B-TM-EN-1.1
3 TELEPROTECTION SCHEME PRINCIPLES

Teleprotection schemes use signalling to convey a trip command to remote circuit breakers to isolate circuits.
Three types of teleprotection commands are commonly encountered:
● Direct Tripping
● Permissive Tripping
● Blocking Scheme
3.1 DIRECT TRIPPING

In direct tripping applications (often described by the generic term: “intertripping”), teleprotection signals are sent
directly to a master trip device. Receipt of a command causes circuit breaker operation without any further
qualification. Communication must be reliable and secure because any signal detected at the receiving end
causes a trip of the circuit at that end. The communications system must be designed so that interference on the
communication circuit does not cause spurious trips. If a spurious trip occurs, the primary system might be
unnecessarily isolated.
3.2 PERMISSIVE TRIPPING

Permissive trip commands are monitored by a protection device. The circuit breaker is tripped when receipt of the
command coincides with a ‘start’ condition being detected by the protection at the receiving. Requirements for the
communications channel are less onerous than for direct tripping schemes, since receipt of an incorrect signal
must coincide with a ‘start’ of the receiving end protection for a trip operation to take place. Permissive tripping is
used to speed up tripping for faults occurring within a protected zone.
P841B-TM-EN-1.1 329
4 IMPLEMENTATION
Electrical InterMiCOM is configured using a combination of settings in the INTERMICOM COMMS column, settings in
the INTERMICOM CONF column, and the programmable scheme logic (PSL).
The eight command signals are mapped to DDB signals within the product using the PSL.
Signals being sent to a remote terminal are referenced in the PSL as IM Output 1 - IM Output 8. Signals received
from the remote terminal are referenced as IM Input 1 - IM Input 8.
Note:
As well as the optional Modem InterMiCOM, some products are available with a feature called InterMiCOM64 (IM64). The
functionality and assignment of commands in InterMiCOM and InterMiCOM64 are similar, but they act independently and are
configured independently.
330 P841B-TM-EN-1.1
5 CONFIGURATION
Electrical Teleprotection is compliant with IEC 60834-1:1999. For your application, you can customise individual
command signals to the differing requirements of security, speed, and dependability as defined in this standard.
You customise the command signals using the IM# Cmd Type cell in the INTERMICOM CONF column.
Any command signal can be configured for:
● Direct intertripping by selecting ‘Direct’. (this is the most secure signalling but incurs a time delay to deliver
the security).
● Blocking applications by selecting ‘Blocking’. (this is the fastest signalling)
● Permissive intertripping applications by selecting ‘Permissive. (this is dependable signalling that balances
speed and security)
You can also select to ‘Disable’ the command.
Note:
When used in the context of a setting, ‘#’ specifies which command signal (1-8) bit is being configured.
To ensure that command signals are processed only by their intended recipient, the command signals are
packaged into a message (sometimes referred to as a telegram) which contains an address field. A sending device
sets a pattern in this field. A receiving device must be set to match this pattern in the address field before the
commands will be acted upon. 10 patterns have been carefully chosen for maximum security. You need to choose
which ones to use, and set them using the Source Address and Receive Address cells in the INTERMICOM COMMS
column.
The value set in the Source Address of the transmitting device should match that set in the Receive Address of the
receiving device. For example set Source Address to 1 at a local terminal and set Receive Address to 1 at the
remote terminal.
The Source Address and Receive Address settings in the device should be set to different values to avoid false
operation under inadvertent loopback conditions.
Where more than one pair of devices is likely to share a communication link, you should set each pair to use a
different pair of address values.
Electrical InterMiCOM has been designed to be resilient to noise on communications links, but during severe noise
conditions, the communication may fail. If this is the case, an alarm is raised and you can choose how the input
signals are managed using the IM# FallBackMode cell in the INTERMICOM CONF column:
• If you choose Latched, the last valid command to be received can be maintained until a new valid message is
received.
• If you choose Default, the signal will revert to a default value after the period defined in the IM#
FrameSyncTim setting has expired. You choose the default value using the IM# DefaultValue setting.
Subsequent receipt of a full valid message will reset the alarm, and the new command signals will be used.
As well as the settings described above, you will need to assign input and output signals in the Programmable
Scheme Logic (PSL). Use the ‘Integral Tripping’ buttons to create the logic you want to apply. A typical example is
shown below.
P841B-TM-EN-1.1 331
E002521
Figure 155: Example assignment of InterMiCOM signals within the PSL
Note:
When an Electrical InterMiCOM signal is sent from a local terminal, only the remote terminal will react to the command. The
local terminal will only react to commands initiated at the remote terminal.
332 P841B-TM-EN-1.1
6 CONNECTING TO ELECTRICAL INTERMICOM

Electrical InterMiCOM uses EIA(RS)232 communication presented on a 9-pin ‘D’ type connector. The connector is
labelled SK5 and is located at the bottom of the 2nd Rear communication board. The port is configured as
standard DTE (Data Terminating Equipment).
6.1 SHORT DISTANCE

EIA(RS)232 is suitable for short distance connections only - less than 15m. Where this limitation is not a problem,
direct connection between devices is possible. For this case, inter-device connections should be made as shown
below the figure below.
IED IED
DCD 1 1 DCD
RxD 2 2 RxD
TxD 3 3 TxD
DTR 4 4 DTR
GND 5 5 GND
6 6
RTS 7 7 RTS
8 8
9 9
E02522
Figure 156: Direct connection
For direct connection, the maximum baud rate can generally be used.
6.2 LONG DISTANCE

EIA(RS)232 is suitable for short distance connections only - less than 15m. Where this limitation is a problem, direct
connection between devices is not possible. For this case, inter-device connections should be made as shown
below the figure below.
IED Modem Modem IED

DCD 1 DCD DCD 1 DCD
RxD 2 RxD RxD 2 RxD
Communication
TxD 3 TxD TxD 3 TxD
Network
DTR 4 4 DTR
GND 5 GND GND 5 GND
6 6
RTS 7 7 RTS
8 8
9 9
E02523
Figure 157: Indirect connection using modems
This type of connection should be used when connecting to devices that have the ability to control the DCD line.
The baud rate should be chosen to be suitable for the communications network. If the Modem does not support
the DCD function, the DCD terminal on the IED should be connected to the DTR terminal.
P841B-TM-EN-1.1 333
7 APPLICATION NOTES
Electrical InterMiCOM settings are contained within two columns; INTERMICOM COMMS and INTERMICOM CONF.
The INTERMICOM COMMS column contains all the settings needed to configure the communications, as well as the
channel statistics and diagnostic facilities. The INTERMICOM CONF column sets the mode of each command signal
and defines how they operate in case of signalling failure.
Short metallic direct connections and connections using fire-optic converters will generally be set to have the
highest signalling speed of 19200b/s. Due to this high signalling rate, the difference in operating time between the
direct, permissive, and blocking type signals is small. This means you can select the most secure signalling
command type (‘Direct’ intertrip) for all commands. You do this with the IM# Cmd Type settings. For these
applications you should set the IM# Fallback Mode to Default. You should also set a minimal intentional delay
by setting IM# FrameSyncTim to 10 msecs. This ensures that whenever two consecutive corrupt messages are
received, the command will immediately revert to the default value until a new valid message is received.
For applications that use Modem and/or multiplexed connections, the trade-off between speed, security, and
dependability is more critical. Choosing the fastest baud rate (data rate) to achieve maximum speed may appear
attractive, but this is likely to increase the cost of the telecommunications equipment. Also, telecommunication
services operating at high data rates are more prone to interference and suffer from longer re-synchronisation
times following periods of disruption. Taking into account these factors we recommend a maximum baud rate
setting of 9600 bps. As baud rates decrease, communications become more robust with fewer interruptions, but
overall signalling times increase.
At slower baud rates, the choice of signalling mode becomes significant. You should also consider what happens
during periods of noise when message structure and content can be lost.
● In ‘Blocking’ mode, the likelihood of receiving a command in a noisy environment is high. In this case, we
recommend you set IM# Fallback Mode to Default, with a reasonably long IM# FrameSyncTim setting.
Set IM# DefaultValue to ‘1’. This provides a substitute for a received blocking signal, applying a failsafe for
blocking schemes.
● In ‘Direct’ mode, the likelihood of receiving commands in a noisy environment is small. In this case, we
recommend you set IM# Fallback Mode to Default with a short IM# FrameSyncTim setting. Set IM#
DefaultValue to ‘0’. This means that if a corrupt message is received, InterMiCOM will use the default value.
This provides a substitute for the intertrip signal not being received, applying a failsafe for direct
intertripping schemes.
● In ‘Permissive’ mode, the likelihood of receiving a valid command under noisy communications conditions is
somwhere between that of the ‘Blocking’ mode and the ‘Direct’ intertrip mode. In this case, we
recommended you set IM# Fallback Mode to Latched.
The table below presents recommended IM# FrameSyncTim settings for the different signalling modes and baud
rates:
Minimum Recommended "IM# FrameSyncTim" Setting
Minimum Setting Maximum Setting
Baud Rate Direct Intertrip Mode Blocking Mode
(ms) (ms)
600 100 250 100 1500
1200 50 130 50 1500
2400 30 70 30 1500
4800 20 40 20 1500
9600 10 20 10 1500
19200 10 10 10 1500
334 P841B-TM-EN-1.1
Note:
As we have recommended Latched operation, the table does not contain recommendations for ‘Permissive’ mode. However, if
you do select ‘Default’ mode, you should set IM# FrameSyncTim greater than those listed above. If you set IM#
FrameSyncTim lower than the minimum setting listed above, the device could interpret a valid change in a message as a
corrupted message.
We recommend a setting of 25% for the communications failure alarm.
P841B-TM-EN-1.1 335
336 P841B-TM-EN-1.1
CHAPTER 16
COMMUNICATIONS
Chapter 16 - Communications P841B
338 P841B-TM-EN-1.1
P841B Chapter 16 - Communications
1 CHAPTER OVERVIEW
This product supports Substation Automation System (SAS), and Supervisory Control and Data Acquisition (SCADA)
communication. The support embraces the evolution of communications technologies that have taken place since
microprocessor technologies were introduced into protection, control, and monitoring devices which are now
ubiquitously known as Intelligent Electronic Devices for the substation (IEDs).
As standard, all products support rugged serial communications for SCADA and SAS applications. By option, any
product can support Ethernet communications for more advanced SCADA and SAS applications.

Communication Interfaces 340
Serial Communication 341
Standard Ethernet Communication 344
Redundant Ethernet Communication 345
Simple Network Management Protocol (SNMP) 367
Data Protocols 374
Read Only Mode 399
Time Synchronisation 401
P841B-TM-EN-1.1 339
2 COMMUNICATION INTERFACES
The products have a number of standard and optional communication interfaces. The standard and optional
hardware and protocols are summarised below:
Port Availability Physical layer Use Data Protocols
Front Standard RS232 Local settings Courier
Rear Port 1 RS232 / RS485 / K- SCADA Courier, MODBUS, IEC60870-5-103, DNP3.0
Standard
(RP1 copper) Bus Remote settings (order option)
Rear Port 1 SCADA Courier, MODBUS, IEC60870-5-103, DNP3.0
Optional Fibre
(RP1 fibre) Remote settings (order option)
Rear Port 2 RS232 / RS485 / K- SCADA SK4: Courier only
Optional
(RP2) Bus Remote settings SK5: InterMicom only
IEC 61850 or DNP3 IEC 61850, Courier (tunnelled) or DNP3.0
Ethernet Optional Ethernet
Remote settings (order option)
Note:
Optional communications boards are always fitted into slot A.
Note:
It is only possible to fit one optional communications board, therefore RP2 and Ethernet communications are mutually
exclusive.
340 P841B-TM-EN-1.1
3 SERIAL COMMUNICATION
The physical layer standards that are used for serial communications for SCADA purposes are:
● EIA(RS)485 (often abbreviated to RS485)
● K-Bus (a proprietary customization of RS485)
EIA(RS)232 is used for local communication with the IED (for transferring settings and downloading firmware
updates).
RS485 is similar to RS232 but for longer distances and it allows daisy-chaining and multi-dropping of IEDs.
K-Bus is a proprietary protocol quite similar to RS485, but it cannot be mixed on the same link as RS485. Unlike
RS485, K-Bus signals applied across two terminals are not polarised.
It is important to note that these are not data protocols. They only describe the physical characteristics required
for two devices to communicate with each other.
For a description of the K-Bus standard see K-Bus (on page342) and General Electric's K-Bus interface guide
reference R6509.
A full description of the RS485 is available in the published standard.
3.1 EIA(RS)232 BUS

The EIA(RS)232 interface uses the IEC 60870-5 FT1.2 frame format.
The device supports an IEC 60870-5 FT1.2 connection on the front-port. This is intended for temporary local
connection and is not suitable for permanent connection. This interface uses a fixed baud rate of 19200 bps, 11-bit
frame (8 data bits, 1 start bit, 1 stop bit, even parity bit), and a fixed device address of '1'.
EIA(RS)232 interfaces are polarised.
3.2 EIA(RS)485 BUS

The RS485 two-wire connection provides a half-duplex, fully isolated serial connection to the IED. The connection is
polarized but there is no agreed definition of which terminal is which. If the master is unable to communicate with
the product, and the communication parameters match, then it is possible that the two-wire connection is
reversed.
The RS485 bus must be terminated at each end with 120 Ω 0.5 W terminating resistors between the signal wires.
The RS485 standard requires that each device be directly connected to the actual bus. Stubs and tees are
forbidden. Loop bus and Star topologies are not part of the RS485 standard and are also forbidden.
Two-core screened twisted pair cable should be used. The final cable specification is dependent on the application,
although a multi-strand 0.5 mm2 per core is normally adequate. The total cable length must not exceed 1000 m. It
is important to avoid circulating currents, which can cause noise and interference, especially when the cable runs
between buildings. For this reason, the screen should be continuous and connected to ground at one end only,
normally at the master connection point.
The RS485 signal is a differential signal and there is no signal ground connection. If a signal ground connection is
present in the bus cable then it must be ignored. At no stage should this be connected to the cable's screen or to
the product’s chassis. This is for both safety and noise reasons.
It may be necessary to bias the signal wires to prevent jabber. Jabber occurs when the signal level has an
indeterminate state because the bus is not being actively driven. This can occur when all the slaves are in receive
mode and the master is slow to turn from receive mode to transmit mode. This may be because the master is
waiting in receive mode, in a high impedance state, until it has something to transmit. Jabber causes the receiving
device(s) to miss the first bits of the first character in the packet, which results in the slave rejecting the message
and consequently not responding. Symptoms of this are; poor response times (due to retries), increasing message
error counts, erratic communications, and in the worst case, complete failure to communicate.
P841B-TM-EN-1.1 341
3.2.1 EIA(RS)485 BIASING REQUIREMENTS

Biasing requires that the signal lines be weakly pulled to a defined voltage level of about 1 V. There should only be
one bias point on the bus, which is best situated at the master connection point. The DC source used for the bias
must be clean to prevent noise being injected.
Note:
Some devices may be able to provide the bus bias, in which case external components would not be required.
6 – 9 V DC
180 Ω bias
Master 120 Ω
180 Ω bias
0V 120 Ω
Slave Slave Slave
V01000
Figure 158: RS485 biasing circuit
Warning:
It is extremely important that the 120 Ω termination resistors are fitted. Otherwise
the bias voltage may be excessive and may damage the devices connected to the
bus.
3.3 K-BUS
K-Bus is a robust signalling method based on RS485 voltage levels. K-Bus incorporates message framing, based on
a 64 kbps synchronous HDLC protocol with FM0 modulation to increase speed and security.
The rear interface is used to provide a permanent connection for K-Bus, which allows multi-drop connection.
A K-Bus spur consists of up to 32 IEDs connected together in a multi-drop arrangement using twisted pair wiring.
The K-Bus twisted pair connection is non-polarised.
It is not possible to use a standard EIA(RS)232 to EIA(RS)485 converter to convert IEC 60870-5 FT1.2 frames to K-
Bus. A protocol converter, namely the KITZ101, KITZ102 or KITZ201, must be used for this purpose. Please consult
General Electric for information regarding the specification and supply of KITZ devices. The following figure
demonstrates a typical K-Bus connection.
342 P841B-TM-EN-1.1
C C C
IED IED IED
RS232 K-Bus
Computer RS232-USB converter KITZ protocol converter

V01001
Figure 159: Remote communication using K-Bus
Note:
An RS232-USB converter is only needed if the local computer does not provide an RS232 port.
Further information about K-Bus is available in the publication R6509: K-Bus Interface Guide, which is available on
request.
P841B-TM-EN-1.1 343
4 STANDARD ETHERNET COMMUNICATION

The type of Ethernet board depends on the chosen model. The available boards and their features are described in
the Hardware Design chapter of this manual.
The Ethernet interface is required for either IEC 61850 or DNP3 over Ethernet (protocol must be selected at time of
order). With either of these protocols, the Ethernet interface also offers communication with the settings
application software for remote configuration and record extraction.
Fibre optic connection is recommended for use in permanent connections in a substation environment, as it offers
advantages in terms of noise rejection. The fibre optic port provides 100 Mbps communication and uses type
BFOC 2.5 (ST) connectors. Fibres should be suitable for 1300 nm transmission and be multimode 50/125 µm or
62.5/125 µm.
Connection can also be made to a 10Base-T or a 100Base-TX Ethernet switch using the RJ45 port.
4.1 HOT-STANDBY ETHERNET FAILOVER

This is used for products which are fitted with a standard Ethernet board. The standard Ethernet board has one
fibre and one copper interface. If there is a fault on the fibre channel it can switch to the copper channel, or vice
versa.
When this function detects a link failure, it generates the NIC Fail Alarm. The failover timer then starts, which has a
settable timeout. During this time, the Hot Standby Failover function continues to check the status of the other
channel. If the link failure recovers before the failover timer times out, the channels are not swapped over. If there
is still a fail when the failover timer times out and the other channel status is ok, the channels are swapped over.
The Ethernet controller is then reconfigured and the link is renegotiated.
To set the function, use the IEC 61850 Configurator tool in the Settings Application Software.
344 P841B-TM-EN-1.1
5 REDUNDANT ETHERNET COMMUNICATION

Redundancy is required where a single point of failure cannot be tolerated. It is required in critical applications
such as substation automation. Redundancy acts as an insurance policy, providing an alternative route if one
route fails.
Ethernet communication redundancy is available for most General Electric products, using a Redundant Ethernet
Board (REB). The REB is a Network Interface Card (NIC), which incorporates an integrated Ethernet switch. The
board provides two Ethernet transmitter/receiver pairs.
By ordering option, a number of different protocols are available to provide the redundancy according to particular
system requirements.
In addition to the two Ethernet transmitter/receiver pairs, the REB provides link activity indication in the form of
LEDs, link fail indication in the form of watchdog contacts, and a dedicated time synchronisation input.
The dedicated time synchronisation input is designed to connect to an IRIG-B signal. Both modulated and un-
modulated IRIG-B formats are supported according to the selected option. Simple Network Time Protocol (SNTP) is
supported over the Ethernet communications.
5.1 SUPPORTED PROTOCOLS

A range of Redundant Ethernet Boards are available to support different protocols for different requirements. One
of the key requirements of substation redundant communications is "bumpless" redundancy. This means the
ability to transfer from one communication path to another without noticeable consequences. Standard protocols
of the time could not meet the demanding requirements of network availability for substation automation
solutions. Switch-over times were unacceptably long. For this reason, companies developed proprietary protocols.
More recently, however, standard protocols, which support bumpless redundancy (namely PRP and HSR) have
been developed and ratified.
As well as supporting standard non-bumpless protocols such as RSTP, the REB was originally designed to support
bumpless redundancy, using proprietary protocols (SHP, DHP) before the standard protocols became available.
Since then, variants have been produced for the newer standard protocols.
REB variants for each of the following protocols are available:
● PRP (Parallel Redundancy Protocol)
● HSR (High-availability Seamless Redundancy)
● RSTP (Rapid Spanning Tree Protocol)
● SHP (Self-Healing Protocol)
● DHP (Dual Homing Protocol)
PRP and HSR are open standards, so their implementation is compatible with any standard PRP or HSR device
respectively. PRP provides "bumpless" redundancy. RSTP is also an open standard, so its implementation is
compatible with any standard RSTP devices. RSTP provides redundancy, however, it is not "bumpless".
SHP and DHP are proprietary protocols intended for use with specific General Electric products:
● SHP is compatible with the C264-SWR212 as well as H35x multimode switches.
● DHP is compatible with the C264-SWD212 as well as H36x multimode switches.
Both SHP and DHP provide "bumpless" redundancy.
Note:
The protocol you require must be selected at the time of ordering.
P841B-TM-EN-1.1 345
5.2 PARALLEL REDUNDANCY PROTOCOL

PRP (Parallel Reundancy Protocol) is defined in IEC 62439-3. PRP provides bumpless redundancy and meets the
most demanding needs of substation automation. The PRP implementation of the REB is compatible with any
standard PRP device.
PRP uses two independent Ethernet networks operating in parallel. PRP systems are designed so that there should
be no common point of failure between the two networks, so the networks have independent power sources and
are not connected together directly.
Devices designed for PRP applications have two ports attached to two separate networks and are called Doubly
Attached Nodes (DAN). A DAN has two ports, one MAC address and one IP address.
The sending node replicates each frame and transmits them over both networks. The receiving node processes the
frame that arrives first and discards the duplicate. Therefore there is no distinction between the working and
backup path. The receiving node checks that all frames arrive in sequence and that frames are correctly received
on both ports.
Devices such as printers that have a single Ethernet port can be connected to either of the networks but will not
directly benefit from the PRP principles. Such devices are called Singly Attached Nodes (SAN). For devices with a
single Ethernet port that need to connect to both LANs, this can be achieved by employing Ethernet Redundancy
Boxes (sometimes abbreviated to RedBox). Devices with a single Ethernet port that connect to both LANs by
means of a RedBox are known as Virtual DAN (VDAN).
The figure below summarises DAN, SAN, VDAN, LAN, and RedBox connectivity.
DAN DAN
SAN DAN
LAN B
LAN A
REDUNDANCY
BOX
VDAN
VDAN SAN SAN
VDAN
E01028
Figure 160: IED attached to separate LANs
In a DAN, both ports share the same MAC address so it does not affect the way devices talk to each other in an
Ethernet network (Address Resolution Protocol at layer 2). Every data frame is seen by both ports.
When a DAN sends a frame of data, the frame is duplicated on both ports and therefore on both LAN segments.
This provides a redundant path for the data frame if one of the segments fails. Under normal conditions, both LAN
segments are working and each port receives identical frames.
346 P841B-TM-EN-1.1
5.3 HIGH-AVAILABILITY SEAMLESS REDUNDANCY (HSR)

HSR is standardized in IEC 62439-3 (clause 5) for use in ring topology networks. Similar to PRP, HSR provides
bumpless redundancy and meets the most demanding needs of substation automation. HSR has become the
reference standard for ring-topology networks in the substation environment. The HSR implementation of the
redundancy Ethernet board (REB) is compatible with any standard HSR device.
HSR works on the premise that each device connected in the ring is a doubly attached node running HSR (referred
to as DANH). Similar to PRP, singly attached nodes such as printers are connected via Ethernet Redundancy Boxes
(RedBox).
5.3.1 HSR MULTICAST TOPOLOGY

When a DANH is sending a multicast frame, the frame (C frame) is duplicated (A frame and B frame), and each
duplicate frame A/B is tagged with the destination MAC address and the sequence number. The frames A and B
differ only in their sequence number, which is used to identify one frame from the other. Each frame is sent to the
network via a separate port. The destination DANH receives two identical frames, removes the HSR tag of the first
frame received and passes this (frame D) on for processing. The other duplicate frame is discarded. The nodes
forward frames from one port to the other unless it was the node that injected it into the ring.
Source
DANH DANH Redbox Switch
D frame C frame D frame

A frame B frame
Singly Attached
Nodes
D frame D frame D frame
DANH DANH DANH

V01030
Figure 161: HSR multicast topology
Only about half of the network bandwidth is available in HSR for multicast or broadcast frames because both
duplicate frames A & B circulate the full ring.
5.3.2 HSR UNICAST TOPOLOGY

With unicast frames, there is just one destination and the frames are sent to that destination alone. All non-
recipient devices simply pass the frames on. They do not process them in any way. In other words, D frames are
produced only for the receiving DANH. This is illustrated below.
P841B-TM-EN-1.1 347
Source
DANH DANH Redbox Switch
C frame
A frame B frame
Singly Attached
Nodes
D frame
DANH DANH DANH
Destination V01031
Figure 162: HSR unicast topology
For unicast frames, the whole bandwidth is available as both frames A & B stop at the destination node.
5.3.3 HSR APPLICATION IN THE SUBSTATION
348 P841B-TM-EN-1.1
T1000 switch
LINK
RX
PC SCADA
TX
reset LINK
RX
TX
DS Agile gateways
Px4x H49 H49 H49 Px4x
C C
C C C C C C
Px4x Px4x Px4x Px4x Px4x Px4x
Bay 1 Bay 2 Bay 3

E01066
Figure 163: HSR application in the substation
5.4 RAPID SPANNING TREE PROTOCOL

RSTP is a standard used to quickly reconnect a network fault by finding an alternative path. It stops network loops
whilst enabling redundancy. It can be used in star or ring connections as shown in the following figure.
Switch 1 Switch 2 Switch 1 Switch 2
IED 1 IED 2 IED 1 IED 2
Star connection with redundant ports Ring connection managed by RST P

managed by RSTP blocking function . blocking function on upper switches
and IEDs interconnected directly .
V01010
Figure 164: IED attached to redundant Ethernet star or ring circuit
The RSTP implementation in this product is compatible with any devices that use RSTP.
RSTP can recover network faults quickly, but the fault recovery time depends on the number of devices on the
network and the network topology. A typical figure for the fault recovery time is 300ms. Therefore, RSTP cannot
achieve the “bumpless” redundancy that some other protocols can.
Refer to IEEE 802.1D 2004 standard for detailed information about the opration of the protocol.
P841B-TM-EN-1.1 349
5.5 SELF HEALING PROTOCOL

The Self-Healing Protocol (SHP) implemented in the REB is a proprietary protocol that responds to the constraints
of critical time applications such as the GOOSE messaging of IEC 61850.
It is designed, primarily, to be used on PACiS Substation Automation Systems that employ the C264-SWR212
and/or H35x switches.
SHP is applied to double-ring network topologies. If adjacent devices detect a break in the ring, then they re-route
communication traffic to restore communication as outlined in the figure below.
MiCOM MiCOM
H35 H35
C264 Px4x C264 Px4x

DS Agile Ethernet DS Agile Ethernet
IEC 61850 ring network IEC 61850 ring network
C C
C
C
under normal conditions self healed

L/R L/R
Px4x Px4x
C C
E01011
Figure 165: IED, bay computer and Ethernet switch with self healing ring facilities
A Self-Healing Management function (SHM) manages the ring.

Under healthy conditions, frames are sent on the main ring (primary fibre) in one direction, with short check frames
being sent every 5 μs in the opposite direction on the back-up ring (secondary fibre).
If the main ring breaks, the SHMs at either side of the break start the network self-healing. On one side of the
break, received messages are no longer sent to the main ring, but are sent to the back-up ring instead. On the
other side of the break, messages received on the back-up ring are sent to the main ring and communications are
re-established. This takes place in less than 1 ms and can be described as “bumpless”.
The principle of SHP is outlined in the figures below.
Primary Fibre
1 2 3 1 2 3 1 2 3
Switch Rx (Ep) Tx (Ep) Switch Switch
A B C D E
Tx (Es) Rx (Rs)
Hx5x IED C264 IED Hx5x
Secondary Fibre
V01013
Figure 166: Redundant Ethernet ring architecture with IED, bay computer and Ethernet switches
350 P841B-TM-EN-1.1
Primary Fibre
1 2 3 1 2 3 1 2 3
Switch Rx (Ep) Tx (Ep) Switch Switch
A B C D E
Tx (Es) Rx (Rs)
Hx5x IED C264 IED Hx5x
Secondary Fibre
V01014
Figure 167: Redundant Ethernet ring architecture with IED, bay computer and Ethernet switches after failure
5.6 DUAL HOMING PROTOCOL

The Dual Homing Protocol (DHP) implemented in the REB is a proprietary protocol. It is designed, primarily to be
used on PACiS systems that employ the C264-SWD212 and/or H36x multimode switches.
DHP addresses the constraints of critical time applications such as the GOOSE messaging of IEC 61850.
DHP is applied to double-star network topologies. If a connection between two devices is broken, the network
continues to operate correctly.
The Dual Homing Manager (DHM) handles topologies where a device is connected to two independent networks,
one being the "main" path, the other being the "backup" path. Both are active at the same time.
Internet frames from a sending device are sent by the DHM to both networks. Receiving devices apply a “duplicate
discard” principle. This means that when both networks are operational, the REB receives two copies of the same
Ethernet frame. If both links are healthy, frames are received on both, and the DHM uses the first frame received.
The second frame is discarded. If one link fails, frames received on the healthy link are used.
DHP delivers a typical recovery time of less than 1 ms. The mechanism is outlined in the figures below.
P841B-TM-EN-1.1 351
Network 1 Network 2
Optical star Optical star

Alstom Alstom
H63x H63x
Dual homing Dual homing Dual homing

SWD21x SWD21x SWD21x
IED IED IED IED IED IED IED IED
Modified frames from network 1

Modified frames from network 2
No modified frames
V01015
Figure 168: Dual homing mechanism
The H36x is a repeater with a standard 802.3 Ethernet switch, plus the DHM.
352 P841B-TM-EN-1.1
MiCOM H382
SCADA or PACiS OI
DS Agile gateways
H600 switch H600 switch
Ethernet
Up to
C C
6 links C264 *
L/R L/R C
C264 H368 Px4x **

Ethernet
Up to
4 links
C
L/R C
RS485
Bay level C Bay level Bay level

Type 1 Type 2 Type 3
TX copper link
FX optical fibre Ethernet
E01017 RS485, RS422
* For PRP this is SRP, for DHP this is SWD
** For PRP this is PRP REB, for DHP this is DHP REB
Figure 169: Application of Dual Homing Star at substation level
5.7 CONFIGURING IP ADDRESSES

An IP address is a logical address assigned to devices in a computer network that uses the Internet Protocol (IP) for
communication between nodes. IP addresses are stored as binary numbers but they are represented using
Decimal Dot Notation, where four sets of decimal numbers are separated by dots as follows:
XXX.XXX.XXX.XXX
For example:
10.86.254.85
An IP address in a network is usually associated with a subnet mask. The subnet mask defines which network the
device belongs to. A subnet mask has the same form as an IP address.
For example:
255.255.255.0
Both the IED and the REB each have their own IP address. The following diagram shows the IED as IP1 and the REB
as IP2.
Note:
IP1 and IP2 are different but use the same subnet mask.
P841B-TM-EN-1.1 353
The switch IP address must be configured through the Ethernet network.
Set by IED Configurator
IED (IP1) AAA.BBB.CCC.DDD
REB (IP2) WWW.XXX.YYY.ZZZ
Set by Hardware Dip Switch SW2 for SHP, DHP, or RSTP

Set by Switch Manager for SHP and DHP Set by PRP/HSR Configurator for PRP or HSR
Set by RSTP Configurator for RSTP
Set by PRP/HSR Configurator for PRP or HSR Fixed at 254 for SHP or DHP
Set by PRP/HSR/RSTP Configurator for PRP, HSR or RSTP
V01018
Figure 170: IED and REB IP address configuration
5.7.1 CONFIGURING THE IED IP ADDRESS

If you are using IEC 61850, set the IED IP address using the IEC 61850 Configurator software. In the IEC 61850
Configurator, set Media to Single Copper or Redundant Fibre.
If you are using DNP3 over Ethernet, set the IED IP address by editing the DNP3 file, using the DNP3 Configurator
software. In the DNP3 Configurator, set Ethernet Media to Copper, even though the redundant Ethernet network
uses fibre optic cables.
5.7.2 CONFIGURING THE REB IP ADDRESS

The board IP address must be configured before connecting the IED to the network to avoid an IP address conflict.
The way you configure the IP address depends on the redundancy protocol you have chosen.
PRP/HSR
If using PRP or HSR, you configure the REB IP address using the PRP/HSR Configurator software.
RSTP
If using RSTP, you configure the REB IP address using the PRP/HSR Configurator software.
SHP or DHP
If using SHP or DHP the first two octets are set by the Switch Manager software or an SNMP MIB browser. The third
octet is fixed at 254 (FE hex, 11111110 binary), and the fourth octet is set by the on-board dip switch.
Note:
An H35 (SHP) or H36 (DHP) network device is needed in the network to configure the REB IP address if you are using SNMP.
5.7.2.1 CONFIGURING THE LAST OCTET (SHP, DHP, RSTP)

If using SHP or DHP, the last octet is configured using board address switch SW2 on the board. Remove the IED
front cover to gain access to the board address switch.
Warning:
Configure the hardware settings before the device is installed.
1. Refer to the safety section of the IED.

2. Switch off the IED. Disconnect the power and all connections.
354 P841B-TM-EN-1.1
3. Before removing the front cover, take precautions to prevent electrostatic discharge damage according to
the ANSI/ESD-20.20 -2007 standard.
4. Wear a 1 MΩ earth strap and connect it to the earth (ground) point on the back of the IED.
E01019
5. Lift the upper and lower flaps. Remove the six screws securing the front panel and pull the front panel
outwards.
E01020
P841B-TM-EN-1.1 355
6. Press the levers either side of the connector to disconnect the ribbon cable from the front panel.
E01021
7. Remove the redundant Ethernet board. Set the last octet of IP address using the DIP switches. The available
range is 1 to 127.
1 Example address 1 + 4 + 16 + 64 = 85
2 decimal 85
4
8
16
32
64
Unused
ON
V01022 SW2 Top view
8. Once you have set the IP address, reassemble the IED, following theses instructions in the reverse order.
Warning:
Take care not to damage the pins of the ribbon cable connector on the front panel when reinserting
the ribbon cable.
5.8 PRP/HSR CONFIGURATOR

The PRP/HSR Configurator tool is intended for MiCOM Px4x IEDs with redundant Ethernet using PRP (Parallel
Redundancy Protocol), or HSR (High-availability Seamless Redundancy). This tool is used to identify IEDs, switch
356 P841B-TM-EN-1.1
between PRP and HSR or configure their parameters, configure the redundancy IP address, or configure the SNTP
IP address.
5.8.1 CONNECTING THE IED TO A PC

Connect the IED to the PC on which the Configurator tool is used. This connection is done through an Ethernet
switch or through a media converter.
RJ45
Ethernet switch
Media
Converter
TXA RXA TXB RXB
TX RX
RXA TXA RXB TXB RXA TXA RXB TXB
IED IED
(a) (b)
V01806
Figure 171: Connection using (a) an Ethernet switch and (b) a media converter
5.8.2 INSTALLING THE CONFIGURATOR

To install the configurator:
1. Double click the WinPcap installer.
2. Double click the Configurator installer.
3. Click Next and follow the on-screen instructions.
5.8.3 STARTING THE CONFIGURATOR

To start the configurator:
1. Select the Configurator from the Windows Programs menu.
2. The Login screen appears. For user mode login, enter the Login name as User and click OK with no
password.
3. If the login screen does not appear, check all network connections.
4. The main window appears. In the bottom right-hand corner of the main window, click the Language button
to select the language.
5. The Network Board drop-down list shows the Network Board, IP Address and MAC Address of the PC in
which the Configurator is running.
P841B-TM-EN-1.1 357
5.8.4 PRP/HSR DEVICE IDENTIFICATION

To configure the redundant Ethernet board, go to the main window and click the Identify Device button. A list of
devices are shown with the following details:
● Device address
● MAC address
● Version number of the firmware
● SNTP IP address
● Date & time of the real-time clock, from the board.
Select the device you wish to configure. The MAC address of the selected device is highlighted.
5.8.5 SELECTING THE DEVICE MODE

You must now select the device mode that you wish to use. This will be either PRP or HSR. To do this, select the
appropriate radio button then click the Update button. You will be asked to confirm a device reboot. Click OK to
confirm.
5.8.6 PRP/HSR IP ADDRESS CONFIGURATION

To change the network address component of the IP address:
1. From the main window click the IP Config button. The Device setup screen appears.
2. Enter the required board IP address and click OK. This is the redundancy network address, not the IEC 61850
IP address.
3. The board network address is updated and displayed in the main window.
5.8.7 SNTP IP ADDRESS CONFIGURATION

To Configure the SNTP server IP address:
1. From the main window click the SNTP Config button. The Device setup screen appears.
2. Enter the required MAC SNTP address and server IP SNTP Address. Click OK.
3. The updated MAC and IP SNTP addresses appear in the main screen.
5.8.8 CHECK FOR CONNECTED EQUIPMENT

To check what devices are connected to the device being monitored:
1. From the main window, select the device.
2. Click the Equipment button.
3. At the bottom of the main window, a box shows the ports where devices are connected and their MAC
addresses.
5.8.9 PRP CONFIGURATION

To view or configure the PRP Parameters:
1. Ensure that you have set the device mode to PRP.
2. Click the PRP/HSR Config button. The PRP Config screen appears.
3. To view the available parameters, click the Get PRP Parameters button.
4. To change the parameters, click the Set Parameters button and modify their values.
If you need to restore the default values of the parameters, click the Restore Defaults button.
358 P841B-TM-EN-1.1
The configurable parameters are as follows:

● Multicast Address: Use this field to configure the multicast destination address. All DANPs in the network
must be configured to operate with the same multicast address for the purpose of network supervision.
● Node Forget Time: This is the time after which a node entry is cleared in the nodes table.
● Life Check Interval: This defines how often a node sends a PRP_Supervision frame. All DANPs shall be
configured with the same Life Check Interval.
5.8.10 HSR CONFIGURATION

To view or configure the HSR Parameters:
1. Click the PRP/HSR Config button. The HSR Config screen appears.
2. To view the available parameters in the board that is connected, click the Retrieve HSR Parameters from
IED button.
3. To change the parameters, click the Set Parameters button and modify their values.
If you need to restore the default values of the parameters, click the Restore Defaults button.
The configurable parameters are as follows:
● Multicast Address: Use this field to configure the multicast destination address. All DANPs in the network
must be configured to operate with the same multicast address for the purpose of network supervision.
● Node Forget Time: This is the time after which a node entry is cleared in the nodes table.
● Life Check Interval: This defines how often a node sends a PRP_Supervision frame. All DANPs must be
configured with the same Life Check Interval.
● Proxy Node Table Forget Time: This is the time after which a node entry is cleared in the ProxyTable
● Proxy Node Table Max Entries: This is the maximum number of entries in the ProxyTable
● Entry Forget Time: This is the time after which an entry is removed from the duplicates
● Node Reboot Interval: This is the minimum time during which a node that reboots remains silent
5.8.11 FILTERING DATABASE

The Filtering Database is used to determine how frames are forwarded or filtered across the on-board Ethernet
switch. Filtering information specifies the set of ports to which frames received from a specific port are forwarded.
The Ethernet switch examines each received frame to see if the frame's destination address matches a source
address listed in the Filtering Database. If there is a match, the device uses the filtering/forwarding information for
that source address to determine how to forward or filter the frame. Otherwise the frame is forwarded to all the
ports in the Ethernet switch (broadcast).
General tab
The Filtering Database contains two types of entry; static and dynamic. The Static Entries are the source addresses
entered by an administrator. The Dynamic Entries are the source addresses learnt by the switch process. The
Dynamic Entries are removed from the Filtering Database after the Ageing Time. The Database holds a maximum
of 1024 entries.
1. To access the forwarding database functions, if required, click the Filtering Database button in the main
window.
2. To view the Forwarding Database Size, Number of Static Entries and Number of Dynamic Entries, click Read
Database Info.
3. To set the Aging Time, enter the number of seconds in the text box and click the Set button.
Filtering Entries tab

The Filtering Database configuration pages are used to view, add or delete entries from the Filtering Database. This
feature is available only for the administrator. This Filtering Database is mainly used during the testing to verify the
P841B-TM-EN-1.1 359
PRP/HSR functionality. To add an entry in the forwarding database, click the Filtering Entries tab. Configure as
follows:
1. Select the Port Number and MAC Address
2. Set the Entry type (Dynamic or Static)
3. Set the cast type (Unicast or Multicast)
4. Set theMGMT and Rate Limit
5. Click the Create button. The new entry appears in the forwarding database.
To delete an entry from the forwarding database, select the entry and click the Delete Entry button.
Goose Filtering tab

This page configures the source MACs from which GOOSE messages will be allowed or blocked. The filtering can be
configured by either the MAC address range boxes or by selecting or unselecting the individual MAC addresses in
the MAC table. After you have defined the addresses to be allowed or blocked you need to update the table and
apply the filter:
● Update Table: This updates the MAC table according to the filtering range entered in the MAC address
range boxes.
● Apply Filter: This applies the filtering configuration in the MAC table to the HSR/PRP board.
5.8.12 END OF SESSION

To finish the session:
1. In the main window, click the Quit button, a new screen appears.
2. If a database backup is required, click Yes, a new screen appears.
3. Click the ... button to browse the path. Enter the name in the text box.
5.9 RSTP CONFIGURATOR

The RSTP Configurator tool is intended for MiCOM Px4x IEDs with redundant Ethernet using RSTP (Rapid Spanning
Tree Protocol). This tool is used to identify IEDs, configure the redundancy IP address, configure the SNTP IP
address and configure the RSTP parameters.
5.9.1 CONNECTING THE IED TO A PC

Connect the IED to the PC on which the Configurator tool is used. This connection is done through an Ethernet
switch or through a media converter.
360 P841B-TM-EN-1.1
RJ45
Ethernet switch
Media
Converter
TX1 RX1 TX2 RX2
TX RX
RX1 TX1 RX2 TX2 RX1 TX1 RX2 TX2
IED IED
(a) (b)
V01803
Figure 172: Connection using (a) an Ethernet switch and (b) a media converter
5.9.2 INSTALLING THE CONFIGURATOR

To install the configurator:
1. Double click the WinPcap installer.
2. Double click the Configurator installer.
3. Click Next and follow the on-screen instructions.
5.9.3 STARTING THE CONFIGURATOR

To start the configurator:
1. Select the Configurator from the Windows Programs menu.
2. The Login screen appears. For user mode login, enter the Login name as User and click OK with no
password.
3. If the login screen does not appear, check all network connections.
4. The main window appears. In the bottom right-hand corner of the main window, click the Language button
to select the language.
5. The Network Board drop-down list shows the Network Board, IP Address and MAC Address of the PC in
which the Configurator is running.
5.9.4 RSTP DEVICE IDENTIFICATION

To configure the redundant Ethernet board, go to the main window and click Identify Device.
P841B-TM-EN-1.1 361
Note:
Due to the time needed to establish the RSTP protocol, wait 25 seconds between connecting the PC to the IED and clicking the
Identify Device button.
The redundant Ethernet board connected to the PC is identified and its details are listed.
● Device address
● MAC address
● Version number of the firmware
● SNTP IP address
● Date & time of the real-time clock, from the board.
5.9.5 RSTP IP ADDRESS CONFIGURATION

To change the network address component of the IP address,
1. From the main window click the IP Config button.
2. The Device Setup screen appears showing the IP Base Address. This is the board redundancy network
address, not the IEC 61850 IP address.
3. Enter the required board IP address.
4. Click OK. The board network address is updated and displayed in the main window.
5.9.6 SNTP IP ADDRESS CONFIGURATION

To Configure the SNTP server IP address:
2. Enter the required MAC SNTP address and server IP SNTP Address. Click OK.

addresses.
5.9.8 RSTP CONFIGURATION

1. To view or configure the RSTP Bridge Parameters, from the main window, click the device address to select
the device. The selected device MAC address appears highlighted.
2. Click the RSTP Config button. The RSTP Config screen appears.
3. To view the available parameters in the board that is connected, click the Get RSTP Parameters button.
4. To set the configurable parameters such as Bridge Max Age, Bridge Hello Time, Bridge Forward Delay, and
Bridge Priority, modify the parameter values according to the following table and click Set RSTP
Parameters.
Maximum value
S.No Parameter Default value (second) Minimum value (second)
(second)
1 Bridge Max Age 20 6 40
2 Bridge Hello Time 2 1 10
362 P841B-TM-EN-1.1
Maximum value
S.No Parameter Default value (second) Minimum value (second)
(second)
3 Bridge Forward Delay 15 4 30
4 Bridge Priority 32768 0 61440
5.9.8.1 BRIDGE PARAMETERS

To read the RSTP bridge parameters from the board,
1. From the main window click the device address to select the device. The RSTP Config window appears and
the default tab is Bridge Parameters.
2. Click the Get RSTP Parameters button. This displays all the RSTP bridge parameters from the Ethernet
board.
3. To modify the RSTP parameters, enter the values and click Set RSTP Parameters.
4. To restore the default values, click Restore Default and click Set RSTP Parameters.
The grayed parameters are read-only and cannot be modified.
Note:
When assigning the bridge priority, make sure the root of the network is the Ethernet switch, not the IEDs. This reduces the
number of hops to reach all devices in the network. Also make sure the priority values for all IEDs are higher than that of the
switch.
5.9.8.2 PORT PARAMETERS

This function is useful if you need to view the parameters of each port.
1. From the main window, click the device address to select the device. The RSTP Config window appears.
2. Select the Port Parameters tab, then click Get Parameters to read the port parameters. Alternatively, select
the port numbers to read the parameters.
5.9.8.3 PORT STATES

This is used to see which ports of the board are enabled or disabled.
1. From the main window, click the device address to select the device. The RSTP Config window appears.
2. Select the Port States tab then click the Get Port States button. This lists the ports of the Ethernet board. A
tick shows they are enabled.

5.10 SWITCH MANAGER

Switch Manager is used to manage Ethernet ring networks and MiCOM H35x-V2 and H36x-V2 SNMP facilities. It is
a set of tools used to manage, optimize, diagnose and supervise your network. It also handles the version software
of the switch.
The Switch Manager tool is also intended for MiCOM Px4x IEDs with redundant Ethernet using Self Healing Protocol
(SHP) and Dual Homing Protocol (DHP). This tool is used to identify IEDs and General Electric Switches, and to
configure the redundancy IP address for the General Electric proprietary Self Healing Protocol and Dual Homing
Protocol.
P841B-TM-EN-1.1 363
Switch hardware
General Electric switches are stand-alone devices (H3xx, H6x families) or embedded in a computer device rack, for
example MiCOM C264 (SWDxxx, SWRxxx, SWUxxx Ethernet boards) or PC board (MiCOM H14x, MiCOM H15x,
MiCOM H16x).
Switch range
There are 3 types of General Electric switches:
● Standard switches: SWU (in C264), H14x (PCI), H34x, H6x
● Redundant Ring switches: SWR (in C264), H15x (PCI), H35x,
● Redundant Dual Homing switches: SWD (in C264), H16x (PCI), H36x
Switch Manager allows you to allocate an IP addresses for General Electric switches. Switches can then be
synchronized using the Simple Network Time Protocol (SNTP) or they can be administrated using the Simple
Network Management Protocol (SNMP).
All switches have a single 6-byte MAC address.
Redundancy Management
Standard Ethernet does not support a loop at the OSI link layer (layer 2 of the 7 layer model). A mesh topology
cannot be created using a standard Hub and switch. Redundancy needs separate networks using hardware in
routers or software in dedicated switches using STP (Spanning Tree Protocol). However, this redundancy
mechanism is too slow for one link failure in electrical automation networks.
General Electric has developed its own Redundancy ring and star mechanisms using two specific Ethernet ports of
the redundant switches. This redundancy works between General Electric switches of the same type. The two
redundant Ethernet connections between General Electric switches create one private redundant Ethernet LAN.
The Ethernet ports dedicated to the redundancy are optical Ethernet ports. The General Electric redundancy
mechanism uses a single specific address for each Ethernet switch of the private LAN. This address is set using DIP
switches or jumpers.
Switch Manager monitors the redundant address of the switches and the link topology between switches.
5.10.1 INSTALLATION
Switch Manager requirements

● PC with Windows XP or later
● Ethernet port
● 200 MB hard disk space
● PC IP address configured in Windows in same IP range as switch
Network IP address
IP addressing is needed for time synchronization of GE switches and for SNMP management.
Switch Manager is used to define IP addresses of GE switches. These addresses must be in the range of the system
IP, depending on the IP mask of the engineering PC for substation maintenance.
GE switches have a default multicast so the 3rd word of the IP address is always 254.
Installation procedure
Run Setup.exe and follow the on-screen instructions.
364 P841B-TM-EN-1.1
5.10.2 SETUP
1. Make sure the PC has one Ethernet port connected to the GE switch.
2. Configure the PC's Ethernet port on the same subnet as the GE switch.
3. Select User or Admin mode. In User mode enter the user name as User, leave the password blank and click
OK. In Admin mode you can not upload the firmware on the Ethernet repeaters.
4. In Admin mode enter the user name as Admin, enter the password and click OK. All functions are available
including Expert Maintenance facilities.
5. Click the Language button in the bottom right of the screen and select your language.
6. If several Ethernet interfaces are used, in the Network board drop-down box, select the PC Network board
connected to the GE switch. The IP and MAC addresses are displayed below the drop-down box.
7. Periodically click the Ring Topology button (top left) to display or refresh the list of GE switches that are
connected.
5.10.3 NETWORK SETUP

To configure the network options:
1. From the main window click the Settings button. The Network Setup screen appears.
2. Enter the required board IP address. The first two octets can be configured. The third octet is always 254.
The last octet is set using the DIP switches (SW2) on the redundant Ethernet board, next to the ribbon
connector.
3. Click OK. The board network address is updated and displayed in the main window.
5. Enter the required MAC SNTP Address and server IP SNTP Address. Click OK.
7. Click the Saturation button. A new screen appears.
8. Set the saturation level and click OK. The default value is 300.
5.10.4 BANDWIDTH USED

To show how much bandwidth is used in the ring,
Click the Ring% button, at the bottom of the main window. The percentage of bandwidth used in the ring is
displayed.
5.10.5 RESET COUNTERS

To reset the switch counters,
1. Click Switch Counter Reset.
2. Click OK.

addresses.
P841B-TM-EN-1.1 365
5.10.7 MIRRORING FUNCTION

Port mirroring is a method of monitoring network traffic that forwards a copy of each incoming and outgoing
packet from one port of the repeater to another port where the data can be studied. Port mirroring is managed
locally and a network administrator uses it as a diagnostic tool.
To set up port mirroring:
1. Select the address of the device in the main window.
2. Click the Mirroring button, a new screen appears.
3. Click the checkbox to assign a a mirror port. A mirror port copies the incoming and outgoing traffic of the
port.
5.10.8 PORTS ON/OFF

To enable or disable ports:
2. Click Ports On/Off, a new screen appears.
3. Click the checkbox to enable or disable a port. A disabled port has an empty checkbox.
5.10.9 VLAN
The Virtual Local Area Network (VLAN) is a technique used to split an interconnected physical network into several
networks. This technique can be used at all ISO/OSI levels. The VLAN switch is mainly at OSI level 1 (physical VLAN)
which allows communication only between some Ethernet physical ports.
Ports on the switch can be grouped into Physical VLANs to limit traffic flooding. This is because it is limited to ports
belonging to that VLAN and not to other ports.
Port-based VLANs are VLANs where the packet forwarding decision is based on the destination MAC address and
its associated port. You must define outgoing ports allowed for each port when using port-based VLANs. The VLAN
only governs the outgoing traffic so is unidirectional. Therefore, if you wish to allow two subscriber ports to talk to
each other, you must define the egress port for both ports. An egress port is an outgoing port, through which a
data packet leaves.
To assign a physical VLAN to a set of ports:
2. Click the VLAN button, a new screen appears.
3. Use the checkboxes to select which ports will be in the same VLAN. By default all the ports share the same
VLAN.

366 P841B-TM-EN-1.1
6 SIMPLE NETWORK MANAGEMENT PROTOCOL (SNMP)

Simple Network Management Protocol (SNMP) is a network protocol designed to manage devices in an IP network.
The MiCOM P40 Modular products can provide up to two SNMP interfaces on Ethernet models; one to the IED’s
Main Processor for device level status information, and another directly to the redundant Ethernet board (where
applicable) for specific Ethernet network level information.
Two versions of SNMP are supported: Version 2c, and a secure implementation of version 3 that includes cyber-
security. Only the Main Processor SNMP interface supports Version 3.
6.1 SNMP MANAGEMENT INFORMATION BASES

SNMP uses a Management Information Base (MIB), which contains information about parameters to supervise. The
MIB format is a tree structure, with each node in the tree identified by a numerical Object Identifier (OID). Each OID
identifies a variable that can be read using SNMP with the appropriate software. The information in the MIB is
standardized.
Each device in a network (workstation, server, router, bridge, etc.) maintains a MIB that reflects the status of the
managed resources on that system, such as the version of the software running on the device, the IP address
assigned to a port or interface, the amount of free hard drive space, or the number of open files. The MIB does not
contain static data, but is instead an object-oriented, dynamic database that provides a logical collection of
managed object definitions. The MIB defines the data type of each managed object and describes the object.
6.2 MAIN PROCESSOR MIBS STRUCTURE

The Main Processor MIB uses a private OID with a specific Alstom Grid number assigned by the IANA. Some items
in this MIB also support SNMP traps (where indicated). These are items that can automatically notify a host without
being read.
Address Name Trigger Trap?
0 ROOT NODE
1 ISO
3 Org
6 DOD
1 Internet
4 Private
1 Enterprise
43534 Alstom Grid (IANA No)
1 Px4x
1 System Data
1 Description YES
2 Plant Reference YES
3 Model Number NO
4 Serial Number NO
5 Frequency NO
6 Plant Status YES
7 Active Group YES
8 Software Ref.1 NO
9 Software Ref.2 NO
10 Access Level (UI) YES
2 Date and Time
P841B-TM-EN-1.1 367
Address Name Trigger Trap?

1 Date Time NO
2 IRIG-B Status YES
3 Battery Status YES
4 Active Sync source YES
5 SNTP Server 1 NO
6 SNTP Server 2 NO
7 SNTP Status YES
8 PTP Status YES
3 System Alarms
1 Invalid Message Format YES
2 Main Protection Fail YES
3 Comms Changed YES
4 Max Prop. Alarm YES
5 9-2 Sample Alarm YES
6 9-2LE Cfg Alarm YES
7 Battery Fail YES
8 Rear Communication Fail YES
9 GOOSE IED Missing YES
10 Intermicom loopback YES
11 Intermicom message fail YES
12 Intermicom data CD fail YES
13 Intermicom Channel fail YES
14 Backup setting fail YES
15 User Curve commit to flash failure YES
16 SNTP time Sync fail YES
17 PTP failure alarm YES
4 Device Mode
1 IED Mod/Beh YES
2 Simulation Mode of Subscription YES
6.3 REDUNDANT ETHERNET BOARD MIB STRUCTURE

The Redundant Ethernet board MIB uses three types of OID:
● sysDescr
● sysUpTime
● sysName
MIB structure for RSTP, DHP and SHP

Address Name
0 CCITT
1 ISO
3 Org
6 DOD
1 Internet
368 P841B-TM-EN-1.1
Address Name
2 mgmt
1 Mib-2
1 sys
1 sysDescr
3 sysUpTime
4 sysName
Remote Monitoring
16 RMON
1 statistics
1 etherstat
1 etherStatsEntry
9 etherStatsUndersizePkts
10 etherStatsOversizePkts
12 etherStatsJabbers
13 etherStatsCollisions
14 etherStatsPkts64Octets
15 etherStatsPkts65to127Octets
MIB structure for PRP/HSR

Address Name
0 ITU
1 ISO
0 Standard
62439 IECHighavailibility
3 PRP
1 linkRedundancyEntityObjects
0 lreConfiguration
0 lreConfigurationGeneralGroup
1 lreManufacturerName
2 lreInterfaceCount
1 lreConfigurationInterfaceGroup
0 lreConfigurationInterfaces
1 lreInterfaceConfigTable
1 lreInterfaceConfigEntry
1 lreInterfaceConfigIndex
2 lreRowStatus
3 lreNodeType
4 lreNodeName
5 lreVersionName
6 lreMacAddressA
P841B-TM-EN-1.1 369
Address Name
7 lreMacAddressB
8 lreAdapterAdminStateA
9 lreAdapterAdminStateB
10 lreLinkStatusA
11 lreLinkStatusB
12 lreDuplicateDiscard
13 lreTransparentReception
14 lreHsrLREMode
15 lreSwitchingEndNode
16 lreRedBoxIdentity
17 lreSanA
18 lreSanB
19 lreEvaluateSupervision
20 lreNodesTableClear
21 lreProxyNodeTableClear
1 lreStatistics
1 lreStatisticsInterfaceGroup
0 lreStatisticsInterfaces
1 lreInterfaceStatsTable
1 lreInterfaceStatsIndex
2 lreCntTotalSentA
3 lreCntTotalSentB
4 lreCntErrWrongLANA
5 lreCntErrWrongLANB
6 lreCntReceivedA
7 lreCntReceivedB
8 lreCntErrorsA
9 lreCntErrorsB
10 lreCntNodes
11 IreOwnRxCntA
12 IreOwnRxCntB
3 lreProxyNodeTable
1 lreProxyNodeEntry
1 reProxyNodeIndex
2 reProxyNodeMacAddress
3 Org
6 Dod
1 Internet
2 mgmt
1 mib-2
1 System
1 sysDescr
3 sysUpTime
370 P841B-TM-EN-1.1
Address Name
5 sysName
7 sysServices
2 interfaces
2 ifTable
1 ifEntry
1 ifIndex
2 ifDescr
3 ifType
4 ifMtu
5 ifSpeed
6 ifPhysAddress
7 ifAdminStatus
8 ifOpenStatus
9 ifLastChange
10 ifInOctets
11 ifInUcastPkts
12 ifInNUcastPkts
13 ifInDiscards
14 ifInErrors
15 ifInUnknownProtos
16 ifOutOctets
17 ifOutUcastPkts
18 ifOutNUcastPkts
19 ifOutDiscards
20 ifOutErrors
21 ifOutQLen
22 ifSpecific
16 rmon
1 statistics
1 etherStatsTable
1 etherStatsEntry
1 etherStatsIndex
2 etherStatsDataSource
3 etherStatsDropEvents
4 etherStatsOctets
5 etherStatsPkts
6 etherStatsBroadcastPkts
7 etherStatsMulticastPkts
8 etherStatsCRCAlignErrors
9 etherStatsUndersizePkts
10 etherStatsOversizePkts
11 etherStatsFragments
12 etherStatsJabbers
P841B-TM-EN-1.1 371
Address Name
13 etherStatsCollisions
14 etherStatsPkts64Octets
20 etherStatsOwner
21 etherStatsStatus
6.4 ACCESSING THE MIB

Various SNMP client software tools can be used. We recommend using an SNMP MIB browser, which can perform
the basic SNMP operations such as GET, GETNEXT and RESPONSE.
Note:
There are two IP addresses visible when communicating with the Redundant Ethernet Card via the fibre optic ports: Use the
one for the IED itself to the Main Processor SNMP interface, and use the one for the on-board Ethernet switch to access the
Redundant Ethernet Board SNMP interface. See the configuration chapter for more information.
6.5 MAIN PROCESSOR SNMP CONFIGURATION

You configure the main processor SNMP interface using the HMI panel. Two different versions are available;
SNMPv2c and SNMPv3:
To enable the main processor SNMP interface:
1. Select the COMMUNICATIONS column and scroll to the SNMP PARAMETERS heading
2. You can select either v2C, V3 or both. Selecting None will disable the main processor SNMP interface.
SNMP Trap Configuration

SNMP traps allow for unsolicited reporting between the IED and up to two SNMP managers with unique IP
addresses. The device MIB details what information can be reported using Traps. To configure the SNMP Traps:
1. Move down to the cell Trap Dest. IP 1 and enter the IP address of the first destination SNMP manager.
Setting this cell to 0.0.0.0 disables the first Trap interface.
2. Move down to the cell Trap Dest. IP 2 and enter the IP address of the second destination SNMP manager.
Setting this cell to 0.0.0.0 disables the Second Trap interface.
SNMP V3 Security Configuration

SNMPv3 provides a higher level of security via authentication and privacy protocols. The IED adopts a secure
SNMPv3 implementation with a user-based security model (USM).
372 P841B-TM-EN-1.1
Authentication is used to check the identity of users, privacy allows for encryption of SNMP messages. Both are
optional, however you must enable authentication in order to enable privacy. To configure these security options:
1. If SNMPv3 has been enabled, set the Security Level setting. There are three levels; without authentication
and without privacy (noAuthNoPriv), with authentication but without privacy (authNoPriv), and with
authentication and with privacy (authPriv).
2. If Authentication is enabled, use the Auth Protocol setting to select the authentication type. There are two
options: HMAC-MD5-96 or HMAC-SHA-96.
3. Using the Auth Password setting, enter the 8-character password to be used by the IED for authentication.
4. If privacy is enabled, use the Encrypt Protocol setting to set the 8-character password that will be used by
the IED for encryption.
SNMP V2C Security Configuration

SNMPv2c implements authentication between the master and agent using a parameter called the Community
Name. This is effectively the password but it is not encrypted during transmission (this makes it inappropriate for
some scenarios in which case version 3 should be used instead). To configure the SNMP 2c security:
1. If SNMPv2c has been enabled, use the Community Name setting to set the password that will be used by
the IED and SNMP manager for authentication. This may be between one and 8 characters.
P841B-TM-EN-1.1 373
7 DATA PROTOCOLS
The products supports a wide range of protocols to make them applicable to many industries and applications.
The exact data protocols supported by a particular product depend on its chosen application, but the following
table gives a list of the data protocols that are typically available.
SCADA data protocols

Data Protocol Layer 1 protocol Description
Courier K-Bus, RS232, RS485, Ethernet Standard for SCADA communications developed by General Electric.
MODBUS RS485 Standard for SCADA communications developed by Modicon.
IEC 60870-5-103 RS485 IEC standard for SCADA communications
Standard for SCADA communications developed by Harris. Used mainly in
DNP 3.0 RS485, Ethernet
North America.
IEC 61850 Ethernet IEC standard for substation automation. Facilitates interoperability.
The relationship of these protocols to the lower level physical layer protocols are as follows:
IEC 60870-5-103
MODBUS IEC 61850
Data Protocols
DNP3.0 DNP3.0
Courier Courier Courier Courier
Data Link Layer EIA(RS)485 Ethernet EIA(RS)232 K-Bus
Physical Layer Copper or Optical Fibre
7.1 COURIER
This section should provide sufficient detail to enable understanding of the Courier protocol at a level required by
most users. For situations where the level of information contained in this manual is insufficient, further
publications (R6511 and R6512) containing in-depth details about the protocol and its use, are available on
request.
Courier is an General Electric proprietary communication protocol. Courier uses a standard set of commands to
access a database of settings and data in the IED. This allows a master to communicate with a number of slave
devices. The application-specific elements are contained in the database rather than in the commands used to
interrogate it, meaning that the master station does not need to be preconfigured. Courier also provides a
sequence of event (SOE) and disturbance record extraction mechanism.
7.1.1 PHYSICAL CONNECTION AND LINK LAYER

Courier can be used with three physical layer protocols: K-Bus, EIA(RS)232 or EIA(RS)485.
Several connection options are available for Courier
● The front serial RS232 port (for connection to Settings application software on, for example, a laptop
● Rear Port 1 (RP1) - for permanent SCADA connection via RS485 or K-Bus
● Optional fibre port (RP1 in slot A) - for permanent SCADA connection via optical fibre
● Optional Rear Port 2 (RP2) - for permanent SCADA connection via RS485, K-Bus, or RS232
For either of the rear ports, both the IED address and baud rate can be selected using the front panel menu or by
the settings application software.
374 P841B-TM-EN-1.1
7.1.2 COURIER DATABASE

The Courier database is two-dimensional and resembles a table. Each cell in the database is referenced by a row
and column address. Both the column and the row can take a range from 0 to 255 (0000 to FFFF Hexadecimal.
Addresses in the database are specified as hexadecimal values, for example, 0A02 is column 0A row 02.
Associated settings or data are part of the same column. Row zero of the column has a text string to identify the
contents of the column and to act as a column heading.
The product-specific menu databases contain the complete database definition.
7.1.3 SETTINGS CATEGORIES

There are two main categories of settings in protection IEDs:
● Control and support settings
● Protection settings
With the exception of the Disturbance Recorder settings, changes made to the control and support settings are
implemented immediately and stored in non-volatile memory. Changes made to the Protection settings and the
Disturbance Recorder settings are stored in ‘scratchpad’ memory and are not immediately implemented. These
need to be committed by writing to the Save Changes cell in the CONFIGURATION column.
7.1.4 SETTING CHANGES

Courier provides two mechanisms for making setting changes. Either method can be used for editing any of the
settings in the database.
Method 1
This uses a combination of three commands to perform a settings change:
First, enter Setting mode: This checks that the cell is settable and returns the limits.
1. Preload Setting: This places a new value into the cell. This value is echoed to ensure that setting corruption
has not taken place. The validity of the setting is not checked by this action.
2. Execute Setting: This confirms the setting change. If the change is valid, a positive response is returned. If
the setting change fails, an error response is returned.
3. Abort Setting: This command can be used to abandon the setting change.
This is the most secure method. It is ideally suited to on-line editors because the setting limits are extracted before
the setting change is made. However, this method can be slow if many settings are being changed because three
commands are required for each change.
Method 2
The Set Value command can be used to change a setting directly. The response to this command is either a
positive confirm or an error code to indicate the nature of a failure. This command can be used to implement a
setting more rapidly than the previous method, however the limits are not extracted. This method is therefore most
suitable for off-line setting editors such as MiCOM S1 Agile, or for issuing preconfigured control commands.
7.1.5 EVENT EXTRACTION

You can extract events either automatically (rear serial port only) or manually (either serial port). For automatic
extraction, all events are extracted in sequential order using the Courier event mechanism. This includes fault and
maintenance data if appropriate. The manual approach allows you to select events, faults, or maintenance data
as desired.
P841B-TM-EN-1.1 375
7.1.5.1 AUTOMATIC EVENT RECORD EXTRACTION

This method is intended for continuous extraction of event and fault information as it is produced. It is only
supported through the rear Courier port.
When new event information is created, the Event bit is set in the Status byte. This indicates to the Master device
that event information is available. The oldest, non-extracted event can be extracted from the IED using the Send
Event command. The IED responds with the event data.
Once an event has been extracted, the Accept Event command can be used to confirm that the event has been
successfully extracted. When all events have been extracted, the Event bit is reset. If there are more events still to
be extracted, the next event can be accessed using the Send Event command as before.
7.1.5.2 MANUAL EVENT RECORD EXTRACTION

The VIEW RECORDS column (location 01) is used for manual viewing of event, fault, and maintenance records. The
contents of this column depend on the nature of the record selected. You can select events by event number and
directly select a fault or maintenance record by number.
Event Record Selection ('Select Event' cell: 0101)

This cell can be set the number of stored events. For simple event records (Type 0), cells 0102 to 0105 contain the
event details. A single cell is used to represent each of the event fields. If the event selected is a fault or
maintenance record (Type 3), the remainder of the column contains the additional information.
Fault Record Selection ('Select Fault' cell: 0105)

This cell can be used to select a fault record directly, using a value between 0 and 4 to select one of up to five
stored fault records. (0 is the most recent fault and 4 is the oldest). The column then contains the details of the fault
record selected.
Maintenance Record Selection ('Select Maint' cell: 01F0)

This cell can be used to select a maintenance record using a value between 0 and 4. This cell operates in a similar
way to the fault record selection.
If this column is used to extract event information, the number associated with a particular record changes when
a new event or fault occurs.
Event Types
The IED generates events under certain circumstances such as:
● Change of state of output contact
● Change of state of opto-input
● Protection element operation
● Alarm condition
● Setting change
● Password entered/timed-out
Event Record Format

The IED returns the following fields when the Send Event command is invoked:
● Cell reference
● Time stamp
● Cell text
● Cell value
376 P841B-TM-EN-1.1
The Menu Database contains tables of possible events, and shows how the contents of the above fields are
interpreted. Fault and Maintenance records return a Courier Type 3 event, which contains the above fields plus two
additional fields:
● Event extraction column
● Event number
These events contain additional information, which is extracted from the IED using column B4. Row 01 contains a
Select Record setting that allows the fault or maintenance record to be selected. This setting should be set to the
event number value returned in the record. The extended data can be extracted from the IED by uploading the text
and data from the column.
7.1.6 DISTURBANCE RECORD EXTRACTION

The stored disturbance records are accessible through the Courier interface. The records are extracted using
column (B4).
The Select Record cell can be used to select the record to be extracted. Record 0 is the oldest non-extracted
record. Older records which have been already been extracted are assigned positive values, while younger records
are assigned negative values. To help automatic extraction through the rear port, the IED sets the Disturbance bit
of the Status byte, whenever there are non-extracted disturbance records.
Once a record has been selected, using the above cell, the time and date of the record can be read from the
Trigger Time cell (B402). The disturbance record can be extracted using the block transfer mechanism from cell
B40B and saved in the COMTRADE format. The settings application software software automatically does this.
7.1.7 PROGRAMMABLE SCHEME LOGIC SETTINGS

The programmable scheme logic (PSL) settings can be uploaded from and downloaded to the IED using the block
transfer mechanism.
The following cells are used to perform the extraction:
● Domain cell (B204): Used to select either PSL settings (upload or download) or PSL configuration data
(upload only)
● Sub-Domain cell (B208): Used to select the Protection Setting Group to be uploaded or downloaded.
● Version cell (B20C): Used on a download to check the compatibility of the file to be downloaded.
● Transfer Mode cell (B21C): Used to set up the transfer process.
● Data Transfer cell (B120): Used to perform upload or download.
The PSL settings can be uploaded and downloaded to and from the IED using this mechanism. The settings
application software must be used to edit the settings. It also performs checks on the validity of the settings before
they are transferred to the IED.
7.1.8 TIME SYNCHRONISATION

The time and date can be set using the time synchronization feature of the Courier protocol. The device will correct
for the transmission delay. The time synchronization message may be sent as either a global command or to any
individual IED address. If the time synchronization message is sent to an individual address, then the device will
respond with a confirm message. If sent as a global command, the (same) command must be sent twice. A time
synchronization Courier event will be generated/produced whether the time-synchronization message is sent as a
global command or to any individual IED address.
If the clock is being synchronized using the IRIG-B input then it will not be possible to set the device time using the
Courier interface. An attempt to set the time using the interface will cause the device to create an event with the
current date and time taken from the IRIG-B synchronized internal clock.
P841B-TM-EN-1.1 377
7.1.9 COURIER CONFIGURATION

To configure the device:
1. Select the CONFIGURATION column and check that the Comms settings cell is set to Visible.
2. Select the COMMUNICATIONS column.
3. Move to the first cell down (RP1 protocol). This is a non-settable cell, which shows the chosen
communication protocol – in this case Courier.
COMMUNICATIONS
RP1 Protocol
Courier
4. Move down to the next cell (RP1 Address). This cell controls the address of the RP1 port on thje device. Up to
32 IEDs can be connected to one spur. It is therefore necessary for each IED to have a unique address so
that messages from the master control station are accepted by one IED only. Courier uses an integer
number between 1 and 254 for the Relay Address. It is set to 255 by default, which has to be changed. It is
important that no two IEDs share the same address.
COMMUNICATIONS
RP1 Address
100
5. Move down to the next cell (RP1 InactivTimer). This cell controls the inactivity timer. The inactivity timer
controls how long the IED waits without receiving any messages on the rear port before revoking any
password access that was enabled and discarding any changes. For the rear port this can be set between 1
and 30 minutes.
COMMUNICATIONS
RP1 Inactivtimer
10.00 mins.
6. If the optional fibre optic connectors are fitted, the RP1 PhysicalLink cell is visible. This cell controls the
physical media used for the communication (Copper or Fibre optic).
COMMUNICATIONS
RP1 PhysicalLink
Copper
7. Move down to the next cell (RP1 Card Status). This cell is not settable. It displays the status of the chosen
physical layer protocol for RP1.
COMMUNICATIONS
RP1 Card Status
K-Bus OK
378 P841B-TM-EN-1.1
8. Move down to the next cell (RP1 Port Config). This cell controls the type of serial connection. Select between
K-Bus or RS485.
COMMUNICATIONS
RP1 Port Config
K-Bus
9. If using EIA(RS)485, the next cell (RP1 Comms Mode) selects the communication mode. The choice is either
IEC 60870 FT1.2 for normal operation with 11-bit modems, or 10-bit no parity. If using K-Bus this cell will not
appear.
COMMUNICATIONS
RP1 Comms Mode
IEC 60870 FT1.2
10. If using EIA(RS)485, the next cell down controls the baud rate. Three baud rates are supported; 9600, 19200
and 38400. If using K-Bus this cell will not appear as the baud rate is fixed at 64 kbps.
COMMUNICATIONS
RP1 Baud rate
19200
7.2 IEC 60870-5-103

The specification IEC 60870-5-103 (Telecontrol Equipment and Systems Part 5 Section 103: Transmission
Protocols), defines the use of standards IEC 60870-5-1 to IEC 60870-5-5, which were designed for communication
with protection equipment
This section describes how the IEC 60870-5-103 standard is applied to the Px40 platform. It is not a description of
the standard itself. The level at which this section is written assumes that the reader is already familiar with the
IEC 60870-5-103 standard.
This section should provide sufficient detail to enable understanding of the standard at a level required by most
users.
The IEC 60870-5-103 interface is a master/slave interface with the device as the slave device. The device conforms
to compatibility level 2, as defined in the IEC 60870-5-103.standard.
The following IEC 60870-5-103 facilities are supported by this interface:
● Initialization (reset)
● Time synchronization
● Event record extraction
● General interrogation
● Cyclic measurements
● General commands
● Disturbance record extraction
● Private codes

Two connection options are available for IEC 60870-5-103:
● Rear Port 1 (RP1) - for permanent SCADA connection via RS485
If the optional fibre optic port is fitted, a menu item appears in which the active port can be selected. However the
selection is only effective following the next power up.
P841B-TM-EN-1.1 379
The IED address and baud rate can be selected using the front panel menu or by the settings application software.
7.2.2 INITIALISATION
Whenever the device has been powered up, or if the communication parameters have been changed a reset
command is required to initialize the communications. The device will respond to either of the two reset
commands; Reset CU or Reset FCB (Communication Unit or Frame Count Bit). The difference between the two
commands is that the Reset CU command will clear any unsent messages in the transmit buffer, whereas the
Reset FCB command does not delete any messages.
The device will respond to the reset command with an identification message ASDU 5. The Cause of Transmission
(COT) of this response will be either Reset CU or Reset FCB depending on the nature of the reset command. The
content of ASDU 5 is described in the IEC 60870-5-103 section of the Menu Database, available from General
Electric separately if required.
In addition to the above identification message, it will also produce a power up event.
7.2.3 TIME SYNCHRONISATION

The time and date can be set using the time synchronization feature of the IEC 60870-5-103 protocol. The device
will correct for the transmission delay as specified in IEC 60870-5-103. If the time synchronization message is sent
as a send/confirm message then the device will respond with a confirm message. A time synchronization Class 1
event will be generated/produced whether the time-synchronization message is sent as a send confirm or a
broadcast (send/no reply) message.
IEC 60870-5-103 interface. An attempt to set the time via the interface will cause the device to create an event
with the current date and time taken from the IRIG-B synchronized internal clock.
7.2.4 SPONTANEOUS EVENTS

Events are categorized using the following information:
● Function type
● Information Number
The IEC 60870-5-103 profile in the Menu Database contains a complete listing of all events produced by the
device.
7.2.5 GENERAL INTERROGATION (GI)

The GI request can be used to read the status of the device, the function numbers, and information numbers that
will be returned during the GI cycle. These are shown in the IEC 60870-5-103 profile in the Menu Database.
7.2.6 CYCLIC MEASUREMENTS

The device will produce measured values using ASDU 9 on a cyclical basis, this can be read from the device using a
Class 2 poll (note ADSU 3 is not used). The rate at which the device produces new measured values can be
controlled using the measurement period setting. This setting can be edited from the front panel menu or using
MiCOM S1 Agile. It is active immediately following a change.
The device transmits its measurands at 2.4 times the rated value of the analogue value.
7.2.7 COMMANDS
A list of the supported commands is contained in the Menu Database. The device will respond to other commands
with an ASDU 1, with a cause of transmission (COT) indicating ‘negative acknowledgement’.
380 P841B-TM-EN-1.1
7.2.8 TEST MODE

It is possible to disable the device output contacts to allow secondary injection testing to be performed using
either the front panel menu or the front serial port. The IEC 60870-5-103 standard interprets this as ‘test mode’. An
event will be produced to indicate both entry to and exit from test mode. Spontaneous events and cyclic measured
data transmitted whilst the device is in test mode will have a COT of ‘test mode’.
7.2.9 DISTURBANCE RECORDS

The disturbance records are stored in uncompressed format and can be extracted using the standard
mechanisms described in IEC 60870-5-103.
Note:
IEC 60870-5-103 only supports up to 8 records.
7.2.10 COMMAND/MONITOR BLOCKING

The device supports a facility to block messages in the monitor direction (data from the device) and also in the
command direction (data to the device). Messages can be blocked in the monitor and command directions using
one of the two following methods
● The menu command RP1 CS103Blcking in the COMMUNICATIONS column
● The DDB signals Monitor Blocked and Command Blocked
7.2.11 IEC 60870-5-103 CONFIGURATION

communication protocol – in this case IEC 60870-5-103.
COMMUNICATIONS
RP1 Protocol
IEC 60870-5-103
4. Move down to the next cell (RP1 Address). This cell controls the IEC 60870-5-103 address of the IED. Up to 32
IEDs can be connected to one spur. It is therefore necessary for each IED to have a unique address so that
messages from the master control station are accepted by one IED only. IEC 60870-5-103 uses an integer
number between 0 and 254 for the address. It is important that no two IEDs have the same IEC 60870 5 103
address. The IEC 60870-5-103 address is then used by the master station to communicate with the IED.
COMMUNICATIONS
RP1 address
162
5. Move down to the next cell (RP1 Baud Rate). This cell controls the baud rate to be used. Two baud rates are
supported by the IED, 9600 bits/s and 19200 bits/s. Make sure that the baud rate selected on the
IED is the same as that set on the master station.
COMMUNICATIONS
RP1 Baud rate
9600 bits/s
P841B-TM-EN-1.1 381
6. Move down to the next cell (RP1 Meas Period). The next cell down controls the period between
IEC 60870-5-103 measurements. The IEC 60870-5-103 protocol allows the IED to supply measurements at
regular intervals. The interval between measurements is controlled by this cell, and can be set between 1
and 60 seconds.
COMMUNICATIONS
RP1 Meas Period
30.00 s
COMMUNICATIONS
RP1 PhysicalLink
Copper
8. The next cell down (RP1 CS103Blcking) can be used for monitor or command blocking.
COMMUNICATIONS
RP1 CS103Blcking
Disabled
9. There are three settings associated with this cell; these are:
Setting: Description:
Disabled No blocking selected.
When the monitor blocking DDB Signal is active high, either by energising an opto input or control input,
Monitor Blocking reading of the status information and disturbance records is not permitted. When in this mode the device
returns a "Termination of general interrogation" message to the master station.
When the command blocking DDB signal is active high, either by energising an opto input or control input,
Command Blocking all remote commands will be ignored (i.e. CB Trip/Close, change setting group etc.). When in this mode the
device returns a "negative acknowledgement of command" message to the master station.
7.3 DNP 3.0

This section describes how the DNP 3.0 standard is applied in the product. It is not a description of the standard
itself. The level at which this section is written assumes that the reader is already familiar with the DNP 3.0
standard.
The descriptions given here are intended to accompany the device profile document that is included in the Menu
Database document. The DNP 3.0 protocol is not described here, please refer to the documentation available from
the user group. The device profile document specifies the full details of the DNP 3.0 implementation. This is the
standard format DNP 3.0 document that specifies which objects; variations and qualifiers are supported. The
device profile document also specifies what data is available from the device using DNP 3.0. The IED operates as a
DNP 3.0 slave and supports subset level 2, as described in the DNP 3.0 standard, plus some of the features from
level 3.
The DNP 3.0 protocol is defined and administered by the DNP Users Group. For further information on DNP 3.0 and
the protocol specifications, please see the DNP website (www.dnp.org).

DNP 3.0 can be used with two physical layer protocols: EIA(RS)485, or Ethernet.
382 P841B-TM-EN-1.1
Several connection options are available for DNP 3.0

● Rear Port 1 (RP1) - for permanent SCADA connection via RS485
● An RJ45 connection on an optional Ethernet board - for permanent SCADA Ethernet connection
● A fibre connection on an optional Ethernet board - for permanent SCADA Ethernet connection
The IED address and baud rate can be selected using the front panel menu or by the settings application software.
When using a serial interface, the data format is: 1 start bit, 8 data bits, 1 stop bit and optional configurable parity
bit.
7.3.2 OBJECT 1 BINARY INPUTS

Object 1, binary inputs, contains information describing the state of signals in the IED, which mostly form part of
the digital data bus (DDB). In general these include the state of the output contacts and opto-inputs, alarm signals,
and protection start and trip signals. The ‘DDB number’ column in the device profile document provides the DDB
numbers for the DNP 3.0 point data. These can be used to cross-reference to the DDB definition list. See the
relevant Menu Database document. The binary input points can also be read as change events using Object 2 and
Object 60 for class 1-3 event data.
7.3.3 OBJECT 10 BINARY OUTPUTS

Object 10, binary outputs, contains commands that can be operated using DNP 3.0. Therefore the points accept
commands of type pulse on (null, trip, close) and latch on/off as detailed in the device profile in the relevant Menu
Database document, and execute the command once for either command. The other fields are ignored (queue,
clear, trip/close, in time and off time).
There is an additional image of the Control Inputs. Described as Alias Control Inputs, they reflect the state of the
Control Input, but with a dynamic nature.
● If the Control Input DDB signal is already SET and a new DNP SET command is sent to the Control Input, the
Control Input DDB signal goes momentarily to RESET and then back to SET.
● If the Control Input DDB signal is already RESET and a new DNP RESET command is sent to the Control
Input, the Control Input DDB signal goes momentarily to SET and then back to RESET.
P841B-TM-EN-1.1 383
DNP Latch DNP Latch DNP Latch DNP Latch

ON ON OFF OFF
Control Input
(Latched)
Aliased Control
Input
(Latched)
Control Input
(Pulsed )
Aliased Control
Input
(Pulsed )
The pulse width is equal to the duration of one protection iteration
V01002
Figure 173: Control input behaviour
Many of the IED’s functions are configurable so some of the Object 10 commands described in the following
sections may not be available. A read from Object 10 reports the point as off-line and an operate command to
Object 12 generates an error response.
Examples of Object 10 points that maybe reported as off-line are:
● Activate setting groups: Ensure setting groups are enabled
● CB trip/close: Ensure remote CB control is enabled
● Reset NPS thermal: Ensure NPS thermal protection is enabled
● Reset thermal O/L: Ensure thermal overload protection is enabled
● Reset RTD flags: Ensure RTD Inputs is enabled
● Control inputs: Ensure control inputs are enabled
7.3.4 OBJECT 20 BINARY COUNTERS

Object 20, binary counters, contains cumulative counters and measurements. The binary counters can be read as
their present ‘running’ value from Object 20, or as a ‘frozen’ value from Object 21. The running counters of object
20 accept the read, freeze and clear functions. The freeze function takes the current value of the object 20 running
counter and stores it in the corresponding Object 21 frozen counter. The freeze and clear function resets the Object
20 running counter to zero after freezing its value.
Binary counter and frozen counter change event values are available for reporting from Object 22 and Object 23
respectively. Counter change events (Object 22) only report the most recent change, so the maximum number of
events supported is the same as the total number of counters. Frozen counter change events (Object 23) are
generated whenever a freeze operation is performed and a change has occurred since the previous freeze
command. The frozen counter event queues store the points for up to two freeze operations.
7.3.5 OBJECT 30 ANALOGUE INPUT

Object 30, analogue inputs, contains information from the IED’s measurements columns in the menu. All object 30
points can be reported as 16 or 32-bit integer values with flag, 16 or 32-bit integer values without flag, as well as
short floating point values.
384 P841B-TM-EN-1.1
Analogue values can be reported to the master station as primary, secondary or normalized values (which takes
into account the IED’s CT and VT ratios), and this is settable in the COMMUNICATIONS column in the IED.
Corresponding deadband settings can be displayed in terms of a primary, secondary or normalized value.
Deadband point values can be reported and written using Object 34 variations.
The deadband is the setting used to determine whether a change event should be generated for each point. The
change events can be read using Object 32 or Object 60. These events are generated for any point which has a
value changed by more than the deadband setting since the last time the data value was reported.
Any analogue measurement that is unavailable when it is read is reported as offline. For example, the frequency
would be offline if the current and voltage frequency is outside the tracking range of the IED. All Object 30 points
are reported as secondary values in DNP 3.0 (with respect to CT and VT ratios).
7.3.6 OBJECT 40 ANALOGUE OUTPUT

The conversion to fixed-point format requires the use of a scaling factor, which is configurable for the various
types of data within the IED such as current, voltage, and phase angle. All Object 40 points report the integer
scaling values and Object 41 is available to configure integer scaling quantities.
7.3.7 OBJECT 50 TIME SYNCHRONISATION

Function codes 1 (read) and 2 (write) are supported for Object 50 (time and date) variation 1. The DNP Need Time
function (the duration of time waited before requesting another time sync from the master) is supported, and is
configurable in the range 1 - 30 minutes.
Courier interface. An attempt to set the time using the interface will cause the device to create an event with the
current date and time taken from the IRIG-B synchronized internal clock.
7.3.8 DNP3 DEVICE PROFILE

This section describes the specific implementation of DNP version 3.0 within General Electric MiCOM P40 Agile IEDs
for both compact and modular ranges.
The devices use the DNP 3.0 Slave Source Code Library version 3 from Triangle MicroWorks Inc.
This document, in conjunction with the DNP 3.0 Basic 4 Document Set, and the DNP Subset Definitions Document,
provides complete information on how to communicate with the devices using the DNP 3.0 protocol.
This implementation of DNP 3.0 is fully compliant with DNP 3.0 Subset Definition Level 2. It also contains many
Subset Level 3 and above features.
7.3.8.1 DNP3 DEVICE PROFILE TABLE

The following table provides the device profile in a similar format to that defined in the DNP 3.0 Subset Definitions
Document. While it is referred to in the DNP 3.0 Subset Definitions as a “Document”, it is just one component of a
total interoperability guide. This table, in combination with the subsequent Implementation and Points List tables
should provide a complete interoperability/configuration guide for the device.
The following table provides the device profile in a similar format to that defined in the DNP 3.0 Subset Definitions
Document. While it is referred to in the DNP 3.0 Subset Definitions as a "Document", it is just one component of a
total interoperability guide. This table, in combination with the subsequent Implementation and Points List tables
should provide a complete interoperability/configuration guide for the device.
DNP 3.0
Device Profile Document
Vendor Name: General Electric
Device Name: MiCOM P40Agile Protection Relays – compact and modular range
P841B-TM-EN-1.1 385
DNP 3.0
Models Covered: All models
Highest DNP Level Supported*: For Requests: Level 2
*This is the highest DNP level FULLY supported. Parts of level 3 are For Responses: Level 2
also supported
Device Function: Slave
Notable objects, functions, and/or qualifiers supported in addition to the highest DNP levels supported (the complete list is described in the
DNP 3.0 Implementation Table):
For static (non-change event) object requests, request qualifier codes 00 and 01 (start-stop), 07 and 08 (limited quantity), and 17 and 28 (index)
are supported in addition to the request qualifier code 06 (no range (all points))
Static object requests sent with qualifiers 00, 01, 06, 07, or 08 will be responded with qualifiers 00 or 01
Static object requests sent with qualifiers 17 or 28 will be responded with qualifiers 17 or 28
For change-event object requests, qualifiers 17 or 28 are always responded
16-bit and 32-bit analogue change events with time may be requested
The read function code for Object 50 (time and date) variation 1 is supported
Analogue Input Deadbands, Object 34, variations 1 through 3, are supported
Floating Point Analogue Output Status and Output Block Objects 40 and 41 are supported
Sequential file transfer, Object 70, variations 2 through 7, are supported
Device Attribute Object 0 is supported
Maximum Data Link Frame Size (octets): Transmitted: 292
Received: 292
Maximum Application Fragment Size (octets) Transmitted: Configurable (100 to 2048). Default 2048
Received: 249
Maximum Data Link Retries: Fixed at 2
Maximum Application Layer Retries: None
Requires Data Link Layer Confirmation: Configurable to Never or Always
Requires Application Layer Confirmation: When reporting event data (Slave devices only)
When sending multi-fragment responses (Slave devices only)
Timeouts while waiting for:
Data Link Confirm: Configurable
Complete Application Fragment: None
Application Confirm: Configurable
Complete Application Response: None
Others:
Data Link Confirm Timeout: Configurable from 0 (Disabled) to 120s, default 10s.
Application Confirm Timeout: Configurable from 1 to 120s, default 2s.
Select/Operate Arm Timeout: Configurable from 1 to 10s, default 10s.
Need Time Interval (Set IIN1-4): Configurable from 1 to 30, default 10min.
Application File Timeout 60 s
Analog Change Event Scan Period: Fixed at 0.5s
Counter Change Event Scan Period Fixed at 0.5s
Frozen Counter Change Event Scan Period Fixed at 1s
Maximum Delay Measurement Error: 2.5 ms
Time Base Drift Over a 10-minute Interval: 7 ms
Sends/Executes Control Operations:
Write Binary Outputs: Never
Select/Operate: Always
386 P841B-TM-EN-1.1
DNP 3.0
Direct Operate: Always
Direct Operate - No Ack: Always
Count > 1 Never
Pulse On Always
Pulse Off Sometimes
Latch On Always
Latch Off Always
Queue Never
Clear Queue Never
Note: Paired Control points will accept Pulse On/Trip and Pulse On/Close, but only single point will accept the Pulse Off control command.
Reports Binary Input Change Events when no specific variation Configurable to send one or the other
requested:
Reports time-tagged Binary Input Change Events when no specific Binary input change with time
variation requested:
Sends Unsolicited Responses: Never
Sends Static Data in Unsolicited Responses: Never
No other options are permitted
Default Counter Object/Variation: Configurable, Point-by-point list attached
Default object: 20
Default variation: 1
Counters Roll Over at: 32 bits
Sends multi-fragment responses: Yes
Sequential File Transfer Support:
Append File Mode No
Custom Status Code Strings No
Permissions Field Yes
File Events Assigned to Class No
File Events Send Immediately Yes
Multiple Blocks in a Fragment No
Max Number of Files Open 1
7.3.8.2 DNP3 IMPLEMENTATION TABLE

The implementation table provides a list of objects, variations and control codes supported by the device:
Request Response
Object
(Library will parse) (Library will respond with)
Object Variation Function Codes (dec) Qualifier Codes Function Codes Qualifier Codes (hex)
Description (dec)
Number Number (hex)
1 0 Binary Input (Variation 0 is used to 1 (read) 00, 01 (start-stop)
request default variation) 22 (assign class) 06 (no range, or all)
07, 08 (limited qty)
17, 27, 28 (index)
1 1 Binary Input 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
(default - see 06 (no range, or all) 17, 28 (index - see note 2)
note 1) 07, 08 (limited qty)
17, 27, 28 (index)
1 2 Binary Input with Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
06 (no range, or all) 17, 28 (index - see note 2)
17, 28 (index)
P841B-TM-EN-1.1 387
Request Response
Object
Description (dec)
Number Number (hex)
2 0 Binary Input Change - Any 1 (read) 06 (no range, or all)
Variation 07, 08 (limited qty)
2 1 Binary Input Change without Time 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
2 2 Binary Input Change with Time 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
10 0 Binary Output Status - Any 1 (read) 00, 01 (start-stop)
Variation 06 (no range, or all)
17, 27, 28 (index)
10 2 Binary Output Status 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 28 (index)
12 1 Control Relay Output Block 3 (select) 17, 28 (index) 129 response echo of request
4 (operate)
5 (direct op)
6 (dir. op, noack)
20 0 Binary Counter - Any Variation 1 (read) 00, 01 (start-stop)
22 (assign class) 06 (no range, or all)
17, 27, 28 (index)
7 (freeze) 00, 01 (start-stop)
8 (freeze noack) 06 (no range, or all)
9 (freeze clear) 07, 08 (limited qty)
10 (frz. cl. Noack)
20 1 32-Bit Binary Counter with Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
20 2 16-Bit Binary Counter with Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
20 5 32-Bit Binary Counter without Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
20 6 16-Bit Binary Counter without Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
21 0 Frozen Counter - Any Variation 1 (read) 00, 01 (start-stop)
06 (no range, or all)
17, 27, 28 (index)
21 1 32-Bit Frozen Counter with Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
21 2 16-Bit Frozen Counter with Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
21 5 32-Bit Frozen Counter with Time of 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
Freeze 06 (no range, or all) 17, 28 (index - see note 1)
17, 27, 28 (index)
21 6 16-Bit Frozen Counter with Time of 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
Freeze 06 (no range, or all) 17, 28 17, 28 (index - see note 1)
17, 27, 28 (index)
21 9 32-Bit Frozen Counter without Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
388 P841B-TM-EN-1.1
Request Response
Object
Description (dec)
Number Number (hex)
21 10 16-Bit Frozen Counter without Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
`22 0 Counter Change Event - Any 1 (read) 06 (no range, or all)
22 1 32-Bit Counter Change Event 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
(default - see without Time 07, 08 (limited qty)
note 1)
22 2 16-Bit Counter Change Event 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
without Time 07, 08 (limited qty)
22 5 32-Bit Counter Change Event with 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
Time 07, 08 (limited qty)
22 6 16-Bit Counter Change Event with 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
23 0 Frozen Counter Event (Variation 0 1 (read) 06 (no range, or all)
is used to request default 07, 08 (limited qty)
variation)
23 1 32-Bit Frozen Counter Event 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
(default - see 07, 08 (limited qty)
note 1)
23 2 16-Bit Frozen Counter Event 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
23 5 32-Bit Frozen Counter Event with 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
23 6 16-Bit Frozen Counter Event with 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
30 0 Analog Input - Any Variation 1 (read) 00, 01 (start-stop)
17, 27, 28 (index)
30 1 32-Bit Analog Input 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
30 2 16-Bit Analog Input 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
30 3 32-Bit Analog Input without Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
30 4 16-Bit Analog Input without Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
30 5 Short floating point 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
32 0 Analog Change Event - Any 1 (read) 06 (no range, or all)
32 1 32-Bit Analog Change Event 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
(default - see without Time 07, 08 (limited qty)
note 1)
32 2 16-Bit Analog Change Event 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
without Time 07, 08 (limited qty)
32 3 32-Bit Analog Change Event with 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
32 4 16-Bit Analog Change Event with 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
32 5 Short floating point Analog 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
Change Event without Time 07, 08 (limited qty)
32 7 Short floating point Analog 1 (read) 06 (no range, or all) 129 response 17, 28 (index)
Change Event with Time 07, 08 (limited qty)
P841B-TM-EN-1.1 389
Request Response
Object
Description (dec)
Number Number (hex)
34 0 Analog Input Deadband (Variation 1 (read) 00, 01 (start-stop)
0 is used to request default 06 (no range, or all)
variation) 07, 08 (limited qty)
17, 27, 28 (index)
34 1 16 Bit Analog Input Deadband 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
2 (write) 00, 01 (start-stop)
17, 27, 28 (index)
34 2 32 Bit Analog Input Deadband 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
17, 27, 28 (index)
34 3 Short Floating Point Analog Input 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
Deadband 06 (no range, or all) 17, 28 (index - see note 2)
17, 27, 28 (index)
17, 27, 28 (index)
40 0 Analog Output Status (Variation 0 1 (read) 00, 01 (start-stop)
is used to request default 06 (no range, or all)
variation) 07, 08 (limited qty)
17, 27, 28 (index)
40 1 32-Bit Analog Output Status 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
40 2 16-Bit Analog Output Status 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
17, 27, 28 (index)
40 3 Short Floating Point Analog 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
Output Status 06 (no range, or all) 17, 28 (index - see note 2)
17, 27, 28 (index)
41 1 32-Bit Analog Output Block 3 (select) 17, 28 (index) 129 response echo of request
4 (operate) 27 (index)
5 (direct op)
6 (dir. op, noack)
41 2 16-Bit Analog Output Block 3 (select) 17, 28 (index) 129 response echo of request
4 (operate) 27 (index)
5 (direct op)
6 (dir. op, noack)
41 3 Short Floating Point Analog 3 (select) 17, 27, 28 (index) 129 response echo of request
Output Block 4 (operate)
5 (direct op)
6 (dir. op, noack)
1 1 (read) 07 (limited qty = 1) 129 response 07 (limited qty = 1)
50 (default - see Time and Date
note 1)
2 (write) 07 (limited qty = 1)
60 0 Not defined
60 1 Class 0 Data 1 (read) 06 (no range, or all)
390 P841B-TM-EN-1.1
Request Response
Object
Description (dec)
Number Number (hex)
70 0 File Event - Any Variation 1 (read) 06 (no range, or all)
70 2 File Authentication 29 (authenticate) 5b (free-format) 129 response 5B (free-format)
70 3 File Command 25 (open) 5b (free-format)
27 (delete)
70 4 File Command Status 26 (close) 5b (free-format) 129 response 5B (free-format)
30 (abort)
70 5 File Transfer 1 (read) 5b (free-format) 129 response 5B (free-format)
70 6 File Transfer Status 129 response 5B (free-format)
70 7 File Descriptor 28 (get file info) 5b (free-format) 129 response 5B (free-format)
80 1 Internal Indications 1 (read) 00, 01 (start-stop) 129 response 00, 01 (start-stop)
No Object (function code only) 13 (cold restart)
No Object (function code only) 14 (warm restart)
No Object (function code only) 23 (delay meas.)
Note:
A Default variation refers to the variation responded to when variation 0 is requested and/or in class 0, 1, 2, or 3 scans.
Note:
For static (non-change-event) objects, qualifiers 17 or 28 are only responded to when a request is sent with qualifiers 17 or
28, respectively. Otherwise, static object requests sent with qualifiers 00, 01, 06, 07, or 08, will be responded to with qualifiers
00 or 01. For change-event objects, qualifiers 17 or 28 are always responded to.
7.3.8.3 DNP3 INTERNAL INDICATIONS

The following table lists the DNP3.0 Internal Indications (IIN) and identifies those that are supported by the device.
The IIN form an information element used to convey the internal states and diagnostic results of a device. This
information can be used by a receiving station to perform error recovery or other suitable functions. The IIN is a
two-octet field that follows the function code in all responses from the device. When a request cannot be
processed due to formatting errors or the requested data is not available, the IIN is always returned with the
appropriate bits set.
Bit Indication Description Supported
Octet 1
Set when a request is received with the destination address of the all stations
address (6553510). It is cleared after the next response (even if a response to a
0 All stations message received global request is required). Yes
This IIN is used to let the master station know that a "broadcast" message was
received by the relay.
P841B-TM-EN-1.1 391
Bit Indication Description Supported

Set when data that has been configured as Class 1 data is ready to be sent to
the master.
1 Class 1 data available Yes
The master station should request this class data from the relay when this bit
is set in a response.
the master.
the master.
The relay requires time synchronization from the master station (using the
Time and Date object).
4 Time-synchronization required Yes
This IIN is cleared once the time has been synchronized. It can also be cleared
by explicitly writing a 0 into this bit of the Internal Indication object.
Set when some or all of the relays digital output points (Object 10/12) are in the
Local state. That is, the relays control outputs are NOT accessible through the
5 Local DNP protocol. No
This IIN is clear when the relay is in the Remote state. That is, the relays control
outputs are fully accessible through the DNP protocol.
Set when an abnormal condition exists in the relay. This IIN is only used when
6 Device in trouble the state cannot be described by a combination of one or more of the other IIN No
bits.
Set when the device software application restarts. This IIN is cleared when the
7 Device restart master station explicitly writes a 0 into this bit of the Internal Indications Yes
object.
Octet 2
0 Function code not implemented The received function code is not implemented within the relay. Yes
The relay does not have the specified objects or there are no objects assigned
to the requested class.
1 Requested object(s) unknown Yes
This IIN should be used for debugging purposes and usually indicates a
mismatch in device profiles or configuration problems.
Parameters in the qualifier, range or data fields are not valid or out of range.
This is a 'catch-all' for application request formatting errors. It should only be
2 Out of range Yes
used for debugging purposes. This IIN usually indicates configuration
problems.
Event buffer(s), or other application buffers, have overflowed. The master
station should attempt to recover as much data as possible and indicate to the
3 Buffer overflow Yes
user that there may be lost data. The appropriate error recovery procedures
should be initiated by the user.
The received request was understood but the requested operation is already
4 Already executing
executing.
Set to indicate that the current configuration in the relay is corrupt. The
5 Bad configuration Yes
master station may download another configuration to the relay.
6 Reserved Always returned as zero.
7 Reserved Always returned as zero.
7.3.8.4 DNP3 RESPONSE STATUS CODES

When the device processes Control Relay Output Block (Object 12) requests, it returns a set of status codes; one for
each point contained within the original request. The complete list of codes appears in the following table:
392 P841B-TM-EN-1.1
Code Number Identifier Name Description

0 Success The received request has been accepted, initiated, or queued.
The request has not been accepted because the ‘operate’ message was received after the
1 Timeout arm timer (Select Before Operate) timed out.
The arm timer was started when the select operation for the same point was received.
The request has not been accepted because no previous matching ‘select’ request exists. (An
2 No select ‘operate’ message was sent to activate an output that was not previously armed with a
matching ‘select’ message).
The request has not been accepted because there were formatting errors in the control
3 Format error
request (‘select’, ‘operate’, or ‘direct operate’).
The request has not been accepted because a control operation is not supported for this
4 Not supported
point.
The request has not been accepted because the control queue is full or the point is already
5 Already active
active.
6 Hardware error The request has not been accepted because of control hardware problems.
7 Local The request has not been accepted because local access is in progress.
8 Too many operations The request has not been accepted because too many operations have been requested.
9 Not authorized The request has not been accepted because of insufficient authorization.
127 Undefined The request not been accepted because of some other undefined reason.
Note:
Code numbers 10 through to 126 are reserved for future use.
7.3.9 DNP3 CONFIGURATION

communication protocol – in this case DNP3.0.
COMMUNICATIONS
RP1 Protocol
DNP3.0
4. Move down to the next cell (RP1 Address). This cell controls the DNP3.0 address of the IED. Up to 32 IEDs can
be connected to one spur, therefore it is necessary for each IED to have a unique address so that messages
from the master control station are accepted by only one IED. DNP3.0 uses a decimal number between 1
and 65519 for the Relay Address. It is important that no two IEDs have the same address.
COMMUNICATIONS
RP1 Address
1
5. Move down to the next cell (RP1 Baud Rate). This cell controls the baud rate to be used. Six baud rates are
supported by the IED 1200 bps, 2400 bps, 4800 bps, 9600 bps, 19200 bps and 38400 bps. Make sure that
the baud rate selected on the IED is the same as that set on the master station.
COMMUNICATIONS
RP1 Baud rate
9600 bits/s
P841B-TM-EN-1.1 393
6. Move down to the next cell (RP1 Parity). This cell controls the parity format used in the data frames. The
parity can be set to be one of None, Odd or Even. Make sure that the parity format selected on the IED is
the same as that set on the master station.
COMMUNICATIONS
RP1 Parity
None
COMMUNICATIONS
RP1 PhysicalLink
Copper
8. Move down to the next cell (RP1 Time Sync). This cell affects the time synchronisation request from the
master by the IED. It can be set to enabled or disabled. If enabled it allows the DNP3.0 master to
synchronise the time on the IED.
COMMUNICATIONS
RP1 Time Sync
Enabled
7.3.9.1 DNP3 CONFIGURATOR

A PC support package for DNP3.0 is available as part of the supplied settings application software (MiCOM S1 Agile)
to allow configuration of the device's DNP3.0 response. The configuration data is uploaded from the device to the
PC in a block of compressed format data and downloaded in a similar manner after modification. The new DNP3.0
configuration takes effect after the download is complete. To restore the default configuration at any time, from
the CONFIGURATION column, select the Restore Defaults cell then select All Settings.
In MiCOM S1 Agile, the DNP3.0 data is shown in three main folders, one folder each for the point configuration,
integer scaling and default variation (data format). The point configuration also includes screens for binary inputs,
binary outputs, counters and analogue input configuration.
If the device supports DNP Over Ethernet, the configuration related settings are done in the folder DNP Over
Ethernet.
7.4 IEC 61850

This section describes how the IEC 61850 standard is applied to General Electric products. It is not a description of
the standard itself. The level at which this section is written assumes that the reader is already familiar with the
IEC 61850 standard.
IEC 61850 is the international standard for Ethernet-based communication in substations. It enables integration of
all protection, control, measurement and monitoring functions within a substation, and additionally provides the
means for interlocking and inter-tripping. It combines the convenience of Ethernet with the security that is so
essential in substations today.
7.4.1 BENEFITS OF IEC 61850

The standard provides:
● Standardised models for IEDs and other equipment within the substation
● Standardised communication services (the methods used to access and exchange data)
● Standardised formats for configuration files
● Peer-to-peer communication
394 P841B-TM-EN-1.1
The standard adheres to the requirements laid out by the ISO OSI model and therefore provides complete vendor
interoperability and flexibility on the transmission types and protocols used. This includes mapping of data onto
Ethernet, which is becoming more and more widely used in substations, in favour of RS485. Using Ethernet in the
substation offers many advantages, most significantly including:
● Ethernet allows high-speed data rates (currently 100 Mbps, rather than tens of kbps or less used by most
serial protocols)
● Ethernet provides the possibility to have multiple clients
● Ethernet is an open standard in every-day use
● There is a wide range of Ethernet-compatible products that may be used to supplement the LAN installation
(hubs, bridges, switches)
7.4.2 IEC 61850 INTEROPERABILITY

A major benefit of IEC 61850 is interoperability. IEC 61850 standardizes the data model of substation IEDs, which
allows interoperability between products from multiple vendors.
An IEC 61850-compliant device may be interoperable, but this does not mean it is interchangeable. You cannot
simply replace a product from one vendor with that of another without reconfiguration. However the terminology
is pre-defined and anyone with prior knowledge of IEC 61850 should be able to integrate a new device very quickly
without having to map all of the new data. IEC 61850 brings improved substation communications and
interoperability to the end user, at a lower cost.
7.4.3 THE IEC 61850 DATA MODEL

The data model of any IEC 61850 IED can be viewed as a hierarchy of information, whose nomenclature and
categorization is defined and standardized in the IEC 61850 specification.
Data Attributes
stVal q t PhA PhB PhC
Data Objects
Pos A
Logical Nodes : 1 to n
LN1: XCBR LN2: MMXU
Logical Device : IEDs 1 to n
Physical Device (network address)
V01008
Figure 174: Data model layers in IEC 61850
The levels of this hierarchy can be described as follows:
Data Frame format

Layer Description
Identifies the actual IED within a system. Typically the device’s name or IP address can be used (for
Physical Device
example Feeder_1 or 10.0.0.2.
P841B-TM-EN-1.1 395
Layer Description
Identifies groups of related Logical Nodes within the Physical Device. For the MiCOM IEDs, 5 Logical
Logical Device
Devices exist: Control, Measurements, Protection, Records, System.
Identifies the major functional areas within the IEC 61850 data model. Either 3 or 6 characters are
used as a prefix to define the functional group (wrapper) while the actual functionality is identified by
Wrapper/Logical Node Instance a 4 character Logical Node name suffixed by an instance number.
For example, XCBR1 (circuit breaker), MMXU1 (measurements), FrqPTOF2 (overfrequency protection,
stage 2).
This next layer is used to identify the type of data you will be presented with. For example, Pos
Data Object
(position) of Logical Node type XCBR.
This is the actual data (measurement value, status, description, etc.). For example, stVal (status value)
Data Attribute
indicating actual position of circuit breaker for Data Object type Pos of Logical Node type XCBR.
7.4.4 IEC 61850 IN MICOM IEDS

IEC 61850 is implemented by use of a separate Ethernet card. This Ethernet card manages the majority of the
IEC 61850 implementation and data transfer to avoid any impact on the performance of the protection functions.
To communicate with an IEC 61850 IED on Ethernet, it is necessary only to know its IP address. This can then be
configured into either:
● An IEC 61850 client (or master), for example a bay computer (MiCOM C264)
● An HMI
● An MMS browser, with which the full data model can be retrieved from the IED, without any prior knowledge
of the IED
The IEC 61850 compatible interface standard provides capability for the following:
● Read access to measurements
● Refresh of all measurements at the rate of once per second.
● Generation of non-buffered reports on change of status or measurement
● SNTP time synchronization over an Ethernet link. (This is used to synchronize the IED's internal real time
clock.
● GOOSE peer-to-peer communication
● Disturbance record extraction by file transfer. The record is extracted as an ASCII format COMTRADE file
● Controls (Direct and Select Before Operate)
Note:
Setting changes are not supported in the current IEC 61850 implementation. Currently these setting changes are carried out
using the settings application software.
7.4.5 IEC 61850 DATA MODEL IMPLEMENTATION

The data model naming adopted in the IEDs has been standardised for consistency. Therefore the Logical Nodes
are allocated to one of the five Logical Devices, as appropriate.
The data model is described in the Model Implementation Conformance Statement (MICS) document, which is
available as a separate document.
7.4.6 IEC 61850 COMMUNICATION SERVICES IMPLEMENTATION

The IEC 61850 communication services which are implemented in the IEDs are described in the Protocol
Implementation Conformance Statement (PICS) document, which is available as a separate document.
396 P841B-TM-EN-1.1
7.4.7 IEC 61850 PEER-TO-PEER (GOOSE) COMMUNICATIONS

The implementation of IEC 61850 Generic Object Oriented Substation Event (GOOSE) enables faster
communication between IEDs offering the possibility for a fast and reliable system-wide distribution of input and
output data values. The GOOSE model uses multicast services to deliver event information. Multicast messaging
means that messages are sent to selected devices on the network. The receiving devices can specifically accept
frames from certain devices and discard frames from the other devices. It is also known as a publisher-subscriber
system. When a device detects a change in one of its monitored status points it publishes a new message. Any
device that is interested in the information subscribes to the data it contains.
7.4.8 MAPPING GOOSE MESSAGES TO VIRTUAL INPUTS

Each GOOSE signal contained in a subscribed GOOSE message can be mapped to any of the virtual inputs within
the PSL. The virtual inputs allow the mapping to internal logic functions for protection control, directly to output
contacts or LEDs for monitoring.
An IED can subscribe to all GOOSE messages but only the following data types can be decoded and mapped to a
virtual input:
● BOOLEAN
● BSTR2
● INT16
● INT32
● INT8
● UINT16
● UINT32
● UINT8
7.4.8.1 IEC 61850 GOOSE CONFIGURATION

All GOOSE configuration is performed using the IEC 61850 Configurator tool available in the MiCOM S1 Agile
software application.
All GOOSE publishing configuration can be found under the GOOSE Publishing tab in the configuration editor
window. All GOOSE subscription configuration parameters are under the External Binding tab in the configuration
editor window.
Settings to enable GOOSE signalling and to apply Test Mode are available using the HMI.
7.4.9 ETHERNET FUNCTIONALITY

IEC 61850 Associations are unique and made between the client and server. If Ethernet connectivity is lost for any
reason, the associations are lost, and will need to be re-established by the client. The IED has a TCP_KEEPALIVE
function to monitor each association, and terminate any which are no longer active.
The IED allows the re-establishment of associations without disruption of its operation, even after its power has
been removed. As the IED acts as a server in this process, the client must request the association. Uncommitted
settings are cancelled when power is lost, and reports requested by connected clients are reset. The client must
re-enable these when it next creates the new association to the IED.
7.4.10 IEC 61850 CONFIGURATION

You cannot configure the device for IEC 61850 edition 1 using the HMI panel on the product. For this you must use
the IEC 61850 Configurator, which is part of the settings application software.
IEC 61850 allows IEDs to be directly configured from a configuration file. The IED’s system configuration
capabilities are determined from an IED Capability Description file (ICD), supplied with the product. By using ICD
P841B-TM-EN-1.1 397
files from the products to be installed, you can design, configure and test (using simulation tools), a substation’s
entire protection scheme before the products are installed into the substation.
To help with this process, the settings application software provides an IEC 61850 Configurator tool, which allows
the pre-configured IEC 61850 configuration file to be imported and transferred to the IED. As well as this, you can
manually create configuration files for all products, based on their original IED capability description (ICD file).
Other features include:
● The extraction of configuration data for viewing and editing.
● A sophisticated error checking sequence to validate the configuration data before sending to the IED.
Note:
Some configuration data is available in the IEC61850 CONFIG. column, allowing read-only access to basic configuration data.
7.4.10.1 IEC 61850 CONFIGURATION BANKS

There are two configuration banks:
● Active Configuration Bank
● Inactive Configuration Bank
Any new configuration sent to the IED is automatically stored in the inactive configuration bank, therefore not
immediately affecting the current configuration.
Following an upgrade, the IEC 61850 Configurator tool can be used to transmit a command, which authorises
activation of the new configuration contained in the inactive configuration bank. This is done by switching the
active and inactive configuration banks. The capability of switching the configuration banks is also available using
the IEC61850 CONFIG. column of the HMI.
The SCL Name and Revision attributes of both configuration banks are available in the IEC61850 CONFIG. column
of the HMI.
7.4.10.2 IEC 61850 NETWORK CONNECTIVITY

Configuration of the IP parameters and SNTP (Simple Network Time Protocol) time synchronisation parameters is
performed by the IEC 61850 Configurator tool. If these parameters are not available using an SCL (Substation
Configuration Language) file, they must be configured manually.
Every IP address on the Local Area Network must be unique. Duplicate IP addresses result in conflict and must be
avoided. Most IEDs check for a conflict on every IP configuration change and at power up and they raise an alarm
if an IP conflict is detected.
The IED can be configured to accept data from other networks using the Gateway setting. If multiple networks are
used, the IP addresses must be unique across networks.
398 P841B-TM-EN-1.1
8 READ ONLY MODE

With IEC 61850 and Ethernet/Internet communication capabilities, security has become an important issue. For
this reason, all relevant General Electric IEDs have been adapted to comply with the latest cyber-security
standards.
In addition to this, a facility is provided which allows you to enable or disable the communication interfaces. This
feature is available for products using Courier, IEC 60870-5-103, or IEC 61850.
8.1 IEC 60870-5-103 PROTOCOL BLOCKING

If Read-Only Mode is enabled for RP1 or RP2 with IEC 60870-5-103, the following commands are blocked at the
interface:
● Write parameters (=change setting) (private ASDUs)
● General Commands (ASDU20), namely:
○ INF16 auto-recloser on/off
○ INF19 LED reset
○ Private INFs (for example: CB open/close, Control Inputs)
The following commands are still allowed:
● Poll Class 1 (Read spontaneous events)
● Poll Class 2 (Read measurands)
● GI sequence (ASDU7 'Start GI', Poll Class 1)
● Transmission of Disturbance Records sequence (ASDU24, ASDU25, Poll Class 1)
● Time Synchronisation (ASDU6)
● General Commands (ASDU20), namely:
○ INF23 activate characteristic 1
Note:
For IEC 60870-5-103, Read Only Mode function is different from the existing Command block feature.
8.2 COURIER PROTOCOL BLOCKING

If Read-Only Mode is enabled for RP1 or RP2 with Courier, the following commands are blocked at the interface:
● Write settings
● All controls, including:Reset Indication (Trip LED)
○ Operate Control Inputs
○ CB operations
○ Auto-reclose operations
○ Reset demands
○ Clear event/fault/maintenance/disturbance records
○ Test LEDs & contacts
P841B-TM-EN-1.1 399

● Read settings, statuses, measurands
● Read records (event, fault, disturbance)
● Time Synchronisation
● Change active setting group
8.3 IEC 61850 PROTOCOL BLOCKING

If Read-Only Mode is enabled for the Ethernet interfacing with IEC 61850, the following commands are blocked at
the interface:
● All controls, including:
○ Enable/disable protection
○ Operate Control Inputs
○ CB operations (Close/Trip, Lock)
○ Reset LEDs
● Read statuses, measurands
● Generate reports
● Extract disturbance records
● Time synchronisation
● Change active setting group
8.4 READ-ONLY SETTINGS

The following settings are available for enabling or disabling Read Only Mode.
● RP1 Read Only
● RP2 Read Only (only for products that have RP2)
● NIC Read Only (where Ethernet is available)
8.5 READ-ONLY DDB SIGNALS

The remote read only mode is also available in the PSL using three dedicated DDB signals:
● RP1 Read Only
● RP2 Read Only (only for products that have RP2)
● NIC Read Only (where Ethernet is available)
Using the PSL, these signals can be activated by opto-inputs, Control Inputs and function keys if required.
400 P841B-TM-EN-1.1
9 TIME SYNCHRONISATION
In modern protection schemes it is necessary to synchronise the IED's real time clock so that events from different
devices can be time stamped and placed in chronological order. This is achieved in various ways depending on the
chosen options and communication protocols.
● Using the IRIG-B input (if fitted)
● Using the SNTP time protocol (for Ethernet IEC 61850 versions + DNP3 OE)
● By using the time synchronisation functionality inherent in the data protocols
9.1 DEMODULATED IRIG-B

IRIG stands for Inter Range Instrumentation Group, which is a standards body responsible for standardising
different time code formats. There are several different formats starting with IRIG-A, followed by IRIG-B and so on.
The letter after the "IRIG" specifies the resolution of the time signal in pulses per second (PPS). IRIG-B, the one which
we use has a resolution of 100 PPS. IRIG-B is used when accurate time-stamping is required.
The following diagram shows a typical GPS time-synchronised substation application. The satellite RF signal is
picked up by a satellite dish and passed on to receiver. The receiver receives the signal and converts it into time
signal suitable for the substation network. IEDs in the substation use this signal to govern their internal clocks and
event recorders.
GPS satellite
GPS time signal
IRIG-B
Satellite dish Receiver IED IED IED
V01040
Figure 175: GPS Satellite timing signal
The IRIG-B time code signal is a sequence of one second time frames. Each frame is split up into ten 100 mS slots
as follows:
● Time-slot 1: Seconds
● Time-slot 2: Minutes
● Time-slot 3: Hours
● Time-slot 4: Days
● Time-slot 5 and 6: Control functions
● Time-slots 7 to 10: Straight binary time of day
P841B-TM-EN-1.1 401
The first four time-slots define the time in BCD (Binary Coded Decimal). Time-slots 5 and 6 are used for control
functions, which control deletion commands and allow different data groupings within the synchronisation strings.
Time-slots 7-10 define the time in SBS (Straight Binary Second of day).
9.1.1 IRIG-B IMPLEMENTATION

Depending on the chosen hardware options, the product can be equipped with an IRIG-B input for time
synchronisation purposes. The IRIG-B interface is implemented either on a dedicated card, or together with other
communication functionality such as Ethernet. The IRIG-B connection is presented by a connector is a BNC
connector. IRIG-B signals are usually presented as an RF-modulated signal. There are two types of input to our
IRIG-B boards: demodulated or modulated. A board that accepts a demodulated input is used where the IRIG-B
signal has already been demodulated by another device before being fed to the IED. A board that accepts a
modulated input has an on-board demodulator.
To set the device to use IRIG-B, use the setting IRIG-B Sync cell in the DATE AND TIME column.
The IRIG-B status can be viewed in the IRIG-B Status cell in the DATE AND TIME column.
9.2 SNTP
SNTP is used to synchronise the clocks of computer systems over packet-switched, variable-latency data
networks, such as IP. SNTP can be used as the time synchronisation method for models using IEC 61850 over
Ethernet.
The device is synchronised by the main SNTP server. This is achieved by entering the IP address of the SNTP server
into the IED using the IEC 61850 Configurator software described in the settings application software manual. A
second server is also configured with a different IP address for backup purposes.
This function issues an alarm when there is a loss of time synchronisation on the SNTP server. This could be
because there is no response or no valid clock signal.
The HMI menu does not contain any configurable settings relating to SNTP, as the only way to configure it is using
the IEC 61850 Configurator. However it is possible to view some parameters in the COMMUNICATIONS column
under the sub-heading SNTP parameters. Here you can view the SNTP server addresses and the SNTP poll rate in
the cells SNTP Server 1, SNTP Server 2 and SNTP Poll rate respectively.
The SNTP time synchronisation status is displayed in the SNTP Status cell in the DATE AND TIME column.
9.2.1 LOSS OF SNTP SERVER SIGNAL ALARM

This function issues an alarm when there is a loss of time synchronization on the SNTP server. It is issued when the
SNTP sever has not detected a valid time synchronisation response within its 5 second window. This is because
there is no response or no valid clock. The alarm is mapped to IEC 61850.
9.3 TIME SYNCHRONSIATION USING THE COMMUNICATION PROTOCOLS

All communication protocols have in-built time synchronisation mechanisms. If an external time synchronisation
mechanism such as IRIG-B, SNTP, or IEEE 1588 PTP is not used to synchronise the devices, the time synchronisation
mechanism within the relevant serial protocol is used. The real time is usually defined in the master station and
communicated to the relevant IEDs via one of the rear serial ports using the chosen protocol. It is also possible to
define the time locally using settings in the DATE AND TIME column.
The time synchronisation for each protocol is described in the relevant protocol description section.
402 P841B-TM-EN-1.1
CHAPTER 17
CYBER-SECURITY
Chapter 17 - Cyber-Security P841B
404 P841B-TM-EN-1.1
P841B Chapter 17 - Cyber-Security
1 OVERVIEW
In the past, substation networks were traditionally isolated and the protocols and data formats used to transfer
information between devices were often proprietary.
For these reasons, the substation environment was very secure against cyber-attacks. The terms used for this
inherent type of security are:
● Security by isolation (if the substation network is not connected to the outside world, it cannot be accessed
from the outside world).
● Security by obscurity (if the formats and protocols are proprietary, it is very difficult to interpret them).
The increasing sophistication of protection schemes, coupled with the advancement of technology and the desire
for vendor interoperability, has resulted in standardisation of networks and data interchange within substations.
Today, devices within substations use standardised protocols for communication. Furthermore, substations can be
interconnected with open networks, such as the internet or corporate-wide networks, which use standardised
protocols for communication. This introduces a major security risk making the grid vulnerable to cyber-attacks,
which could in turn lead to major electrical outages.
Clearly, there is now a need to secure communication and equipment within substation environments. This
chapter describes the security measures that have been put in place for our range of Intelligent Electronic Devices
(IEDs).
Note:
Cyber-security compatible devices do not enforce NERC compliance, they merely facilitate it. It is the responsibility of the user
to ensure that compliance is adhered to as and when necessary.

Overview 405
The Need for Cyber-Security 406
Standards 407
Cyber-Security Implementation 411
P841B-TM-EN-1.1 405
2 THE NEED FOR CYBER-SECURITY

Cyber-security provides protection against unauthorised disclosure, transfer, modification, or destruction of
information or information systems, whether accidental or intentional. To achieve this, there are several security
requirements:
● Confidentiality (preventing unauthorised access to information)
● Integrity (preventing unauthorised modification)
● Availability / Authentication (preventing the denial of service and assuring authorised access to information)
● Non-repudiation (preventing the denial of an action that took place)
● Traceability / Detection (monitoring and logging of activity to detect intrusion and analyse incidents)
The threats to cyber-security may be unintentional (e.g. natural disasters, human error), or intentional (e.g. cyber-
attacks by hackers).
Good cyber-security can be achieved with a range of measures, such as closing down vulnerability loopholes,
implementing adequate security processes and procedures and providing technology to help achieve this.
Examples of vulnerabilities are:
● Indiscretions by personnel (users keep passwords on their computer)
● Bad practice (users do not change default passwords, or everyone uses the same password to access all
substation equipment)
● Bypassing of controls (users turn off security measures)
● Inadequate technology (substation is not firewalled)
Examples of availability issues are:

● Equipment overload, resulting in reduced or no performance
● Expiry of a certificate preventing access to equipment
To help tackle these issues, standards organisations have produced various standards. Compliance with these
standards significantly reduces the threats associated with lack of cyber-security.
406 P841B-TM-EN-1.1
3 STANDARDS
There are several standards, which apply to substation cyber-security. The standards currently applicable to
General Electric IEDs are NERC and IEEE1686.
Standard Country Description
NERC CIP (North American Electric Reliability
USA Framework for the protection of the grid critical Cyber Assets
Corporation)
BDEW (German Association of Energy and Water Requirements for Secure Control and Telecommunication
Germany
Industries) Systems
ICS oriented then Relevant for EPU completing existing standard
ANSI ISA 99 USA
and identifying new topics such as patch management
International Standard for substation IED cyber-security
IEEE 1686 International
capabilities
IEC 62351 International Power system data and Comm. protocol
ISO/IEC 27002 International Framework for the protection of the grid critical Cyber Assets
NIST SP800-53 (National Institute of Standards and
USA Complete framework for SCADA SP800-82and ICS cyber-security
Technology)
CPNI Guidelines (Centre for the Protection of National Clear and valuable good practices for Process Control and SCADA
UK
Infrastructure) security
3.1 NERC COMPLIANCE

The North American Electric Reliability Corporation (NERC) created a set of standards for the protection of critical
infrastructure. These are known as the CIP standards (Critical Infrastructure Protection). These were introduced to
ensure the protection of 'Critical Cyber Assets', which control or have an influence on the reliability of North
America’s electricity generation and distribution systems.
These standards have been compulsory in the USA for several years now. Compliance auditing started in June
2007, and utilities face extremely heavy fines for non-compliance.
NERC CIP standards

CIP standard Description
CIP-002-1 Critical Cyber Assets Define and document the Critical Assets and the Critical Cyber Assets
Define and document the Security Management Controls required to protect the
CIP-003-1 Security Management Controls
Critical Cyber Assets
Define and Document Personnel handling and training required protecting Critical
CIP-004-1 Personnel and Training
Cyber Assets
Define and document logical security perimeters where Critical Cyber Assets reside.
CIP-005-1 Electronic Security Define and document measures to control access points and monitor electronic
access
Define and document Physical Security Perimeters within which Critical Cyber Assets
CIP-006-1 Physical Security
reside
Define and document system test procedures, account and password management,
CIP-007-1 Systems Security Management security patch management, system vulnerability, system logging, change control
and configuration required for all Critical Cyber Assets
Define and document procedures necessary when Cyber-security Incidents relating
CIP-008-1 Incident Reporting and Response Planning
to Critical Cyber Assets are identified
CIP-009-1 Recovery Plans Define and document Recovery plans for Critical Cyber Assets
P841B-TM-EN-1.1 407
3.1.1 CIP 002

CIP 002 concerns itself with the identification of:
● Critical assets, such as overhead lines and transformers
● Critical cyber assets, such as IEDs that use routable protocols to communicate outside or inside the
Electronic Security Perimeter; or are accessible by dial-up
Power utility responsibilities: General Electric's contribution:

We can help the power utilities to create this asset register automatically.
Create the list of the assets
We can provide audits to list the Cyber assets
3.1.2 CIP 003

CIP 003 requires the implementation of a cyber-security policy, with associated documentation, which
demonstrates the management’s commitment and ability to secure its Critical Cyber Assets.
The standard also requires change control practices whereby all entity or vendor-related changes to hardware
and software components are documented and maintained.

We can help the power utilities to have access control to its critical assets by
providing centralized Access control.
To create a Cyber-security Policy
We can help the customer with its change control by providing a section in the
documentation where it describes changes affecting the hardware and software.
3.1.3 CIP 004

CIP 004 requires that personnel with authorized cyber access or authorized physical access to Critical Cyber
Assets, (including contractors and service vendors), have an appropriate level of training.

To provide appropriate training of its personnel We can provide cyber-security training
3.1.4 CIP 005

CIP 005 requires the establishment of an Electronic Security Perimeter (ESP), which provides:
● The disabling of ports and services that are not required
● Permanent monitoring and access to logs (24x7x365)
● Vulnerability Assessments (yearly at a minimum)
● Documentation of Network Changes

To monitor access to the ESP
To disable all ports not used in the IED
To perform the vulnerability assessments
To monitor and record all access to the IED
To document network changes
3.1.5 CIP 006

CIP 006 states that Physical Security controls, providing perimeter monitoring and logging along with robust
access controls, must be implemented and documented. All cyber assets used for Physical Security are considered
critical and should be treated as such:
408 P841B-TM-EN-1.1

Provide physical security controls and perimeter
monitoring.
General Electric cannot provide additional help with this aspect.
Ensure that people who have access to critical cyber
assets don’t have criminal records.
3.1.6 CIP 007

CIP 007 covers the following points:
● Test procedures
● Ports and services
● Security patch management
● Antivirus
● Account management
● Monitoring
● An annual vulnerability assessment should be performed

Test procedures, we can provide advice and help on testing.
Ports and services, our devices can disable unused ports and services
To provide an incident response team and have Security patch management, we can provide assistance
appropriate processes in place Antivirus, we can provide advise and assistance
Account management, we can provide advice and assistance
Monitoring, our equipment monitors and logs access
3.1.7 CIP 008

CIP 008 requires that an incident response plan be developed, including the definition of an incident response
team, their responsibilities and associated procedures.

To provide an incident response team and have
General Electric cannot provide additional help with this aspect.
appropriate processes in place.
3.1.8 CIP 009

CIP 009 states that a disaster recovery plan should be created and tested with annual drills.

To provide guidelines on recovery plans and backup/restore
To implement a recovery plan
documentation
3.2 IEEE 1686-2007

IEEE 1686-2007 is an IEEE Standard for substation IEDs' cyber-security capabilities. It proposes practical and
achievable mechanisms to achieve secure operations.
The following features described in this standard apply:
● Passwords are 8 characters long and can contain upper-case, lower-case, numeric and special characters.
● Passwords are never displayed or transmitted to a user.
P841B-TM-EN-1.1 409
● IED functions and features are assigned to different password levels. The assignment is fixed.
● The audit trail is recorded, listing events in the order in which they occur, held in a circular buffer.
● Records contain all defined fields from the standard and record all defined function event types where the
function is supported.
● No password defeat mechanism exists. Instead a secure recovery password scheme is implemented.
● Unused ports (physical and logical) may be disabled.
410 P841B-TM-EN-1.1
4 CYBER-SECURITY IMPLEMENTATION
The General Electric IEDs have always been and will continue to be equipped with state-of-the-art security
measures. Due to the ever-evolving communication technology and new threats to security, this requirement is
not static. Hardware and software security measures are continuously being developed and implemented to
mitigate the associated threats and risks.
This section describes the current implementation of cyber-security. This is valid for the release of platform
software to which this manual pertains. This current cyber-security implementation is known as Cyber-security
Phase 1.
At the IED level, these cyber-security measures have been implemented:
● NERC-compliant default display
● Four-level access
● Enhanced password security
● Password recovery procedure
● Disabling of unused physical and logical ports
● Inactivity timer
● Security events management
External to the IEDs, the following cyber-security measures have been implemented:
● Antivirus
● Security patch management
4.1 NERC-COMPLIANT DISPLAY

For the device to be NERC-compliant, it must provide the option for a NERC-compliant default display. The default
display that is implemented in our cyber-security concept contains a warning that the IED can be accessed by
authorised users. You can change this if required with the User Banner setting in the SECURITY CONFIG column.
ACCESS ONLY FOR

AUTHORISED USERS
HOTKEY
If you try to change the default display from the NERC-compliant one, a further warning is displayed:
DISPLAY NOT NERC

COMPLIANT OK?
The default display navigation map shows how NERC-compliance is achieved with the product's default display
concept.
P841B-TM-EN-1.1 411
NERC compliant
banner
NERC Compliance NERC Compliance

Warning Warning
System Current
Access Level
Measurements
System Voltage
System Frequency
Measurements
System Power
Plant Reference
Measurements
Description Date & Time
V00403
Figure 176: Default display navigation
4.2 FOUR-LEVEL ACCESS

The menu structure contains four levels of access, three of which are password protected.
Password levels
Level Meaning Read Operation Write Operation
SYSTEM DATA column:
Description
Plant Reference
Model Number
Serial Number
S/W Ref.
Access Level
Read Some Password Entry
0 Security Feature
Write Minimal LCD Contrast (UI only)
SECURITY CONFIG column:
User Banner
Attempts Remain
Blk Time Remain
Fallback PW level
Security Code (UI only)
All items writeable at level 0.
Level 1 Password setting
Read All All data and settings are readable.
1 Extract Disturbance Record
Write Few Poll Measurements
Select Event, Main and Fault (upload)
Extract Events (e.g. via MiCOM S1 Studio)
412 P841B-TM-EN-1.1
Level Meaning Read Operation Write Operation

Setting Cells that change visibility (Visible/Invisible).
Setting Values (Primary/Secondary) selector
Commands:
2 Reset Indication
Write Some Poll Measurements
Reset Demand
Reset Statistics
Reset CB Data / counters
Level 2 Password setting
Change all Setting cells
Operations:
Extract and download Setting file.
Extract and download PSL
Extract and download MCL61850 (IEC61850 CONFIG)
Auto-extraction of Disturbance Recorder
Courier/Modbus Accept Event (auto event extraction, e.g. via
3 A2R)
Write All Poll Measurements
Commands:
Change Active Group setting
Close / Open CB
Change Comms device address.
Set Date & Time
Switch MCL banks / Switch Conf. Bank in UI (IEC61850 CONFIG)
Enable / Disable Device ports (in SECURITY CONFIG column)
Level 3 password setting
4.2.1 BLANK PASSWORDS

A blank password is effectively a zero-length password. Through the front panel it is entered by confirming the
password entry without actually entering any password characters. Through a communications port the Courier
and Modbus protocols each have a means of writing a blank password to the IED. A blank password disables the
need for a password at the level that this password is applied.
Blank passwords have a slightly different validation procedure. If a blank password is entered through the front
panel, the following text is displayed, after which the procedure is the same as already described:
BLANK PASSWORD
ENTERED CONFIRM
Blank passwords cannot be configured if the lower level password is not blank.
Blank passwords affect the fall back level after inactivity timeout or logout.
The ‘fallback level’ is the password level adopted by the IED after an inactivity timeout, or after the user logs out.
This will be either the level of the highest-level password that is blank, or level 0 if no passwords are blank.
P841B-TM-EN-1.1 413
4.2.2 PASSWORD RULES

● Default passwords are blank for Level 1 and are AAAA for Levels 2 and 3
● Passwords may be any length between 0 and 8 characters long
● Passwords may or may not be NERC compliant
● Passwords may contain any ASCII character in the range ASCII code 33 (21 Hex) to ASCII code 122 (7A Hex)
inclusive
● Only one password is required for all the IED interfaces
4.2.3 ACCESS LEVEL DDBS

The 'Access level' cell is in the 'System data' column (address 00D0). Also the current level of access for each
interface is available for use in the Programming Scheme Logic (PSL) by mapping to these Digital Data Bus (DDB)
signals:
● HMI Access Lvl 1
● HMI Access Lvl 2
● FPort AccessLvl1
● FPort AccessLvl2
● RPrt1 AccessLvl1
Each pair of DDB signals indicates the access level as follows:

● Level 1 off, Level 2 off = 0
● Level 1 on, Level 2 off = 1
● Level 1 off, Level 2 on = 2
● Level 1 on, Level 2 on = 3
Key:
HMI = Human Machine Interface
FPort = Front Port
RPrt = Rear Port
Lvl = Level
4.3 ENHANCED PASSWORD SECURITY

Cyber-security requires strong passwords and validation for NERC compliance.
4.3.1 PASSWORD STRENGTHENING

NERC compliant passwords have the following requirements:
● At least one upper-case alpha character
● At least one lower-case alpha character
● At least one numeric character
● At least one special character (%,$...)
● At least six characters long
414 P841B-TM-EN-1.1
4.3.2 PASSWORD VALIDATION

The IED checks for NERC compliance. If the password is entered through the front panel, this is briefly displayed on
the LCD.
If the entered password is NERC compliant, the following text is displayed.
NERC COMPLIANT
P/WORD WAS SAVED
If the password entered is not NERC-compliant, the user is required to actively confirm this, in which case the non-
compliance is logged.
If the entered password is not NERC compliant, the following text is displayed:
NERC COMPLIANCE
NOT MET CONFIRM?
On confirmation, the non-compliant password is stored and the following acknowledgement message is displayed
for 2 seconds.
NON-NERC P/WORD
SAVED OK
If the action is cancelled, the password is rejected and the following message is displayed for 2 seconds.
NON-NERC P/WORD
NOT SAVE
If the password is entered through a communications port using Courier or Modbus protocols, the device will store
the password, irrespective of whether it is NERC-compliant or not. It then uses appropriate response codes to
inform the client of the NERC-compliancy status. You can then choose to enter a new NERC-compliant password
or accept the non-NERC compliant password just entered.
4.3.3 PASSWORD BLOCKING

You are locked out temporarily, after a defined number of failed password entry attempts. Each invalid password
entry attempt decrements the 'Attempts Remain' data cell by 1. When the maximum number of attempts has been
reached, access is blocked. If the attempts timer expires, or the correct password is entered before the 'attempt
count' reaches the maximum number, then the 'attempts count' is reset to 0.
An attempt is only counted if the attempted password uses only characters in the valid range, but the attempted
password is not correct (does not match the corresponding password in the IED). Any attempt where one or more
characters of the attempted password are not in the valid range will not be counted.
Once the password entry is blocked, a 'blocking timer' is started. Attempts to access the interface while the
'blocking timer' is running results in an error message, irrespective of whether the correct password is entered or
not. Once the 'blocking timer' has expired, access to the interface is unblocked and the attempts counter is reset to
zero.
P841B-TM-EN-1.1 415
If you try to enter the password while the interface is blocked, the following message is displayed for 2 seconds.
NOT ACCEPTED
ENTRY IS BLOCKED
A similar response occurs if you try to enter the password through a communications port.
The parameters can then be configured using the Attempts Limit, Attempts Timer and Blocking Timer settings in
the SECURITY CONFIG column.
Password blocking configuration

Cell
Setting Units Default Setting Available Setting
col row
Attempts Limit 25 02 3 0 to 3 step 1
Attempts Timer 25 03 Minutes 2 1 to 3 step 1
Blocking Timer 25 04 Minutes 5 1 to 30 step 1
4.4 PASSWORD RECOVERY

If you mislay a device's password, they can be recovered. To obtain the recovery password you must contact the
Contact Centre and supply the Serial Number and its Security Code. The Contact Centre will use these items to
generate a Recovery Password.
The security code is a 16-character string of upper case characters. It is a read-only parameter. The device
generates its own security code randomly. A new code is generated under the following conditions:
● On power up
● Whenever settings are set back to default
● On expiry of validity timer (see below)
● When the recovery password is entered
As soon as the security code is displayed on the LCD, a validity timer is started. This validity timer is set to 72 hours
and is not configurable. This provides enough time for the contact centre to manually generate and send a
recovery password. The Service Level Agreement (SLA) for recovery password generation is one working day, so 72
hours is sufficient time, even allowing for closure of the contact centre over weekends and bank holidays.
To prevent accidental reading of the IED security code, the cell will initially display a warning message:
PRESS ENTER TO
READ SEC. CODE
The security code is displayed on confirmation. The validity timer is then started. The security code can only be
read from the front panel.
4.4.1 ENTRY OF THE RECOVERY PASSWORD

The recovery password is intended for recovery only. It is not a replacement password that can be used
continually. It can only be used once – for password recovery.
Entry of the recovery password causes the IED to reset all passwords back to default. This is all it is designed to do.
After the passwords have been set back to default, it is up to the user to enter new passwords. Each password
should be appropriate for its intended function, ensuring NERC compliance, if required.
416 P841B-TM-EN-1.1
On this action, the following message is displayed:
PASSWORDS HAVE
BEEN SET TO
DEFAULT
The recovery password can be applied through any interface, local or remote. It will achieve the same result
irrespective of which interface it is applied through.
4.4.2 PASSWORD ENCRYPTION

The IED supports encryption for passwords entered remotely. The encryption key can be read from the IED through
a specific cell available only through communication interfaces, not the front panel. Each time the key is read the
IED generates a new key that is valid only for the next password encryption write. Once used, the key is invalidated
and a new key must be read for the next encrypted password write. The encryption mechanism is otherwise
transparent to the user.
4.5 DISABLING PHYSICAL PORTS

It is possible to disable unused physical ports. A level 3 password is needed to perform this action.
To prevent accidental disabling of a port, a warning message is displayed according to whichever port is required
to be disabled. For example if rear port 1 is to be disabled, the following message appears:
REAR PORT 1 TO BE
DISABLED.CONFIRM
The following ports can be disabled, depending on the model.

● Front port (Front Port setting)
● Rear port 1 (Rear Port 1 setting)
● Rear port 2 (Rear Port 2 setting)
● Ethernet port (Ethernet setting)
Note:
It is not possible to disable a port from which the disabling port command originates.
Note:
We do not generally advise disabling the physical Ethernet port.
4.6 DISABLING LOGICAL PORTS

It is possible to disable unused logical ports. A level 3 password is needed to perform this action.
Note:
The port disabling setting cells are not provided in the settings file. It is only possible to do this using the HMI front panel.
P841B-TM-EN-1.1 417
The following protocols can be disabled:

● IEC 61850 (IEC61850 setting)
● DNP3 Over Ethernet (DNP3 OE setting)
● Courier Tunnelling (Courier Tunnel setting)
Note:
If any of these protocols are enabled or disabled, the Ethernet card will reboot.
4.7 SECURITY EVENTS MANAGEMENT

To implement NERC-compliant cyber-security, a range of Event records need to be generated. These log security
issues such as the entry of a non-NERC-compliant password, or the selection of a non-NERC-compliant default
display.
Security event values

Event Value Display
USER LOGGED IN
PASSWORD LEVEL UNLOCKED
ON {int} LEVEL {n}
USER LOGGED OUT
PASSWORD LEVEL RESET
ON {int} LEVEL {n}
P/WORD SET BLANK
PASSWORD SET BLANK
BY {int} LEVEL {p}
P/WORD NOT-NERC
PASSWORD SET NON-COMPLIANT
BY {int} LEVEL {p}
PASSWORD CHANGED
PASSWORD MODIFIED
BY {int} LEVEL {p}
PASSWORD BLOCKED
PASSWORD ENTRY BLOCKED
ON {int}
P/WORD UNBLOCKED
PASSWORD ENTRY UNBLOCKED
ON {int}
INV P/W ENTERED
INVALID PASSWORD ENTERED
ON <int}
P/WORD EXPIRED
PASSWORD EXPIRED
ON {int}
P/W ENT WHEN BLK
PASSWORD ENTERED WHILE BLOCKED
ON {int}
RCVY P/W ENTERED
RECOVERY PASSWORD ENTERED
ON {int}
IED SEC CODE RD
IED SECURITY CODE READ
ON {int}
IED SEC CODE EXP
IED SECURITY CODE TIMER EXPIRED
-
PORT DISABLED
PORT DISABLED
BY {int} PORT {prt}
PORT ENABLED
PORT ENABLED
BY {int} PORT {prt}
DEF. DISPLAY NOT NERC COMPLIANT DEF DSP NOT-NERC
PSL STNG D/LOAD
PSL SETTINGS DOWNLOADED
BY {int} GROUP {grp}
418 P841B-TM-EN-1.1
Event Value Display

DNP STNG D/LOAD
DNP SETTINGS DOWNLOADED
BY {int}
TRACE DAT D/LOAD
TRACE DATA DOWNLOADED
BY {int}
IED CONFG D/LOAD
IEC61850 CONFIG DOWNLOADED
BY {int}
USER CRV D/LOAD
USER CURVES DOWNLOADED
BY {int} GROUP {crv}
PSL CONFG D/LOAD
PSL CONFIG DOWNLOADED
SETTINGS D/LOAD
SETTINGS DOWNLOADED
PSL STNG UPLOAD
PSL SETTINGS UPLOADED
DNP STNG UPLOAD
DNP SETTINGS UPLOADED
BY {int}
TRACE DAT UPLOAD
TRACE DATA UPLOADED
BY {int}
IED CONFG UPLOAD
IEC61850 CONFIG UPLOADED
BY {int}
USER CRV UPLOAD
USER CURVES UPLOADED
BY {int} GROUP {crv}
PSL CONFG UPLOAD
PSL CONFIG UPLOADED
SETTINGS UPLOAD
SETTINGS UPLOADED
EVENTS EXTRACTED
EVENTS HAVE BEEN EXTRACTED
BY {int} {nov} EVNTS
ACTIVE GRP CHNGE
ACTIVE GROUP CHANGED
C & S CHANGED
CS SETTINGS CHANGED
BY {int}
DR CHANGED
DR SETTINGS CHANGED
BY {int}
SETTINGS CHANGED
SETTING GROUP CHANGED
POWER ON
POWER ON
-
S/W DOWNLOADED
SOFTWARE_DOWNLOADED
-
where:
● int is the interface definition (UI, FP, RP1, RP2, TNL, TCP)
● prt is the port ID (FP, RP1, RP2, TNL, DNP3, IEC, ETHR)
● grp is the group number (1, 2, 3, 4)
P841B-TM-EN-1.1 419
● crv is the Curve group number (1, 2, 3, 4)

● n is the new access level (0, 1, 2, 3)
● p is the password level (1, 2, 3)
● nov is the number of events (1 – nnn)
Each new event has an incremented unique number, therefore missing events appear as ‘gap’ in the sequence.
The unique identifier forms part of the event record that is read or uploaded from the IED.
Note:
It is no longer possible to clear Event, Fault, Maintenance, and Disturbance Records.
4.8 LOGGING OUT

If you have been configuring the IED, you should 'log out'. Do this by going up to the top of the menu tree. When
you are at the Column Heading level and you press the Up button, you may be prompted to log out with the
following display:
DO YOU WANT TO
LOG OUT?
You will only be asked this question if your password level is higher than the fallback level.
If you confirm, the following message is displayed for 2 seconds:
LOGGED OUT
Access Level #
Where # is the current fallback level.

If you decide not to log out, the following message is displayed for 2 seconds.
LOGOUT CANCELLED
Access Level #
where # is the current access level.
420 P841B-TM-EN-1.1
CHAPTER 18
INSTALLATION
Chapter 18 - Installation P841B
422 P841B-TM-EN-1.1
P841B Chapter 18 - Installation
1 CHAPTER OVERVIEW
This chapter provides information about installing the product.
Handling the Goods 424
Mounting the Device 425
Cables and Connectors 428
Case Dimensions 432
P841B-TM-EN-1.1 423
2 HANDLING THE GOODS

Our products are of robust construction but require careful treatment before installation on site. This section
discusses the requirements for receiving and unpacking the goods, as well as associated considerations regarding
product care and personal safety.
Caution:
Before lifting or moving the equipment you should be familiar with the Safety
Information chapter of this manual.
2.1 RECEIPT OF THE GOODS

On receipt, ensure the correct product has been delivered. Unpack the product immediately to ensure there has
been no external damage in transit. If the product has been damaged, make a claim to the transport contractor
and notify us promptly.
For products not intended for immediate installation, repack them in their original delivery packaging.
2.2 UNPACKING THE GOODS

When unpacking and installing the product, take care not to damage any of the parts and make sure that
additional components are not accidentally left in the packing or lost. Do not discard any CDROMs or technical
documentation. These should accompany the unit to its destination substation and put in a dedicated place.
The site should be well lit to aid inspection, clean, dry and reasonably free from dust and excessive vibration. This
particularly applies where installation is being carried out at the same time as construction work.
2.3 STORING THE GOODS

If the unit is not installed immediately, store it in a place free from dust and moisture in its original packaging. Keep
any de-humidifier bags included in the packing. The de-humidifier crystals lose their efficiency if the bag is
exposed to ambient conditions. Restore the crystals before replacing it in the carton. Ideally regeneration should
be carried out in a ventilating, circulating oven at about 115°C. Bags should be placed on flat racks and spaced to
allow circulation around them. The time taken for regeneration will depend on the size of the bag. If a ventilating,
circulating oven is not available, when using an ordinary oven, open the door on a regular basis to let out the
steam given off by the regenerating silica gel.
On subsequent unpacking, make sure that any dust on the carton does not fall inside. Avoid storing in locations of
high humidity. In locations of high humidity the packaging may become impregnated with moisture and the de-
humidifier crystals will lose their efficiency.
The device can be stored between –25º to +70ºC for unlimited periods or between -40°C to + 85°C for up to 96
hours (see technical specifications).
2.4 DISMANTLING THE GOODS

If you need to dismantle the device, always observe standard ESD (Electrostatic Discharge) precautions. The
minimum precautions to be followed are as follows:
● Use an antistatic wrist band earthed to a suitable earthing point.
● Avoid touching the electronic components and PCBs.
424 P841B-TM-EN-1.1
3 MOUNTING THE DEVICE

The products are dispatched either individually or as part of a panel or rack assembly.
Individual products are normally supplied with an outline diagram showing the dimensions for panel cut-outs and
hole centres.
The products are designed so the fixing holes in the mounting flanges are only accessible when the access covers
are open.
If you use a P991 or MMLG test block with the product, when viewed from the front, position the test block on the
right-hand side of the associated product. This minimises the wiring between the product and test block, and
allows the correct test block to be easily identified during commissioning and maintenance tests.
If you need to test the product for correct operation during installation, open the lower access cover, hold the
battery in place and pull the red tab to remove the battery isolation strip.
V01412
Figure 177: Location of battery isolation strip
3.1 FLUSH PANEL MOUNTING

Panel-mounted devices are flush mounted into panels using M4 SEMS Taptite self-tapping screws with captive
3 mm thick washers (also known as a SEMS unit).
Caution:
Do not use conventional self-tapping screws, because they have larger heads and could
damage the faceplate.
Alternatively, you can use tapped holes if the panel has a minimum thickness of 2.5 mm.
For applications where the product needs to be semi-projection or projection mounted, a range of collars are
available.
If several products are mounted in a single cut-out in the panel, mechanically group them horizontally or vertically
into rigid assemblies before mounting in the panel.
P841B-TM-EN-1.1 425
Caution:
Do not fasten products with pop rivets because this makes them difficult to remove if
repair becomes necessary.
3.2 RACK MOUNTING

Panel-mounted variants can also be rack mounted using single-tier rack frames (our part number FX0021 101), as
shown in the figure below. These frames are designed with dimensions in accordance with IEC 60297 and are
supplied pre-assembled ready to use. On a standard 483 mm (19 inch) rack this enables combinations of case
widths up to a total equivalent of size 80TE to be mounted side by side.
The two horizontal rails of the rack frame have holes drilled at approximately 26 mm intervals. Attach the products
by their mounting flanges using M4 Taptite self-tapping screws with captive 3 mm thick washers (also known as a
SEMS unit).
Caution:
Risk of damage to the front cover molding. Do not use conventional self-tapping
screws, including those supplied for mounting MiDOS products because they have
slightly larger heads.
Once the tier is complete, the frames are fastened into the racks using mounting angles at each end of the tier.
Figure 178: Rack mounting of products
Products can be mechanically grouped into single tier (4U) or multi-tier arrangements using the rack frame. This
enables schemes using products from different product ranges to be pre-wired together before mounting.
Use blanking plates to fill any empty spaces. The spaces may be used for installing future products or because the
total size is less than 80TE on any tier. Blanking plates can also be used to mount ancillary components. The part
numbers are as follows:
Case size summation Blanking plate part number

5TE GJ2028 101
10TE GJ2028 102
426 P841B-TM-EN-1.1
Case size summation Blanking plate part number

15TE GJ2028 103
20TE GJ2028 104
25TE GJ2028 105
30TE GJ2028 106
35TE GJ2028 107
40TE GJ2028 108
P841B-TM-EN-1.1 427
4 CABLES AND CONNECTORS

This section describes the type of wiring and connections that should be used when installing the device. For pin-
out details please refer to the Hardware Design chapter or the wiring diagrams.
Caution:
Before carrying out any work on the equipment you should be familiar with the Safety
Section and the ratings on the equipment’s rating label.
4.1 TERMINAL BLOCKS

The device may use one or more of the terminal block types shown in the following diagram. The terminal blocks
are fastened to the rear panel with screws.
● Heavy duty (HD) terminal blocks for CT and VT circuits
● Medium duty (MD) terminal blocks for the power supply, relay outputs and rear communications port
● MiDOS terminal blocks for CT and VT circuits
● RTD/CLIO terminal block for connection to analogue transducers
Figure 179: Terminal block types
MiCOM products are supplied with sufficient M4 screws for making connections to the rear mounted terminal
blocks using ring terminals, with a recommended maximum of two ring terminals per terminal.
If required, M4 90° crimp ring terminals can be supplied in three different sizes depending on wire size. Each type is
available in bags of 100.
Part number Wire size Insulation color
ZB9124 901 0.25 - 1.65 mm2 (22 – 16 AWG) Red
ZB9124 900 1.04 - 2.63 mm2 (16 – 14 AWG) Blue
428 P841B-TM-EN-1.1
4.2 POWER SUPPLY CONNECTIONS

These should be wired with 1.5 mm PVC insulated multi-stranded copper wire terminated with M4 ring terminals.
The wire should have a minimum voltage rating of 300 V RMS.
Caution:
Protect the auxiliary power supply wiring with a maximum 16 A high rupture capacity
(HRC) type NIT or TIA fuse.
4.3 EARTH CONNNECTION

Every device must be connected to the cubicle earthing bar using the M4 earth terminal.
Use a wire size of at least 2.5 mm2 terminated with a ring terminal.
Due to the physical limitations of the ring terminal, the maximum wire size you can use is 6.0 mm2 using ring
terminals that are not pre-insulated. If using pre insulated ring terminals, the maximum wire size is reduced to 2.63
mm2 per ring terminal. If you need a greater cross-sectional area, use two wires in parallel, each terminated in a
separate ring terminal.
Note:
To prevent any possibility of electrolytic action between brass or copper ground conductors and the rear panel of the product,
precautions should be taken to isolate them from one another. This could be achieved in several ways, including placing a
nickel-plated or insulating washer between the conductor and the product case, or using tinned ring terminals.
4.4 CURRENT TRANSFORMERS

Current transformers would generally be wired with 2.5 mm2 PVC insulated multi-stranded copper wire terminated
with M4 ring terminals.
Due to the physical limitations of the ring terminal, the maximum wire size you can use is 6.0 mm2 using ring
terminals that are not pre-insulated. If using pre insulated ring terminals, the maximum wire size is reduced to 2.63
mm2 per ring terminal. If you need a greater cross-sectional area, use two wires in parallel, each terminated in a
separate ring terminal.
Caution:
Current transformer circuits must never be fused.
Note:
If there are CTs present, spring-loaded shorting contacts ensure that the terminals into which the CTs connect are shorted
before the CT contacts are broken.
Note:
For 5A CT secondaries, we recommend using 2 x 2.5 mm2 PVC insulated multi-stranded copper wire.
P841B-TM-EN-1.1 429
4.5 VOLTAGE TRANSFORMER CONNECTIONS

Voltage transformers should be wired with 2.5 mm2 PVC insulated multi-stranded copper wire terminated with M4
ring terminals.
4.6 WATCHDOG CONNECTIONS

These should be wired with 1 mm PVC insulated multi-stranded copper wire terminated with M4 ring terminals.
4.7 EIA(RS)485 AND K-BUS CONNECTIONS

For connecting the EIA(RS485) / K-Bus ports, use 2-core screened cable with a maximum total length of 1000 m or
200 nF total cable capacitance.
To guarantee the performance specifications, you must ensure continuity of the screen, when daisy chaining the
connections.
Two-core screened twisted pair cable should be used. It is important to avoid circulating currents, which can cause
noise and interference, especially when the cable runs between buildings. For this reason, the screen should be
continuous and connected to ground at one end only, normally at the master connection point.
The K-Bus signal is a differential signal and there is no signal ground connection. If a signal ground connection is
present in the bus cable then it must be ignored. At no stage should this be connected to the cable's screen or to
the product’s chassis. This is for both safety and noise reasons.
A typical cable specification would be:
● Each core: 16/0.2 mm2 copper conductors, PVC insulated
● Nominal conductor area: 0.5 mm2 per core
● Screen: Overall braid, PVC sheathed
4.8 IRIG-B CONNECTION

The IRIG-B input and BNC connector have a characteristic impedance of 50 ohms. We recommend that
connections between the IRIG-B equipment and the product are made using coaxial cable of type RG59LSF with a
halogen free, fire retardant sheath.
4.9 OPTO-INPUT CONNECTIONS

These should be wired with 1 mm2 PVC insulated multi-stranded copper wire terminated with M4 ring terminals.
Each opto-input has a selectable preset ½ cycle filter. This makes the input immune to noise induced on the wiring.
This can, however slow down the response. If you need to switch off the ½ cycle filter, either use double pole
switching on the input, or screened twisted cable on the input circuit.
Caution:
Protect the opto-inputs and their wiring with a maximum 16 A high rupture capacity
(HRC) type NIT or TIA fuse.
4.10 OUTPUT RELAY CONNECTIONS

These should be wired with 1 mm PVC insulated multi-stranded copper wire terminated with M4 ring terminals.
430 P841B-TM-EN-1.1
4.11 ETHERNET METALLIC CONNECTIONS

If the device has a metallic Ethernet connection, it can be connected to either a 10Base-T or a 100Base-TX
Ethernet hub. Due to noise sensitivity, we recommend this type of connection only for short distance connections,
ideally where the products and hubs are in the same cubicle. For increased noise immunity, CAT 6 (category 6) STP
(shielded twisted pair) cable and connectors can be used.
The connector for the Ethernet port is a shielded RJ-45. The pin-out is as follows:
4 - Not used
5 - Not used
7 - Not used
8 - Not used
4.12 ETHERNET FIBRE CONNECTIONS

We recommend the use of fibre-optic connections for permanent connections in a substation environment. The
100 Mbps fibre optic port uses type ST connectors (one for Tx and one for Rx), compatible with 50/125 µm or
62.5/125 µm multimode fibres at 1300 nm wavelength.
Note:
For models equipped with redundant Ethernet connections the product must be partially dismantled to set the fourth octet of
the second IP address. This ideally, should be done before installation.
4.13 RS232 CONNECTION

Short term connections to the EIA(RS)232 port, located behind the bottom access cover, can be made using a
screened multi-core communication cable up to 15 m long, or a total capacitance of 2500 pF. The cable should be
terminated at the product end with a standard 9-pin D-type male connector.
4.14 DOWNLOAD/MONITOR PORT

Short term connections to the download/monitor port, located behind the bottom access cover, can be made
using a screened 25-core communication cable up to 4 m long. The cable should be terminated at the product end
with a 25-pin D-type male connector.
4.15 GPS FIBRE CONNECTION

Some products use a GPS 1 PPS timing signal. If applicable, this is connected to a fibre-optic port on the
coprocessor board in slot B. The fibre-optic port uses an ST type connector, compatible with fibre multimode
50/125 µm or 62.5/125 µm – 850 nm.
4.16 FIBRE COMMUNICATION CONNECTIONS

The fibre optic port consists of one or two channels using ST type connectors (one for Tx and one for Rx). The type
of fibre used depends on the option selected.
850 nm and 1300 nm multimode systems use 50/125 µm or 62.5/125 µm multimode fibres. 1300 nm and 1550 nm
single mode systems use 9/125 µm single mode fibres.
P841B-TM-EN-1.1 431
5 CASE DIMENSIONS
Not all products are available in all case sizes.
5.1 CASE DIMENSIONS 40TE

Sealing
155.40 8 off holes Dia. 3.4 strip
23.30
AB BA
168.00
177.0
159.00 (4U)
AB BA
10.35 181.30 483 (19” rack)

202.00
A = Clearance holes Flush mouting panel

Panel cut-out details
B = Mouting holes
200.00
Note: If mouting plate is required
use flush mounting cut out
dimensions
All dimensons in mm
240.00
Front view Incl. wiring
177.00
157.5
max.
C
Side view
206.00 25.00 E01411
Figure 180: 40TE case dimensions
432 P841B-TM-EN-1.1
E01409
P841B-TM-EN-1.1 433

74.95 116.55 142.45 12 OFF HOLES 3.40
FLUSH MOUNTING PANEL

CUT-OUT DETAIL
159.00 168.00
62.00 155.40 129.50

4.50
408.90
407.10
MOUNTING SCREW : M4 X 12 SEM UNIT STEEL THREAD

FORMING SCREW.
TERMINAL SCREWS : M4 X 7 BRASS CHEESE HEAD SCREWS WITH

222.00 LOCK WASHERS PROVIDED.
240.00
Incl. wiring
157.5
177.00 max.
SIDE VIEW
413.2
25.00
FRONT VIEW
E01410
434 P841B-TM-EN-1.1
CHAPTER 19
COMMISSIONING INSTRUCTIONS
Chapter 19 - Commissioning Instructions P841B
436 P841B-TM-EN-1.1
P841B Chapter 19 - Commissioning Instructions
1 CHAPTER OVERVIEW
General Guidelines 438
Commissioning Test Menu 439
Commissioning Equipment 443
Product Checks 445
Electrical Intermicom Communication Loopback 454
Setting Checks 456
Protection Timing Checks 458
System Check and Check Synchronism 460
Check Trip and Autoreclose Cycle 461
Onload Checks 462
Final Checks 464
P841B-TM-EN-1.1 437
2 GENERAL GUIDELINES
General Electric IEDs are self-checking devices and will raise an alarm in the unlikely event of a failure. This is why
the commissioning tests are less extensive than those for non-numeric electronic devices or electro-mechanical
relays.
To commission the devices, you (the commissioning engineer) do not need to test every function. You need only
verify that the hardware is functioning correctly and that the application-specific software settings have been
applied. You can check the settings by extracting them using the settings application software, or by means of the
front panel interface (HMI panel).
The menu language is user-selectable, so you can change it for commissioning purposes if required.
Note:
Remember to restore the language setting to the customer’s preferred language on completion.
Caution:
Before carrying out any work on the equipment you should be familiar with the
contents of the Safety Section or Safety Guide SFTY/4LM as well as the ratings on the
equipment’s rating label.
Warning:
With the exception of the CT shorting contacts check, do not disassemble the device
during commissioning.
438 P841B-TM-EN-1.1
3 COMMISSIONING TEST MENU

The IED provides several test facilities under the COMMISSION TESTS menu heading. There are menu cells that
allow you to monitor the status of the opto-inputs, output relay contacts, internal Digital Data Bus (DDB) signals
and user-programmable LEDs. This section describes these commissioning test facilities.
3.1 OPTO I/P STATUS CELL (OPTO-INPUT STATUS)

This cell can be used to monitor the status of the opto-inputs while they are sequentially energised with a suitable
DC voltage. The cell is a binary string that displays the status of the opto-inputs where '1' means energised and '0'
means de-energised. If you move the cursor along the binary numbers, the corresponding label text is displayed
for each logic input.
3.2 RELAY O/P STATUS CELL (RELAY OUTPUT STATUS)

This cell can be used to monitor the status of the relay outputs. The cell is a binary string that displays the status of
the relay outputs where '1' means energised and '0' means de-energised. If you move the cursor along the binary
numbers, the corresponding label text is displayed for each relay output.
The cell indicates the status of the output relays when the IED is in service. You can check for relay damage by
comparing the status of the output contacts with their associated bits.
Note:
When the Test Mode cell is set to Contacts Blocked, the relay output status indicates which contacts would operate if
the IED was in-service. It does not show the actual status of the output relays, as they are blocked.
3.3 TEST PORT STATUS CELL

This cell displays the status of the DDB signals that have been allocated in the Monitor Bit cells. If you move the
cursor along the binary numbers, the corresponding DDB signal text string is displayed for each monitor bit.
By using this cell with suitable monitor bit settings, the state of the DDB signals can be displayed as various
operating conditions or sequences are applied to the IED. This allows you to test the Programmable Scheme Logic
(PSL).
3.4 MONITOR BIT 1 TO 8 CELLS

The eight Monitor Bit cells allows you to select eight DDB signals that can be observed in the Test Port Status cell or
downloaded via the front port.
Each Monitor Bit cell can be assigned to a particular DDB signal. You set it by entering the required DDB signal
number from the list of available DDB signals.
The pins of the monitor/download port used for monitor bits are as follows:
Monitor Bit 1 2 3 4 5 6 7 8
Monitor/Download Port Pin 11 12 15 13 20 21 23 24
The signal ground is available on pins 18, 19, 22 and 25.
Caution:
The monitor/download port is not electrically isolated against induced voltages on
the communications channel. It should therefore only be used for local
communications.
P841B-TM-EN-1.1 439
3.5 TEST MODE CELL

This cell allows you to perform secondary injection testing. It also lets you test the output contacts directly by
applying menu-controlled test signals.
To go into test mode, select the Test Mode option in the Test Mode cell. This takes the IED out of service causing
an alarm condition to be recorded and the Out of Service LED to illuminate. This also freezes any information
stored in the CB CONDITION column. In IEC 60870-5-103 versions, it changes the Cause of Transmission (COT) to
Test Mode.
In Test Mode, the output contacts are still active. To disable the output contacts you must select the Contacts
Blocked option.
Once testing is complete, return the device back into service by setting the Test Mode Cell back to Disabled.
Caution:
When the cell is in Test Mode, the Scheme Logic still drives the output relays, which
could result in tripping of circuit breakers. To avoid this, set the Test Mode cell to
Contacts Blocked.
Note:
Test mode and Contacts Blocked mode can also be selected by energising an opto-input mapped to the Test Mode
signal, and the Contact Block signal respectively.
3.6 TEST PATTERN CELL

The Test Pattern cell is used to select the output relay contacts to be tested when the Contact Test cell is set to
Apply Test. The cell has a binary string with one bit for each user-configurable output contact, which can be
set to '1' to operate the output and '0' to not operate it.
3.7 CONTACT TEST CELL

When the Apply Test command in this cell is issued, the contacts set for operation change state. Once the test
has been applied, the command text on the LCD will change to No Operation and the contacts will remain in the
Test state until reset by issuing the Remove Test command. The command text on the LCD will show No
Operation after the Remove Test command has been issued.
Note:
When the Test Mode cell is set to Contacts Blocked the Relay O/P Status cell does not show the current status of the
output relays and therefore cannot be used to confirm operation of the output relays. Therefore it will be necessary to monitor
the state of each contact in turn.
3.8 TEST LEDS CELL

When the Apply Test command in this cell is issued, the user-programmable LEDs illuminate for approximately
2 seconds before switching off, and the command text on the LCD reverts to No Operation.
3.9 TEST AUTORECLOSE CELL

Where the IED provides an auto-reclose function, this cell will be available for testing the sequence of circuit
breaker trip and auto-reclose cycles.
The Trip 3 Pole option in the Test Autoreclose cell causes the device to perform the first three phase trip/
reclose cycle so that associated output contacts can be checked for operation at the correct times during the
440 P841B-TM-EN-1.1
cycle. Once the trip output has operated the command text will revert to No Operation whilst the rest of the
auto-reclose cycle is performed. To test subsequent three-phase autoreclose cycles, you repeat the Trip 3
Pole command. You can also test the single phases with Trip Pole A , Trip Pole B and Trip Pole B.
Note:
The default settings for the programmable scheme logic has the AR Trip Test signals mapped to the Trip Input
signals. If the programmable scheme logic has been changed, it is essential that these signals retain this mapping for the
Test Autoreclose facility to work.
3.10 STATIC TEST MODE

Static Test Mode can be set to Enabled or Disabled. When the Static Test mode is enabled it allows injection
test that don't support dynamic switching to be used to commission and test the device.
Dynamic secondary injection test sets are able to accurately mimic real power system faults. The test sets mimic
an instantaneous fault “shot”, with the real rate of rise of current, and the decaying DC exponential component.
Dynamic injection test sets are available, which cater for all three phases, providing a six signal set of analogue
inputs: Va, Vb, Vc, Ia, Ib, Ic. Such injection test sets can be used with the device, with no special testing limitations.
Static test sets, also known as Static Simulators, may not properly provide or simulate:
● A healthy pre-fault voltage
● A real fault shot (instead a gradually varying current or voltage would be used)
● The rate of rise of current and DC components
● A complete set of three-phase analogue inputs
● Real dynamic step changes in current and voltage.
Some of the protection in this product is based on delta techniques which recognise step changes in actual power
system quantities. Because these may not be produced by static test sets,, certain functions are can be disabled or
bypassed to allow injection testing with static test sets. Enabling the Static Test Mode option does this..
For the tests, the delta directional line is replaced by a conventional distance directional line. Extra filtering of
distance comparators is used so the filtering slows to use a fixed one cycle window. Memory polarising is replaced
by cross-polarising from unfaulted phases.
Note:
Trip times may be up to ½ cycle longer when tested in the static mode, due to the nature of the test voltage and current, and
the slower filtering. This is normal, and perfectly acceptable.
3.11 LOOPBACK MODE

Loopback Mode can be used to test InterMiCOM64 signalling.
Note:
If the cell is set to Internal, only the IED software is checked. If the cell is set to External, both the software and hardware
are checked.
When the device is switched into Loopback Mode, it automatically uses generic addresses 0-0. It responds as if it is
connected to a remote device. The sent and received IM64 signals continue to be routed to and from the signals
defined in the programmable logic.
Note:
Loopback mode can also be selected by energising an opto-input mapped to the Loopback signal.
P841B-TM-EN-1.1 441
3.12 IM64 TEST PATTERN

This cell is used with the IM64 Test Mode cell to set a 16-bit pattern (8 bits per channel), which is transmitted
whenever the IM64 Test Mode cell is set to Enabled. The IM64 TestPattern cell has a binary string with one bit for
each user-defined Inter-MiCOM command. These can be set to '1' to operate the IM64 output under test conditions
and '0' for no operation.
3.13 IM64 TEST MODE

When the Enable command in this cell is issued, the InterMiCOM64 commands change to reflect the state of the
values set in the IM64 TestPattern cell. If the cell is set to Disabled, the InterMiCOM64 commands reflect the state
of the signals generated by the protection and control functions.
3.14 RED AND GREEN LED STATUS CELLS

These cells contain binary strings that indicate which of the user-programmable red and green LEDs are
illuminated when accessing from a remote location. A '1' indicates that a particular LED is illuminated.
Note:
When the status in both Red LED Status and Green LED Status cells is ‘1’, this indicates the LEDs illumination is yellow.
3.15 USING A MONITOR PORT TEST BOX

A test box containing eight LEDs and a switchable audible indicator is available. It is housed in a small plastic box
with a 25-pin male D-connector that plugs directly into the monitor/download port. There is also a 25-pin female
D-connector which allows other connections to be made to the monitor/download port while the monitor/
download port test box is in place.
Each LED corresponds to one of the monitor bit pins on the monitor/download port. Monitor Bit 1 is on the left-
hand side when viewed from the front of the IED. The audible indicator can be selected to sound if a voltage
appears on any of the eight monitor pins. Alternatively it can be set to remain silent, using only the LEDs.
442 P841B-TM-EN-1.1
4 COMMISSIONING EQUIPMENT
Specialist test equipment is required to commission this product. We recognise three classes of equipment for
commissioning :
● Recommended
● Essential
● Advisory
Recommended equipment constitutes equipment that is both necessary, and sufficient, to verify correct
performance of the principal protection functions.
Essential equipment represents the minimum necessary to check that the product includes the basic expected
protection functions and that they operate within limits.
Advisory equipment represents equipment that is needed to verify satisfactory operation of features that may be
unused, or supplementary, or which may, for example, be integral to a distributed control/automation scheme.
Operation of such features may, perhaps, be more appropriately verified as part of a customer defined
commissioning requirement, or as part of a system-level commissioning regime.
4.1 RECOMMENDED COMMISSIONING EQUIPMENT

The minimum recommended equipment is a multifunctional three-phase AC current and voltage injection test set
featuring :
● Controlled three-phase AC current and voltage sources,
● Transient (dynamic) switching between pre-fault and post-fault conditions (to generate delta conditions),
● Dynamic impedance state sequencer (capable of sequencing through 4 impedance states),
● Integrated or separate variable DC supply (0 - 250 V)
● Integrated or separate AC and DC measurement capabilities (0-440V AC, 0-250V DC)
● Integrated and/or separate timer,
● Integrated and/or separate test switches.
In addition, you will need :

● A portable computer, installed with appropriate software to liaise with the equipment under test (EUT).
Typically this software will be proprietary to the product’s manufacturer (for example MiCOM S1 Agile).
● Suitable electrical test leads.
● Electronic or brushless insulation tester with a DC output not exceeding 500 V
● Continuity tester
● Verified application-specific settings files
4.2 ESSENTIAL COMMISSIONING EQUIPMENT

As an absolute minimum, the following equipment is required:
● AC current source coupled with AC voltage source
● Variable DC supply (0 - 250V)
● Multimeter capable of measuring AC and DC current and voltage (0-440V AC, 0-250V DC)
● Timer
● Test switches
● Suitable electrical test leads
● Continuity tester
P841B-TM-EN-1.1 443
4.3 ADVISORY TEST EQUIPMENT

Advisory test equipment may be required for extended commissioning procedures:
● Current clamp meter
● Multi-finger test plug:
○ P992 for test block type P991
○ MMLB for test block type MMLG blocks
● Electronic or brushless insulation tester with a DC output not exceeding 500 V
● KITZ K-Bus - EIA(RS)232 protocol converter for testing EIA(RS)485 K-Bus port
● EIA(RS)485 to EIA(RS)232 converter for testing EIA(RS)485 Courier/MODBUS/IEC60870-5-103/DNP3 port
● A portable printer (for printing a setting record from the portable PC) and or writeable, detachable memory
device.
● Phase angle meter
● Phase rotation meter
● Fibre-optic power meter.
● Fibre optic test leads (minimum 2). 10m minimum length, multimode 50/125 µm or 62.5µm terminated with
BFOC (ST) 2.5 connectors for testing the fibre-optic RP1 port.
444 P841B-TM-EN-1.1
5 PRODUCT CHECKS
These product checks are designed to ensure that the device has not been physically damaged prior to
commissioning, is functioning correctly and that all input quantity measurements are within the stated tolerances.
If the application-specific settings have been applied to the IED prior to commissioning, you should make a copy of
the settings. This will allow you to restore them at a later date if necessary. This can be done by:
● Obtaining a setting file from the customer.
● Extracting the settings from the IED itself, using a portable PC with appropriate setting software.
If the customer has changed the password that prevents unauthorised changes to some of the settings, either the
revised password should be provided, or the original password restored before testing.
Note:
If the password has been lost, a recovery password can be obtained from General Electric.
5.1 PRODUCT CHECKS WITH THE IED DE-ENERGISED
Warning:
The following group of tests should be carried out without the auxiliary supply being
applied to the IED and, if applicable, with the trip circuit isolated.
The current and voltage transformer connections must be isolated from the IED for these checks. If a P991 test
block is provided, the required isolation can be achieved by inserting test plug type P992. This open circuits all
wiring routed through the test block.
Before inserting the test plug, you should check the scheme diagram to ensure that this will not cause damage or
a safety hazard (the test block may, for example, be associated with protection current transformer circuits). The
sockets in the test plug, which correspond to the current transformer secondary windings, must be linked before
the test plug is inserted into the test block.
Warning:
Never open-circuit the secondary circuit of a current transformer since the high
voltage produced may be lethal and could damage insulation.
If a test block is not provided, the voltage transformer supply to the IED should be isolated by means of the panel
links or connecting blocks. The line current transformers should be short-circuited and disconnected from the IED
terminals. Where means of isolating the auxiliary supply and trip circuit (for example isolation links, fuses and MCB)
are provided, these should be used. If this is not possible, the wiring to these circuits must be disconnected and the
exposed ends suitably terminated to prevent them from being a safety hazard.
5.1.1 VISUAL INSPECTION
P841B-TM-EN-1.1 445
Warning:
Check the rating information under the top access cover on the front of the IED.
Warning:
Check that the IED being tested is correct for the line or circuit.
Warning:
Record the circuit reference and system details.
Warning:
Check the CT secondary current rating and record the CT tap which is in use.
Carefully examine the IED to see that no physical damage has occurred since installation.
Ensure that the case earthing connections (bottom left-hand corner at the rear of the IED case) are used to
connect the IED to a local earth bar using an adequate conductor.
5.1.2 CURRENT TRANSFORMER SHORTING CONTACTS

Check the current transformer shorting contacts to ensure that they close when the heavy-duty terminal block is
disconnected from the current input board.
The heavy-duty terminal blocks are fastened to the rear panel using four crosshead screws. These are located two
at the top and two at the bottom.
Note:
Use a magnetic bladed screwdriver to minimise the risk of the screws being left in the terminal block or lost.
Pull the terminal block away from the rear of the case and check with a continuity tester that all the shorting
switches being used are closed.
5.1.3 INSULATION
Insulation resistance tests are only necessary during commissioning if explicitly requested.
Isolate all wiring from the earth and test the insulation with an electronic or brushless insulation tester at a DC
voltage not exceeding 500 V. Terminals of the same circuits should be temporarily connected together.
The insulation resistance should be greater than 100 MW at 500 V.
On completion of the insulation resistance tests, ensure all external wiring is correctly reconnected to the IED.
5.1.4 EXTERNAL WIRING
Caution:
Check that the external wiring is correct according to the relevant IED and scheme
diagrams. Ensure that phasing/phase rotation appears to be as expected.
5.1.5 WATCHDOG CONTACTS

Using a continuity tester, check that the Watchdog contacts are in the following states:
446 P841B-TM-EN-1.1
Terminals Contact state with product de-energised

11 - 12 on power supply board Closed
13 - 14 on power supply board Open
5.1.6 POWER SUPPLY

Depending on its nominal supply rating, the IED can be operated from either a DC only or an AC/DC auxiliary
supply. The incoming voltage must be within the operating range specified below.
Without energising the IED measure the auxiliary supply to ensure it is within the operating range.
Nominal supply rating Nominal supply rating
DC operating range AC operating range
DC AC RMS
24 - 54 V N/A 19 to 65 V N/A
48 - 125 V 30 - 100 V 37 to 150 V 24 - 110 V
110 - 250 V 100 - 240 V 87 to 300 V 80 to 265 V
Note:
The IED can withstand an AC ripple of up to 12% of the upper rated voltage on the DC auxiliary supply.
Warning:
Do not energise the IED or interface unit using the battery charger with the battery
disconnected as this can irreparably damage the power supply circuitry.
Caution:
Energise the IED only if the auxiliary supply is within the specified operating ranges.
If a test block is provided, it may be necessary to link across the front of the test plug
to connect the auxiliary supply to the IED.
5.2 PRODUCT CHECKS WITH THE IED ENERGISED
Warning:
The current and voltage transformer connections must remain isolated from the IED
for these checks. The trip circuit should also remain isolated to prevent accidental
operation of the associated circuit breaker.
The following group of tests verifies that the IED hardware and software is functioning correctly and should be
carried out with the supply applied to the IED.
5.2.1 WATCHDOG CONTACTS

Using a continuity tester, check that the Watchdog contacts are in the following states when energised and
healthy.
Terminals Contact state with product energised
11 - 12 on power supply board Open
13 - 14 on power supply board Closed
P841B-TM-EN-1.1 447
5.2.2 TEST LCD

The Liquid Crystal Display (LCD) is designed to operate in a wide range of substation ambient temperatures. For
this purpose, the IEDs have an LCD Contrast setting. The contrast is factory pre-set, but it may be necessary to
adjust the contrast to give the best in-service display.
To change the contrast, you can increment or decrement the LCD Contrast cell in the CONFIGURATION column.
Caution:
Before applying a contrast setting, make sure that it will not make the display so
light or dark such that menu text becomes unreadable. It is possible to restore the
visibility of a display by downloading a setting file, with the LCD Contrast set within
the typical range of 7 - 11.
5.2.3 DATE AND TIME

The date and time is stored in memory, which is backed up by an auxiliary battery situated at the front of the
device behind the lower access cover. When delivered, this battery is isolated to prevent battery drain during
transportation and storage.
Before setting the date and time, ensure that the isolation strip has been removed. With the lower access cover
open, the battery isolation strip can be identified by a red tab protruding from the positive side of the battery
compartment. Pull the red tab to remove the isolation strip.
The method for setting the date and time depends on whether an IRIG-B signal is being used or not. The IRIG-B
signal will override the time, day and month settings, but not the initial year setting. For this reason, you must
ensure you set the correct year, even if the device is using IRIG-B to maintain the internal clock.
You set the Date and Time by one of the following methods:
● Using the front panel to set the Date and Time cells respectively
● By sending a courier command to the Date/Time cell (Courier reference 0801)
Note:
If the auxiliary supply fails, the time and date will be maintained by the auxiliary battery. Therefore, when the auxiliary supply
is restored, you should not have to set the time and date again. To test this, remove the IRIG-B signal, and then remove the
auxiliary supply. Leave the device de-energised for approximately 30 seconds. On re energisation, the time should be correct.
When using IRIG-B to maintain the clock, the IED must first be connected to the satellite clock equipment (usually a
P594/RT430), which should be energised and functioning.
1. Set the IRIG-B Sync cell in the DATE AND TIME column to Enabled.
2. Ensure the IED is receiving the IRIG-B signal by checking that cell IRIG-B Status reads Active.
3. Once the IRIG-B signal is active, adjust the time offset of the universal co coordinated time (satellite clock
time) on the satellite clock equipment so that local time is displayed.
4. Check that the time, date and month are correct in the Date/Time cell. The IRIG-B signal does not contain
the current year so it will need to be set manually in this cell.
5. Reconnect the IRIG-B signal.
If the time and date is not being maintained by an IRIG-B signal, ensure that the IRIG-B Sync cell in the DATE AND
TIME column is set to Disabled.
1. Set the date and time to the correct local time and date using Date/Time cell or using the serial protocol.
448 P841B-TM-EN-1.1
5.2.4 TEST LEDS

On power-up, all LEDs should first flash yellow. Following this, the green "Healthy" LED should illuminate indicating
that the device is healthy.
The IED's non-volatile memory stores the states of the alarm, the trip, and the user-programmable LED indicators
(if configured to latch). These indicators may also illuminate when the auxiliary supply is applied.
If any of these LEDs are ON then they should be reset before proceeding with further testing. If the LEDs
successfully reset (the LED goes off), no testing is needed for that LED because it is obviously operational.
5.2.5 TEST ALARM AND OUT-OF-SERVICE LEDS

The alarm and out of service LEDs can be tested using the COMMISSION TESTS menu column.
1. Set the Test Mode cell to Contacts Blocked.
2. Check that the out of service LED illuminates continuously and the alarm LED flashes.
It is not necessary to return the Test Mode cell to Disabled at this stage because the test mode will be required
for later tests.
5.2.6 TEST TRIP LED

The trip LED can be tested by initiating a manual circuit breaker trip. However, the trip LED will operate during the
setting checks performed later. Therefore no further testing of the trip LED is required at this stage.
5.2.7 TEST USER-PROGRAMMABLE LEDS

To test these LEDs, set the Test LEDs cell to Apply Test. Check that all user-programmable LEDs illuminate.
5.2.8 TEST FIELD VOLTAGE SUPPLY

The IED generates a field voltage of nominally 48 V that can be used to energise the opto-inputs (alternatively the
substation battery may be used).
1. Measure the field voltage across the terminals 7 and 9 of the power supply terminal block
2. Check that the field voltage is within the range 40 V to 60 V when no load is connected and that the polarity
is correct.
3. Repeat for terminals 8 and 10.
5.2.9 TEST OPTO-INPUTS

This test checks that all the opto-inputs on the IED are functioning correctly.
The opto-inputs should be energised one at a time. For terminal numbers, please see the external connection
diagrams in the "Wiring Diagrams" chapter. Ensuring correct polarity, connect the supply voltage to the
appropriate terminals for the input being tested.
The status of each opto-input can be viewed using either the Opto I/P Status cell in the SYSTEM DATA column, or
the Opto I/P Status cell in the COMMISSION TESTS column.
A '1' indicates an energised input and a '0' indicates a de-energised input. When each opto-input is energised, one
of the characters on the bottom line of the display changes to indicate the new state of the input.
P841B-TM-EN-1.1 449
5.2.10 TEST OUTPUT RELAYS

This test checks that all the output relays are functioning correctly.
1. Ensure that the IED is still in test mode by viewing the Test Mode cell in the COMMISSION TESTS column.
Ensure that it is set to Contacts Blocked.
2. The output relays should be energised one at a time. To select output relay 1 for testing, set the Test Pattern
cell as appropriate.
3. Connect a continuity tester across the terminals corresponding to output relay 1 as shown in the external
connection diagram.
4. To operate the output relay set the Contact Test cell to Apply Test.
5. Check the operation with the continuity tester.
6. Measure the resistance of the contacts in the closed state.
7. Reset the output relay by setting the Contact Test cell to Remove Test.
8. Repeat the test for the remaining output relays.
9. Return the IED to service by setting the Test Mode cell in the COMMISSION TESTS menu to Disabled.
5.2.11 TEST SERIAL COMMUNICATION PORT RP1

You need only perform this test if the IED is to be accessed from a remote location with a permanent serial
connection to the communications port. The scope of this test does not extend to verifying operation with
connected equipment beyond any suppied protocol converter. It verifies operation of the rear communication port
(and if applicable the protocol converter) and varies according to the protocol fitted.
5.2.11.1 CHECK PHYSICAL CONNECTIVITY

The rear communication port RP1 is presented on terminals 16, 17 and 18 of the power supply terminal block.
Screened twisted pair cable is used to make a connection to the port. The cable screen should be connected to pin
16 and pins 17 and 18 are for the communication signal:
Figure 183: RP1 physical connection
450 P841B-TM-EN-1.1
For K-Bus applications, pins 17 and 18 are not polarity sensitive and it does not matter which way round the wires
are connected. EIA(RS)485 is polarity sensitive, so you must ensure the wires are connected the correct way round
(pin 18 is positive, pin 17 is negative).
If K-Bus is being used, a Kitz protocol converter (KITZ101, KITZ102 OR KITZ201) will have been installed to convert
the K-Bus signals into RS232. Likewise, if RS485 is being used, an RS485-RS232 converter will have been installed.
In the case where a protocol converter is being used, a laptop PC running appropriate software (such as MiCOM S1
Agile) can be connected to the incoming side of the protocol converter. An example for K-bus to RS232 conversion
is shown below. RS485 to RS232 would follow the same principle, only using a RS485-RS232 converter. Most
modern laptops have USB ports, so it is likely you will also require a RS232 to USB converter too.
C C C
IED IED IED
RS232 K-Bus
Computer RS232-USB converter KITZ protocol converter

V01001
Figure 184: Remote communication using K-bus
Fibre Connection
Some models have an optional fibre optic communications port fitted (on a separate communications board). The
communications port to be used is selected by setting the Physical Link cell in the COMMUNICATIONS column, the
values being Copper or K-Bus for the RS485/K-bus port and Fibre Optic for the fibre optic port.
5.2.11.2 CHECK LOGICAL CONNECTIVITY

The logical connectivity depends on the chosen data protocol, but the principles of testing remain the same for all
protocol variants:
1. Ensure that the communications baud rate and parity settings in the application software are set the same
as those on the protocol converter.
2. For Courier models, ensure that you have set the correct RP1 address
3. Check that communications can be established with this IED using the portable PC/Master Station.
5.2.12 TEST SERIAL COMMUNICATION PORT RP2

RP2 is an optional second serial port board providing additional serial connectivity. It provides two 9-pin D-type
serial port connectors SK4 and SK5. Both ports are configured as DTE (Date Terminal Equipment) ports. That means
they can be connected to communications equipment such as a modem with a straight-through cable.
SK4 can be configured as an EIA(RS232), EIA(RS485), or K-Bus connection for Courier protocol only, whilst SK5 is
fixed to EIA(RS)232 for InterMiCOM signalling only.
P841B-TM-EN-1.1 451
It is not the intention of this test to verify the operation of the complete communication link between the IED and
the remote location, just the IED's rear communication port and, if applicable, the protocol converter.
The only checks that need to be made are as follows:
1. Set the RP2 Port Config cell in the COMMUNICATIONS column to the required physical protocol; (K-Bus,
EIA(RS)485, or EIA(RS)232.
2. Set the IED's Courier address to the correct value (it must be between 1 and 254).
5.2.13 TEST ETHERNET COMMUNICATION

For products that employ Ethernet communications, we recommend that testing be limited to a visual check that
the correct ports are fitted and that there is no sign of physical damage.
If there is no board fitted or the board is faulty, a NIC link alarm will be raised (providing this option has been set in
the NIC Link Report cell in the COMMUNICATIONS column).
5.3 SECONDARY INJECTION TESTS

Secondary injection testing is carried out to verify the integrity of the VT and CT readings. All devices leave the
factory set for operation at a system frequency of 50 Hz. If operation at 60 Hz is required, you must set this in the
Frequency cell in the SYSTEM DATA column.
The PMU must be installed and connected to a 1pps fibre optic synchronising signal and a demodulated IRIG-B
signal, provided by a device such as a P594 or a REASON RT430.
Connect the current and voltage outputs of the test set to the appropriate terminals of the first voltage and current
channel and apply nominal voltage and current with the current lagging the voltage by 90 degrees.
5.3.1 TEST CURRENT INPUTS

This test verifies that the current measurement inputs are configured correctly.
1. Using secondary injection test equipment such as an Omicron, apply and measure nominal rated current to
each CT in turn.
2. Check its magnitude using a multi-meter or test set readout. Check this value against the value displayed
on the HMI panel (usually in MEASUREMENTS 1 column).
3. Record the displayed value. The measured current values will either be in primary or secondary Amperes. If
the Local Values cell in the MEASURE’T SETUP column is set to Primary, the values displayed should be
equal to the applied current multiplied by the corresponding current transformer ratio (set in the CT AND VT
RATIOS column). If the Local Values cell is set to Secondary, the value displayed should be equal to the
applied current.
Note:
If a PC connected to the IED using the rear communications port is being used to display the measured current, the process
will be similar. However, the setting of the Remote Values cell in the MEASURE’T SETUP column will determine whether the
displayed values are in primary or secondary Amperes.
The measurement accuracy of the IED is +/- 1%. However, an additional allowance must be made for the accuracy
of the test equipment being used.
452 P841B-TM-EN-1.1
5.3.2 TEST VOLTAGE INPUTS

This test verifies that the voltage measurement inputs are configured correctly.
1. Using secondary injection test equipment, apply and measure the rated voltage to each voltage
transformer input in turn.
2. Check its magnitude using a multimeter or test set readout. Check this value against the value displayed on
the HMI panel (usually in MEASUREMENTS 1 column).
3. Record the value displayed. The measured voltage values will either be in primary or secondary Volts. If the
Local Values cell in the MEASURE’T SETUP column is set to Primary, the values displayed should be equal
to the applied voltage multiplied by the corresponding voltage transformer ratio (set in the CT AND VT
RATIOS column). If the Local Values cell is set to Secondary, the value displayed should be equal to the
applied voltage.
Note:
If a PC connected to the IED using the rear communications port is being used to display the measured current, the process
will be similar. However, the setting of the Remote Values cell in the MEASURE’T SETUP column will determine whether the
displayed values are in primary or secondary Amperes.
The measurement accuracy of the IED is +/- 1%. However, an additional allowance must be made for the accuracy
of the test equipment being used.
P841B-TM-EN-1.1 453
6 ELECTRICAL INTERMICOM COMMUNICATION LOOPBACK

If the IED is used in a scheme with standard InterMiCOM communication (Electrical Teleprotection), you need to
configure a loopback for testing purposes.
6.1 SETTING UP THE LOOPBACK

The communication path may include various connectors and signal converters before leaving the substation. We
therefore advise making the loopback as close as possible to where the communication link leaves the substation.
This way, as much of the wiring as possible and all associated communication signal converters are included in
the test.
1. Set CONFIGURATION > InterMiCOM to Enabled.
2. Set INTERMICOM COMMS > Ch Statistics and Ch Diagnostics to Visible.
3. Check that INTERMICOM COMMS > IM H/W Status displays OK. This means the InterMiCOM hardware is
fitted and initialised.
6.2 LOOPBACK TEST

INTERMICOM COMMS > Loopback Mode allows you to test the InterMiCOM channel. In normal service it must be
disabled. INTERMICOM COMMS > Loopback Status shows the status of the InterMiCOM loopback mode.
Note:
If INTERMICOM COMMS > Loopback Mode is set to Internal, only the internal software of the device is checked. This is
useful for testing functionality if no communications connections are made. Use the 'External' setting during commissioning
because it checks both the software and hardware. When the IED is switched into either Internal or External Loopback Mode it
automatically inhibits InterMiCOM messages to the PSL by setting all eight InterMiCOM message command states to zero.
Set INTERMICOM COMMS > Loopback Mode to External and form a communications loopback by connecting
the transmit signal (pin 2) to the receive signal (pin 3).
Note:
The DCD signal must be held high (by connecting pin 1 to pin 4) if the connected equipment does not support DCD.
DCD 1
RxD 2
TxD 3
DTR 4
GND 5
6
RTS 7
8
9
E01450
Figure 185: InterMicom loopback testing
The loopback mode is shown on the front panel by an Alarm LED and the message IM Loopback on the LCD.
Check that all connections are correct and the software is working correctly.
Check that INTERMICOM COMMS > Loopback Status shows OK.
454 P841B-TM-EN-1.1
6.2.1 INTERMICOM COMMAND BITS

To test the InterMiCOM command bits, go to the INTERMICOM COMMS column and do the following:
1. Enter any test pattern in the Test Pattern cell in the by scrolling through and changing selected bits
between 1 and 0. The entered pattern is transmitted through the loopback.
2. Check that the IM Output Status cell matches the applied Test Pattern.
3. Check that all 8 bits in the IM Input Status cell are zero.
6.2.2 INTERMICOM CHANNEL DIAGNOSTICS

Check that the following cells in the INTERMICOM COMMS column all read OK.
● Data CD Status
● FrameSync Status
● Message Status
● Channel Status
6.2.3 SIMULATING A CHANNEL FAILURE

1. Simulate a failure of the communications link by breaking a connection and checking that some of these
cells show Fail.
2. Restore the communications loopback and ensure that the four diagnostic cells display OK.
Note:
Some or all of these cells show Fail depending on the communications configuration and the way the link has failed.
P841B-TM-EN-1.1 455
7 SETTING CHECKS
The setting checks ensure that all of the application-specific settings (both the IED’s function and programmable
scheme logic settings) have been correctly applied.
Note:
If applicable, the trip circuit should remain isolated during these checks to prevent accidental operation of the associated
circuit breaker.
7.1 APPLY APPLICATION-SPECIFIC SETTINGS

There are two different methods of applying the settings to the IED
● Transferring settings to the IED from a pre-prepared setting file using MiCOM S1 Agile
● Enter the settings manually using the IED’s front panel HMI
7.1.1 TRANSFERRING SETTINGS FROM A SETTINGS FILE

This is the preferred method for transferring function settings. It is much faster and there is a lower margin for
error.
1. Connect a PC running the Settings Application Software to the IED's front port, or a rear Ethernet port.
Alternatively connect to the rear Courier communications port, using a KITZ protocol converter if necessary.
2. Power on the IED
3. Enter the IP address of the device if it is Ethernet enabled
4. Right-click the appropriate device name in the System Explorer pane and select Send
5. In the Send to dialog select the setting files and click Send
Note:
The device name may not already exist in the system shown in System Explorer. In this case, perform a Quick Connect to the
IED, then manually add the settings file to the device name in the system. Refer to the Settings Application Software help for
details of how to do this.
7.1.2 ENTERING SETTINGS USING THE HMI

1. Starting at the default display, press the Down cursor key to show the first column heading.
2. Use the horizontal cursor keys to select the required column heading.
3. Use the vertical cursor keys to view the setting data in the column.
4. To return to the column header, either press the Up cursor key for a second or so, or press the Cancel key
once. It is only possible to move across columns at the column heading level.
5. To return to the default display, press the Up cursor key or the Cancel key from any of the column headings.
If you use the auto-repeat function of the Up cursor key, you cannot go straight to the default display from
one of the column cells because the auto-repeat stops at the column heading.
6. To change the value of a setting, go to the relevant cell in the menu, then press the Enter key to change the
cell value. A flashing cursor on the LCD shows that the value can be changed. You may be prompted for a
password first.
7. To change the setting value, press the vertical cursor keys. If the setting to be changed is a binary value or a
text string, select the required bit or character to be changed using the left and right cursor keys.
456 P841B-TM-EN-1.1
8. Press the Enter key to confirm the new setting value or the Clear key to discard it. The new setting is
automatically discarded if it is not confirmed within 15 seconds.
9. For protection group settings and disturbance recorder settings, the changes must be confirmed before
they are used. When all required changes have been entered, return to the column heading level and press
the down cursor key. Before returning to the default display, the following prompt appears.
Update settings?
ENTER or CLEAR
10. Press the Enter key to accept the new settings or press the Clear key to discard the new settings.
Note:
If the menu time-out occurs before the setting changes have been confirmed, the setting values are also discarded.
Control and support settings are updated immediately after they are entered, without the Update settings prompt.
It is not possible to change the PSL using the IED’s front panel HMI.
Caution:
Where the installation needs application-specific PSL, the relevant .psl files, must be
transferred to the IED, for each and every setting group that will be used. If you do
not do this, the factory default PSL will still be resident. This may have severe
operational and safety consequences.
P841B-TM-EN-1.1 457
8 PROTECTION TIMING CHECKS

There is no need to check every protection function. Only one protection function needs to be checked as the
purpose is to verify the timing on the processor is functioning correctly.
8.1 OVERCURRENT CHECK

If the overcurrent protection function is being used, test the overcurrent protection for stage 1.
1. Check for any possible dependency conditions and simulate as appropriate.
2. In the CONFIGURATION column, disable all protection elements other than the one being tested.
3. Make a note of which elements need to be re-enabled after testing.
4. Connect the test circuit.
5. Perform the test.
6. Check the operating time.
8.2 CONNECTING THE TEST CIRCUIT

1. Use the PSL to determine which output relay will operate when an overcurrent trip occurs.
2. Use the output relay assigned to Trip Output A.
3. Use the PSL to map the protection stage under test directly to an output relay.
Note:
If using the default PSL, use output relay 3 as this is already mapped to the DDB signal Trip Command Out.
4. Connect the output relay so that its operation will trip the test set and stop the timer.
5. Connect the current output of the test set to the A-phase current transformer input.
If the I>1 Directional cell in the OVERCURRENT column is set to Directional Fwd, the current should
flow out of terminal 2. If set to Directional Rev, it should flow into terminal 2.
If the I>1 Directional cell in the OVERCURRENT column has been set to Directional Fwd or
Directional Rev, the rated voltage should be applied to terminals 20 and 21.
6. Ensure that the timer starts when the current is applied.
Note:
If the timer does not stop when the current is applied and stage 1 has been set for directional operation, the connections may
be incorrect for the direction of operation set. Try again with the current connections reversed.
8.3 PERFORMING THE TEST

1. Ensure that the timer is reset.
2. Apply a current of twice the setting shown in the I>1 Current Set cell in the OVERCURRENT column.
3. Note the time displayed when the timer stops.
4. Check that the red trip LED has illuminated.
8.4 CHECK THE OPERATING TIME

Check that the operating time recorded by the timer is within the range shown below.
For all characteristics, allowance must be made for the accuracy of the test equipment being used.
458 P841B-TM-EN-1.1
Operating time at twice current setting and time multiplier/

Characteristic
time dial setting of 1.0
Nominal (seconds) Range (seconds)
DT I>1 Time Delay setting Setting ±2%
IEC S Inverse 10.03 9.53 - 10.53
IEC V Inverse 13.50 12.83 - 14.18
IEC E Inverse 26.67 24.67 - 28.67
UK LT Inverse 120.00 114.00 - 126.00
IEEE M Inverse 3.8 3.61 - 4.0
IEEE V Inverse 7.03 6.68 - 7.38
IEEE E Inverse 9.50 9.02 - 9.97
US Inverse 2.16 2.05 - 2.27
US ST Inverse 12.12 11.51 - 12.73
Note:
With the exception of the definite time characteristic, the operating times given are for a Time Multiplier Setting (TMS) or Time
Dial Setting (TDS) of 1. For other values of TMS or TDS, the values need to be modified accordingly.
Note:
For definite time and inverse characteristics there is an additional delay of up to 0.02 second and 0.08 second respectively.
You may need to add this the IED's acceptable range of operating times.
Caution:
On completion of the tests, you must restore all settings to customer specifications.
P841B-TM-EN-1.1 459
9 SYSTEM CHECK AND CHECK SYNCHRONISM

This function performs a comparison between the line voltage and the bus voltage.
For a single circuit breaker application, there are two voltage inputs to compare:
● one from the voltage transformer input from the line side of the circuit breaker (Main VT)
● one from the VT on the bus side of the circuit breaker (CS VT).
For a dual circuit breaker installation (breaker-and-a-half switch or mesh/ring bus), three VT inputs are required:
● one from the common point of the two circuit breakers, identified as the line (Main VT)
● one from the bus side of CB1 (CB1 CS VT)
● one from the bus side of CB2 (CB2 CS VT)
In most cases the line VT input is three phase, whereas the bus VTs are single phase.
The bus VT inputs are normally single phase so the system voltage checks are made on single phases and the VT
may be connected to either a phase-to-phase or phase to neutral voltage.
For these reasons, the IED has to be programmed with the appropriate connection. The CS Input setting in the CT
AND VT RATIOS column can be set to A-N, B-N, C-N, A-B, B-C or C-A according to the application.
The single-phase bus VT inputs each have associated phase shift and voltage magnitude compensation settings
to compensate for healthy voltage angle and magnitude differences between the check sync VT input and the
selected main VT reference phase. These are:
● CB1 CS VT PhShft, CB1 CS VT Mag, CB2 CS VT PhShft, CB2 CS VT Mag
Any voltage measurements or comparisons using bus VT inputs are made using the compensated values.
Each circuit breaker controlled can have two stages of check synchronism enabled according to the settings:
● Sys Checks CB1, CB1 CS1 Status, CB1 CS2 Status, Sys Checks CB2, CB2 CS1 Status, CB1 CS2 Status
When the system voltage check conditions are satisfied, the relevant DDB signals are asserted high as follows:
● DDB (883): CB1 CS1 OK
● DDB (884): CB1 CS2 OK
● DDB (1577): CB2 CS1 OK
● DDB (1463): CB2 CS2 OK
These DDB signals should be mapped to the monitor/download port and used to indicate that the system check
synchronism condition has been satisfied.
9.1 CHECK SYNCHRONISM PASS

1. Taking note of the check synchronism settings, identify the appropriate VT input terminals and inject voltage
signals that should satisfy the system voltage check synchronism criteria.
2. Check that the DDB signals are asserted high.
9.2 CHECK SYNCHRONISM FAIL

1. Change the voltage signals so that the criteria are not satisfied
2. Check that the appropriate DDB signals are driven low
460 P841B-TM-EN-1.1
10 CHECK TRIP AND AUTORECLOSE CYCLE

If the auto-reclose function is being used, the circuit breaker trip and auto reclose cycle can be tested
automatically by using the application-specific settings.
To test the trip and close operation without operating the breaker, the following conditions must be satisfied:
● The CB Healthy DDB signal should either not be mapped, or if it is mapped it must be asserted high.
● The CB status inputs (52A, etc.) should either not be mapped, or if they are mapped they should be activated
to mimic the circuit breaker operation.
● Some models can be configured for single-pole tripping. If configured for single pole tripping, either set
CT/VT RATIO > VT Connected to No, or apply appropriate voltage signals to prevent the pole dead logic from
converting to 3-pole tripping.
1. To test the first three-phase auto-reclose cycle, set COMMISSION TESTS > Test Autoreclose to Trip 3
Pole. The IED performs a trip/reclose cycle.
2. Repeat this operation to test the subsequent three-phase auto-reclose cycles.
3. Check all output relays (used for such as circuit breaker tripping and closing, or blocking other devices)
operate at the correct times during the trip/close cycle.
Check the auto-reclose cycles for single phase trip conditions one at a time by sequentially setting COMMISSION
TESTS > Test Autoreclose to Trip Pole A, Trip Pole B and Trip Pole C.
P841B-TM-EN-1.1 461
11 ONLOAD CHECKS
Warning:
Onload checks are potentially very dangerous and may only be carried out by
qualified and authorised personnel.
Onload checks can only be carried out if there are no restrictions preventing the energisation of the plant, and the
other devices in the group have already been commissioned.
Remove all test leads and temporary shorting links, then replace any external wiring that has been removed to
allow testing.
Warning:
If any external wiring has been disconnected for the commissioning process, replace
it in accordance with the relevant external connection or scheme diagram.
11.1 CONFIRM VOLTAGE CONNECTIONS

1. Using a multimeter, measure the voltage transformer secondary voltages to ensure they are correctly rated.
2. Check that the system phase rotation is correct using a phase rotation meter.
3. Compare the values of the secondary phase voltages with the measured voltage magnitude values, which
can be found in the MEASUREMENTS 1 menu column.
Cell in MEASUREMENTS 1 Column Corresponding VT ratio in CT/VT RATIOS column

VAB MAGNITUDE
VBC MAGNITUDE
VCA MAGNITUDE
Main VT Primary / Main VT Sec'y
VAN MAGNITUDE
VBN MAGNITUDE
VCN MAGNITUDE
C/S Voltage Mag CS VT Primary / CS VT Secondary
If the Local Values cell is set to Secondary, the values displayed should be equal to the applied secondary
voltage. The values should be within 1% of the applied secondary voltages. However, an additional allowance must
be made for the accuracy of the test equipment being used.
If the Local Values cell is set to Primary, the values displayed should be equal to the applied secondary voltage
multiplied the corresponding voltage transformer ratio set in the CT & VT RATIOS column. The values should be
within 1% of the expected values, plus an additional allowance for the accuracy of the test equipment being used.
11.2 CONFIRM CURRENT CONNECTIONS

1. Measure the current transformer secondary values for each input either by:
a. reading from the device's HMI panel (providing it has first been verified by a secondary injection test)
b. using a current clamp meter
2. Check that the current transformer polarities are correct by measuring the phase angle between the
current and voltage, either against a phase meter already installed on site and known to be correct or by
determining the direction of power flow by contacting the system control centre.
3. Ensure the current flowing in the neutral circuit of the current transformers is negligible.
462 P841B-TM-EN-1.1
If the Local Values cell is set to Secondary, the values displayed should be equal to the applied secondary
voltage. The values should be within 1% of the applied secondary voltages. However, an additional allowance must
be made for the accuracy of the test equipment being used.
If the Local Values cell is set to Primary, the values displayed should be equal to the applied secondary voltage
multiplied the corresponding voltage transformer ratio set in the CT & VT RATIOS column. The values should be
within 1% of the expected values, plus an additional allowance for the accuracy of the test equipment being used.
11.3 ON-LOAD DIRECTIONAL TEST

This test ensures that directional overcurrent and fault locator functions have the correct forward/reverse
response to fault and load conditions. For this test you must first know the actual direction of power flow on the
system. If you do not already know this you must determine it using adjacent instrumentation or protection
already in-service.
● For load current flowing in the Forward direction (power export to the remote line end), the A Phase Watts
cell in the MEASUREMENTS 2 column should show positive power signing.
● For load current flowing in the Reverse direction (power import from the remote line end), the A Phase
Watts cell in the MEASUREMENTS 2 column should show negative power signing.
Note:
This check applies only for Measurement Modes 0 (default), and 2. This should be checked in the MEASURE’T SETUP column
(Measurement Mode = 0 or 2). If measurement modes 1 or 3 are used, the expected power flow signing would be opposite to
that shown above.
In the event of any uncertainty, check the phase angle of the phase currents with respect to their phase voltage.
P841B-TM-EN-1.1 463
12 FINAL CHECKS
1. Remove all test leads and temporary shorting leads.
2. If you have had to disconnect any of the external wiring in order to perform the wiring verification tests,
replace all wiring, fuses and links in accordance with the relevant external connection or scheme diagram.
3. The settings applied should be carefully checked against the required application-specific settings to ensure
that they are correct, and have not been mistakenly altered during testing.
4. Ensure that all protection elements required have been set to Enabled in the CONFIGURATION column.
5. Ensure that the IED has been restored to service by checking that the Test Mode cell in the COMMISSION
TESTS column is set to Disabled.
6. If the IED is in a new installation or the circuit breaker has just been maintained, the circuit breaker
maintenance and current counters should be zero. These counters can be reset using the Reset All Values
cell. If the required access level is not active, the device will prompt for a password to be entered so that the
setting change can be made.
7. If the menu language has been changed to allow accurate testing it should be restored to the customer’s
preferred language.
8. If a P991/MMLG test block is installed, remove the P992/MMLB test plug and replace the cover so that the
protection is put into service.
9. Ensure that all event records, fault records, disturbance records, alarms and LEDs and communications
statistics have been reset.
Note:
Remember to restore the language setting to the customer’s preferred language on completion.
464 P841B-TM-EN-1.1
CHAPTER 20
MAINTENANCE AND TROUBLESHOOTING

Chapter 20 - Maintenance and Troubleshooting P841B
466 P841B-TM-EN-1.1
P841B Chapter 20 - Maintenance and Troubleshooting
1 CHAPTER OVERVIEW
The Maintenance and Troubleshooting chapter provides details of how to maintain and troubleshoot products
based on the Px4x and P40Agile platforms. Always follow the warning signs in this chapter. Failure to do so may
result injury or defective equipment.
Caution:
contents of the Safety Section or the Safety Guide SFTY/4LM and the ratings on the
The troubleshooting part of the chapter allows an error condition on the IED to be identified so that appropriate
corrective action can be taken.
If the device develops a fault, it is usually possible to identify which module needs replacing. It is not possible to
perform an on-site repair to a faulty module.
If you return a faulty unit or module to the manufacturer or one of their approved service centres, you should
include a completed copy of the Repair or Modification Return Authorization (RMA) form.
Maintenance 468
Troubleshooting 476
P841B-TM-EN-1.1 467
2 MAINTENANCE
2.1 MAINTENANCE CHECKS

In view of the critical nature of the application, General Electric products should be checked at regular intervals to
confirm they are operating correctly. General Electric products are designed for a life in excess of 20 years.
The devices are self-supervising and so require less maintenance than earlier designs of protection devices. Most
problems will result in an alarm, indicating that remedial action should be taken. However, some periodic tests
should be carried out to ensure that they are functioning correctly and that the external wiring is intact. It is the
responsibility of the customer to define the interval between maintenance periods. If your organisation has a
Preventative Maintenance Policy, the recommended product checks should be included in the regular program.
Maintenance periods depend on many factors, such as:
● The operating environment
● The accessibility of the site
● The amount of available manpower
● The importance of the installation in the power system
● The consequences of failure
Although some functionality checks can be performed from a remote location, these are predominantly restricted
to checking that the unit is measuring the applied currents and voltages accurately, and checking the circuit
breaker maintenance counters. For this reason, maintenance checks should also be performed locally at the
substation.
Caution:
contents of the Safety Section or the Safety Guide SFTY/4LM and the ratings on the
2.1.1 ALARMS
First check the alarm status LED to see if any alarm conditions exist. If so, press the Read key repeatedly to step
through the alarms.
After dealing with any problems, clear the alarms. This will clear the relevant LEDs.
2.1.2 OPTO-ISOLATORS
Check the opto-inputs by repeating the commissioning test detailed in the Commissioning chapter.
2.1.3 OUTPUT RELAYS

Check the output relays by repeating the commissioning test detailed in the Commissioning chapter.
2.1.4 MEASUREMENT ACCURACY

If the power system is energised, the measured values can be compared with known system values to check that
they are in the expected range. If they are within a set range, this indicates that the A/D conversion and the
calculations are being performed correctly. Suitable test methods can be found in Commissioning chapter.
Alternatively, the measured values can be checked against known values injected into the device using the test
block, (if fitted) or injected directly into the device's terminals. Suitable test methods can be found in the
Commissioning chapter. These tests will prove the calibration accuracy is being maintained.
468 P841B-TM-EN-1.1
2.2 REPLACING THE DEVICE

If your product should develop a fault while in service, depending on the nature of the fault, the watchdog
contacts will change state and an alarm condition will be flagged. In the case of a fault, you can replace either the
complete device or just the faulty PCB, identified by the in-built diagnostic software.
If possible you should replace the complete device, as this reduces the chance of damage due to electrostatic
discharge and also eliminates the risk of fitting an incompatible replacement PCB. However, we understand it may
be difficult to remove an installed product and you may be forced to replace the faulty PCB on-site. The case and
rear terminal blocks are designed to allow removal of the complete device, without disconnecting the scheme
wiring.
Caution:
Replacing PCBs requires the correct on-site environment (clean and dry) as well as
suitably trained personnel.
Caution:
If the repair is not performed by an approved service centre, the warranty will be
invalidated.
Caution:
Before carrying out any work on the equipment, you should be familiar with the
contents of the Safety Information section of this guide or the Safety Guide SFTY/4LM,
as well as the ratings on the equipment’s rating label. This should ensure that no
damage is caused by incorrect handling of the electronic components.
Warning:
Before working at the rear of the device, isolate all voltage and current supplying it.
Note:
The current transformer inputs are equipped with integral shorting switches which will close for safety reasons, when the
terminal block is removed.
To replace the complete device:

1. Carefully disconnect the cables not connected to the terminal blocks (e.g. IRIG-B, fibre optic cables, earth),
as appropriate, from the rear of the device.
2. Remove the terminal block screws using a magnetic screwdriver to minimise the risk of losing the screws or
leaving them in the terminal block.
3. Without exerting excessive force or damaging the scheme wiring, pull the terminal blocks away from their
internal connectors.
4. Remove the terminal block screws that fasten the device to the panel and rack. These are the screws with
the larger diameter heads that are accessible when the access covers are fitted and open.
5. Withdraw the device from the panel and rack. Take care, as the device will be heavy due to the internal
transformers.
6. To reinstall the device, follow the above instructions in reverse, ensuring that each terminal block is
relocated in the correct position and the chassis ground, IRIG-B and fibre optic connections are replaced.
The terminal blocks are labelled alphabetically with ‘A’ on the left hand side when viewed from the rear.
Once the device has been reinstalled, it should be re-commissioned as set out in the Commissioning chapter.
P841B-TM-EN-1.1 469
Caution:
If the top and bottom access covers have been removed, some more screws with
smaller diameter heads are made accessible. Do NOT remove these screws, as they
secure the front panel to the device.
Note:
There are four possible types of terminal block: RTD/CLIO input, heavy duty, medium duty, and MiDOS. The terminal blocks are
fastened to the rear panel with slotted or cross-head screws depending on the type of terminal block. Not all terminal block
types are present on all products.
Figure 186: Possible terminal block types
2.3 REPAIRING THE DEVICE

If your product should develop a fault while in service, depending on the nature of the fault, the watchdog
contacts will change state and an alarm condition will be flagged. In the case of a fault, either the complete unit or
just the faulty PCB, identified by the in-built diagnostic software, should be replaced.
Replacement of printed circuit boards and other internal components must be undertaken by approved Service
Centres. Failure to obtain the authorization of after-sales engineers prior to commencing work may invalidate the
product warranty.
We recommend that you entrust any repairs to Automation Support teams, which are available world-wide.
2.4 REMOVING THE FRONT PANEL
Warning:
Before removing the front panel to replace a PCB, you must first remove the auxiliary
power supply and wait 5 seconds for the internal capacitors to discharge. You should
also isolate voltage and current transformer connections and trip circuit.
470 P841B-TM-EN-1.1
Caution:
Before removing the front panel, you should be familiar with the contents of the Safety
Information section of this guide or the Safety Guide SFTY/4LM, as well as the ratings
on the equipment’s rating label.
To remove the front panel:

1. Open the top and bottom access covers. You must open the hinged access covers by more than 90° before
they can be removed.
2. If fitted, remove the transparent secondary front cover.
3. Apply outward pressure to the middle of the access covers to bow them and disengage the hinge lug, so the
access cover can be removed. The screws that fasten the front panel to the case are now accessible.
4. Undo and remove the screws. The 40TE case has four cross-head screws fastening the front panel to the
case, one in each corner, in recessed holes. The 60TE/80TE cases have an additional two screws, one
midway along each of the top and bottom edges of the front plate.
5. When the screws have been removed, pull the complete front panel forward to separate it from the metal
case. The front panel is connected to the rest of the circuitry by a 64-way ribbon cable.
6. The ribbon cable is fastened to the front panel using an IDC connector; a socket on the cable and a plug
with locking latches on the front panel. Gently push the two locking latches outwards which eject the
connector socket slightly. Remove the socket from the plug to disconnect the front panel.
Caution:
Do not remove the screws with the larger diameter heads which are accessible when
the access covers are fitted and open. These screws hold the relay in its mounting
(panel or cubicle).
Caution:
The internal circuitry is now exposed and is not protected against electrostatic
discharge and dust ingress. Therefore ESD precautions and clean working conditions
must be maintained at all times.
2.5 REPLACING PCBS

1. To replace any of the PCBs, first remove the front panel.
2. Once the front panel has been removed, the PCBs are accessible. The numbers above the case outline
identify the guide slot reference for each printed circuit board. Each printed circuit board has a label stating
the corresponding guide slot number to ensure correct relocation after removal. To serve as a reminder of
the slot numbering there is a label on the rear of the front panel metallic screen.
3. Remove the 64-way ribbon cable from the PCB that needs replacing
4. Remove the PCB in accordance with the board-specific instructions detailed later in this section.
Note:
To ensure compatibility, always replace a faulty PCB with one of an identical part number.
2.5.1 REPLACING THE MAIN PROCESSOR BOARD

The main processor board is situated in the front panel. This board contains application-specific settings in its non-
volatile memory. You may wish to take a backup copy of these settings. This could save time in the re-
commissioning process.
P841B-TM-EN-1.1 471
To replace the main processor board:

1. Remove front panel.
2. Place the front panel with the user interface face down and remove the six screws from the metallic screen,
as shown in the figure below. Remove the metal plate.
3. Remove the two screws either side of the rear of the battery compartment recess. These are the screws
that hold the main processor board in position.
4. Carefully disconnect the ribbon cable. Take care as this could easily be damaged by excessive twisting.
5. Replace the main processor board
6. Reassemble the front panel using the reverse procedure. Make sure the ribbon cable is reconnected to the
main processor board and that all eight screws are refitted.
7. Refit the front panel.
8. Refit and close the access covers then press the hinge assistance T-pieces so they click back into the front
panel moulding.
9. Once the unit has been reassembled, carry out the standard commissioning procedure as defined in the
Commissioning chapter.
Note:
After replacing the main processor board, all the settings required for the application need to be re-entered. This may be done
either manually or by downloading a settings file.
V01601
Figure 187: Front panel assembly
2.5.2 REPLACEMENT OF COMMUNICATIONS BOARDS

Most products will have at least one communications board of some sort fitted. There are several different boards
available offering various functionality, depending on the application. Some products may even be fitted two
boards of different types.
To replace a faulty communications board:
2. Disconnect all connections at the rear.
3. The board is secured in the relay case by two screws, one at the top and another at the bottom. Remove
these screws carefully as they are not captive in the rear panel.
4. Gently pull the communications board forward and out of the case.
5. Before fitting the replacement PCB check that the number on the round label next to the front edge of the
PCB matches the slot number into which it will be fitted. If the slot number is missing or incorrect, write the
correct slot number on the label.
472 P841B-TM-EN-1.1
6. Fit the replacement PCB carefully into the correct slot. Make sure it is pushed fully back and that the
securing screws are refitted.
7. Reconnect all connections at the rear.
panel moulding.
10. Once the unit has been reassembled, commission it according to the Commissioning chapter.
2.5.3 REPLACEMENT OF THE INPUT MODULE

Depending on the product, the input module consists of two or three boards fastened together and is contained
within a metal housing. One board contains the transformers and one contains the analogue to digital conversion
and processing electronics. Some devices have an additional auxiliary transformer contained on a third board.
To replace an input module:
2. The module is secured in the case by two screws on its right-hand side, accessible from the front, as shown
below. Move these screws carefully as they are not captive in the front plate of the module.
3. On the right-hand side of the module there is a small metal tab which brings out a handle (on some
modules there is also a tab on the left). Grasp the handle(s) and pull the module firmly forward, away from
the rear terminal blocks. A reasonable amount of force is needed due to the friction between the contacts of
the terminal blocks.
4. Remove the module from the case. The module may be heavy, because it contains the input voltage and
current transformers.
5. Slot in the replacement module and push it fully back onto the rear terminal blocks. To check that the
module is fully inserted, make sure the v-shaped cut-out in the bottom plate of the case is fully visible.
6. Refit the securing screws.
panel moulding.
Caution:
With non-mounted IEDs, the case needs to be held firmly while the module is
withdrawn. Withdraw the input module with care as it suddenly comes loose once the
friction of the terminal blocks is overcome.
Note:
If individual boards within the input module are replaced, recalibration will be necessary. We therefore recommend
replacement of the complete module to avoid on-site recalibration.
2.5.4 REPLACEMENT OF THE POWER SUPPLY BOARD
Caution:
Before removing the front panel, you should be familiar with the contents of the Safety
Information section of this guide or the Safety Guide SFTY/4LM, as well as the ratings
on the equipment’s rating label.
P841B-TM-EN-1.1 473
The power supply board is fastened to an output relay board with push fit nylon pillars. This doubled-up board is
secured on the extreme left hand side, looking from the front of the unit.
2. Pull the power supply module forward, away from the rear terminal blocks and out of the case. A
reasonable amount of force is needed due to the friction between the contacts of the terminal blocks.
3. Separate the boards by pulling them apart carefully. The power supply board is the one with two large
electrolytic capacitors.
4. Before reassembling the module, check that the number on the round label next to the front edge of the
PCB matches the slot number into which it will be fitted. If the slot number is missing or incorrect, write the
correct slot number on the label
5. Reassemble the module with a replacement PCB. Push the inter-board connectors firmly together. Fit the
four push fit nylon pillars securely in their respective holes in each PCB.
6. Slot the power supply module back into the housing. Push it fully back onto the rear terminal blocks.
panel moulding.
2.5.5 REPLACEMENT OF THE I/O BOARDS

There are several different types of I/O boards, which can be used, depending on the product and application.
Some boards have opto-inputs, some have relay outputs and others have a mixture of both.
2. Gently pull the board forward and out of the case
3. If replacing the I/O board, make sure the setting of the link above IDC connector on the replacement board
is the same as the one being replaced.
4. Before fitting the replacement board check the number on the round label next to the front edge of the
board matches the slot number into which it will be fitted. If the slot number is missing or incorrect, write
the correct slot number on the label.
5. Carefully slide the replacement board into the appropriate slot, ensuring that it is pushed fully back onto the
rear terminal blocks.
7. Refit and close the access covers then press at the hinge assistance T-pieces so they click back into the
front panel moulding.
2.6 RECALIBRATION
Recalibration is not needed when a PCB is replaced, unless it is one of the boards in the input module. If any of the
boards in the input module is replaced, the unit must be recalibrated.
Although recalibration is needed when a board inside the input module is replaced, it is not needed if the input
module is replaced in its entirety.
Although it is possible to carry out recalibration on site, this requires special test equipment and software. We
therefore recommend that the work be carried out by the manufacturer, or entrusted to an approved service
centre.
2.7 CHANGING THE BATTERY

Each IED has a battery to maintain status data and the correct time when the auxiliary supply voltage fails. The
data maintained includes event, fault and disturbance records and the thermal state at the time of failure.
474 P841B-TM-EN-1.1
As part of the product's continuous self-monitoring, an alarm is given if the battery condition becomes poor.
Nevertheless, you should change the battery periodically to ensure reliability.
To replace the battery:
1. Open the bottom access cover on the front of the relay.
2. Gently remove the battery. If necessary, use a small insulated screwdriver.
3. Make sure the metal terminals in the battery socket are free from corrosion, grease and dust.
4. Remove the replacement battery from its packaging and insert it in the battery holder, ensuring correct
polarity.
5. Ensure that the battery is held securely in its socket and that the battery terminals make good contact with
the socket terminals.
6. Close the bottom access cover.
Caution:
Only use a type ½AA Lithium battery with a nominal voltage of 3.6 V and safety
approvals such as UL (Underwriters Laboratory), CSA (Canadian Standards Association)
or VDE (Vereinigung Deutscher Elektrizitätswerke).
Note:
Events, disturbance and maintenance records will be lost if the battery is replaced whilst the IED is de-energised.
2.7.1 POST MODIFICATION TESTS

To ensure that the replacement battery maintains the time and status data if the auxiliary supply fails, scroll across
to the DATE AND TIME cell, then scroll down to Battery Status which should read Healthy.
2.7.2 BATTERY DISPOSAL

Dispose of the removed battery according to the disposal procedure for Lithium batteries in the country in which
the relay is installed.
2.8 CLEANING
Warning:
Before cleaning the device, ensure that all AC and DC supplies and transformer
connections are isolated, to prevent any chance of an electric shock while cleaning.
Only clean the equipment with a lint-free cloth dampened with clean water. Do not use detergents, solvents or
abrasive cleaners as they may damage the product's surfaces and leave a conductive residue.
P841B-TM-EN-1.1 475
3 TROUBLESHOOTING
3.1 SELF-DIAGNOSTIC SOFTWARE

The device includes several self-monitoring functions to check the operation of its hardware and software while in
service. If there is a problem with the hardware or software, it should be able to detect and report the problem, and
attempt to resolve the problem by performing a reboot. In this case, the device would be out of service for a short
time, during which the ‘Healthy’ LED on the front of the device is switched OFF and the watchdog contact at the
rear is ON. If the restart fails to resolve the problem, the unit takes itself permanently out of service; the ‘Healthy’
LED stays OFF and watchdog contact stays ON.
If a problem is detected by the self-monitoring functions, the device attempts to store a maintenance record to
allow the nature of the problem to be communicated to the user.
The self-monitoring is implemented in two stages: firstly a thorough diagnostic check which is performed on boot-
up, and secondly a continuous self-checking operation, which checks the operation of the critical functions whilst
it is in service.
3.2 POWER-UP ERRORS

If the IED does not appear to power up, use the following to determine whether the fault is in the external wiring,
auxiliary fuse, IED power supply module or IED front panel.
Test Check Action
Measure the auxiliary voltage on terminals 1 and 2.
Verify the voltage level and polarity against the rating If the auxiliary voltage is correct, go to test 2. Otherwise check the wiring
1
label on the front. and fuses in the auxiliary supply.
Terminal 1 is –dc, 2 is +dc
If the LEDs and LCD backlight switch on, or the contact closes and no error
Check the LEDs and LCD backlight switch on at code is displayed, the error is probably on the main processor board in the
2 power-up. Also check the N/O (normally open) front panel.
watchdog contact for closing. If the LEDs and LCD backlight do not switch on and the contact does not
close, go to test 3.
If there is no field voltage, the fault is probably in the IED power supply
3 Check the output (nominally 48 V DC)
module.
3.3 ERROR MESSAGE OR CODE ON POWER-UP

The IED performs a self-test during power-up. If it detects an error, a message appears on the LCD and the power-
up sequence stops. If the error occurs when the IED application software is running, a maintenance record is
created and the device reboots.
Test Check Action
If the IED locks up and displays an error code permanently, go to test 2.
Is an error message or code permanently displayed
1 If the IED prompts for user input, go to test 4.
during power up?
If the IED reboots automatically, go to test 5.
Record whether the same error code is displayed when the IED is
Record displayed error, and then remove and re-apply rebooted. If no error code is displayed, contact the local service centre
2
IED auxiliary supply. stating the error code and IED information. If the same code is
displayed, go to test 3.
476 P841B-TM-EN-1.1
Test Check Action

Error Code Identification
The following text messages (in English) are displayed if a
These messages indicate that a problem has been detected on the IED’s
fundamental problem is detected, preventing the system
main processor board in the front panel.
from booting:
Bus Fail – address lines
3 SRAM Fail – data lines
FLASH Fail format error
FLASH Fail checksum
Code Verify Fail
The following hex error codes relate to errors detected in
specific IED modules:
3.1 0c140005/0c0d0000 Input Module (including opto-isolated inputs)
3.2 0c140006/0c0e0000 Output IED Cards
Other error codes relate to hardware or software problems on the main
3.3 The last four digits provide details on the actual error.
processor board. Contact with details of the problem for a full analysis.
The IED displays a message for corrupt settings and The power-up tests have detected corrupted IED settings. Restore the
4 prompts for the default values to be restored for the default settings to allow the power-up to complete, and then reapply
affected settings. the application-specific settings.
Error 0x0E080000, programmable scheme logic error due to excessive
execution time. If the IED powers up successfully, check the
The IED resets when the power-up is complete. A record
5 programmable logic for feedback paths.
error code is displayed
Other error codes relate to software errors on the main processor
board.
3.4 OUT OF SERVICE LED ON AT POWER-UP
Test Check Action

Using the IED menu, confirm the Commission Test or Test If the setting is Enabled, disable the test mode and make sure the Out of
1
Mode setting is Enabled. If it is not Enabled, go to test 2. Service LED is OFF.
Check for the H/W Verify Fail maintenance record. This indicates a
discrepancy between the IED model number and the hardware. Examine
Select the VIEW RECORDS column then view the last
2 the Maint Data; cell. This indicates the causes of the failure using bit
maintenance record from the menu.
fields:
Bit Meaning
The application type field in the model number does not
0
match the software ID
The application field in the model number does not match
1
the software ID
The variant 1 field in the model number does not match the
2
software ID
The variant 2 field in the model number does not match the
3
software ID
The protocol field in the model number does not match the
4
software ID
The language field in the model number does not match the
5
software ID
The VT type field in the model number is incorrect (110 V VTs
6
fitted)
The VT type field in the model number is incorrect (440 V VTs
7
fitted)
The VT type field in the model number is incorrect (no VTs
8
fitted)
P841B-TM-EN-1.1 477
3.5 ERROR CODE DURING OPERATION

The IED performs continuous self-checking. If the IED detects an error it displays an error message, logs a
maintenance record and after a short delay resets itself. A permanent problem (for example due to a hardware
fault) is usually detected in the power-up sequence. In this case the IED displays an error code and halts. If the
problem was transient, the IED reboots correctly and continues operation. By examining the maintenance record
logged, the nature of the detected fault can be determined.
3.5.1 BACKUP BATTERY

If the IED’s self-check detects a failure of the lithium battery, the IED displays an alarm message and logs a
maintenance record but the IED does not reset.
To prevent the IED from issuing an alarm when there is a battery failure, select DATE AND TIME then Battery Alarm
then Disabled. The IED can then be used without a battery and no battery alarm message appears.
3.6 MAL-OPERATION DURING TESTING
3.6.1 FAILURE OF OUTPUT CONTACTS

An apparent failure of the relay output contacts can be caused by the configuration. Perform the following tests to
identify the real cause of the failure. The self-tests verify that the coils of the output relay contacts have been
energized. An error is displayed if there is a fault in the output relay board.
Test Check Action
If this LED is ON, the relay may be in test mode or the protection has
1 Is the Out of Service LED ON?
been disabled due to a hardware verify error.
Examine the Contact status in the Commissioning If the relevant bits of the contact status are operated, go to test 4; if not,
2
section of the menu. go to test 3.
If the protection element does not operate, check the test is correctly
Examine the fault record or use the test port to check the applied.
3
protection element is operating correctly. If the protection element operates, check the programmable logic to
make sure the protection element is correctly mapped to the contacts.
Using the Commissioning or Test mode function, apply a If the output relay operates, the problem must be in the external wiring
test pattern to the relevant relay output contacts. to the relay. If the output relay does not operate the output relay
4 Consult the correct external connection diagram and use contacts may have failed (the self-tests verify that the relay coil is being
a continuity tester at the rear of the relay to check the energized). Ensure the closed resistance is not too high for the continuity
relay output contacts operate. tester to detect.
3.6.2 FAILURE OF OPTO-INPUTS

The opto-isolated inputs are mapped onto the IED's internal DDB signals using the programmable scheme logic. If
an input is not recognised by the scheme logic, use the Opto I/P Status cell in the COMMISSION TESTS column to
check whether the problem is in the opto-input itself, or the mapping of its signal to the scheme logic functions.
If the device does not correctly read the opto-input state, test the applied signal. Verify the connections to the
opto-input using the wiring diagram and the nominal voltage settings in the OPTO CONFIG column. To do this:
1. Select the nominal voltage for all opto-inputs by selecting one of the five standard ratings in the Global
Nominal V cell.
2. Select Custom to set each opto-input individually to a nominal voltage.
3. Using a voltmeter, check that the voltage on its input terminals is greater than the minimum pick-up level
(See the Technical Specifications chapter for opto pick-up levels).
If the signal is correctly applied, this indicates failure of an opto-input, which may be situated on standalone opto-
input board, or on an opto-input board that is part of the input module. Separate opto-input boards can simply be
replaced. If, however, the faulty opto-input board is part of the input module, the complete input module should be
478 P841B-TM-EN-1.1
replaced. This is because the analogue input module cannot be individually replaced without dismantling the
module and recalibration of the IED.
3.6.3 INCORRECT ANALOGUE SIGNALS

If the measured analogue quantities do not seem correct, use the measurement function to determine the type of
problem. The measurements can be configured in primary or secondary terms.
1. Compare the displayed measured values with the actual magnitudes at the terminals.
2. Check the correct terminals are used.
3. Check the CT and VT ratios set are correct.
4. Check the phase displacement to confirm the inputs are correctly connected.
3.7 COPROCESSOR BOARD FAILURES

If a coprocessor board is used, this may cause the IED to report one or more of the following alarms:
● Signalling failure alarm (on its own)
● C diff failure (on its own)
● Signalling failure and C diff failure together
● Incompatible IED
● Comms changed
● IEEE C37.94 fail
3.7.1 SIGNALLING FAILURE ALARM (ON ITS OWN)

This indicates that there is a problem with one of the fibre-optic signalling channels. This alarm can occur in dual
redundant or three terminal schemes. The fibre may have been disconnected, the device may have been
incorrectly configured at one of the ends, or there is a problem with the communications equipment. Further
information about the status of the signalling channels can be found in MEASUREMENTS 4 column.
3.7.2 C DIFF FAILURE ALARM (ON ITS OWN)

This indicates there is a problem with the Coprocessor board. As a result the current differential/distance
protection is not available and backup protection will operate, if configured to do so. Further information can be
found in the maintenance records.
3.7.3 SIGNALLING FAILURE AND C DIFF FAILURE ALARMS TOGETHER

This indicates that there is a problem with one or both fibre-optic signalling channels. The fibre may have been
disconnected, the device may have been incorrectly configured at one of the ends, or there is a problem with the
communications equipment. As a result the current differential protection is not available and backup protection
will operate, if configured to do so. Further information about the status of the signalling channels can be found in
MEASUREMENTS 4 column.
3.7.4 INCOMPATIBLE IED

This occurs if the IEDs trying to communicate with each other are of incompatible types.
3.7.5 COMMS CHANGED

This indicates that the Comms Mode setting has been changed without a subsequent power off and on.
P841B-TM-EN-1.1 479
3.7.6 IEEE C37.94 FAIL

This indicates a Signal Lost, a Path Yellow (indicating a fault on the communications channel) or a mismatch in the
number of N*64 channels used on either channel 1 or channel 2. Further information can be found in the
MEASUREMENTS 4 column.
3.8 PSL EDITOR TROUBLESHOOTING

A failure to open a connection could be due to one or more of the following:
● The IED address is not valid (this address is always 1 for the front port)
● Password in not valid
● Communication set-up (COM port, Baud rate, or Framing) is not correct
● Transaction values are not suitable for the IED or the type of connection
● The connection cable is not wired correctly or broken
● The option switches on any protocol converter used may be incorrectly set
3.8.1 DIAGRAM RECONSTRUCTION

Although a scheme can be extracted from an IED, a facility is provided to recover a scheme if the original file is
unobtainable.
A recovered scheme is logically correct but much of the original graphical information is lost. Many signals are
drawn in a vertical line down the left side of the canvas. Links are drawn orthogonally using the shortest path from
A to B. Any annotation added to the original diagram such as titles and notes are lost.
Sometimes a gate type does not appear as expected. For example, a single-input AND gate in the original scheme
appears as an OR gate when uploaded. Programmable gates with an inputs-to-trigger value of 1 also appear as
OR gates
3.8.2 PSL VERSION CHECK

The PSL is saved with a version reference, time stamp and CRC check (Cyclic Redundancy Check). This gives a
visual check whether the default PSL is in place or whether a new application has been downloaded.
3.9 REPAIR AND MODIFICATION PROCEDURE

Please follow these steps to return an Automation product to us:
1. Get the Repair and Modification Return Authorization (RMA) form
An electronic version of the RMA form is available from the following:
2. Fill in the RMA form
Fill in only the white part of the form.
Please ensure that all fields marked (M) are completed such as:
○ Equipment model
○ Model No. and Serial No.
○ Description of failure or modification required (please be specific)
○ Value for customs (in case the product requires export)
○ Delivery and invoice addresses
○ Contact details
480 P841B-TM-EN-1.1
3. Send the RMA form to your local contact

For a list of local service contacts worldwide, email us at:
4. The local service contact provides the shipping information
Your local service contact provides you with all the information needed to ship the product:
○ Pricing details
○ RMA number
○ Repair centre address
If required, an acceptance of the quote must be delivered before going to the next stage.
5. Send the product to the repair centre
○ Address the shipment to the repair centre specified by your local contact
○ Make sure all items are packaged in an anti-static bag and foam protection
○ Make sure a copy of the import invoice is attached with the returned unit
○ Make sure a copy of the RMA form is attached with the returned unit
○ E-mail or fax a copy of the import invoice and airway bill document to your local contact.
P841B-TM-EN-1.1 481
482 P841B-TM-EN-1.1
CHAPTER 21
TECHNICAL SPECIFICATIONS
Chapter 21 - Technical Specifications P841B
484 P841B-TM-EN-1.1
P841B Chapter 21 - Technical Specifications
1 CHAPTER OVERVIEW
This chapter describes the technical specifications of the product.
Interfaces 486
Protection Functions 490
Monitoring, Control and Supervision 494
Measurements and Recording 496
Ratings 497
Input / Output Connections 500
Mechanical Specifications 502
Type Tests 503
Environmental Conditions 504
Electromagnetic Compatibility 505
Standards Compliance 508
P841B-TM-EN-1.1 485
2 INTERFACES
2.1 FRONT SERIAL PORT
Front serial port (SK1)

Use For local connection to laptop for configuration purposes
Standard EIA(RS)232
Designation SK1
Connector 9 pin D-type female connector
Isolation Isolation to ELV level
Protocol Courier
Constraints Maximum cable length 15 m
2.2 DOWNLOAD/MONITOR PORT
Front download port (SK2)

Use For firmware downloads or monitor connection
Standard Compatible with IEEE1284-A
Designation SK2
Isolation Isolation to ELV level
Protocol Proprietary
2.3 REAR SERIAL PORT 1
Rear serial port 1 (RP1)

Use For SCADA communications (multi-drop)
Standard EIA(RS)485, K-bus
Connector General purpose block, M4 screws (2 wire)
Cable Screened twisted pair (STP)
Supported Protocols * Courier, IEC-60870-5-103, DNP3.0, MODBUS
Isolation Isolation to SELV level
* Not all models support all protocols - see ordering options
2.4 FIBRE REAR SERIAL PORT 1
Optional fibre rear serial port (RP1)

Main Use Serial SCADA communications over fibre
Connector IEC 874-10 BFOC 2.5 –(ST®) (1 each for Tx and Rx)
Fibre type Multimode 50/125 µm or 62.5/125 µm
Supported Protocols Courier, IEC870-5-103, DNP 3.0, MODBUS
Wavelength 850 nm
486 P841B-TM-EN-1.1
2.5 REAR SERIAL PORT 2
Optional rear serial port (RP2)

Use For SCADA communications (multi-drop)
Standard EIA(RS)485, K-bus, EIA(RS)232
Designation SK4
Supported Protocols Courier
Constraints Maximum cable length 1000 m for RS485 and K-bus, 15 m for RS232
2.6 OPTIONAL REAR SERIAL PORT (SK5)
Optional rear serial port for teleprotection

Use For teleprotection in distance products
Standard EIA(RS)232
Designation SK5
Supported Protocols InterMiCOM (IM)
2.7 IRIG-B (DEMODULATED)
IRIG-B Interface (Demodulated)

Use External clock synchronisation signal
Standard IRIG 200-98 format B00X
Connector BNC
Cable type 50 ohm coaxial
Input signal TTL level
Input impedance 10 k ohm at dc
Accuracy +/- 1 ms
2.8 IRIG-B (MODULATED)
IRIG-B Interface (Modulated)

Use External clock synchronisation signal
Standard IRIG 200-98 format B12X
Connector BNC
Cable type 50 ohm coaxial
P841B-TM-EN-1.1 487
IRIG-B Interface (Modulated)

Input signal peak to peak, 200 mV to 20 mV
Input impedance 6 k ohm at 1000 Hz
Accuracy +/- 1 ms
2.9 REAR ETHERNET PORT COPPER
Rear Ethernet port using CAT 5/6/7 wiring

Main Use Substation Ethernet communications
Standard IEEE 802.3 10BaseT/100BaseTX
Connector RJ45
Cable type Screened twisted pair (STP)
Isolation 1.5 kV
Supported Protocols IEC 61850, DNP3.0 OE
2.10 REAR ETHERNET PORT FIBRE
Rear Ethernet port using fibre-optic cabling

Main Use Substation Ethernet communications
Connector IEC 874-10 BFOC 2.5 –(ST®) (1 each for Tx and Rx)
Standard IEEE 802.3 100 BaseFX
Fibre type Multimode 50/125 µm or 62.5/125 µm
Supported Protocols IEC 61850, DNP3.0
Rapid spanning tree protocol (RSTP)
Self-healing protocol (SHP)
Optional Redundancy Protocols Supported
Dual homing protocol (DHP)
Parallel Redundancy Protocol (PRP)
Wavelength 1300 nm
2.10.1 100 BASE FX RECEIVER CHARACTERISTICS
Parameter Sym Min. Typ. Max. Unit

Input Optical Power Minimum at
PIN Min. (W) -33.5 –31 dBm avg.
Window Edge
Input Optical Power Minimum at
PIN Min. (C) -34.5 -31.8 Bm avg.
Eye Center
Input Optical Power Maximum PIN Max. -14 -11.8 dBm avg.
Conditions: TA = 0°C to 70°C
2.10.2 100 BASE FX TRANSMITTER CHARACTERISTICS

Output Optical Power BOL 62.5/125 µm -19
PO -16.8 -14 dBm avg.
NA = 0.275 Fibre EOL -20
Output Optical Power BOL 50/125 µm -22.5
PO -20.3 -14 dBm avg.
NA = 0.20 Fibre EOL -23.5
488 P841B-TM-EN-1.1

10 %
Optical Extinction Ratio
-10 dB
Output Optical Power at Logic "0" State PO -45 dBm avg.
Conditions: TA = 0°C to 70°C
P841B-TM-EN-1.1 489
3 PROTECTION FUNCTIONS
3.1 AUTORECLOSE AND CHECK SYNYCHRONISM
Accuracy
Timers +/- 20 ms or 2%, whichever is greater
3.2 PHASE OVERCURRENT PROTECTION
Accuracy
IDMT pick-up 1.05 x Setting +/-5%
DT pick-up Setting +/-5%
Drop-off (IDMT and DT) 0.98 x setting +/-5%
IDMT operate +/-5% of expected operating time or 40 ms, whichever is greater*
IEEE reset +/-5% or 40 ms, whichever is greater
DT operate +/-2% of setting or 40 ms, whichever is greater
DT reset Setting +/-5%
Repeatability <5%
Characteristic UK IEC 60255-3 1998
Characteristic US IEEE C37.112 1996
Note:
*Reference conditions: TMS = 1, TD = 7, I> = 1A, operating range = 2-20In
3.2.1 TRANSIENT OVERREACH AND OVERSHOOT
Additional tolerance due to increasing X/R ratios +/-5% over the X/R ratio of 1 to 90
Overshoot of overcurrent elements < 30 ms
3.2.2 PHASE OVERCURRENT DIRECTIONAL PARAMETERS
Accuracy
Directional boundary pickup (RCA +/-90%) +/-2°
Directional boundary hysteresis < 2°
Directional boundary repeatability <2%
3.3 EARTH FAULT PROTECTION
Accuracy
DT pick-up Setting +/-5%, or 20 mA, whichever is greater
Drop-off (IDMT and DT) 0.95 x setting +/-5%
IDMT Operate +/-5% or 40 ms, whichever is greater*
490 P841B-TM-EN-1.1
Accuracy
IEEE reset +/-10% or 40 ms, whichever is greater
Repeatability < 5%
DT operate +/-2% or 50 ms, whichever is greater
DT reset +/- 5% or 50 ms, whichever is greater
Note:
Reference conditions: TMS = 1, TD = 1, IN> = 1A, operating range = 2-20In.
3.3.1 EARTH FAULT DIRECTIONAL PARAMETERS
Zero Sequence Polarising accuracy

Directional boundary pick-up (RCA +/- 90°) +/-2°
Hysteresis <3°
VN> pick-up Setting+/-10%
VN> drop-off 0.9 x Setting +/-10%
Negative Sequence Polarising accuracy

Directional boundary pick-up (RCA +/- 90°) +/-2°
Hysteresis <3°
VN2> pick-up Setting+/-10%
VN2> drop-off 0.9 x Setting +/-10%
IN2> pick-up Setting+/-10%
IN2> drop-off 0.9 x Setting +/-10%
3.4 SENSITIVE EARTH FAULT PROTECTION

DT Pick-up Setting +/- 5%
Drop-off (IDMT + DT) 0.95 x Setting +/-5%
IDMT operate +/- 5% or 40 ms, whichever is greater*
DT operate +/- 2% or 50 ms, whichever is greater
DT reset Setting +/- 5% or 50 ms, whichever is greater
Repeatability < 5%
Note:
Reference conditions: TMS = 1, TD = 1, IN> setting = 100 mA with operating range of 2-20Is.
3.4.1 SENSITIVE EARTH FAULT PROTECTION DIRECTIONAL ELEMENT
Wattmetric SEF
Pick-up P = 0 W ISEF > +/-5% or 5 mA
Pick-up P > 0 W P > +/-5%
P841B-TM-EN-1.1 491
Wattmetric SEF
Drop-off P = 0 W 0.95 x ISEF> +/- 5% or 5 mA
Drop-off P > 0 W 0.9 x P> +/- 5% or 5 mA
Boundary accuracy +/-5% with hysteresis < 1°
Repeatability < 1%
3.5 HIGH IMPEDANCE RESTRICTED EARTH FAULT PROTECTION
High Impedance and Low Impedance

Pick-up Setting formula +/- 5%
Drop-off 0.8 x Setting formula +/-5%
Operating time < 60 ms
High set pick-up Setting +/- 10%
High set operating time < 30 ms
Repeatability < 5%
3.6 NEGATIVE SEQUENCE OVERCURRENT PROTECTION

DT pick-up Setting +/- 5%
Drop-off (IDMT and DT) 0.95 x Setting +/-5%
IDMT operate +/- 5% or 40 ms, whichever is greater
DT Reset Setting +/- 5%
3.6.1 NPSOC DIRECTIONAL PARAMETERS
Directional boundary pick-up (RCA +/-90%) +/-2°

Directional boundary hysteresis < 1°
Directional boundary repeatability < 1%
3.7 CIRCUIT BREAKER FAIL AND UNDERCURRENT PROTECTION
I< Pick-up Setting +/- 10% or 0.025 In, whichever is greater

I< Drop-off Setting +/- 5% or 20 mA, whichever is greater
Operate time < 12 ms
Timers +/- 2% or 20 ms, whichever is greater
Reset time < 15 ms
492 P841B-TM-EN-1.1
3.8 BROKEN CONDUCTOR PROTECTION
Pick-up Setting +/- 2.5%

Drop-off 0.95 x Setting +/- 2.5%
Reset time <25 ms
3.9 THERMAL OVERLOAD PROTECTION
Thermal alarm pick-up Calculated trip time +/- 10%

Thermal overload pick-up Calculated trip time +/- 10%
Cooling time accuracy +/- 15% of theoretical
Repeatability <5%
Note:
Operating time measured with applied current of 20% above thermal setting.
P841B-TM-EN-1.1 493
4 MONITORING, CONTROL AND SUPERVISION
4.1 VOLTAGE TRANSFORMER SUPERVISION
Fast block operation < 1 cycle

Fast block reset < 1.5 cycles
Time delay +/- 2% or 20 ms, whichever is greater
4.2 STANDARD CURRENT TRANSFORMER SUPERVISION
IN> Pick-up Setting +/- 5%

VN< Pick-up Setting +/- 5%
IN> Drop-off 0.9 x setting +/- 5%
VN< Drop-off 1.05 x setting +/-5% or 1 V, whichever is greater
Time delay operation Setting +/-2% or 20 ms, whichever is greater
CTS block operation < 1 cycle
CTS reset < 35 ms
4.3 DIFFERENTIAL CURRENT TRANSFORMER SUPERVISION
Accuracy
I1> Pick-up Setting +/- 5%
I1> Drop-off 0.9 x setting +/- 5%
I2/I1> Pick-up Setting +/- 5%
I2/I1> Drop-off 0.9 x setting +/-5%
I2/I1>> Pick-up Setting +/- 5%
I2/I1 >> Drop-off 0.9 x setting +/-5%
Time delay operation Setting +/-2% or 20 ms, whichever is greater
CTS block diff operation < 1 cycle
CTS reset < 35 ms
4.4 CB STATE AND CONDITION MONITORING
Accuracy
Timers +/- 40 ms or 2%, whichever is greater
Broken current accuracy +/- 5%
Reset time < 30 ms
494 P841B-TM-EN-1.1
4.5 PSL TIMERS
Output conditioner timer Setting +/- 2% or 50 ms, whichever is greater

Dwell conditioner timer Setting +/- 2% or 50 ms, whichever is greater
Pulse conditioner timer Setting +/- 2% or 50 ms, whichever is greater
P841B-TM-EN-1.1 495
5 MEASUREMENTS AND RECORDING
5.1 GENERAL
General Measurement Accuracy

General measurement accuracy Typically +/- 1%, but +/- 0.5% between 0.2 - 2 In/Vn
Phase 0° to 360° +/- 0.5%
Current (0.05 to 3 In) +/- 1.0% of reading, or 4mA (1A input), or 20mA (5A input)
Voltage (0.05 to 2 Vn) +/- 1.0% of reading
Frequency (45 to 65 Hz) +/- 0.025 Hz
Power (W) (0.2 to 2 Vn and 0.05 to 3 In) +/- 5.0% of reading at unity power factor
Reactive power (Vars) (0.2 to 2 Vn and 0.05 to 3 In) +/- 5.0% of reading at zero power factor
Apparent power (VA) (0.2 to 2 Vn and 0.05 to 3 In) +/- 5.0% of reading
Energy (Wh) (0.2 to 2 Vn and 0.2 to 3 In) +/- 5.0% of reading at unity power factor
Energy (Varh) (0.2 to 2 Vn and 0.2 to 3In) +/- 5.0% of reading at zero power factor
5.2 DISTURBANCE RECORDS
Disturbance Records Measurement Accuracy

Minimum record duration 0.1 s
Maximum record duration 10.5 s
Minimum number of records at 10.5 seconds 8
Magnitude and relative phases accuracy +/- 5% of applied quantities
Duration accuracy +/- 2%
Trigger position accuracy +/- 2% (minimum Trigger 100 ms)
5.3 EVENT, FAULT AND MAINTENANCE RECORDS
Event, Fault & Maintenance Records

Record location Battery-backed memory
Viewing method Front panel display or Settings Application Software
Extraction method Extracted via the front serial port
Number of Event records Up to 1024 time tagged event records (newest overwrites oldest)
Number of Fault Records Up to 15
Number of Maintenance Records Up to 10
Event time stamp resolution 1 ms
5.4 FAULT LOCATOR
Accuracy
+/- 2% of line length
Fault Location
Reference conditions: solid fault applied on line
496 P841B-TM-EN-1.1
6 RATINGS
6.1 AC MEASURING INPUTS
AC Measuring Inputs
Nominal frequency 50 Hz or 60 Hz (settable)
Operating range 45 to 65 Hz
Phase rotation ABC or CBA
6.2 CURRENT TRANSFORMER INPUTS

AC Current Inputs
Nominal current (In) 1A or 5A
Nominal burden per phase < 0.2 VA at In
20 A (continuous operation)
AC current thermal withstand (5A input) 150 A (for 10 s)
500 A (for 1 s)
4 A (continuous operation)
AC current thermal withstand (1A input) 30 A (for 10 s)
100 A (for 1 s)
Linearity Linear up to 64 × In (non-offset)
6.3 VOLTAGE TRANSFORMER INPUTS
AC Voltage Inputs
Nominal voltage 100 V to 120 V
Nominal burden per phase < 0.1 VA at Vn
2 x Vn (continuous operation)
Thermal withstand
2.6 x Vn (for 10 seconds)
Linear up to 200 V (100/120 V supply)
Linearity
Linear up to 800 V (380/400 V supply)
6.4 AUXILIARY SUPPLY VOLTAGE
Cortec option (DC only)

24 to 48 V DC
Cortec option (rated for AC or DC operation)
48 to 110 V DC
Nominal operating range
40 to 100 V AC rms
110 to 250 V DC
100 to 240 V AC rms
P841B-TM-EN-1.1 497
Cortec option (DC only)

19 to 65 V DC
37 to 150 V DC
Maximum operating range
32 to 110 V AC rms
87 to 300 V DC
80 to 265 V AC rms
Frequency range for AC supply 45 to 65 Hz
Ripple <15% for a DC supply (compliant with IEC 60255-11:2013)
Power up time < 11 seconds
6.5 NOMINAL BURDEN
Quiescent burden 11 W
2nd rear communications port 1.25 W
Each relay output burden 0.13 W per output relay
Each opto-input burden (24 – 27 V) 0.065 W max
6.6 POWER SUPPLY INTERRUPTION
Standard IEC 60255-26:2013 (DC and AC)

20 ms at 24 V (half and full load)
24-48V DC SUPPLY
100% interruption without de-energising
20 ms at 37V (half and full load)
48-110V DC SUPPLY
100 ms at 72 V (half load)
100 ms at 85 V (full load)
110-250V DC SUPPLY
40-100V AC SUPPLY 50 ms at 32 V (half load)
100% voltage dip without de-energising 10 ms at 32 V (full load)
100-240V AC SUPPLY
50 ms at 80 V (full and half load)
100% voltage dip without de-energising
498 P841B-TM-EN-1.1
Note:
Maximum loading = all inputs/outputs energised.
Note:
Quiescent or 1/2 loading = 1/2 of all inputs/outputs energised.
6.7 BATTERY BACKUP
Location Front panel

Type 1/2 AA, 3.6V Lithium Thionyly Chloride
Battery reference LS14250
Lifetime > 10 years (IED energised for 90% of the time)
P841B-TM-EN-1.1 499
7 INPUT / OUTPUT CONNECTIONS
7.1 ISOLATED DIGITAL INPUTS
Opto-isolated digital inputs (opto-inputs)

Compliance ESI 48-4
Rated nominal voltage 24 to 250 V dc
Operating range 19 to 265 V dc
Withstand 300 V dc
Recognition time with half-cycle ac
< 2 ms
immunity filter removed
Recognition time with filter on < 12 ms
7.1.1 NOMINAL PICKUP AND RESET THRESHOLDS
Nominal battery
Logic levels: 60-80% DO/PU Logic Levels: 50-70% DO/PU
voltage
24/27 V Logic 0 < 16.2V, Logic 1 > 19.2V Logic 0 <12V, Logic 1 > 16.8V
30/34 Logic 0 < 20.4V, Logic 1 > 24V Logic 0 < 15V, Logic 1 > 21V
48/54 Logic 0 < 32.4V, Logic 1 > 38.4V Logic 0 < 24V, Logic 1 > 33.6V
110/125 Logic 0 < 75V, Logic 1 > 88V Logic 0 < 55.V, Logic 1 > 77V
220/250 Logic 0 < 150V, Logic 1 > 176V Logic 0 < 110V, Logic 1 > 154V
Note:
Filter is required to make the opto-inputs immune to induced AC voltages.
7.2 STANDARD OUTPUT CONTACTS
Compliance In accordance with IEC 60255-1:2009

Use General purpose relay outputs for signalling, tripping and alarming
Rated voltage 300 V
Maximum continuous current 10 A
30 A for 3 s
Short duration withstand carry
250 A for 30 ms
Make and break, dc resistive 50 W
Make and break, dc inductive 62.5 W (L/R = 50 ms)
Make and break, ac resistive 2500 VA resistive (cos phi = unity)
Make and break, ac inductive 2500 VA inductive (cos phi = 0.7)
Make and carry, dc resistive 30 A for 3 s, 10000 operations (subject to a maximum load of 7500W))
4 A for 1.5 s, 10000 operations (subject to the above limit for make and break, dc
Make, carry and break, dc resistive
resistive load)
0.5 A for 1 s, 10000 operations (subject to the above limit for make and break, dc
Make, carry and break, dc inductive
inductive load)
Make, carry and break ac resistive 30 A for 200 ms, 2000 operations (subject to the above limits)
500 P841B-TM-EN-1.1
Make, carry and break ac inductive 10 A for 1.5 s, 10000 operations (subject to the above limits)
Loaded contact 10000 operations min.
Unloaded contact 100000 operations min.
Operate time < 5 ms
Reset time < 10 ms
7.3 HIGH BREAK OUTPUT CONTACTS
Compliance In accordance with IEC 60255-1:2009

Use For applications requiring high rupture capacity
Rated voltage 300 V
Maximum continuous current 10 A DC
30 A DC for 3 s
Short duration withstand carry
250 A for 30 ms
Make and break, dc resistive 7500 W
Make and break, dc inductive 2500 W (L/R = 50 ms)
Make and carry, dc resistive 30 A for 3 s, 10000 operations (subject to the above limits)
30 A for 3 s, 5000 operations (subject to the above limit for make and break, dc
resistive load)
Make, carry and break, dc resistive
30 A for 200 ms, 10000 operations (subject to the above limit for make and break,
dc resistive load)
10 A for 40 ms, 10000 operations (subject to the above limit for make and break,
dc inductive load)
Make, carry and break, dc inductive
10 A for 20 ms (250V, 4 shots per second, subject to the above limit for make and
break, dc inductive load)
Loaded contact 10,000 operations minimum.
Unloaded contact 100,000 operations minimum.
Operate time < 0.2 ms
Reset time < 8 ms
MOV Protection Maximum voltage 330 V DC
7.4 WATCHDOG CONTACTS
Use Non-programmable contacts for relay healthy/relay fail indication

Breaking capacity, dc resistive 30 W
Breaking capacity, dc inductive 15 W (L/R = 40 ms)
Breaking capacity, ac inductive 375 VA inductive (cos phi = 0.7)
P841B-TM-EN-1.1 501
8 MECHANICAL SPECIFICATIONS
8.1 PHYSICAL PARAMETERS
40TE
Case Types* 60TE
80TE
Weight (40TE case) 7 kg – 8 kg (depending on chosen options)
Weight (60TE case) 9 kg – 12 kg (depending on chosen options)
Weight (80TE case) 13 kg - 16 kg (depending on chosen options)
Dimensions in mm (w x h x l) (40TE case) W: 206.0 mm H: 177.0 mm D: 243.1 mm
Dimensions in mm (w x h x l) (60TE case) W: 309.6 mm H: 177.0 mm D: 243.1 mm
Dimensions in mm (w x h x l) (80TE case) W 413.2 mm H 177.0 mm D 243.1 mm
Mounting Panel, rack, or retrofit
Note:
*Case size is product dependent.
8.2 ENCLOSURE PROTECTION
Against dust and dripping water (front face) IP52 as per IEC 60529:2002
Protection against dust (whole case) IP50 as per IEC 60529:2002
Protection for sides of the case (safety) IP30 as per IEC 60529:2002
Protection for rear of the case (safety) IP10 as per IEC 60529:2002
8.3 MECHANICAL ROBUSTNESS
Vibration test per EN 60255-21-1:1996 Response: class 2, Endurance: class 2

Shock response: class 2, Shock withstand: class 1, Bump withstand:
Shock and bump immunity per EN 60255-21-2:1995
class 1
Seismic test per EN 60255-21-3: 1995 Class 2
8.4 TRANSIT PACKAGING PERFORMANCE
Primary packaging carton protection ISTA 1C

Vibration tests 3 orientations, 7 Hz, amplitude 5.3 mm, acceleration 1.05g
10 drops from 610 mm height on multiple carton faces, edges and
Drop tests
corners
502 P841B-TM-EN-1.1
9 TYPE TESTS
9.1 INSULATION
Compliance IEC 60255-27: 2005

Insulation resistance > 100 M ohm at 500 V DC (Using only electronic/brushless insulation tester)
9.2 CREEPAGE DISTANCES AND CLEARANCES

Pollution degree 3
Overvoltage category lll
Impulse test voltage (not RJ45) 5 kV
Impulse test voltage (RJ45) 1 kV
9.3 HIGH VOLTAGE (DIELECTRIC) WITHSTAND
IEC Compliance IEC 60255-27: 2005

Between all independent circuits 2 kV ac rms for 1 minute
Between independent circuits and protective earth conductor terminal 2 kV ac rms for 1 minute
Between all case terminals and the case earth 2 kV ac rms for 1 minute
Across open watchdog contacts 1 kV ac rms for 1 minute
Across open contacts of changeover output relays 1 kV ac rms for 1 minute
Between all RJ45 contacts and protective earth 1 kV ac rms for 1 minute
Between all screw-type EIA(RS)485 contacts and protective earth 1 kV ac rms for 1 minute
ANSI/IEEE Compliance ANSI/IEEE C37.90-2005
Across open contacts of normally open output relays 1.5 kV ac rms for 1 minute
Across open contacts of normally open changeover output relays 1 kV ac rms for 1 minute
Across open watchdog contacts 1 kV ac rms for 1 minute
9.4 IMPULSE VOLTAGE WITHSTAND TEST

Between all independent circuits Front time: 1.2 µs, Time to half-value: 50 µs, Peak value: 5 kV, 0.5 J
Between terminals of all independent circuits Front time: 1.2 µs, Time to half-value: 50 µs, Peak value: 5 kV, 0.5 J
Between all independent circuits and protective
Front time: 1.2 µs, Time to half-value: 50 µs, Peak value: 5 kV, 0.5 J
earth conductor terminal
Note:
Exceptions are communications ports and normally-open output contacts, where applicable.
P841B-TM-EN-1.1 503
10 ENVIRONMENTAL CONDITIONS
10.1 AMBIENT TEMPERATURE RANGE

Test Method IEC 60068-2-1:2007 and IEC 60068-2-2 2007
Operating temperature range -25°C to +55°C (continuous)
Storage and transit temperature range -25°C to +70°C (continuous)
10.2 TEMPERATURE ENDURANCE TEST
Temperature Endurance Test

Test Method IEC 60068-2-1: 1993 and 60068-2-2: 2007
-40°C (96 hours)
Operating temperature range
+70°C (96 hours)
-40°C (96 hours)
Storage and transit temperature range
+70°C (96 hours)
10.3 AMBIENT HUMIDITY RANGE
Compliance IEC 60068-2-78: 2001 and IEC 60068-2-30: 2005

Durability 56 days at 93% relative humidity and +40°C
Damp heat cyclic six (12 + 12) hour cycles, 93% RH, +25 to +55°C
10.4 CORROSIVE ENVIRONMENTS
Compliance IEC 60068-2-42: 2003, IEC 60068-2-43: 2003

Industrial corrosive environment/poor environmental 21 days exposure to elevated concentrations (25ppm) of SO2 at
control, Sulphur Dioxide 75% relative humidity and +25°C
Industrial corrosive environment/poor environmental 21 days exposure to elevated concentrations (10ppm) of H2S at
control, Hydrogen Sulphide 75% relative humidity and +25°C
Salt mist IEC 60068-2-52: 1996 KB severity 3
504 P841B-TM-EN-1.1
11 ELECTROMAGNETIC COMPATIBILITY
11.1 1 MHZ BURST HIGH FREQUENCY DISTURBANCE TEST
Compliance IEC 60255-22-1: 2008, Class III, IEC 60255-26:2013

Common-mode test voltage (level 3) 2.5 kV
Differential test voltage (level 3) 1.0 kV
11.2 DAMPED OSCILLATORY TEST
EN61000-4-18: 2011: Level 3, 100 kHz and 1 MHz. Level 4: 3 MHz,

Compliance
10 MHz and 30 MHz, IEC 60255-26:2013
Differential mode test voltage 1.0 kV
11.3 IMMUNITY TO ELECTROSTATIC DISCHARGE
Compliance IEC 60255-22-2: 2009 Class 3 and Class 4, IEC 60255-26:2013

Class 4 Condition 15 kV discharge in air to user interface, display, and exposed metalwork
Class 3 Condition 8 kV discharge in air to all communication ports
11.4 ELECTRICAL FAST TRANSIENT OR BURST REQUIREMENTS
IEC 60255-22-4: 2008 and EN61000-4-4:2004. Test severity level lll and lV, IEC
Compliance
60255-26:2013
Applied to communication inputs Amplitude: 2 kV, burst frequency 5 kHz and 100 KHz (level 4)
Applied to power supply and all other inputs
Amplitude: 4 kV, burst frequency 5 kHz and 100 KHz (level 4)
except for communication inputs
11.5 SURGE WITHSTAND CAPABILITY
Compliance IEEE/ANSI C37.90.1: 2002

4 kV fast transient and 2.5 kV oscillatory applied common mode and differential
Condition 1
mode to opto inputs, output relays, CTs, VTs, power supply
4 kV fast transient and 2.5 kV oscillatory applied common mode to communications,
Condition 2
IRIG-B
P841B-TM-EN-1.1 505
11.6 SURGE IMMUNITY TEST
Compliance IEC 61000-4-5: 2005 Level 4, IEC 60255-26:2013

Pulse duration Time to half-value: 1.2/50 µs
Between all groups and protective earth conductor terminal Amplitude 4 kV
Between terminals of each group (excluding communications ports,
Amplitude 2 kV
where applicable)
11.7 IMMUNITY TO RADIATED ELECTROMAGNETIC ENERGY
Compliance IEC 60255-22-3: 2007, Class III, IEC 60255-26:2013

Frequency band 80 MHz to 3.0 GHz
Spot tests at 80, 160, 380, 450, 900, 1850, 2150 MHz
Test field strength 10 V/m
Test using AM 1 kHz @ 80%
Compliance IEEE/ANSI C37.90.2: 2004
Frequency band 80 MHz to 1 GHz
Spot tests at 80, 160, 380, 450 MHz
Waveform 1 kHz @ 80% am and pulse modulated
Field strength 35 V/m
11.8 RADIATED IMMUNITY FROM DIGITAL COMMUNICATIONS
Compliance IEC 61000-4-3: 2006, Level 4, IEC 60255-26:2013

Frequency bands 800 to 960 MHz, 1.4 to 2.0 GHz
Test using AM 1 kHz / 80%
11.9 RADIATED IMMUNITY FROM DIGITAL RADIO TELEPHONES
Compliance IEC 61000-4-3: 2006, IEC 60255-26:2013

Frequency bands 900 MHz and 1.89 GHz
11.10 IMMUNITY TO CONDUCTED DISTURBANCES INDUCED BY RADIO FREQUENCY

FIELDS
Compliance IEC 61000-4-6: 2008, Level 3, IEC 60255-26:2013

Frequency bands 150 kHz to 80 MHz
506 P841B-TM-EN-1.1
Test disturbance voltage 10 V rms

Test using AM 1 kHz @ 80%
Spot tests 27 MHz and 68 MHz
11.11 MAGNETIC FIELD IMMUNITY
IEC 61000-4-8: 2009 Level 5

Compliance
IEC 61000-4-9/10: 2001 Level 5
IEC 61000-4-8 test 100 A/m applied continuously, 1000 A/m applied for 3 s
IEC 61000-4-9 test 1000 A/m applied in all planes
100 A/m applied in all planes at 100 kHz/1 MHz with a burst duration of 2
IEC 61000-4-10 test
seconds
11.12 CONDUCTED EMISSIONS
Compliance EN 55022: 2010, IEC 60255-26:2013

Power supply test 1 0.15 - 0.5 MHz, 79 dBµV (quasi peak) 66 dBµV (average)
Power supply test 2 0.5 – 30 MHz, 73 dBµV (quasi peak) 60 dBµV (average)
RJ45 test 1 (where applicable) 0.15 - 0.5 MHz, 97 dBµV (quasi peak) 84 dBµV (average)
RJ45 test 2 (where applicable) 0.5 – 30 MHz, 87 dBµV (quasi peak) 74 dBµV (average)
11.13 RADIATED EMISSIONS
Compliance EN 55022: 2010, IEC 60255-26:2013

Test 1 30 – 230 MHz, 40 dBµV/m at 10 m measurement distance
Test 2 230 – 1 GHz, 47 dBµV/m at 10 m measurement distance
Test 3 1 – 2 GHz, 76 dBµV/m at 10 m measurement distance
11.14 POWER FREQUENCY
Compliance IEC 60255-22-7:2003, IEC 60255-26:2013

Opto-inputs (Compliance is achieved using the opto-input 300 V common-mode (Class A)
filter) 150 V differential mode (Class A)
Note:
Compliance is achieved using the opto-input filter.
P841B-TM-EN-1.1 507
12 STANDARDS COMPLIANCE
Compliance with the European Commission Directive on EMC and LVD is demonstrated by self certification against
international standards.
12.1 EMC COMPLIANCE: 2004/108/EC

Compliance with EN60255-26:2009 was used to establish conformity.
12.2 PRODUCT SAFETY: 2006/95/EC

Compliance with EN60255-27:2005 was used to establish conformity.
Protective Class
IEC 60255-27: 2005 Class 1 (unless otherwise specified in equipment documentation). This equipment requires a
protective conductor (earth) to ensure user safety.
Installation category
IEC 60255-27: 2005 Overvoltage Category 3. Equipment in this category is qualification tested at 5kV peak, 1.2/50
mS, 500 Ohms, 0.5 J, between all supply circuits and earth and also between independent circuits.
Environment
IEC 60255-27: 2005, IEC 60255-26:2009. The equipment is intended for indoor use only. If it is required for use in an
outdoor environment, it must be mounted in a cabinet with the appropriate degree of ingress protection.
12.3 R&TTE COMPLIANCE

Radio and Telecommunications Terminal Equipment (R&TTE) directive 99/5/EC.
Conformity is demonstrated by compliance to both the EMC directive and the Low Voltage directive, to zero volts.
12.4 UL/CUL COMPLIANCE

If marked with this logo, the product is compliant with the requirements of the Canadian and USA Underwriters
Laboratories.
The relevant UL file number and ID is shown on the equipment.
508 P841B-TM-EN-1.1
APPENDIX A
ORDERING OPTIONS
Appendix A - Ordering Options P841B
P841B-TM-EN-1.1
P841B Appendix A - Ordering Options
Variants Order No.

Multi-functional line terminal IED P841 **
Nominal auxiliary voltage
24-54 Vdc 7
48-125 Vdc (40-100 Vac) 8
110-250 Vdc (100-240 Vac) 9
In/Vn rating + Main Functionality

Model A: Autoreclose for one CB (60TE) Dual rated CT(1/5A :100-120V) 1
Model B: Autoreclose for one/two CB (80TE) Dual rated CT(1/5A :100-120V) 3
Model B: Autoreclose for one/two CB (80TE) With Ed.1 & IEC 61850-9-2LE Sampled Analog. Values Ethernet board *
C
Model B: Autoreclose for one/two CB (40TE) With Ed.2 & IEC 61850-9-2LE Sampled Analog. Values Ethernet board **
* Only available with '74' Software ** Only available with '80' Software
Hardware options Protocol Compatibilty

Nothing 1, 3 & 4 1
IRIG-B Only (Modulated) 1, 3 & 4 2
Fibre Optic Converter Only (Withdrawn) 1, 3 & 4 3
IRIG-B (Modulated) & Fibre Optic Converter 1, 3 & 4 4
Ethernet (100Mbit/s) 6, 7 & 8 6
Second Rear Comms 1, 3 & 4 7
IRIG-B (Modulated) + Second Rear Comms 1, 3 & 4 8
Ethernet (100Mbit/s) plus IRIG-B (Modulated) 6, 7 & 8 A
Ethernet (100Mbit/s) plus IRIG-B (Un-modulated) 6, 7 & 8 B
IRIG-B (Un-modulated) 1, 3 & 4 C
InterMiCOM + Courier Rear Port * 1, 3 & 4 E
InterMiCOM + Courier Rear Port + IRIG-B modulated * 1, 3 & 4 F
Redundant Ethernet Self-Healing Ring, 2 multi-mode fibre ports + Modulated IRIG 6, 7 & 8 G
Redundant Ethernet Self-Healing Ring, 2 multi-mode fibre ports + Un-modulated 6, 7 & 8 H
Redundant Ethernet RSTP, 2 multi-mode fibre ports + Modulated IRIG-B 6, 7 & 8 J
Redundant Ethernet RSTP, 2 multi-mode fibre ports + Un-modulated IRIG-B 6, 7 & 8 K
Redundant Ethernet Dual-Homing Star, 2 multi-mode fibre ports + Modulated IRI 6, 7 & 8 L
Redundant Ethernet Dual-Homing Star, 2 multi-mode fibre ports + Un-modulated 6, 7 & 8 M
Redundant Ethernet PRP/HSR, 2 fibre ports + Modulated IRIG-B 6, 7 & 8 N
Redundant Ethernet PRP/HSR, 2 fibre ports + Unmodulated IRIG-B 6, 7 & 8 P
Redundant Ethernet PRP/HSR/RSTP, 2 multi-mode fibre ports + Modulated/Un- 6, 7 & 8 R
Redundant Ethernet PRP/HSR/RSTP, 2 copper ports RJ45 + Modulated/Un-Mod 6, 7 & 8 S
Single Ethernet, 1 multi-mode fibre ports + Modulated/Un-Modulated IRIG-B ** 6, 7 & 8 T
* Only with 47/ 57 Software & later, replaces hardware options '7' & '8'
** Contact GE
** For HSR – contact Alstom for details
Product Options
16 Inputs & 14 Standard Outputs (60TE only) A
16 Inputs & 7 Standard + 4 High Break Outputs (60TE only) B
24 Inputs & 32 Standard Outputs (80TE) 8 inputs, 8 outputs mounting option 'R' (40TE) C
24 Inputs & 16 Standard + 8 High Break Outputs (80TE only) D
24 Inputs & 8 Standard + 12 High Break Outputs (80TE only) E
Protocol options Hardware Compatibilty

K-Bus 1, 2, 3, 4, C, E & F 1
IEC60870-5-103 1, 2, 3, 4, C, E & F 3
DNP3.0 1, 2, 3, 4, C, E & F 4
IEC61850 + Courier via rear RS485 port 6, A, B, G, H, J, K, L, M, N, P 6
IEC61850+IEC60870-5-103 via rear RS485 port 6, A, B, G, H, J, K, L, M, N, P 7
DNP3.0 Over Ethernet with Courier rear port K-Bus/RS485 protocol 6, A, B, G, H, J, K, L, M, N, P 8
Mounting
Flush/Panel Mounting with Harsh Environment Coating M
Rack Mounting with Harsh Environmental Coating (80TE only) N
Flush/panel mounting with harsh environment coating P
Rack mounting with harsh environmental coating Q
40TE Case (9-2LE models only) Flush/Panel Mounting with Harsh Environmetal Coating R
Language
English, French, German, Spanish 0
English, French, German, Russian 5
English, Italian, Polish and Portuguese 7
Chinese, English or French via HMI, with English or French only via Communications port C
Software version
Autoreclose for single Circuit Breaker (60TE) 4/6/8*
Autoreclose for two Circuit breakers (80TE) 5/7/8*
Customer specific options

Standard version 0
Customer version A
Hardware version
Extended main processor (XCPU2) With Function Keys & Tri-colour LEDs K
Main processor (CPU3) 40TE P
As K plus increased main processor memory (XCPU3), Cyber Security M
P841B-EN-TM-N A1
Appendix A - Ordering Options P841B
A2 P841B-EN-TM-N
APPENDIX B
SETTINGS AND SIGNALS

Appendix B - Settings and Signals P841B
Tables, containing a full list of settings, measurement data and DDB signals for each product model, are provided
in a separate interactive PDF file attached as an embedded resource.
Tables are organized into a simple menu system allowing selection by language (where available), model and table
type, and may be viewed and/or printed using an up-to-date version of Adobe Reader.
Settings & Signals
P841B-TM-EN-1.1
APPENDIX C
WIRING DIAGRAMS
Appendix C - Wiring Diagrams P841B
P841B-TM-EN-1.1
P841B Appendix C – Wiring Diagrams
MODEL CORTEC OPTION* EXTERNAL CONNECTION DIAGRAM TITLE DRAWING-SHEET ISSUE
Px4x - COMMS OPTIONS MICOM Px40 PLATFORM 10Px4001-1 K

EXTERNAL CONNECTION DIAGRAM: AUTORECLOSE (80 TE) POWER SYSTEM CONNECTIONS
- 10P84100-1 D
ONLY
Model C EXTERNAL CONNECTION DIAGRAM: AUTORECLOSE (80TE) 24 INPUTS AND 32 OUTPUTS 10P84103-1 D
Model C DEFAULT MAPPING DIAGRAM: AUTORECLOSE (80TE) 24 INPUTS AND 32 OUTPUTS 10P84103-2 C
EXTERNAL CONNECTION DIAGRAM: AUTORECLOSE (80TE) 24 INPUTS, 16 STANDARD RELAYS
Model D 10P84104-1 E
& 8 HIGH BREAK RELAYS
P841B
DEFAULT MAPPING DIAGRAM: AUTORECLOSE (80TE) 24 INPUTS, 16 STANDARD RELAYS & 8
Model D 10P84104-2 D
HIGH BREAK RELAYS
EXTERNAL CONNECTION DIAGRAM : AUTORECLOSE (80TE) 24 INPUTS, 8 STANDARD RELAYS
Model E 10P84105-1 D
AND 12 HIGH BREAK RELAYS
DEFAULT MAPPING DIAGRAM: AUTORECLOSE (80TE) 24 INPUTS, 8 STANDARD RELAYS AND
Model E 10P84105-2 C1
12 HIGH BREAK RELAYS
* When selecting the applicable wiring diagram(s), refer to appropriate model’s CORTEC.
P841B-EN-TM-N C1
PART DESCRIPTION MATERIAL
Date: Name: Drg Next Stage: Drg ECN No: Revision: Iteration:
Date: Chkd:
Title: No:
10PX4001 K 3
Sub-contractor reference: Linear Tol PLM Sht: Status:
Finish:
CAD DATA 1:1 DIMENSIONS: mm
DO NOT SCALE
mm:
Angular Tol
Grid Solutions
No:
A20022917 Next
Sht:
IN WORK
deg:
A B C TYPICAL CONNECTIONS FOR DUAL CB SCHEME WITH SYNCHRONISM CHECK C B A
A
CB1 CB2 CB3
P1 P2 P2 P1
S1 S2 S2 S1
C B
PHASE ROTATION
NOTE 6
A A
MiCOM P841 (PART)
BUS A B C BUS
N A D19 5A F1 N
A (2)
n N n
1A NOTE 5
LINE F3 NOTE 4. LINE
n
NOTE 5 a B D20 5A F4 a
B (2)
a b c
1A
F6
C D21 5A F7
C(2)
N D22 1A
F9
5A
D23 F23
CS(1) D24 F24 CS (2)
D1 5A
NOTE 4. A(1)
1A
D3
D4 5A
NOTES 1.
B(1)
(a) C.T. SHORTING LINKS
1A
D6
D7 5A
C(1)
(b) PIN TERMINAL (P.C.B. TYPE)
D9 1A 2. USED FOR SEF PROTECTION. NSENSITIVE SHOULD BE DRIVEN FROM

D10 5A A CORE BALANCE CT WHEN SENSITIVE SETTINGS ARE USED.
M 3. M INPUT IS FOR OPTIONAL MUTUAL COMPENSATION.

NOTE 3.
4. C.T. CONNECTIONS ARE SHOWN 1A CONNECTED AND ARE TYPICAL ONLY
1A FOR A 1 1/2 BREAKER SCHEME.
D12
D13 5A
5. CHECK SYNCH. V.T. CONNECTIONS ARE TYPICAL ONLY.
N
6. REVERSE PHASE ROTATION IS ALSO SUPPORTED.
SENSITIVE
NOTE 2. 1A 7. SEE DRAWINGS 10P84101 TO 10P84105 FOR THE VARIOUS I/O OPTIONS.
D15
Issue: Revision: Title:

CID PWIG-8K5GBQ EXTERNAL CONNECTION DIAGRAM P841 : AUTORECLOSE (80 TE)
D POWER SYSTEM CONNECTIONS ONLY
Drg
Date: 27/07/2011 Name: P.WIGGIN CAD DATA 1:1 DIMENSIONS: mm Sht: 1
Date: Chkd: N.ROBINSON DO NOT SCALE
No:
10P84100 Next
Sht: 2
MiCOM P841 (PART) MiCOM P841 (PART)
E1 G1 J1 M11
- RELAY 17 WATCHDOG
OPTO 17 J2 M12 CONTACT
OPTO 1 E2 G2
+ J3 M13
E3 G3 RELAY 18 WATCHDOG
- J4 M14 CONTACT
OPTO 2 E4 G4 OPTO 18 J5 L1
+
RELAY 19 J6 L2 RELAY 1
E5 G5
- J7 L3
OPTO 3 E6 G6 OPTO 19
+ RELAY 20 J8 L4 RELAY 2
E7 G7 J9 L5
-
OPTO 4 E8 G8 OPTO 20 RELAY 21 J10 L6 RELAY 3
+
E9 G9 J11 L7
- RELAY 22 J12 L8 RELAY 4
+ J13 L9
E11 G11 J14 L10 RELAY 5
- RELAY 23
OPTO 6 E12 G12 OPTO 22 J15 L11
+ RELAY 6
E13 G13 J16 L12
- J17 L13
OPTO 7 E14 G14 OPTO 23 RELAY 24
+ J18 L14 RELAY 7
E15 G15 H1 L15
- RELAY 25
OPTO 8 E16 G16 OPTO 24 H2 L16
+ H3 L17
E17 G17 RELAY 8
RELAY 26 H4 L18
COMMON COMMON
CONNECTION E18 G18 CONNECTION H5
K1
C1 RELAY 27 H6
K2 RELAY 9
OPTO 9 C2 H7
K3
RELAY 28 H8
K4 RELAY 10
C3
H9
OPTO 10 K5
C4 RELAY 29 H10
K6 RELAY 11
C5 H11
K7
RELAY 30 H12
OPTO 11 C6 K8 RELAY 12
M17 H13
C7 K9
- EIA 485/ H14
RELAY 31 K10 RELAY 13
OPTO 12 C8 NOTE 1 H15 K11
M18 H16 RELAY 14
+ KBUS PORT K12
C9 H17
- M16 RELAY 32 K13
OPTO 13 C10 SCN H18
+ K14 RELAY 15
C11 K15
- M1
OPTO 14 C12 K16
+ AC OR DC
M2 x K17 RELAY 16
C13
- K18
OPTO 15 C14
+
C15
-
OPTO 16 C16
+
C17
COMMON
C18
CONNECTION
* POWER SUPPLY VERSION 24-48V (NOMINAL) D.C. ONLY 1. FOR COMMS OPTIONS SEE DRAWING 10Px4001.
2. PIN TERMINAL (PCB TYPE)

SWOO-A33E8E. FIELD VOLTAGE REMOVED. EXT CONN DIAG: AUTORECLOSE (80TE)
D 24 INPUTS AND 32 OUTPUTS
Drg
Date: 09/11/2015 Name: S.WOOTTON CAD DATA 1:1 DIMENSIONS: mm Sht: 1
Date: Chkd: DO NOT SCALE
No:
10P84103 Next
Sht: 2
CUSTOMER SETTING DEFAULT SETTING E1
-
NOT USED OPTO 1 E2 M11
+ WATCHDOG
E3 M12 CONTACT
- M13
BAR OPTO 2 E4 WATCHDOG
+ M14 CONTACT DEFAULT SETTING CUSTOMER SETTING
E5
- L1
NOT USED OPTO 3 E6 L2 RELAY 1 NOT USED
+
E7 L3
-
OPTO 4 L4 RELAY 2 ANY START
NOT USED E8
+ L5
E9
- L6 RELAY 3 ANY TRIP
RESET LEDS OPTO 5 E10
+ L7
E11 RELAY 4 GENERAL ALARM
- L8
CB2 AUXA 52-B OPTO 6 E12 L9
+
E13 L10 RELAY 5 NOT USED
-
CB2 AUXB 52-B OPTO 7 E14 L11
+ L12 RELAY 6 CB1 FAIL 1 TRIP
E15
- L13
CB2 AUXC 52-B OPTO 8 E16
+ L14 RELAY 7
E17 CNTL CB1 CLOSE
L15
COMMON
CONNECTION E18 MiCOM P841 L16
-
C1 (PART) L17
RELAY 8 CNTL CB1 TRIP
CB1 AUXA 52-B OPTO 9 C2 L18
+
C3 K1
-
OPTO 10 K2 RELAY 9 CB1 TRIP A
CB1 AUXB 52-B C4
+ K3
C5
- K4 RELAY 10 CB1 TRIP B
CB1 AUXC 52-B OPTO 11 C6
+ K5
C7 RELAY 11 CB1 TRIP C
- K6
MCB/VTS OPTO 12 C8 K7
+
C9 K8 RELAY 12 CB2 FAIL 2 TRIP
-
CB1 CLOSE MAN OPTO 13 C10 K9
+ K10 RELAY 13 CNTL CB2 CLOSE
C11
- K11
CB2 CLOSE MAN OPTO 14 C12
+ K12 RELAY 14 CNTL CB2 TRIP
C13
- K13
CB1 HEALTHY OPTO 15 C14 K14
+ RELAY 15 CB1 FAIL 2 TRIP
C15 K15
-
NOT USED OPTO 16 C16 K16
+ K17
C17 RELAY 16 CB2 FAIL 2 TRIP
COMMON K18
CONNECTION C18
J1
J2 RELAY 17 CB2 TRIP A
G1
- J3
CB2 HEALTHY OPTO 17 G2 RELAY 18 CB2 TRIP B
+ J4
G3 J5
-
NOT USED OPTO 18 J6 RELAY 19 CB2 TRIP C
G4
+ J7
G5
- J8 RELAY 20 NOT USED
CB1 EXT TRIP A OPTO 19 G6
+ J9
G7 J10 RELAY 21 NOT USED
-
CB1 EXT TRIP B OPTO 20 G8 J11
+ J12 RELAY 22 NOT USED
G9
- J13
CB1 EXT TRIP C OPTO 21 G10
+ J14 RELAY 23 NOT USED
G11 J15
-
CB2 EXT TRIP A OPTO 22 G12 J16
+ J17
G13 RELAY 24 NOT USED
- J18
CB2 EXT TRIP B OPTO 23 G14
+ H1
G15 RELAY 25 NOT USED
- H2
CB2 EXT TRIP C OPTO 24 G16 H3
+
H4 RELAY 26 NOT USED
G17
COMMON H5
CONNECTION G18
H6 RELAY 27 VTS
H7
H8 RELAY 28 NOT USED
H9
H10 RELAY 29 AR CB1 LOCKOUT
H11
H12 RELAY 30 AR CB2 LOCKOUT
H13
H14 RELAY 31 ARIP
H15
H16
H17
RELAY 32 SUCCESS CLOSE
H18

DRAWING OUTLINE UPDATED. CID BLIN-8BHLDT EXT CONN DIAG: AUTORECLOSE (80TE)
C 24 INPUTS AND 32 OUTPUTS
Drg
Date: 30/11/2010 Name: W.LINTERN CAD DATA 1:1 DIMENSIONS: mm Sht: 2
No:
10P84103 Next
Sht:
-
MiCOM P841 (PART) MiCOM P841 (PART) M11
WATCHDOG
M12 CONTACT
G1 E1 J3 M13
- WATCHDOG
- M14
OPTO 17 G2 E2 OPTO 1 RELAY 17 CONTACT
+ J4 L1
+
G3 E3 L2 RELAY 1
- - J7
OPTO 18 G4 E4 OPTO 2 L3
+ RELAY 18 RELAY 2
G5 E5 L4
HIGH BREAK + J8
- L5
OPTO 19 G6 E6 OPTO 3 CONTACTS
+ - J11 L6 RELAY 3
G7 E7 RELAY 19 L7
-
OPTO 20 OPTO 4 + J12 RELAY 4
G8 E8 L8
+
E9 - J15 L9
G9
- RELAY 20 L10 RELAY 5
OPTO 21 G10 E10 OPTO 5
+ + J16 L11
G11 E11 H3 L12 RELAY 6
- -
OPTO 22 G12 E12 OPTO 6 RELAY 21 L13
+
+ H4 L14 RELAY 7
G13 E13
- L15
OPTO 23 G14 E14 OPTO 7 - H7
+ L16
RELAY 22
G15 E15 L17
- HIGH BREAK + H8 RELAY 8
OPTO 24 G16 E16 OPTO 8 CONTACTS L18
+ - H11
G17 E17 K1
RELAY 23
COMMON COMMON K2 RELAY 9
G18 E18 + H12
CONNECTION CONNECTION
K3
- H15 RELAY 10
C1 K4
- RELAY 24
K5
C2 OPTO 9 + H16
+ K6 RELAY 11
M17 C3
- K7
-
EIA485/ C4 OPTO 10 K8 RELAY 12
KBUS NOTE 1 +
PORT M18 K9
C5
+ - K10 RELAY 13
M16 C6 OPTO 11
SCN + K11
C7 K12 RELAY 14
-
C8 OPTO 12 K13
+ K14 RELAY 15
C9 K15
OPTO 13 K16
C10
K17 RELAY 16
M1 * C11
K18
-
AC OR DC C12 OPTO 14
x M2
+
C13
C14 OPTO 15
C15
C16 OPTO 16
C17
COMMON
C18
CONNECTION
1. FOR COMMS OPTIONS SEE DRAWING 10Px4001.
2. PIN TERMINAL (PCB TYPE)
* POWER SUPPLY VERSION 24-48V (NOMINAL) D.C. ONLY

DC FIELD OUTPUT VOLTAGE REMOVED. CID HONG-98JC6A. EXTERNAL CONNECTION DIAGRAM : AUTORECLOSE (80TE)
E 24 INPUTS, 16 STANDARD RELAYS & 8 HIGH BREAK RELAYS
Drg
Date: 08/07/2013 Name: N.JOHNSON CAD DATA 1:1 DIMENSIONS: mm Sht: 1
No:
10P84104 Next
Sht: 2
-
+ WATCHDOG
E3 M12 CONTACT
- M13
E5
- L1
NOT USED OPTO 3 E6 SEE NOTE 1 SEE NOTE 1 L2 RELAY 1 AR LOCKOUT
+
E7 L3
-
NOT USED E8 SEE NOTE 1
+ L5
E9
+ L7
- L8
+
E13 L10 RELAY 5 ARIP
-
+ L12 RELAY 6 CB1 FAIL 1 TRIP
E15
- L13
+ L14 RELAY 7
E17 CNTL CB1 CLOSE
L15
COMMON
-
C1 (PART) L17
RELAY 8 CNTL CB1 TRIP
+
C3 K1
-
OPTO 10 K2 RELAY 9 CB1 TRIP A
CB1 AUXB 52-B C4
+ K3
C5
- K4 RELAY 10 CB1 TRIP B
+ K5
C7 RELAY 11 CB1 TRIP C
- K6
MCB/VTS OPTO 12 C8 K7
+
C9 K8 RELAY 12 NOT USED
-
CB1 CLOSE MAN OPTO 13 C10 K9
+ RELAY 13 CNTL CB2 CLOSE
C11 K10
- K11
+ K12 RELAY 14 CNTL CB2 TRIP
C13
- K13
CB1 HEALTHY OPTO 15 C14 K14
+ RELAY 15 CB2 FAIL 1 TRIP
C15 K15
-
NOT USED OPTO 16 C16 K16
+ K17
C17 RELAY 16 NOT USED
COMMON K18
CONNECTION
C18
J3
G1 RELAY 17 CB1 TRIP A

- J4
CB2 HEALTHY OPTO 17 G2
+ J7
G3
- RELAY 18 CB1 TRIP B
NOT USED OPTO 18 G4 J8
+ HIGH BREAK
G5 J11 CONTACTS
-
CB1 EXT TRIP A OPTO 19 G6 RELAY 19 CB1 TRIP C
+ J12
G7
- J15
+ RELAY 20 CB1 TRIP 3PH
G9 J16
-
+
G11 RELAY 21 CB2 TRIP A
- H4
+ H7
G13
CB2 EXT TRIP B OPTO 23 G14 H8
+
G15 HIGH BREAK
H11
- CONTACTS
CB2 EXT TRIP C OPTO 24 G16 RELAY 23 CB2 TRIP C
+ H12
G17
COMMON G15
CONNECTION G18
RELAY 24 CB2 TRIP 3PH
H16
NOTE 1:
ONLY FOR RELAYS WITH DISTANCE PROTECTION OPTION.

CID PWIG-8C4LA6 EXTERNAL CONNECTION DIAGRAM : AUTORECLOSE (80TE)
D 24 INPUTS, 16 STANDARD RELAYS & 8 HIGH BREAK RELAYS
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Sht:
-
MiCOM P841 (PART) MiCOM P841 (PART)
E1 G1 K3 M11
- - WATCHDOG
OPTO 1 OPTO 17 M12 CONTACT
E2 G2 RELAY 9
+ K4 M13
E3 G3 + WATCHDOG
- M14 CONTACT
- K7
OPTO 2 E4 G4 OPTO 18 L1
+ RELAY 10 L2 RELAY 1
E5 G5 K8
- HIGH BREAK + L3
+ CONTACTS - K11 L4 RELAY 2
E7 G7 RELAY 11 L5
-
OPTO 4 OPTO 20 K12 RELAY 3
E8 G8 + L6
+
E9 G9 - K15 L7
- L8 RELAY 4
OPTO 5 E10 G10 OPTO 21 RELAY 12
+ K16 L9
+
E11 G11 J3 L10 RELAY 5
- -
OPTO 6 E12 G12 OPTO 22 L11
+ RELAY 13
J4 L12 RELAY 6
E13 G13 +
- L13
OPTO 7 E14 G14 OPTO 23 - J7
+ L14 RELAY 7
E15 G15 RELAY 14
J8 L15
- +
OPTO 8 E16 G16 OPTO 24 HIGH BREAK L13
+ CONTACTS - J11
L14 RELAY 8
E17 G17
COMMON RELAY 15 L15
COMMON J12
CONNECTION E18 G18 CONNECTION +
C1 - J15
OPTO 9 C2 RELAY 16
J16
+
C3
- H3
OPTO 10 C4
RELAY 17
C5 H4
+
OPTO 11 C6 M17 H7
-
C7 EIA485/ RELAY 18
NOTE 1 KBUS H8
OPTO 12 HIGH BREAK +
C8 M18 PORT
CONTACTS - H11
M16 RELAY 19
C9 SCN
- H12
OPTO 13 C10 +
+ H15
-
C11 M1
- AC OR DC RELAY 20
OPTO 14 C12 M2 x H16
+ +
C13
-
OPTO 15 C14
+
C15
-
OPTO 16 C16
+
C17
COMMON
CONNECTION C18
1. FOR COMMS OPTIONS SEE DRAWING 10Px4001.
POWER SUPPLY VERSION 24-48V (NOMINAL) D.C. ONLY 2. PIN TERMINAL (PCB TYPE)
*
DC FIELD OUTPUT VOLTAGE REMOVED. CID HONG-98JC6A. EXTERNAL CONNECTION DIAGRAM : AUTORECLOSE (80TE)
D 24 INPUTS, 8 STANDARD RELAYS AND 12 HIGH BREAK RELAY
Drg
Date: 08/07/2013 Name: N.JOHNSON CAD DATA 1:1 DIMENSIONS: mm Sht: 1
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Sht: 2
-
+ WATCHDOG
E3 M12 CONTACT
- M13
E5
- L1
NOT USED OPTO 3 E6 L2 RELAY 1 AR LOCKOUT
+
E7 L3
-
NOT USED E8
+ L5
E9
+ L7
- L8
+
E13 L10 RELAY 5 ARIP
-
+ RELAY 6 CNTL CB1 CLOSE
E15 L12
- L13
+ L14 RELAY 7
E17 CNTL CB2 CLOSE
L15
COMMON
-
C1 (PART) L17
RELAY 8 NOT USED
+
C3
-
CB1 AUXB 52-B OPTO 10 C4
+
C5
-
+
C7
- J3
MCB/VTS OPTO 12 C8
+ RELAY 9 CB1 TRIP A
C9 J4
-
+ J7
C11
CB2 CLOSE MAN OPTO 14 C12 J8
+ HIGH BREAK
C13 J11
- CONTACTS
CB1 HEALTHY OPTO 15 C14 RELAY 11 CB1 TRIP C
+ J12
C15
-
NOT USED OPTO 16 C16 J15
+
C17 RELAY 12 CB2 TRIP A
COMMON J16
CONNECTION C18
J3
G1 RELAY 13 CB2 TRIP B

- J4
CB2 HEALTHY OPTO 17 G2
+ J7
G3
- RELAY 14 CB2 TRIP C
NOT USED OPTO 18 G4 J8
+ HIGH BREAK
G5 J11 CONTACTS
-
CB1 EXT TRIP A OPTO 19 G6 RELAY 15 CB1 TRIP A
+ J12
G7
- J15
+ RELAY 16 CB1 TRIP B
G9 J16
-
+
G11 RELAY 17 CB1 TRIP C
- H4
+ H7
G13
- RELAY 18 CB2 TRIP A
CB2 EXT TRIP B OPTO 23 G14 H8
+
G15 HIGH BREAK
H11
- CONTACTS
CB2 EXT TRIP C OPTO 24 G16 RELAY 19 CB2 TRIP B
+ H12
G17
COMMON G15
CONNECTION G18
RELAY 20 CB2 TRIP C
H16

CheckedOut for Editing EXTERNAL CONNECTION DIAGRAM : AUTORECLOSE (80TE)
C.1 24 INPUTS, 8 STANDARD RELAYS AND 12 HIGH BREAK RELAYS
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-
APPENDIX D
VERSION HISTORY
Appendix D - Version History P841B
P841B-EN-TM-N
1 HARDWARE AND SOFTWARE VERSION HISTORY
S/W S/W
H/W Original Technical
Version Version Description of Changes S1 Compatibility
Version Date of Issue Documentation
Major Minor
01 A A Feb 2000  First release to production V1.07 or later TG8613A
 PSB. Three settings added to set zone 6 to increase flexibility
 Protection address. Universal address added
 SEF & EF. Polarizing voltage setting range increased
 Thermal. Setting range increased
 Trip conversion logic. 3 DDB signals added to simplify logic for users
02 A A 30 Mar 2000  Distance. Min polarizing voltage increased to prevent tripping for close up three V1.08 or later TG8613B
phase faults
 Check sync. angle measurement improved
 PSB. Text for power swing indication improved
 Include pole discrepancy logic to P543
 Susceptance setting corrected
 German text changed
 Spanish text changed
 Changes to DDB names & properties
03 A A 8 May 2000  Improvements in autoreclose and reset from lockout code V1.09 or later TG8613B
 Changes to pole dead & trip conversion logic
 Changes to P544 circuit breaker fail logic
 Added DDB for CS103 test mode
S/W S/W
Major Minor
All builds released for maintenance upgrades
 Resolved possible reboot caused by disturbance recorder
 Resolved possible reboot caused by invalid MODBUS requests
 Resolved a loss of measurements (column 3 & 4) problem that can occur in 3
terminal applications
 Problem whereby MiCOM S1 could only set group 1 line length corrected
 Fixed capacitive charging current compensation in P544
 Corrected P544 display of phase C current phase angle
03 B A 28 Feb 2002  IDMT curves improvements V1.09 or later TG8613B
 Removed rounding error in calculation of tp
 Menu dependence using ripple bit corrected
 Directional/non-direction earth fault fixed
 Battery fail alarm improvements
 Power measurements read over MODBUS may be incorrect
 Resolved problem caused by rapid changing self resetting alarm resetting the
relay when read key pressed
 Prevented software errors from clearing event log
04 A A 21 Aug 2000  Trip conversion logic moved from internal fixed logic to PSL V1.10 or later TG8613B
Only P543 CS103 builds released
04 B A 26 Mar 2001 V1.10 or later TG8613B
 Improvements to the CS103 time synchronization
Only P543 CS103 builds released. Based on 04B
04 C A 5 Jun 2001  Resolved a loss of measurements (columns 3 & 4) problem that can occur in 3 V1.10 or later TG8613B
Only P543 CS103 build released. Based on 04C
04 D A 28 Jun 2001 V1.10 or later TG8613B
 Prevents a reboot on power-up when battery is removed
Internal release for validation only
 Includes DNP3.0
 Courier bay module compatibility modification
 MODBUS bay module compatibility modification
 Distance - Z3 selectable forward/reverse
 Spanish text corrected
05 A A 12 Sep 2000 V2.0 or later TG8613B
 Menu dependence using ripple bit corrected
 MODBUS problem reading negative values of fault location corrected
 RDF file modified
 Directional/non-direction earth fault fixed
 Battery fail alarm corrected
 Very low fault location could be shown incorrectly as negative
S/W S/W
Major Minor
Released to production
 Includes all of 05A changes
 Requirement to use relays 8, 9 & 10 for Trip A, B & C removed
05 B A 11 Oct 2000  MODBUS communication problem when used with P140 fixed V2.0 or later TG8613B
 Power measurements read over MODBUS may be incorrect
 MODBUS status register reports disturbance records incorrectly following power
cycle
Only P543 & P544 builds released for customer tests
05 C A 29 Mar 2001 V2.0 or later TG8613B
 PSB now works with single pole open
Only P543 & P544 builds released for customer tests
 Distance directional line fixed at -30º New PSL will be
05 D A 30 May 2001 -
 PSB block issued when impedance passes into any Z1, Z2 or Z3 required
 PSB unblock via negative sequence current now done via PSL
All builds released to production. Based on 05B software
05 E A 5 Jun 2001  Resolved a loss of measurements (column 3 & 4) problem that can occur in 3 V2.0 or later TG8613B
All builds released to production. Based on 05E software
 Fixed capacitive charging current compensation in P544
05 F A 10 Sep 2001  Corrected P544 display of phase C current phase angle V2.0 or later TG8613B
 IDMT curves improvements
 Removed rounding error in calculation of tp
 Fixed problems caused by changes to DNP3.0 address
All builds except MODBUS released to production. Based on 05F software
05 G A 14 Jan 2002 V2.0 or later TG8613B
All builds released to production. Based on 05G software
05 H A 24 Jan 2002 V2.0 or later TG8613B
 Resolved possible reboot caused by invalid MODBUS requests
Limited release - not released to production. Based on 05H software
05 I A 28 Oct 2002 V2.0 or later TG8613B
 Correct the format used to display frequency over the MODBUS interface
All builds released to production. Based on 05I software
 Resolved incorrect operation of C diff failure alarm in 3 terminal schemes
 Correct operation of capacitive charging current compensation in 3 terminal
05 J A 6 Nov 2002 V2.0 or later TG8613B
schemes
 Resolved problem which caused short duration current differential trips in some
applications
05 K A 4 Feb 2003 V2.0 or later TG8613B
 Resolved problem with IEC 60870-5-103 time synchronization
S/W S/W
Major Minor
Maintenance release based on 05K (not formally released)
 Prevents compressed disturbance recorder stalling
05 L A 5 Jan 2004 V2.0 or later TG8613B
 Prevent a maintenance record when reading from an inaccessible MODBUS
register
Maintenance release based on 05L
 Improved self-checking of analogue data acquisition
 Improved self checking of SRAM
05 M A 30 Jun 2004 V2.0 or later TG8613B
 Reception of MODBUS frame improved
 Rejection of spurious messages injected onto RS485 network improved
 Permissive intertrip in dual redundant schemes corrected
Maintenance release based on 05M
05 N A 14 Jun 2005 V2.0 or later TG8613B
 Changed MODBUS driver
Internal Release for validation only - runs on phase 1 hardware with an old co-
processor board
 In non GPS mode the char modification timer has been made visible in P545/6
 The char modification timer setting was not being seen by the co-processor
06 A A 7 May 2001 board - -
 GPS detected flag was not cleared when switching from GPS to non GPS mode
 Equal prop delay command was not resetting inhibit following a comms. switch
 Problem displaying Rx & Tx when comms. path was short fixed
Note: Non of the above are relevant to software in production
Internal release for validation only - runs on phase 1 hardware with an old co-
processor board
 Prevent loss of measurements in 3 ended schemes
 Added a 1s drop off timer to C diff inhibit
 Changed max value of char mod timer to 2s
06 B A 7 Jun 2001  Increased number of PSL timers to 16 (all models) - -
 Corrected PSL default reference
 Added a setting to P543/5 AR to select which edge of trip initiates AR
 Added 3 DDB signals to block distance
 Removed force 3 pole trip DDB
Limited release (P543 only) - not released to production. Based on 05K software
07 A A 19 Feb 2002 V2.08 or later -
 Additional check sync signals added to PSL
S/W S/W
Major Minor
Internal release for validation only - runs on phase 1 hardware with a modified
co-processor board to accept a 1pps input
 GPS synchronization
 Flexible intertripping
 Signaling message format changed
 Models 5 & 6 (but limited to 16 optos & 14 relays)
 Remains of neutral C diff removed
 Event optimization & filtering
 Watt hour measurement correction
 Addition of digital opto filtering control
 Changes & additions to error codes
 Increase in protection signaling address No official release to
 DDB increased in size to 1022 and also support functions changed support this version.
10 A B 12 Feb 2001 -
 Support for universal optos (model number suffix B) Will need V2 to
 Support for new output relays added extract PSL files
 Internal loopback setting added (not full functional)
 PSL references added
 Reset LEDs DDB name change
 Text for cells 0F20 - 0F2F changed
 Control inputs added
 Restore defaults now restores DNP3.0 cells correctly
 Prevent non DNP3.0 builds generating fatal error when S1 request DNP3.0
upload
 MODBUS enabling/disabling of IRIG-B now works
 Courier/MODBUS event bit functionality corrected
Internal release for validation only - runs on phase 1 hardware with a modified
co-processor board to accept a 1pps input
10 B B 3 Apr 2001  Fixed a reset indications problem in CS103 build As per 10A -
 Fixed a problem with P544 display of phase C current phase angle
 Setting relay address via rear port corrupted other setting ranges
S/W S/W
Major Minor
Internal release for validation only - runs on phase 2 hardware with a new co-
processor board
 Support for new co-processor board added
 In non GPS mode the char modification timer has been made visible in P545/6
 The char modification timer setting was not being seen by the co-processor
10 C B 7 May 2001 board As per 10A -
 GPS detected flag was not cleared when switching from GPS to non GPS mode
 Equal prop delay command was not resetting inhibit following a comms. switch
 Problem displaying Rx & Tx when comms. path was short fixed
 Opto filtering corrected
processor board
 Prevent loss of measurements in 3 ended schemes
 Added a 1s drop off timer to C diff inhibit
 Changed max value of char mod timer to 2s
 Increased number of PSL timers to 16 (all models)
V2.01b
10 D B 6 Jun 2001  Corrected PSL default reference -
(not issued)
 Added a setting to P543/5 AR to select which edge of trip initiates AR
 Added 3 DDB signals to block distance
 Removed force 3 pole trip DDB
 Resolved problem caused by rapid changing self resetting alarm resetting the
relay when read key pressed
processor board
 Fixed capacitive charging current compensation in P544 & P546
 Fixed fast operating times for IDMT at a particular multiply of setting
 Added MODBUS control of opto filter cell
 Removed the quick start up for GPS because it was causing general start-up V2.01b
10 E B 30 Jul 2001 problems -
(not issued)
 Fixed the GPS inhibit in dual redundant mode
 Fixed an error in GPS synchronization when a timer wraps round
 Fixed comms. delay equal command in 3 terminal schemes
 CS103 time sync modified not to generate courier events
S/W S/W
Major Minor
processor board
 Added CS103 private codes
 Added uncompressed disturbance recorder to CS103 build
 Added translations for filter control
 Fixed the GI list for P545 & P546
 Fixed the incorrect response in three terminal mode with GPS present and
running on a split path followed by a power cycle at one end
 Fixed the occasional incorrect calculation of tp being caused by rounding errors V2.01b
10 F B - -
 Fixed the incorrect response in dual redundant schemes with GPS failure (not issued)
followed by a switch to a split path on one channel and a comms. failure on the
other
 Prevented software errors from clearing event log
 Unextracted disturbance records now set the courier status flag on power up
 Added support for MODBUS function code 7
 Corrected the MODBUS status bit 0
 Corrected the OTEV bit in the status of fault in IEC 60870-5-103
First phase 2 release to production
 Includes all of 10F
 Added CS103 monitor/command blocking
 PSB now uses 6 comparators
 Distance directional line fixed at -30º
11 A B 13 Sep 2001 V2.03 or later P54x/EN T/D11
 PSB block issued when impedance passes into any Z1, Z2 or Z3
 PSB unblock via negative sequence current now done via PSL
 Modified co-processor initiation to run on 1 wait state (memory access problem)
 Fixed a problem with P545 & P546 opto & relay labels in disturbance record
 Fixed the GPS inhibit
All builds released to production. Based on 11A software
 Modified the co-processor start-up routine to work with alternative types of
SRAM
 Improved response to a CS103 poll class 1 when monitor blocked was active
 Resolved a time alignment problem which resulted in C diff failure alarms being
11 B B 19 Oct 2001 raised V2.03 or later P54x/EN T/D11
 Corrected some MODBUS address for P545 & P546
 Fixed a problem with the relays response to MODBUS commands read coils and
read inputs
 Fixed an incorrect response to a DNP3.0 command
S/W S/W
Major Minor
 Fixed a problem in P541 & P542 CS103 builds where the voltage and power
11 C B 19 Dec 2001 measurements were not being marked as invalid V2.03 or later P54x/EN T/D11
 Fixed a problem in P544 & P546 where the SEF current measurement was
incorrect when set to 1A & 60Hz
All builds released to production. Based on 11C software
11 D B 28 Jan 2002  Resolved possible reboot caused by invalid MODBUS requests V2.03 or later P54x/EN T/D11
 Resolved problem when internal loopback was selected with external clocks
 Resolved a problem which caused the loss of IEC 60870-5-103 class 1 messages
All builds released to production. Based on 11D software
11 E B 1 Oct 2002  Correct operation of capacitive charging current compensation in 3 terminal V2.03 or later P54x/EN T/D11
schemes
 Resolved problem which caused short duration GPS failure alarms
All builds ready. Based on 11E software
 Resolved several problems related to the IEC 60870-5-103 protocol
11 F B 17 Feb 2003 V2.03 or later P54x/EN T/D11
 Resolved problem which may cause short duration current differential trips
 Corrected the format used to display frequency over the MODBUS interface
All builds ready. Based on 11F software
 Changes to clock recovery circuits to improve operation with multiplexers
11 G B 19 May 2003  PSL logic for user defined intertrips corrected P545 & P546 V2.03 or later P54x/EN T/D11
 Prevented unwanted comms. delay alarms
All builds ready. Based on 11G software
11 H B 16 Sep 2003 V2.03 or later P54x/EN T/D11
 Prevents CS103 reporting more non-compressed disturbance records than
actually present
S/W S/W
Major Minor
 Differential intertrip in IEC 60870-5-103 reported with correct FAN
 SRAM self checking added to co-processor board
 Fixed an incorrect response of the summertime time bit in IEC 60870-5-103
11 I B 19 Oct 2004 protocol V2.03 or later P54x/EN T/D11
 Prevented incorrect behaviour of P545/P546 when one relay is energized when
there is noise on the signaling channel
 Status of local GPS reported incorrectly in dual redundant schemes
 Setting “Char Mod Time” was missing on P541 - P544
register
 Prevents relay crashing when phase 2 software used with phase 1 optos
 Cell 0709 now replies OK change
11 J B 27 Jul 2005 V2.03 or later P54x/EN T/D11
Released for validation testing only
 2nd rear comms. added
 Alarms increased to 64 with user programmable alarms
 Enhancements and corrections to CS103
 Prevented additional events being generated on power up
12 A B 28 Mar 2002  French language text improvements V2.05 or later P54x/EN T/E21
register
 Setting “Char Mod Time” was missing on P541 - P544
 Prevents relay crashing when phase 2 software used with phase 1 optos
 Cell 0709 now replies OK change
S/W S/W
Major Minor
 Correct operation of capacitive charging current compensation in 3 terminal
schemes
 Resolved problem which caused short duration GPS failure alarms
 Resolved problem selecting setting group via optos
 Resolved a circuit breaker lockout problem
 Corrected the thermal measurement displayed when thermal protection is
disabled
 Spanish text for user defined alarms contained an extra letter
 Blocked overcurrent elements now generate events
 Correct DNP3.0 operation of object 10
 Resolved problem with P541 & P542 IEC 60870-5-103 builds not running
12 B B 19 Nov 2002 V2.05 or later P54x/EN T/E21
 Resolved a problem with IEC 60870-5-103 class 1 polling
 Resolved a problem with IEC 60870-5-103 ASDU2 events which occurred prior to
a start event
 Correct the format used to display frequency over the MODBUS interface
 Resolved problem related to incorrect CB trip/close commands via MODBUS
 Resolved problem related to CB trip/close commands via MODBUS being
accepted when not selected
 Resolved a problem which prevented protection setting being saved after
control and support setting had been saved
 Corrected the saving of fault locator settings in groups 2, 3, 7 & 4 when made via
user interface
 Added object 10 to DNP3.0 class 0 poll
 Corrected the way DNP3.0 handled the season bit in the time & date
 Improved self diagnostics relating to input module clock
12 C B 17 Mar 2003  Modified courier block transfer mechanism so it can handle more than 255 V2.05 or later P54x/EN T/E21
blocks
 Intermittent loss of data from 2nd rear comms. port corrected
 PSL logic for user defined intertrips corrected P545 & P546
12 D B 4 Jun 2003  Changes to clock recovery circuits to improve operation with multiplexers V2.05 or later P54x/EN T/E21
S/W S/W
Major Minor
12 E B 16 Sep 2003  Correction to operation of reset relays/LEDs opto V2.05 or later P54x/EN T/E21
 Prevents CS103 reporting more non-compressed disturbance records than
actually present
Not released to production. Supplied to one customer. Based on 12E software
12 F B 10 Jun 2004  Improved self-checking of analogue data acquisition V2.05 or later P54x/EN T/E21
12 G B 11 Oct 2004 V2.05 or later P54x/EN T/E21
protocol
12 H B 4 May 2005 V2.05 or later P54x/EN T/E21
12 I B 3 May 2006 V2.05 or later P54x/EN T/E21
 Improvements to the distance protection
S/W S/W
Major Minor
 Control inputs enhancements including non-volatile, latched, pulsed and support
for DNP3.0 pulsed.
 Enhanced DNP3.0
 Distance Residual compensation angle range extended
 Display of number of good messages via MODBUS is corrected
 Prevented DNP3.0 time sync causes relay to reboot when IRIG-B is active
13 A B 22 Apr 2004 V2.10 or later P54x/EN T/E21
 Added TRIP & ALARM to MODBUS status word
 Addition of MODBUS only setting to allow transmission of IEC time format in
reverse IEC byte order
 Handling of FAN in IEC 60870-5-103 improved
 Fault location & cumulative broken current measurements reported over DNP3.0 V2.10 or later
13 B B 5 Aug 2004 (DNP3.0 files) P54x/EN T/E21
 Accuracy of MODBUS time sync improved
different from 13A
 Invalid MODBUS register 4x00966 removed
 Resolved a problem relating to co-processor SRAM checking
 Fixed an incorrect response of the summertime time bit in IEC 60870-5-103 V2.10 or later
13 C B 5 Oct 2004 protocol (DNP3.0 files) P54x/EN T/E21
 Prevented incorrect behavior of P545/P546 when one relay is energized when different from 13A
S/W S/W
Major Minor
 Correction to single pole auto-reclose
 Remapped fun/inf. 192/130 in P543 & P545
 Display of no. valid messages on LCD corrected
 DNP3.0 improved binary scanning
V2.10 or later
 Operation of CB maintenance alarm corrected
13 D B 21 Mar 2005 (DNP3.0 files) P54x/EN T/E21
 Corrections to allow extended courier characters to be used in string setting different from 13A
cells for courier and MODBUS
 Corrected default display of neutral current for 5A CTs
 Prevented a reboot for DNP3.0 versions when control & support settings are
changed rapidly
 Changes to co-processor start-up to eliminate a timing problem
V2.10 or later
13 E B 28 Apr 2005 (DNP3.0 files) P54x/EN T/E21
different from 13A
 Add interframe gap to DNP3.0
 Corrections to IRIG-B V2.10 or later
13 F B 19 Jun 2006  Vector group compensations for YY2 and YY10 corrected (DNP3.0 files) P54x/EN T/E21
 Corrected reporting of distance & C diff stars over CS103 different from 13A
 Reports the correct COT for reset LEDs command sent via S1
 Corrected a problem which occurs when two relays power up when one is
configured out
V2.10 or later
Only P543 DNP3.0 released to a customer. Based on 13F software
13 G B 13 Nov 2007 (DNP3.0 files) P54x/EN T/E21
 Improvements to DNP3.0
different from 13A
All builds released to production. Based on 13F software.
 Improvements to DNP3.0
 Fixed auto-reclose problem
 Resolved a problem relating to CT Ratio’s not being restored when restoring V2.10 or later
13 H B 19 Dec 2007 default settings (DNP3.0 files) P54x/EN T/E21
 Resolved a problem with the disturbance recorder which saturates for High different from 13A
current levels into 5A CT
 Resolved problem with relay recognising non zero entry in 14th position of
model number
V2.10 or later
Only P545 builds released to production. Based on 13H software
13 I B 1 Oct 2008 (DNP3.0 files) P54x/EN T/E21
 Resolved auto-reclose problems
different from 13A
S/W S/W
Major Minor
Released for China only
14 A B 12 Nov 2003  Current transformer Supervision added V2.10 or later -
 A number of bugs have been fixed
Released to China only. Based on 14A software
 Differential Intertrip in IEC 60870-5-103 reported with correct FAN
 Corrected a CTS setting when 5A inputs selected
14 B B 25 Oct 2004  Rejection of spurious messages injected onto RS485 network improved V2.10 or later -
protocol
Released to China only. Based on 14B software
14 C B 22 Jun 2005 V2.10 or later -
 Removal of distance protection
 Corrected a CTS setting when 5A inputs selected
15 A B 18 Mar 2004  Small changes to CTS V2.10 or later -
 CT ratio correction setting moved into setting groups
 Default setting for measurements and settings changed to secondary
 A number of bugs have been fixed
 Correction to CTS for 5A applications
15 B B 23 Jul 2004  Improved self checking of SRAM V2.10 or later -
 Corrected VTS setting which was only actioned on power up
 MODBUS protocol added
15 C B 24 Aug 2004 V2.10 or later -
protocol
S/W S/W
Major Minor
 Migration of Platform from version C4.2 to C4.7
 Display of good messages could go negative corrected
 Corrected wrong display of number of good messages via MODBUS
 Resolved changing settings on a DNP3.0 relay rapidly sometimes causing a
15 D B 17 Nov 2005 reboot. It appeared the problem occurred if 4 or more control & support settings V2.10 or later -
were sent in quick succession
 Resolved attempts to set the data cell [04 20] Thermal State, returning 'Local
Access in Progress' instead of 'Remote Access Denied'
 Resolved CTS Block operating transiently when MODBUS communications were
running
Release of P543 CS103 for Germany only. Based on 13F
16 A B 24 Jul 2006 Patch for V2.12 P54x/EN T/E21
 CS103/auto-reclose modifications
Release of P543 CS103 for Germany only. Based on 16A
 Corrected some German text
16 B B 1 Dec 2006 Patch for V2.12 P54x/EN T/E21
 Generated events for main starts
 Added some DDB to disturbance recorder
Internal release for validation only - runs on phase 2 processor board. Based on
12B
 UCA2 option added
 Russian text added (not complete)
 Added fault location to for IEC 60870-5-103
 Added TRIP & ALARM to MODBUS status word
 Distance direction setting added
 Distance residual compensation angle range extended
 Indication of password status on DDB (code added but not run)
 Improvements to auto-reclose
20 A G 19 Nov 2002 - -
 Alarms increased to 96
 Corrected the response to courier SEND EVENT
 Removed the setting for IEC 60870-5-103 over fiber when hardware not present
 Resolved problem related to CB trip/close commands via MODBUS being
accepted when not selected
 Corrected the saving of fault locator settings in groups 2, 3 & 4 when made via
user interface
 Added object 10 to DNP3.0 class 0 poll
 Corrected the way DNP3.0 handled the season bit in the time & date
S/W S/W
Major Minor
Internal release for validation only. Based on 20A
 Enhanced check synchronization feature
 Control inputs enhancements including non-volatile, latched, pulsed and support
for DNP3.0 pulsed
 BBRAM used in disturbance recorder optimized
20 B G 29 Apr 2003 - -
 Modified courier block transfer mechanism so it can handle more than 255
blocks
 PSL logic for user defined intertrips corrected P545 & P546
 Operation of manual reset alarms corrected
 A number of bug fixes relating to CPU2
Internal release for validation only. Based on 20B
20 C G 29 Apr 2003  CB control via hot keys - -
Internal release for validation only. Based on 20C
 Changes to clock recovery circuits to improve operation with multiplexers
 Enhanced auto-reclose feature added
 Alarms handled better in CS103 GI
20 D G 7 Jul 2003  Time synchronization via opto added V2.09 or later P54x/EN T/F32
 Platform alarms copied to DDB
 Correction to operation of reset relays/LEDs opto
 Backup protection run if co-processor fails to start up on power on
 Correction to cell 0B25
Limited release for NiCAP + selected others
 Extraction of disturbance recorder over MODBUS added
 Resolve nucleus missing HISR problems
20 E G 23 Oct 2003 V2.09 or later P54x/EN T/F32
 Enhancements to IDMT curves
 Display of number of good messages via MODBUS is corrected
S/W S/W
Major Minor
Release to production. Based on 20E
 UCA2: Increase max. pending requests & max. connected clients
 Enhanced DNP3.0
20 F G 4 Feb 2004  Prevented DNP3.0 time sync causes relay to reboot when IRIG-B is active V2.09 or later P54x/EN T/F32
 Corrected cause of transmission which may be returned for "Fault Location"
 Prevents relay rebooting during EMC ANSI fast transient and IEC high frequency
Release to production. Based on 20F software
 Prevented repeated downloads of GSL files without Ethernet card restart
rebooting Ethernet card
 Correction to uploading of disturbance records over UCA2
 Corrected operation of Ethernet card link LED for 10 Base-FL
 Closed UCA2 association after "dirty" client disconnection
 Made UCA2 disturbance record directory service compatible with PACiS
20 G G 1 Jun 2004 V2.09 or later P54x/EN T/G42
 Corrected under and over voltage blocking of check sync
 Handling of FAN in IEC 60870-5-103 improved
 Prevented C diff fail alarm occurs before signaling fail alarm for loss of
communications
Release to production. Based on 20G software
protocol
20 H G 5 Oct 2004 V2.09 or later P54x/EN T/G42
 Accuracy of MODBUS time sync improved
protocol
 Prevented Ethernet card restarting after approximately 20 hours when no
connection made
 Improvements to time sync for courier, CS103 and DNP3.0
S/W S/W
Major Minor
Release to production. Based on 20G software
 Corrections to allow extended courier characters to be used in string setting
20 I G 22 Nov 2004 cells for courier and MODBUS V2.09 or later P54x/EN T/G42
 Prevented a reboot for MODBUS versions during event extraction when
messages where close together
 Correction to prevent the 2nd rear comms. locking up
Release to production. Based on 20I software
20 J G 7 Apr 2006  Correction to IEEE/US inverse reset setting V2.09 or later P54x/EN T/G42
Release to production. Based on 20J software
 Corrections to IRIG-B
20 K G 26 Apr 2006  Vector group compensations for YY2 and YY10 corrected V2.09 or later P54x/EN T/G42
 Corrected reporting of distance & C diff stars over CS103
configured out
P545 Release to Production. Based on 20K software.
 Resolved a problem which interrupted the UCA2 communications periodically
 Resolved a problem relating to CT Ratio’s not being restored when restoring
default settings
20 L G - V2.09 or later P54x/EN T/G42
 Resolved a problem with the Disturbance Recorder which saturates for High
 Resolved problem with relay recognising non zero entry in 14th position of
model number
Release to Production. Based on 20L software.
 Improvements to the GPS code
 Improvements in the clock recover circuits used by the differential comms.
20 M G 4 Nov 2009  Correction to the way latched LED/Relays are cleared V2.09 or later P54x/EN T/G42
 Correction to auto-reclose operation for switch on to fault condition
 Prevented CB Operating Time displaying 4.295Ms
 Bug fixes
S/W S/W
Major Minor
Release to Production. Based on 20M software
 Prevented the differential protection inhibiting in three terminal schemes when
20 N G 14 Jan 2010 GPS is enabled and loopback mode selected V2.09 or later P54x/EN T/G42
 Fault locator measurements in ohms corrected when 5A CT used or displayed in
primary
Released to selected customers only. Based on 20G
 Interface to optical multiplexer (IEEE standard C37.94)
 SRAM checking in co-processor
 Dual range optos
 AREVA livery & software changes
 Extended residual angle in fault locator to match distance
 Rename GOOSE signals in line with P443
 Add virtual signals, control inputs & user alarms to DR in line with P443
 Relay settings shall be stored in FLASH EEPROM instead of EEPROM memory
V2.11 or later
30 A J 24 Sep 2004  Extend range of time dial to line up with P140 P54x/EN T/G42
(No language file
 Accuracy of MODBUS time sync improved support)
 Improvements to time sync for courier, CS103 and DNP3.0
 Addition of MODBUS only time and date format setting to common courier
settings for access from the other interfaces
 Vector group compensations for YY2 and YY10 corrected
 Prevented Ethernet card restarting after approximately 20 hours when no
connection made
S/W S/W
Major Minor
Released to production but held. Based on 30A
 Courier, MODBUS & DNP3.0 communications over Fiber added
 Some text in auto-reclose column made consistent with that in overcurrent
column
 Improvements to VTS and auto-reclose in single pole tripping applications
 Corrections to allow extended courier characters to be used in string setting
30 B J 12 Nov 2004 cells for courier and MODBUS V2.11 or later P54x/EN T/H53
protocol
 Corrected reporting of local GPS fail in dual redundant schemes
 Prevented a reboot for DNP3.0 versions when control & support settings are
changed rapidly
 Prevented a reboot for MODBUS versions during event extraction when
messages were close together
Released to production. Based on 30B
 Correction to prevent the 2nd rear comms. locking up
30 C J 29 Nov 2004  Correction to prevent the front panel UI and comms. lockup after continued V2.11 or later P54x/EN T/H53
operation
Released to production. Based on 30C
30 D J 15 Dec 2004  Improvements to operation when subjected to multiple communication switches V2.11 or later P54x/EN T/H53
when operating in non-GPS mode
Released to production. Based on 30D
30 E J 31 Jan 2005  VTS enhanced to restore 3 software version 20 performance for three pole V2.11 or later P54x/EN T/H53
tripping whist keeping the improvements for 1 pole tripping added at 30B
Released to production. Based on 30E
 Enhancements to the current differential performance under switched
30 F J 18 Mar 2005 communication channels V2.11 or later P54x/EN T/H53
 Correction to the CS103 mapping for platform alarms
Released to production. Based on 30E
30 G J 5 Apr 2006 V2.11 or later P54x/EN T/H53
 Correction to IEEE/US Inverse reset setting
Limited release P542 DNP3.0 to a customer
30 H J 18 Apr 2006 V2.11 or later P54x/EN T/H53
S/W S/W
Major Minor
Released to production. Based on 30G
 Corrections to IRIG-B
 Vector group compensations for YY2 and YY10 corrected
30 I J 24 May 2006 V2.11 or later P54x/EN T/H53
 Corrected reporting of distance & C diff stars over CS103
configured out
 Modification to allow individual MODBUS register access
Release of P543, P544, P545 & P546 without distance protection
 CTS
 Definitive time directional negative sequence overcurrent I2>
 GPS synchronization of current differential in all models
 P543 and P545 now facilitate in zone transformer-feeder applications
Patch for V2.12
40 A K 4 May 2006  All models support ABC and ACB phase rotation P54x/EN M/I64
V2.13 or later
 Standard and Inverted CT polarity setting for each set of CTs in the relay
 User interface with tri colored LED and function keys
 InterMiCOM64
 Voltage protection
 Backwards compatibility mode
Release of P543, P544, P545 & P546 without distance protection based on 40A
 IEC 61850-8-1
 High break options
 Demodulated IRIG-B options Patch for V2.12
41 C K 30 Jul 2006 P54x/EN M/J74
 Reduction of distance minimum reach settings to 0.05 ohm V2.13 or later
 Permissive trip reinforcement
 Poledead modifications for Hydro Quebec
Release of P543, P544, P545 & P546 without distance protection based on 41C
 Prevents a possible reboot 15 minutes after browsing the front courier port but
not making a setting change i.e. browsing using PAS&T. Patch for V2.12
41 D K 16 Aug 2006 P54x/EN M/J74
 Extended GOOSE enrolment capability V2.13 or later
 Correction to ICD files, enumeration (value) and fixed data mapping
S/W S/W
Major Minor
Release of P543, P544, P545 & P546 without distance protection based on 41D
 Prevent a reboot in 61850 builds when NIC link is inactive and avalanche of DDB
activity
 Correctly report a fatal error generated by the sampling call-back
 Correct the operation of the GOOSE messaging and a problem with the Patch for V2.12
41 E K 14 Nov 2006 download of an IED Configuration file P54x/EN M/J74
V2.13 or later
 Correct the operation of the check sync
 Correct the operation of the overcurrent reset curves
 Removed check on the14th position of model number
 Fixed Telegrams for public inf. 64-67
Release of P543, P544, P545 & P546 without distance protection based on 41E
 Prevent a fatal error from an incorrect DNP address in not using DNP evolutions
platform
 Default setting for 450B 'I< Current Set' reduced to 50mA
 French translations for DDBs 1368-1371 corrected
 Fun & INF values related to CS103 Command Blocking corrected
 Angle for negative sequence phase overcurrent setting corrected
 Corrected operation when using MiCOM S1 is used to activate settings group by
right clicking on the group Patch for V2.12
41 F K 15 May 2007 P54x/EN M/J74
 Corrected the latching of Function Key DDB signals on relay power up V2.13 or later
 Corrected disturbance recorder scaling to prevent high current levels into 5A CT
causing the disturbance recorder to saturate
 Restring defaults appears not to change the 1/5A CT selection
 Corrected the performance of the IM64 direct mode
 CB control via direct access does not work with 2CB versions of P540D
 Auto-reclose dead time/close cycle continues even if AR switched out of service
 Ch2 Statistics may not be displayed
P543, P544, P545 & P546 non 61850 builds without distance protection based on
41 G K May 2007 41F was approved for release but withdrawn before release Patch for V2.12 P54x/EN M/J74
 Corrections to enable/disable of auto-reclose
Release of P543, P544, P545 & P546 without distance protection based on 41G
41 H K 4 Jul 2007 Patch for V2.12 P54x/EN M/J74
S/W S/W
Major Minor
Release of P543, P544, P545 & P546 non 61850 builds without distance protection
based on 41H
GPS is enabled and loopback mode selected
 Improvements in the clock recover circuits used by the differential comms
 Correction to P545/P541 compatibility when used in transformer compensation
mode
 Correction to the way latched LED/Relays are cleared
41 I K 14 Jan 2010  Corrections to the Current Differential Inhibit when the GPS synchronization is Patch for V2.12 P54x/EN M/J74
disabled
 Corrections to menu text
 Corrected some French and German text
 Fixed Inhibit CB Fail Protection in P544/6
 Improved co-processor error reporting
 Fixed a SOTF problem
Release of P543, P544, P545 & P546 non 61850 builds without distance protection
41 J K 5 Oct 2010 based on 41J Patch for V2.12 P54x/EN M/J74
 Fixed a problem with the co-processor stack check which could cause a re-boot
S/W S/W
Major Minor
Release of P543, P544, P545 & P546 without distance protection
 Chinese interface
 Replacing the existing DNP3.0 with the DNP3.0 evolutions
 Replacement of existing negative sequence overcurrent with multi stage (2 IDMT
+ 2 DT) negative sequence overcurrent.
 Addition of IDG curve, commonly used in Sweden, to Earth Fault & Sensitive
Earth Fault (involves moving settings)
 Reduction of all TMS step sizes to 0.005
 Addition of Channel propagation delay statistics and alarms
 Changes to CTS so both techniques can be selected together
 Regrouping of CTS settings
 Addition of four stages of under frequency protection and two stages of P54x/EN M/J74
42 A K May 2007 overfrequency protection Patch for V2.14 + Addendum
 Addition of df/dt protection P54x/EN AD/J84
 Changes to under and overvoltage to enable each stage to be independently set
 Extensions to the check sync VT position setting
 Changes to Permissive Inter Trip (PIT) logic to enable the user to select either
local or remote current to be used.
 Includes local time zone settings for date & time
 Reduced minimum setting for IN> I2pol Set
 Addition of propagation delay times to Fault Record
 Enhancement to self checking of output relays
 Change tunnelled courier address to follow the 1st Rear Port’s KBUS or CS103
address
 Improvements to VTS
 Corrections to enable/disable of auto-reclose P54x/EN M/J74
42 B K 4 Jul 2007  Resolved a problem relating to CT Ratio’s not being restored when restoring Patch for V2.14 + Addendum
default settings P54x/EN AD/J84
 Resolved a problem with the Disturbance Recorder which saturates for high
Release of P543, P544, P545 & P546 without distance protection based on 42B
 Fixed a number of 61850/Goose problems
P54x/EN M/J74
 Minor correction to fault record
42 D K 17 Dec 2007 Patch for V2.14 + Addendum
 Corrections to over voltage stage 2 inhibit
P54x/EN AD/J84
 Fixed the max. prop alarm
 Corrected some DDB German text
S/W S/W
Major Minor
P54x/EN M/J74
 Fixed a number of 61850 problems
42 E K 14 May 2008 Patch for V2.14 + Addendum
P54x/EN AD/J84
Not released to production. Based on 42E
P54x/EN M/J74
42 F K - Patch for V2.14 + Addendum
P54x/EN AD/J84
 Bug fixes
P54x/EN M/J74
Release of P543, P544, P545 & P546 without distance protection based on 42F
42 G K 28 Oct 2008 Patch for V2.14 + Addendum
 Correction to the distance cross polarizing when the memory expires
P54x/EN AD/J84
Release of P543, P544, P545 & P546 without distance protection based on 42G
 Corrected some menu translations
 Corrected Breaker Fail - WI Aided1 trips so they can be disabled via setting "WI
Prot Reset"
 Timestamp in fault record adjusted for the local time setting
 Corrected P543 default PSL
 Corrections to the Current Differential Inhibit when the GPS synchronisation is
disabled
 Corrected Thermal State measurement via DNP3.0 P54x/EN M/J74
42 H K 21 Sep 2009  Correction to the way latched LED/Relays are cleared Patch for V2.14 + Addendum
 Correction to negative sequence overcurrent settings when 5A input used P54x/EN AD/J84
mode
 Prevented CTS generating events when CTS is disabled
 Prevent Z5 from setting slow swing when PSB is disabled
 Fixed problem which prevented residual overvoltage from initiating CB Fail
 Various improvements to DNP3.0, CS103 & IEC 61850 protocols
 Bug fixes
Release of P543, P544, P545 & P546 without distance protection based on 42H
 Fixed a 61850 issue which blocked clients when one was disconnected P54x/EN M/J74
42 I K 6 Dec 2010  Rebranded as Alstom. Minor change to software number plus changes to 61850 Patch for V2.14 + Addendum
(New ICD files required) P54x/EN AD/J84
 Bug fixes
S/W S/W
Major Minor
Release of P543, P544, P545 & P546 without distance protection based on 52J
 Current Differential communications are not stopped temporarily when
navigating the default display.
42 K K 12 Sep 2014  CT Supervision can be operated in P543 42K software.
 CB Fail trip can be operated under faults with DC transient offsets.
 Fix some bugs.
Release of P543 & P545 with distance protection based on 42J
 Disconnection of one of IEC 61850 Client causes other IEC 61850 Connections
being Lost
 The disturbance record list does not show the most recent DR
42 K K 12 Sep 2014
 P145 reboots periodically when IEC 61850 comms active and SNTP active
 Discrepancy in the DR analogue signals magnitudes if the CT and VT ratios
(primary/secondary) are not integers.
 Incorrect behaviour of the latched LED
 Positional information added to PSL
 DNP 3.0 Over Ethernet protocol added
 Extended I/O – status inputs increased from 24 to 32
 Compensated overvoltage protection added
 IEC-103 Generic Services Measurements added Patch for V2.14 P54x/EN M/J74
44 A K 18 Mar 2008  Set/Reset Latch Logic Gates added to PSL First release of + Addendum
 Fault record to include current differential currents recorded at the time of the Studio P54x/EN AD/J94
current differential trip in addition to the existing data from 1 cycle later
 Fault record increased max. number of fault records to 15
 GPS Alarm modifications
 DNP enhancements for SSE
 Bug fixes
Patch for V2.14 P54x/EN M/J74
44 B K 25 Jun 2008 First release of + Addendum
Studio P54x/EN AD/J94
 Fixed a problem which prevented extraction of DNP3.0 setting files from DNP3.0
over Ethernet variants
S/W S/W
Major Minor
 Corrections to the Current Differential Inhibit when the GPS synchronisation is
disabled Patch for V2.14 P54x/EN M/J74
44 D K 20 Jan 2009  Corrected Thermal State measurement via DNP3.0 First release of + Addendum
 Timestamp in fault record adjusted for the local time setting Studio P54x/EN AD/J94
Prot Reset"
 Prevents the loss of IEC 61850 messages and fixed the handling of the ACD flag
44 E K 20 Mar 2009 during GI First release of + Addendum
 Improved the Ethernet card boot code
 Corrected P543 default PSL
 Correction to negative sequence overcurrent settings when 5A input used
44 F K 21 Sep 2009 mode First release of + Addendum
 Bug fixes
 Fixed a 61850 issue which blocked clients when one was disconnected
44 G K 19 Oct 2010 First release of + Addendum
 Improvements to Fault record display over Courier and DNP3.0
 Bug fixes
Release of P543, P544, P545 & P546 with out distance protection based on 44G
 Rebranded as Alstom. Minor change to software number plus changes to 61850 Patch for V2.14 P54x/EN M/J74
44 H K 11 Jan 2011 (New ICD files required) First release of + Addendum
Release of P543, P544, P545 & P546 without distance protection based on 44E Patch for V2.14
45 B K 30 Mar 2009 P54x/EN M/KA4
 Auto-reclose, Check Sync and CB Monitoring added to P544 & P546 Studio FTP server
S/W S/W
Major Minor
 Improvements to the Ethernet card start-up and configuration
mode Patch for V2.14
45 C K 15 May 2009 P54x/EN M/KA4
 Correction to the way latched LED/Relays are cleared Studio FTP server
 Bug fixes
Release of P543, P544, P545 & P546 without distance protection based on 45C
 Improvements to the GPS code Patch for V2.14
45 D K 28 Oct 2009 P54x/EN M/KA4
 Improvements in the clock recover circuits used by the Differential Comms. Studio FTP server
 Bug fixes
 Rebranded as Alstom. Minor change to software number plus changes to 61850 Patch for V2.14
45 E K 11 Jan 2011 (New ICD files required) P54x/EN M/KA4
Studio FTP server
 Fixed dnp3 control of CB2
 Improved the distance performance for cross country faults
 Enhanced the OST feature to make it more stable when currents are low
 Time stamping and status of IEC61850 Data attribute sofPSOF1.ST.general.Op
improved
 Improvements to Fault record display over courier and dnp3 Patch for V2.14
45 F K 15 Jun 2012 P54x/EN M/KA4
 Fixes to Autoreclose Studio FTP server
 Improvements to co-processor SRAM checking
 Fixed PIT
 Several fixes to IEC61850 problems
 Added Frequency trips to P445 default PSL
 Fixed an issue where Disturbance recorder could get out of sync
S/W S/W
Major Minor
 IEC 61850 phase 2 and 2.1 implemented
 Application for Inzone Transformers (2nd and 5th Harmonic Blocking/restraint)
 Differential Highset can be disabled when Inrush protection is enabled P54x/EN M/KA4
Patch for V2.14
47 A K -  Restricted Earth Fault Protection (REF) + Addendum
Studio FTP server
 Modification to Char Mod timer functionality P54x/EN AD/KB4
 Separate measurements for each set of CT’s
 Interrupt Driven InterMiCOM in all models
 Read Only Mode
P54x/EN M/KA4
GPS is enabled and loopback mode selected Patch for V2.14
47 B K 10 Feb 2010 + Addendum
 Fault locator measurements in ohms corrected when 5A CT used or displayed in Studio FTP server
primary P54x/EN AD/KB4
 Frequency measurement in DNP3.0 fault record corrected
 Enhancement to GOOSE performance
 Fixes to 61850 P54x/EN M/KA4
Patch for V2.14
47 D K 15 Oct 2010  Fixed protection comms. address problem in three ended scheme selected + Addendum
Studio FTP server
 Fixed DNP3.0 control of CB2 P54x/EN AD/KB4
 Incorrect mapping of XCBR(n).CBOpCap.stVal data attribute corrected
 Improvements to fault record display over Courier and DNP3.0
Release of P543, P544, P545 & P546 without distance protection based on 47D P54x/EN M/KA4
Patch for V2.14
47 E K 11 Jan 2011  Rebranded as Alstom. Minor change to software number plus changes to 61850 + Addendum
(New ICD files required) Studio FTP server
P54x/EN AD/KB5
 Improvements to CB Fail reset times
P54x/EN AD/Lb4
 Several fixes to IEC 61850 problems
Patch for V2.14 +
47 F K 9 Aug 2012  Improved the co-processor SRAM checking
Studio FTP server P54x/EN M/La4
 Fixed an issue relating to Permissive Intertripping
 Improvement to disturbance recorder
 Bug fixes
S/W S/W
Major Minor
 DTS PX40PL-33 Error code “0x0C160013”
 P540D-108 The enabling logic for P445 AutoReclose does not allow for local
P54x/EN AD/Lb4
override by DDB. PQIM : 2014.009 Patch for V2.14
47 H K 5 Aug 2015 +
 P540D-66 CB Fail trip may fail to operate under faults with DC transient offsets. Studio FTP server
P54x/EN M/La4
 P540D-22 When using a Dual Redundant IEE C37.94 Differential Scheme with
N=12, if one leg of the communications path is broken the relay can reboot.
 Bug fixes
Release of P543, P544, P545 & P546 with distance protection
 Distance protection from P443
 DEF from P443
 Aided distance & DEF schemes from P443
 CTS
 Definitive time directional negative sequence overcurrent I2>
 GPS synchronization of current differential in all models Patch for V2.12
50 A K 4 May 2006 P54x/EN M/I64
 P543 and P545 now facilitate in zone transformer-feeder applications V2.13 or later
 All models support ABC and ACB phase rotation
 Standard and inverted CT polarity setting for each set of CTs in the relay
 User interface with tri-colored LED and function keys
 InterMiCOM64
 Voltage protection
 Backwards compatibility mode
Release of P543, P544, P545 & P546 with distance protection based on 50A
 IEC 61850-8-1
 High break options
 Demodulated IRIG-B options
Patch for V2.12
51 C K 30 Jul 2006  Reduction of distance minimum reach settings to 0.05 ohm P54x/EN M/J74
V2.13 or later
 Permissive trip reinforcement
 Poledead modifications for Hydro Quebec
 Out of step tripping
Release of P543, P544, P545 & P546 with distance protection based on 51C
 Prevents a possible reboot 15 minutes after browsing the front courier port but
not making a setting change i.e. browsing using PAS&T Patch for V2.12
51 D K 16 Aug 2006 P54x/EN M/J74
 Extended GOOSE enrolment capability V2.13 or later
 Correction to ICD files, Enumeration (value) and fixed data mapping
S/W S/W
Major Minor
Release of P543, P544, P545 & P546 with distance protection based on 51D
 Prevent a reboot in 61850 builds when NIC link is inactive and avalanche of DDB
activity
 Correctly report a fatal error generated by the sampling call-back
 Correct the operation of the GOOSE messaging and a problem with the Patch for V2.12
51 E K 14 Nov 2006 download of an IED configuration file P54x/EN M/J74
V2.13 or later
 Correct the operation of the check sync
 Correct the operation of the overcurrent reset curves
 Removed check on the14th position of model number
 Fixed Telegrams for public inf. 64-67
Release of P543, P544, P545 & P546 non 61850 builds with distance protection
based on 51E
 Prevent a fatal error from an incorrect DNP3.0 address in not using DNP3.0
evolutions platform
 French Translations for DDBs 1368-1371 corrected
 Dependencies for cells 3242 & 3245 corrected
 Fun & INF values related to CS103 Command Blocking corrected
 Angle for negative sequence phase overcurrent setting corrected
 Corrected operation when using MiCOM S1 is used to activate settings group by
right clicking on the group Patch for V2.12
51 F K 15 May 2007 P54x/EN M/J74
 Corrected the latching of Function Key DDB signals on relay power up V2.13 or later
 Corrected disturbance recorder scaling to prevent high current levels into 5A CT
causing the Disturbance Recorder to saturate
 Restring defaults appears not to change the 1/5A CT selection
 Corrected the performance of the IM64 direct mode
 CB control via direct access does not work with 2CB versions of P540D
 Auto-reclose dead time/close cycle continues even if AR switched out of service
 Distance setting are not updated in simple setting mode in setting groups other
than the active one
 Ch2 Statistics may not be displayed
P543, P544, P545 & P546 non 61850 builds with distance protection based on 51F
51 G K - was approved for release but withdrawn before release Patch for V2.12 P54x/EN M/J74
based on 51G
51 H K 4 Jul 2007  Corrected power swing detection when both distance and current differential Patch for V2.12 P54x/EN M/J74
enabled
S/W S/W
Major Minor
based on 51H
GPS is enabled and loopback mode selected
 Improvements in the clock recover circuits used by the Differential Comms.
mode
 Corrections to the Current Differential Inhibit when the GPS synchronization is
disabled
51 I K 14 Jan 2010 Patch for V2.12 P54x/EN M/J74
 Fix for DEF reverse operation
 Fix to Blocking scheme
 Fixed a SOTF problem
based on 51I
51 J K 5 Oct 2010  Fixed a problem with the co-processor stack check which could cause a re-boot Patch for V2.12 P54x/EN M/J74
 Improved the distance performance for 2ph-g and also cross country faults
S/W S/W
Major Minor
Release of P543, P544, P545 & P546 with distance protection
 Chinese interface
 Replacing the existing DNP3.0 with the DNP3.0 evolutions
 Addition of a current but no volts trip option to Switch on to Fault and Trip on
Reclose feature (SOTF/TOR)
 Replacement of existing negative sequence overcurrent with multi stage (2 IDMT
+ 2 DT) negative sequence overcurrent
 Addition of IDG curve, commonly used in Sweden, to Earth Fault & Sensitive
Earth Fault (involves moving settings)
 Reduction of all TMS step sizes to 0.005
 Addition of channel propagation delay statistics and alarms
 Changes to CTS so both techniques can be selected together
 Regrouping of CTS settings
 Addition of four stages of under frequency protection and two stages of
overfrequency protection
 Addition of df/dt protection P54x/EN M/J74
52 A K -  Changes to under and overvoltage to enable each stage to be independently set Patch for V2.14 + Addendum
 Extensions to the Check Sync VT position setting P54x/EN AD/J84
 Replacing fixed Trip on Close (TOC) Delay with a setting
 Improvements to slow power swing detection
 Changes to distance count strategy to restore the same operating time when
phase differential protection is enabled
 Changes to Permissive Inter Trip (PIT) logic to enable the user to select either
local or remote current to be used
 Includes local time zone settings for date & time
 Addition of flexible settings for distance quadrilateral top line
 Reduced minimum setting for IN> I2pol Set
 Addition of propagation delay times to Fault Record
 Enhancement to self checking of output relays
 Change tunnelled courier address to follow the 1st Rear Port’s KBUS or CS103
address
S/W S/W
Major Minor
 Phase comparison protection P547 added to range
 Improvements to VTS
 Improvements to slow power swing detection
 Corrected power swing detecting when both distance and current differential P54x/EN M/J74
52 B K 4 Jul 2007 enabled Patch for V2.14 + Addendum
 Corrections to enable/disable of auto-reclose P54x/EN AD/J84
 Resolved a problem relating to CT Ratio’s not being restored when restoring
default settings
 Resolved a problem with the Disturbance Recorder which saturates for high
Release of P543, P544, P545 & P546 with distance protection based on 52B
P54x/EN M/J74
 Tilt angle of ground quadrilateral characteristic corrected
52 C K 31 Jul 2007 Patch for V2.14 + Addendum
 Minor correction to fault record
P54x/EN AD/J84
 Corrections to over voltage stage 2 inhibit
 Fixed a number of 61850/Goose problems
 Fixed a problem in P547 related o the transient starters
P54x/EN M/J74
 Fixed the max prop alarm
52 D K 17 Dec 2007 Patch for V2.14 + Addendum
 Corrected some DDB German text
P54x/EN AD/J84
 Fixed a problem with weak infeed inhibit
 Fixed a SOTF problem when there is a short duration pre-fault
 Fixed a primary scaling issue relating to Zone 5 & 6
 Fixed a number of 61850 problems P54x/EN M/J74
52 E K 14 May 2008  Improved co-processor error reporting Patch for V2.14 + Addendum
 Fix to Blocking scheme P54x/EN AD/J84
Not released to production. Based on 52E
P54x/EN M/J74
52 F K - Patch for V2.14 + Addendum
P54x/EN AD/J84
 Bug fixes
P54x/EN M/J74
Release of P543, P544, P545 & P546 with distance protection based on 52F
52 G K 28 Oct 2008 Patch for V2.14 + Addendum
P54x/EN AD/J84
S/W S/W
Major Minor
Release of P543, P544, P545 & P546 with distance protection based on 52G
Prot Reset"
disabled
 Corrected Thermal State measurement via DNP3.0
P54x/EN M/J74
52 H K 21 Sep 2009 Patch for V2.14 + Addendum
mode P54x/EN AD/J84
 Resolved problem in P543/P545 which prevent correct reporting of fault record
over 61850
 Bug fixes
Release of P543, P544, P545 & P546 with distance protection based on 52H
 Time stamping and status of IEC 61850 data attribute sofPSOF1.ST.general.Op
improved
 Fixed a 61850 issue which blocked clients when one was disconnected P54x/EN M/J74
52 I K 6 Dec 2010  Enhanced the OST feature to make it more stable when currents are low Patch for V2.14 + Addendum
 Improved the distance performance for cross country faults P54x/EN AD/J84
 Rebranded as Alstom. Minor change to software number plus changes to 61850
(New ICD files required)
 Bug fixes
Release of P543 & P545 with distance protection based on 52I
P54x/EN M/J74
 Improved the co-processor SRAM checking
52 J K 19 Dec 2013 Patch for V2.14 + Addendum
P54x/EN AD/J84
 Corrected the OST current sensitivity
 Bug fixes
S/W S/W
Major Minor
Release of P543, P544, P545 & P546 with distance protection based on 52J
navigating the default display.
52 K K 12 Sep 2014  CT Supervision can be operated in P543 52K software.
 CB Fail trip can be operated under faults with DC transient offsets.
 Fix some bugs.
 Positional information added to PSL
 DNP3.0 Over Ethernet protocol added
 Extended I/O – status inputs increased from 24 to 32
 Compensated overvoltage protection added
 IEC-103 Generic Services Measurements added
 Set/Reset Latch Logic Gates added to PSL Patch for V2.14 P54x/EN M/J74
54 A K 18 Mar 2008  Improved Sensitivity Range for DEF First release of + Addendum
 Fault record to include current differential currents recorded at the time of the Studio P54x/EN AD/J94
current differential trip in addition to the existing data from 1 cycle later
 Fault record increased max. number of fault records to 15
 GPS Alarm modifications
 Scheme Delta from P443 included
 DNP3.0 enhancements for SSE
 Bug fixes
 Fix to Blocking scheme
 Fix for DEF reverse operation Patch for V2.14 P54x/EN M/J74
54 B K 25 Jun 2008  Fixed Inhibit CB Fail Protection in P544/6 First release of + Addendum
 Corrected some French and German text Studio P54x/EN AD/J94
 Fixed a problem which prevented extraction of DNP3.0 setting files from DNP3.0
over Ethernet variants
 Bug fixes
Release of P543 & P545 with distance protection based on 54B
54 C K 25 Jun 2008 First release of + Addendum
S/W S/W
Major Minor
disabled
54 D K 20 Jan 2009 First release of + Addendum
 Corrected Thermal State measurement via DNP3.0
Prot Reset"
 Prevents the loss of IEC6 1850 messages and fixed the handling of the ACD flag
54 E K 20 Mar 2009 during GI First release of + Addendum
 Improved the Ethernet card boot code
Release of P543, P544, P545 & P546 with distance protection based on 54E
mode
54 F K 21 Sep 2009 First release of + Addendum
 Resolved problem in P543/P545 which prevent correct reporting of fault record
over 61850
 Bug fixes
Release of P543, P544, P545 & P546 with distance protection based on 54F
 Time stamping and status of IEC 61850 data attribute sofPSOF1.ST.general.Op
improved
 Fixed a 61850 issue which blocked clients when one was disconnected Patch for V2.14 P54x/EN M/J74
54 G K 19 Oct 2010  Enhanced the OST feature to make it more stable when currents are low First release of + Addendum
 Bug fixes
Release of P543, P544, P545 & P546 with distance protection based on 54G Patch for V2.14 P54x/EN M/J74
54 H K 11 Jan 2011  Rebranded as Alstom. Minor change to software number plus changes to 61850 First release of + Addendum
(New ICD files required) Studio P54x/EN AD/J94
S/W S/W
Major Minor
Release of P543, P544, P545 & P546 with distance protection based on 54E Patch for V2.14
55 B K 30 Mar 2009 P54x/EN M/KA4
 Auto-reclose, Check Sync and CB Monitoring added to P544 & P546 Studio FTP server
 Improvements to the Ethernet card start-up and configuration
mode Patch for V2.14
55 C K 15 May 2009 P54x/EN M/KA4
 Correction to the way latched LED/Relays are cleared Studio FTP server
 Bug fixes
 Correction to slow power swing configuration Patch for V2.14
55 D K 28 Oct 2009 P54x/EN M/KA4
 Improvements in the clock recover circuits used by the Differential Comms. Studio FTP server
 Bug fixes
Patch for V2.14
55 E K 11 Jan 2011  Rebranded as Alstom. Minor change to software number plus changes to 61850 P54x/EN M/KA4
Release of P543, P544, P545 & P546 with distance protection based on 55E
 Fixed dnp3 control of CB2
 Time stamping and status of IEC61850 Data attribute sofPSOF1.ST.general.Op
improved
 Improvements to Fault record display over courier and dnp3 Patch for V2.14
55 F K 14 Jun 2012 P54x/EN M/KA4
 Fixes to Autoreclose Studio FTP server
 Improvements to co-processor SRAM checking
 Fixed PIT
 Several fixes to IEC61850 problems
 Added Frequency trips to P445 default PSL
 Fixed an issue where Disturbance recorder could get out of sync
S/W S/W
Major Minor
Release of P545 with distance protection based on 55F
 PX40PL-33 Error code “0x0C160013” issue
 Several fixes to IEC 61850 and IEC-103 problems
 When using a Dual Redundant IEE C37.94 Differential Scheme with N=12, if one Patch for V2.14
55 G K 18 Dec 2014 leg of the communications path is broken the relay can reboot P54x/EN M/KA4
Studio FTP server
 The enabling logic for P445 AutoReclose does not allow for local override by
DDB.
 Bug fixes
Limited Release of P543, P544, P545 & P546 with distance protection based on
55D
 IEC 61850 phase 2 and 2.1 implemented
 Application for Inzone Transformers (2nd and 5th Harmonic Blocking/restraint)
 Differential Highset can be disabled when Inrush protection is enabled P54x/EN M/KA4
Patch for V2.14
57 A K -  Restricted Earth Fault Protection (REF) + Addendum
Studio FTP server
 Modification to Char Mod timer functionality P54x/EN AD/KB4
 Separate measurements for each set of CT’s
 Interrupt Driven InterMiCOM in all models
 Read Only Mode
P54x/EN M/KA4
GPS is enabled and loopback mode selected Patch for V2.14
57 B K 10 Feb 2010 + Addendum
 Fault locator measurements in ohms corrected when 5A CT used or displayed in Studio FTP server
primary P54x/EN AD/KB4
 Frequency measurement in DNP3.0 fault record corrected
Release of P543 61850 with distance protection based on 57B
P54x/EN M/KA4
 Fixes to 61850 Patch for V2.14
57 C K 5 May 2010 + Addendum
 Fixed protection comms. address problem in three ended scheme selected Studio FTP server
P54x/EN AD/KB4
 Fixed DNP3.0 control of CB2
 Fixed a small issue with the detection of slow swings
S/W S/W
Major Minor
 Fixes to 61850
 Fixed protection comms. address problem in three ended scheme selected
 Fixed DNP3.0 control of CB2
P54x/EN M/KA4
 Fixed a small issue with the detection of slow swings Patch for V2.14
57 D K 15 Oct 2010 + Addendum
 Incorrect mapping of XCBR(n).CBOpCap.stVal data attribute corrected Studio FTP server
P54x/EN AD/KB4
 Time stamping and status of IEC 61850 Data attribute sofPSOF1.ST.general.Op
improved
Release of P543, P544, P545 & P546 with distance protection based on 57D P54x/EN M/KA4
Patch for V2.14
57 E K 11 Jan 2011  Rebranded as Alstom. Minor change to software number plus changes to 61850 + Addendum
P54x/EN AD/KB5
Release of P543, P544, P545, P546 & P547 with distance protection based on 57E
P54x/EN AD/Lb4
57 F K 9 Aug 2012 Studio FTP server +
P54x/EN M/La4
 Corrected the OST current sensitivity
 Bug fixes
Release of P547 with distance protection based on 57F
P54x/EN AD/Lb4
 Addition of PSL based phase selection for P547
57 G K 13 Dec 2012 Studio FTP server +
 Fixed an issue where the carrier was not muted when it should have been.
P54x/EN M/La4
 Bug Fixes
Release of P543, P544, P545, P546 & P547 with distance protection based on 57G
 DTS PX40PL-33 Error code “0x0C160013”
 P540D-108 The enabling logic for P445 AutoReclose does not allow for local
P54x/EN AD/Lb4
override by DDB. PQIM : 2014.009 Patch for V2.14
57 H K 5 Aug 2015 +
 P540D-66 CB Fail trip may fail to operate under faults with DC transient offsets. Studio FTP server
P54x/EN M/La4
 P540D-22 When using a Dual Redundant IEE C37.94 Differential Scheme with
N=12, if one leg of the communications path is broken the relay can reboot.
 Bug fixes
S/W S/W
Major Minor
Release of P546 without distance protection based on 57D
 Cyber Security MiCOM S1 studio
v3.3 P54x/EN M/KA4 +
60 A M 1 Feb 2011  Main processor board replaced by ZN0069 001
P54x/EN AD/KB4
 Final Assembly for P546 GN0364 changed to issue F or later
 New sheet 3 & 4 of Final Assembly User Interface GN0341 added
Release of P543, P544, P545 & P546 without distance protection and P841-A based
on SW 47E.
 Cyber security phase 1
 Separate CT ratios for models with 2 sets of CTs
 Option to use 2nd Check Sync VT as a measured VT input for earth fault
protection
 Increase the number of available protection scheme addresses from 20 to 32
 Single End Testing operation
 Stub Bus logic enhancement
 CB Fail improvements MiCOM S1 Agile v1.3 P543&5/EN M/M
61 A M 1 Aug 2011  Common auto-reclose, check sync and CB status for P540D products or later P544&6/EN M/M
 Check sync stage 2 enhancements
 Inhibit SEF feature added
 Enhanced disturbance recorder
 Increase in number of event records
 Increase PSL timers to 32
 User Programmable Curves feature added
 Improvements to GOOSE performance
 IEC 870-5-103 fault location added to ASDU4
 Bug fixes
on SW 61 A.
 Fix to the alternative basic scheme to cover changing faults
 Fixed an issue relating to restoring user curves MiCOM S1 Agile v1.3
61 B M 9 August 2012 P543&5/EN M/M
or later
 Optimized the start-up of 61850 models
 Bug fixes
S/W S/W
Major Minor
Release of P543, P544, P545 & P546 without distance protection and P841-A
based on SW 61 B.
 Fixed several IEC 61850 problems MiCOM S1 Agile v1.3 P543&5/EN M/M
61 C M 12 Sep 2012  Corrected the password required to clear alarms or later P544&6/EN M/M
 Fixed a DR problem
Bug fixes
Release of P543, P544, P545 & P546 with distance protection and P841-A based on
SW 1 B.
 Improved MMI response when events are being generated
 Fixed an evolving fault issue in the Auto-reclose Logic
MiCOM S1 Agile v1.3 P543&5/EN M/M
61 D M 24 Sep 2013  Fixed a number of IEC 61850 issues
or later P544&6/EN M/M
 Fixed a number of DNP3.0 issues
 Resolved a setting change issue which caused the co-processor to reconfigure
un-necessarily
 Bug fixes
Release of P543, P544, P545 & P546 without distance protection and P841-A. This
software is based on 61D software which is the last full release but also
incorporating the P446 71E changes. MiCOM S1 Agile v1.3 P543&5/EN M/M
61 F M 20 Jan 2015
 P540D Goose/Bandwidth Code Optimisation or later P544&6/EN M/M
 Bug fixes
Release P545 without distance protection. This release is mainly to solve a mal
operation of current differential protection when CIT<->NCIT mixed mode scheme.
Is based on SW 71F. MiCOM S1 Agile v1.3 P543&5/EN M/M
61 G M 28 Aug 2015  Fixed several bugs related to IEC 61850 issues or later P544&6/EN M/M
 Fixed a SNTP configuration performance
 Other minor bug fixes
Release of P543, P544, P545 & P546 with distance protection, P547, P443, P446
and P841-B . The main reason for this release is to include the changes that were
made /fixed in version G.
 Code optimisation
 Changes to CB fail function to include External DDB reset inputs MiCOM S1 Agile v1.3 P543&5/EN M/M
61 I M 17 Jan 2017
 Fixed several bugs related to IEC 61850 issues or later P544&6/EN M/M
 Fixed bug related to measurements
 Fixed bug: CS1 and CS2 do not work independently when CB Comp enabled for
CS2
S/W S/W
Major Minor
Release of P543 & P545 High Break versions without distance protection based on
61B or 71B P543&5/EN M/M
MiCOM S1 Agile v1.3
63 A M 4 Sep 2012  Sub Cycle Differential Protection +
or later
 Note: This version is not compatible with any other P540 P543&5/EN RN/A
on SW 61C
 CB Fail enhancements
 2nd Harmonic Blocking Based on SEF Input
 Addition of Polish, Italian and Portuguese languages P543&5/EN M/M
 Addition of Checksync Voltage Diff Measurement P544&6/EN M/M
MiCOM S1 Agile v1.3
65 A M 14 Jan 2013  Improvements to GOOSE +
or later
 Ethernet Failover P540D-RNC1-TM-EN-
001
 SNTP Alarm
 Minimum setting value of CheckSync UV [48 8B] changed to 10V
 Fixed several bugs related to IEC 61850 issues
on SW 65A
 Improved MMI response when events are being generated P543&5/EN M/M
 Fixed reporting of power swing blocking over IEC 61850 P544&6/EN M/M
 Fixed an evolving fault issue in the Auto-reclose Logic MiCOM S1 Agile v1.3
65 B M 21 Mar 2013 +
or later
 Fixed a number of IEC 61850 issues P540D-RNC1-TM-EN-
 Fixed a number of DNP3.0 issues 001
 Fixed an issue with the Delta Direction count state
on SW 65B P543&5/EN M/M
 Resolved a setting change issue which caused the co-processor to reconfigure P544&6/EN M/M
MiCOM S1 Agile v1.3
65 C M 5 Dec 2013 un-necessarily +
or later
 Additional English/Italian/Polish/Portuguese language option (7) P540D-RNC1-TM-EN-
 Other minor bug fixes 001
Release of P546 without distance protection based on SW 65C with only MiCOM S1 Agile v1.3
65 D M 9 Dec 2013 IEC61850 protocol. This version was released only for one customer. or later
S/W S/W
Major Minor
Release of P543, P544, P545 & P546 without distance protection an P841-A, based
on SW 65B including all bug fixes of SW 75C.
 Addition of starters to Current Differential protection P543&5/EN M/M
 Addition of Current Differential Supervision P544&6/EN M/M
MiCOM S1 Agile v1.3
66 A M 5 Dec 2013 +
 Additional English/Italian/Polish/Portuguese language option (7) or later
 Correction of stamping issues involving 61850 P540D-RNC1-TM-EN-
 Fixed the CB open echo feature in POR scheme for 2 CB 001
on SW 66 A
 Code optimisation P543&5/EN M/M
 Improved CB fail algorithm to avoid incorrect operation under faults with DC P544&6/EN M/M
MiCOM S1 Agile v1.3
66 B M 9 May 2014 transient offsets +
or later
 Fixed bug: Frequent changes in data causes IEC 61850 application to stop P540D-RNC1-TM-EN-
 Fixed bug: Vn Measured is not measured following a power cycle of relay 001
on SW 66 B
P543&5/EN M/M
 Goose/Bandwidth Code Optimisation.
P544&6/EN M/M
 Fixed bugs related to IEC61850 and IEC103 protocols MiCOM S1 Agile v1.3
66 C M 22 Jan 2015 +
 Fixed bug that occurs when using a Dual Redundant IEE C37.94 Differential or later
Scheme with N=12 : if one leg of the communications path was broken, the relay P540D-RNC1-TM-EN-
coud reboot 001
P543&5/EN M/M
P544&6/EN M/M
on SW 66 C MiCOM S1 Agile v1.3
66 D M 12 Feb 2015  Fixed an issue with IEC61850 models: Digital Inputs, Virtual Inputs and PSL +
or later
validity could be recognised at a different time P540D-RNC1-TM-EN-
001
P543&5/EN M/M
Release of P546 without distance protection based on 76E P544&6/EN M/M
 Fixed a number of IEC 61850 issues MiCOM S1 Agile v1.3
66 G M 24 Jan 2017 +
 Other minor bug fixes or later
P540D-RNC1-TM-EN-
001
S/W S/W
Major Minor
Release of P546 without distance protection based on 66F P543&5/EN M/M
 Fixed bug: Current of phase A is not the sum of currents in CT1 and CT2 in the P544&6/EN M/M
corresponding phase MiCOM S1 Agile v1.3
66 H M 15 Feb 2017 +
 Fixed bug: CS1 and CS2 do not work independently when CB Comp enabled for or later
CS2 P540D-RNC1-TM-EN-
P543&5/EN M/M
P544&6/EN M/M
Release of P543, P544, P545 & P546 without distance protection and P841-A. This MiCOM S1 Agile v1.3
66 I M 31 Mar 2017 release include all bug fixes of SW 66G and SW 66H. +
or later
P540D-RNC1-TM-EN-
001
on SW 76I . This release is to include 3 new options (R,S,T) in the CORTEC related to
the IRIG B as follows: P543&5/EN M/M
 R - Redundant Ethernet PRP/HSR/RSTP, 2 multi-mode fibre ports + P544&6/EN M/M
Modulated/Un-Modulated IRIG-B MiCOM S1 Agile v1.3
66 J M 12 Jan 2017 +
 S - Redundant Ethernet PRP/HSR/RSTP, 2 coper ports RJ45 + Modulated/Un- or later
Modulated IRIG-B P540D-RNC1-TM-EN-
 T - Single Ethernet, 1 multi-mode fibre ports + Modulated/Un-Modulated IRIG-B 001
This release is not a general release but for particular customers.

P543&5/EN M/M
Release of P546 without distance and for only one model : IEC61850 + 103 based P544&6/EN M/M
on 66J Particular customer. MiCOM S1 Agile v1.3
66 K M 21 Dec 2017 +
or later
 Fixed bug: Reboot of IEDs after Maintenance Records P540D-RNC1-TM-EN-
001
P543&5/EN M/M
Release of P546 without distance protection based on 66K P544&6/EN M/M
MiCOM S1 Agile v1.3
66 L M 29 Mar 2018  Threshold for the undercurrent of pole dead as fix threshold of 5%In +
or later
 Minor bug fixes P540D-RNC1-TM-EN-
001
and P841-B based on 66I
 Additional Comms mode added to allow 128 kBPS comms P543&51Z-EN-TM-N
 In models with current differential, additional IM64 option can be selected
between 8 or 32 ‘IM64’ bits per channel MiCOM S1 Agile v1.3 P543&51NZ-EN-TM-N
69 A M 25 May 2018
or later
 In models with distance , additional IM64 option can be selected between 8 or 24 P544&61Z-EN-TM-N
‘IM64’ bits per channel P544&61NZ-EN-TM-N
 Settable hysteresis for overvoltage
S/W S/W
Major Minor
Release of P543, P544, P545, P546 without distance protection, and P841-A based P543&51NZ-EN-TM-N
69 C M 27 September 2018 on 69B (Interim SW not released to production). P544&61NZ-EN-TM-N
 Fixed bugs related to IEC61850 P841A-EN-TM-N
Release of P543, P544, P545 & P546 without distance protection and P841-A based P543&51NZ-EN-TM-N
8 January 2019 on SW 79C MiCOM S1 Agile v1.3
69 D M  Threshold for undercurrent of pole dead changed has been fixed to 5% or later
P544&61NZ-EN-TM-N
Fixed bugs related to IEC61850 P841A-EN-TM-N
Release of P543, P544, P545 & P546 with distance protection and P841-B, based
on SW 57E.
 Cyber security phase 1
 Separate CT ratios for models with 2 sets of CTs
 Option to use 2nd Check Sync VT as a measured VT input for earth fault
protection
 Neutral Differential Protection Element
 Phase Differential Transient Bias
 Increase the number of available protection scheme addresses from 20 to 32
 Single End Testing operation
 Improvements to distance protection
 DEF Virtual Current Polarizing option
 OST/PSB improvements MiCOM S1 Agile v1.3 P543&5/EN M/M
71 A M 1 Aug 2011
 Stub Bus logic enhancement or later P544&6/EN M/M
 CB Fail improvements
 Common auto-reclose, check sync and CB status for P540D Products
 Check sync stage 2 enhancements
 Inhibit SEF feature added
 Enhanced disturbance recorder
 Increase in number of event records
 Increase PSL timers to 32
 User Programmable Curves feature added
 Improvements to GOOSE performance
 IEC 870-5-103 fault location added to ASDU4
 Bug fixes
S/W S/W
Major Minor
and P841-B based on SW 71 A
 Fix to the alternative basic scheme to cover changing faults
 Fixed an issue relating to restoring user curves MiCOM S1 Agile v1.3 P543&5/EN M/M
71 B M 9 August 2012
 Optimized the start-up of 61850 models
 Bug fixes
and P841-B based on SW 71 B
 Corrected language translations for some distance settings
 Fixed several IEC 61850 problems MiCOM S1 Agile v1.3 P543&5/EN M/M
71 C M 12 Sep 2012
 Corrected the password required to clear alarms
 Fixed a DR problem
 Bug fixes
and P841-B based on SW 71 C
 Improved MMI response when events are being generated
 Fixed reporting of power swing blocking over IEC 61850
 Fixed an evolving fault issue in the Auto-reclose Logic
 Fixed a number of IEC 61850 issues MiCOM S1 Agile v1.3 P543&5/EN M/M
71 D M 24 Sep 2013
 Fixed a number of DNP3.0 issues or later P544&6/EN M/M
 Fixed an issue with the Delta Direction count strategy
 Resolved a setting change issue which caused the co-processor to reconfigure
un-necessarily
 Fixed the CB open echo feature in POR scheme for 2 CB
 Bug fixes
Release of P446 based on SW 71 D
 Fixed bug related to the Vn measurement MiCOM S1 Agile v1.3
71 E M 9 Dec 2013
or later
 Fixed other minor bug related to df/dt function
S/W S/W
Major Minor
and P841-B. This software is based on 71D and 61D software which is the last full
release but also incorporating the P446 71E changes.
 Goose/Bandwidth Code Optimisation
 Bug fixes related to IEC61850 MiCOM S1 Agile v1.3 P543&5/EN M/M
71 F M 20 Jan 2015
 Fix bug: CB Control Interlocking Fail
 Fixed bug: When using a Dual Redundant IEE C37.94 Differential Scheme with
N=12, if one leg of the communications path is broken the relay can reboot
 Fix other minor bugs
Release P545 with distance protection. This release is mainly to solve the mal
operation of current differential protection when CIT<->NCIT mixed mode scheme.
Is based on SW 71F.
 P540 NCIT and CIT combination trips for some external fault. MiCOM S1 Agile v1.3 P543&5/EN M/M
71 G M 28 Aug 2015
 Fixed an issue with IEC61850 models: Digital Inputs, Virtual Inputs and PSL
validity could be recognised at a different time
Release of P545 with distance protection and P443 based on 71G. P543&5/EN M/M
MiCOM S1 Agile v1.3
71 H M 14 Oct 2015  Fix bug when reporting of complex data points (ACD/ACT) on IEC 61850 or later P544&6/EN M/M
 Fix other minor issues related to IEC61850 and 103 protocols
MiCOM S1 Agile v1.3 P543&5/EN M/M
71 I M 17 Jan 2017 and P841-B . The main reason for this release is to include the changes that were
made /fixed in versions G and H or later P544&6/EN M/M
Release of P546 with distance protection, P446 and P841-B based on SW 70A.
 Support of 9-2 LE P54x/EN AD/Lb4
 GOOSE performance improvement MiCOM S1 Agile v1.3 +
72 A M 29 Jun 2012
 Replace of analogue CT/VT board with 9-2LE board or later P54x/EN M/La4
 Update the 80TE case for 9-2 relay Px4x_92LE-TM-EN-002
 Bug fixes
Release of P546 with distance protection, P446 and P841-B based on SW 72A
 NCIT version of P546 sometimes reboots with error code 0xE0050004 following a - P54x/EN AD/Lb4
setting change MiCOM S1 Agile v1.3 +
72 B M 13 Jul 2012
 Use ASE2000 send 'Device Attribute' command to P546 DNP3 builds, relay or later P54x/EN M/La4
reboot. Px4x_92LE-TM-EN-002
 Bug fixes
S/W S/W
Major Minor
Release of P546 with distance protection, P446 and P841-B based on 72B
 VT selection
P54x/EN AD/Lb4
 Addition of Checksync Voltage Diff Measurement
MiCOM S1 Agile v1.3 +
74 B M 24 Jan 2013  Improvements to GOOSE
or later P54x/EN M/La4
 Ethernet Failover
Px4x_92LE-TM-EN-002
 SNTP Alarm
 Bug fixes
Release of P546 with distance protection, P446 and P841-B based on 74B
 All protection functions are not blocked for IEC 61850-9.2LE IEDs if the secondary
current exceeds 64A.
P54x/EN AD/Lb4
navigating the default display. MiCOM S1 Agile v1.3 +
74 C M 24 Jun 2014
 Goose/Bandwidth Code Optimisation. or later P54x/EN M/La4
 CB Fail trip can be operated under faults with DC transient offsets. Px4x_92LE-TM-EN-002
 IEC61850 Application is not stopped when frequent changes in data are caused.
 Fix some bugs.
P54x/EN AD/Lb4
Release of P546 with distance protection based on 74C
MiCOM S1 Agile v1.3 +
74 D M 29 Sep 2016  Fixed a number of IEC 61850 issues
or later P54x/EN M/La4
 Bug fix
Px4x_92LE-TM-EN-002
Release of P543, P544, P545 & P546 with distance protection, P443, P446 and
P841-B based on SW 71C
MiCOM S1 Agile v1.3
75 A M 14 Jan 2013 +
 Additional English/Italian/Polish/Portuguese language option (7) or later
 Correction of two time stamping issues involving 61850 P540D-RNC1-TM-EN-
and P841-B based on SW 75A
 Improved MMI response when events are being generated P543&5/EN M/M
 Fixed reporting of power swing blocking over IEC 61850 P544&6/EN M/M
 Fixed an evolving fault issue in the Auto-reclose Logic MiCOM S1 Agile v1.3
75 B M 21 Mar 2013 +
or later
 Fixed a number of IEC 61850 issues P540D-RNC1-TM-EN-
 Fixed a number of DNP3.0 issues 001
 Fixed an issue with the Delta Direction count state
S/W S/W
Major Minor
P543&5/EN M/M
and P841-B based on SW 75B
P544&6/EN M/M
 Resolved a setting change issue which caused the co-processor to reconfigure MiCOM S1 Agile v1.3
75 C M 5 Dec 2013 un-necessarily +
or later
 Additional English/Italian/Polish/Portuguese language option (7) P540D-RNC1-TM-EN-
001
Release of P546 with distance protection based on SW 65C with only IEC61850 MiCOM S1 Agile v1.3
75 D M 9 Dec 2013 protocol. This version was released only for one customer or later
MiCOM S1 Agile v1.3
76 A M 5 Dec 2013  Additional English/Italian/Polish/Portuguese language option (7) +
or later
 Correction of stamping issues involving 61850 P540D-RNC1-TM-EN-
and P841-B based on SW 76 A
 Code optimisation P543&5/EN M/M
 Improved CB fail algorithm to avoid incorrect operation under faults with DC P544&6/EN M/M
MiCOM S1 Agile v1.3
76 B M 9 May 2014 transient offsets +
or later
 Fixed bug: Frequent changes in data causes IEC 61850 application to stop P540D-RNC1-TM-EN-
 Fixed bug: Vn Measured is not measured following a power cycle of relay 001
and P841-B based on SW 76 B
P543&5/EN M/M
 Goose/Bandwidth Code Optimisation.
P544&6/EN M/M
 Fixed bugs related to IEC61850 and IEC103 protocols MiCOM S1 Agile v1.3
76 C M 22 Jan 2015 +
 Fixed bug that occurs when using a Dual Redundant IEE C37.94 Differential or later
Scheme with N=12 : if one leg of the communications path was broken, the relay P540D-RNC1-TM-EN-
coud reboot 001
P543&5/EN M/M
P544&6/EN M/M
and P841-B based on SW 76 B MiCOM S1 Agile v1.3
76 D M 12 Feb 2015 +
 Fixed an issue with IEC61850 models: Digital Inputs, Virtual Inputs and PSL or later
validity could be recognised at a different time P540D-RNC1-TM-EN-
001
Release of P443 based on SW 76 D MiCOM S1 Agile v1.3
76 E M 12 Oct 2015  Fixed an issue related to P443 InterMiCOM or later
S/W S/W
Major Minor
P543&5/EN M/M
Release of P546 only for model P54681KA6N0760M based on SW 76 D P544&6/EN M/M
MiCOM S1 Agile v1.3
76 F M 24 Aug 2016  Fixed bug: Periodic loss of GOOSE subscription +
or later
P540D-RNC1-TM-EN-
001
Release of P546 with distance protection based on 76E P543&5/EN M/M
 Fixed a number of IEC 61850 issues P544&6/EN M/M
 Fixed bug: For Power swing, the relay is not using angle " Alpha cell 3D.49 " of MiCOM S1 Agile v1.3
76 G M 24 Jan 2017 +
Power Swing settings but angle " Blinder angle cell 3D.2C " of Out of Step setting or later
P540D-RNC1-TM-EN-
Release of P546 with distance protection based on 76F P543&5/EN M/M
 Fixed bug: Current of phase A is not the sum of currents in CT1 and CT2 in the P544&6/EN M/M
corresponding phase MiCOM S1 Agile v1.3
76 H M 15 Feb 2017 +
 Fixed bug: CS1 and CS2 do not work independently when CB Comp enabled for or later
CS2 P540D-RNC1-TM-EN-
P543&5/EN M/M
P544&6/EN M/M
Release of P543, P544, P545 & P546 with distance protection, P547, P443, P446 MiCOM S1 Agile v1.3
76 I M 31 Mar 2017 and P841-B. This release includes all bug fixes of SW 76G and SW 76H. +
or later
P540D-RNC1-TM-EN-
001
and P841-B based on SW 76 I. This release is to include 3 new options (R,S,T) in the
CORTEC related to the IRIG B as follows:
P543&5/EN M/M
 R - Redundant Ethernet PRP/HSR/RSTP, 2 multi-mode fibre ports + Modulated/Un-
P544&6/EN M/M
Modulated IRIG-B MiCOM S1 Agile v1.3
76 J M 12 Jan 2017  S - Redundant Ethernet PRP/HSR/RSTP, 2 coper ports RJ45 + Modulated/Un- +
or later
Modulated IRIG-B P540D-RNC1-TM-EN-
 T - Single Ethernet, 1 multi-mode fibre ports + Modulated/Un-Modulated IRIG-B 001
This release is a restricted release for particular customers.
P543&5/EN M/M
Release of P546 with distance and for only one model : IEC61850 + 103 based on P544&6/EN M/M
76J for Particular customer. MiCOM S1 Agile v1.3
76 K M 21 Dec 2017 +
or later
 Fixed bug: Reboot of IEDs after Maintenance Records P540D-RNC1-TM-EN-
001
S/W S/W
Major Minor
P543&5/EN M/M
Release of P546 with distance protection based on 76K P544&6/EN M/M
MiCOM S1 Agile v1.3
76 L M 29 Mar 2018  Threshold for the undercurrent of pole dead as fix threshold of 5%In +
or later
 Minor bug fixes P540D-RNC1-TM-EN-
001
P543&5/EN M/M
S Release of P544 with distance protection for all models and P546 IEC61850 P544&6/EN M/M
MiCOM S1 Agile v1.3
76 M M 10 Aug 2018 models. SW based on 76L +
or later
 Some bug fixes related to IEC61850 and DNP P540D-RNC1-TM-EN-
001
Release of P546 with distance protection and P446 based on 76E
 Add new function for IRIG-B local time
 The IM input CT can be used as IN measured for earth fault function (residual MiCOM S1 Agile v1.3
77 A M 2 Dec 2015 E/F) or later
P54x2-TM-EN-1
 The IM input CT can be used as IN measured for Aided DEF function.
 Updated set range of stage2 of earth fault in case of DT.
 Measured IN always include the IEC61850, CS103 and DNP protocols.
Release of P443 based on 77A
 Added a new distance zone Q
 Delink of power swing and DeltaZ
 Modify RAW comparator for the isolated or compensated earthing system
78 A M 16 April 2015
 Added option of Measure the residual voltage through the check sync input
channel
 Added new indication for all elapsed timers of distance zones
 Minor bug fixes
Release of P443 based on 78A
78 B M 22 May 2015  Minor bug fixes
and P841-B based on 76I
 Additional Comms mode added to allow 128 kBPS comms P543&51Z-EN-TM-N
 In models with current differential, additional IM64 option can be selected MiCOM S1 Agile v1.3 P543&51NZ-EN-TM-N
79 A M 25 May 2018 between 8 or 32 ‘IM64’ bits per channel or later P544&61Z-EN-TM-N
 In models with distance , additional IM64 option can be selected between 8 or 24
‘IM64’ bits per channel P544&61NZ-EN-TM-N
 Settable hysteresis for overvoltage
Release of P543, P544, P545 & P546 with distance protection, P547, P443, P446 P543&51Z-EN-TM-N
and P841-B based on 79B (SW 79B was an Interim SW which was not released to MiCOM S1 Agile v1.3
79 C M 27 September 2018
production). or later
P544&61Z-EN-TM-N
 Fixed bugs related to IEC61850 P841B-EN-TM-N
S/W S/W
Major Minor
6 December 2018 for
P543 and P545 P443-EN-TM-N
Release of P543, P544, P545 & P546 with distance protection, P547, P443, P446 P446-EN-TM-N
8 January 2019 for
and P841-B based on SW 79C MiCOM S1 Agile v1.3
79 D M P544,P546,P547,
 Threshold for undercurrent of pole dead changed has been fixed to 5% or later
P543&51Z-EN-TM-N
P443,P446 and P544&61Z-EN-TM-N
P841-B
 Bug fixes
P841B-EN-TM-N
Release of P546 with distance protection, P446 and P841B sample values relays
based on 74B
 IEC 61850 Ed.2 platform integration MiCOM S1 Agile v1.3
80 A M 9 Oct 2014  Logical nodes extensions or later
P40L-AD-ED2-EN
 Minimum I/O boards with 40TE front panel for P540D post intelligent relay
 Bug fixes
based on 80A
 IEC 61850 Ed.2 platform integration
 Logical nodes extensions, Editable Logic Nodes MiCOM S1 Agile v1.3
80 B M 19 Dec 2014
or later
P40L-AD-ED2-EN
 Minimum I/O boards with 40TE front panel for P540D post intelligent relay
 FAST GOOSE Solution
 Bug fix
based on 80B
 Fix bug : NCIT and CIT combination trips for external fault. MiCOM S1 Agile v1.3
80 C M 28 Aug 2015 P40L-AD-ED2-EN
 Fix bugs when using IEC61850 models, Digital Inputs, Virtual Inputs and PSL or later
validity are recognised at a different times
 Some other bugs related to IEC61850
Release of P543, P544, P545 & P546 with distance protection P443, P446 and
P841-B based on SW 76B
 IEC 61850 Ed.2 platform integration MiCOM S1 Agile v1.3
82 A M 24 Sep 2015  Logical nodes extensions P54x1Z TM EN
or later
 Other bug fix
Release of P543 & P545 without distance protection based on 63A . This is the
relay with Sub Cycle Differential Protection
 IEC 61850 Ed.2 platform integration
 Logical nodes extensions, Editable Logic Nodes MiCOM S1 Agile v1.3 P543&5/EN M/M
83 A M 13 Mar 2015
or later P543&5/EN RN/A
 GOOSE Bandwidth Optimisation
 Other Bug fix
S/W S/W
Major Minor
Release of P546 with distance protection and only IEC61850 plus 103 protocol
based on 82A
 Allow control inputs to be set as enabled/disabled in the setting file MiCOM S1 Agile v1.3
84 A M 28 Jun 2016
or later
P544&6/EN M
 New DDB’s inputs to be able to reset CB failure externally
 Other bug fix
 Release of P546 with distance protection and only IEC61850 plus103 protocol
based on 84A MiCOM S1 Agile v1.3
84 B M 31 Aug 2016  Check sync options improvement allowing possible check sync between busbars or later
P544&6/EN M
 Scheme Logic Column visible in setting file when Distance & DEF disabled.
Release of P543 & P545 with distance protection and P443, based on SW 82 A
 Add a new distance zone Q
 Delink Delta I power swing and slow power swing
 Include option to use distance relays with phase preference logic for isolated
compensated system MiCOM S1 Agile v1.3 P443i-TM-EN-1
85 A M 19 Jan 2017  Measure the residual voltage through the check sync input channel or later P54x1i-TM-EN-1
 Add new indication for all elapsed timers of distance zones
 Add Transient Ground Fault (TGFD)
 Rebranded to GE
 Other bug fix
Release of sample values relays P5469CNA6R0860P and P8419CNC6R0860P only
based on SW 80C
 Auto reclose reclaim time extended logic
 Auto reclose new DDB’s signals for dead time is complete & enable and CB in
service
 New system split function MiCOM S1 Agile v1.3 P546SV-TM-EN-1
86 A M 12 Jan 2018
or later P841SV-TM-EN-1
 Addition of differential starters and differential supervision
 Self-reset alarms have been increased from 4 to 8 and manual reset alarms
have been increased from 4 to 20
 Main VT location control for use with check synchronism and auto recloser
 Other bug fix
Release of sample values relays P5469CNA6R0860P and P8419CNC6R0860P only
based on SW 86A MiCOM S1 Agile v1.3 P546SV-TM-EN-1
86 B M 27 Feb 2018
 System split function new DDB’s for CB1 & CB2 SS to enable SS from PSL besides or later P841SV-TM-EN-1
setting.
S/W S/W
Major Minor
based on 86B
 Support for new Ethernet board (ZN0087) P446SV-TM-EN-2
 Inclusion of Duplicate GOOSE feature MiCOM S1 Agile v1.4
86 E M 5 Jul 2018 P546SV-TM-EN-1
or later
 IRIG-B Type setting P841SV-TM-EN-1
 Rebranded SW to GE
 Other bug fix
Release of P543 & P545 with distance protection and P443 based on SW 85A
 6 Fully Directional Distance Zone (all zones 100% reverse reach).
 Distance Protection “Force No Memory” option via DDB.
 4 stages of Directional Power Protection (each stage configurable as under/over
Power). MiCOM S1 Agile v1.4 P443i-TM-EN-2
87 A M 7 September 2018
or later P54x1i-TM-EN-2
 Separate UnderCurrent setting for Pole Dead and CBFail.
 Inclusion of Duplicate GOOSE feature.
 IEC61850 Modelling of Sensitive Earth fault.
 Other bug fix
2 SOFTWARE VERSION COMPATIBILITY
IED S/W
Setting File Version Menu Text File Version*8 PSL File Version
Version
01 01 01 01
02 02 02 02
03 03, 04*1 03 03
04 04, 05*2, 07*2 04 04
05 05, 07 05, 07 05, 07*1
07 05, 07 05, 07 07
11 11, 12, 13*2, 14*2, 20*2 11 11, 12, 13, 20*1, 30*1
12 11, 12, 13*2, 14*2, 20*2 12 12, 13, 20*1, 30*1
13 11, 12, 13, 14*2, 20*2 13 13, 20*1, 30*1
14 14 14 14
15 15 15 15
20 20, 30*3 20 20*1, 30*1
30 30 30 30
40 40, 50*4 40 40, 50*2
41 41, 51*4 41 41, 51*2
50 40*5, 50 50 50
51 41*5, 51 51 51
52 52, 54*3 52 52
54 54 54 54
55 55 55 55
57 57 57 57
61 61, 65*1 61 61, 65*3
65 65, 66*1 65 65, 66*3
66 66 66 66
71 71, 75*1 71 71, 75*3
75 75, 76*1 75 75, 76*3
76 76 76 76
77 77 77 77
79 79 79 79
IED S/W
Setting File Version Menu Text File Version*8 PSL File Version
Version
80 80 80 80
82 82 82 82
83 83 83 83
84 84 84 84
85 85 85 85
86 86 86 86
Notes:
*1: Compatible except for Disturbance recorder digital channel selection
*2: Additional functionality added such that setting files from earlier software versions will need additional settings to be made
*3: Compatible except for Disturbance recorder digital channel selection & settings for additional functionality will be missing
*4: Compatible except for the Disturbance recorder digital channel selection and the distance settings
*5: Compatible except for Disturbance recorder digital channel selection & the setting file contains a large number of Distance setting which will each produce an error on
download
*6: Additional DDBs were added such that PSL files from earlier software versions will not be able to access them
*7: Additional DDB for the Distance protection will not be included
*8: Menu text remains compatible within each software version but is NOT compatible across different versions
Imagination at work
Grid Solutions
St Leonards Building
Redhill Business Park
Stafford, ST16 1WT, UK
+44 (0) 1785 250 070
© 2019 General Electric. All rights reserved. Information contained in this document is indicative only. No representation or warranty is given or
should be relied on that it is complete or correct or will apply to any particular project. This will depend on the technical and commercial
circumstances. It is provided without liability and is subject to change without notice. Reproduction, use or disclosure to third parties, without
express written authority, is strictly prohibited.
P841B-TM-EN-1.1

Micom P40 Agile: Ge Grid Solutions

Uploaded by

Micom P40 Agile: Ge Grid Solutions

Uploaded by

GE

MiCOM P40 Agile

Chapter 2 Safety Information 15

Chapter 3 Hardware Design 29

4.1.4 Front Parallel Port (SK2) 37

Chapter 4 Software Design 59

3.2 Getting Started 76

5.4.1 Autoreclose Enable Logic Diagram 136

5.24.1 Three-phase Autoreclose Leader Check Logic Diagram 180

Chapter 7 CB Fail Protection 189

Chapter 8 Current Protection Functions 201

5.4.1 Insulated Systems 217

Chapter 9 Voltage Protection Functions 229

Chapter 10 Frequency Protection Functions 243

Chapter 11 Current Transformer Requirements 251

1 Chapter Overview 253

Chapter 12 Monitoring and Control 259

9.1.1 VT Connections 288

Chapter 13 Supervision 297

Chapter 14 Digital I/O and PSL Configuration 311

Chapter 15 Electrical Teleprotection 325

3 Teleprotection Scheme Principles 329

Chapter 16 Communications 337

5.10.1 Installation 364

7.4.10 IEC 61850 Configuration 397

Chapter 17 Cyber-Security 403

Chapter 18 Installation 421

4 Cables and Connectors 428

Chapter 19 Commissioning Instructions 435

5.2.3 Date and Time 448

Chapter 20 Maintenance and Troubleshooting 465

2.7 Changing the battery 474

Chapter 21 Technical Specifications 483

4 Monitoring, Control and Supervision 494

12.1 EMC Compliance: 2004/108/EC 508

Appendix A Ordering Options 509

Appendix B Settings and Signals 511

Appendix C Wiring Diagrams 513

Figure 39: Autoreclose System Map - part 2 108

Figure 118: Residual Overvoltage logic 240

Figure 158: RS485 biasing circuit 342

2.1 TARGET AUDIENCE

2.2 TYPOGRAPHICAL CONVENTIONS

Feature Model C Model D Model E

3.1 PRODUCT VERSIONS

 Current Differential  IEC 61850 Edition 2

Figure 1: P40L family - version evolution

3.2 ORDERING OPTIONS

4 FEATURES AND FUNCTIONS

4.1 PROTECTION FUNCTIONS

Feature IEC 61850 ANSI

4.2 CONTROL FUNCTIONS

Feature IEC 61850 ANSI

Feature IEC 61850 ANSI

4.3 MEASUREMENT FUNCTIONS

Measurement Function IEC 61850 ANSI

4.4 COMMUNICATION FUNCTIONS

Internal Signal OR gate 1

DDB Signal XOR gate XOR

Internal function NOT gate

Setting cell Logic 0 0

Setting value Timer

HMI key Latched on positive edge

Connection / Node Inverted logic input

Comparator for detecting

Figure 2: Key to logic diagrams

2 nd Remote Remote Loca l

49 50/51 50 N/ 50BF-2 67 67N 67N 67 / 25 -2 79 -2 46BC CTS

conve ntiona l IEC GOOSE prote ction

Figure 3: Functional Overview

2 HEALTH AND SAFETY

Protective conductor (earth) terminal

Instructions on disposal requirements

4 INSTALLATION, COMMISSIONING AND SERVICING

4.1 LIFTING HAZARDS

4.2 ELECTRICAL HAZARDS