Pad Ring and Floor Planning

Pad
Ring

Core
Block 1

Block 4
Block 2

Block 6
Block 3

Block 5

• The core of the chip (made up of one or more top level blocks) is surrounded
by a ring of pads.
• The design of the blocks and the arrangement of blocks and pads can signifi-
cantly affect the overall chip area (and hence the cost/yield).

5001
Pad Ring

Pad
Ring
Pad
Ring
Core

Core

Pad Limited: small core and/or many pads

minimum pad to pad distance – gaps around core
Core Limited: large core and/or few pads
gaps between pads1
1
these gaps will be filled with special filler cells

5002
Floor Planning

• Re-arrange and re-orient blocks to:

– create a minimum number of major routing channels2
– reduce block to block and block to pad routing
At top of the hierarchy, chips should be near square, other constraints exist at
lower levels.

2
for multi layer metal processes (≈ 5 metal layers or more) it should be possible to route over
the blocks allowing closer placement

5003
Block Design for easy Floor Planning

• Block shape

Where blocks share a common width, efficient placement is much easier.

• Block ports
If possible arrange the ports on a block for ease of routing to pads and other
blocks.

5004
Floor Planning for Standard Cell Layout

Automatic layout:
• Flatten hierarchy.
• Placement is controlled by algorithms designed to minmize routing.
• Aspect ratio easy to control, also control number of columns and rows.

Manual layout:
• Placement based on layout hierarchy (essential for managing complexity).
• Aspect ratio and port position must be considered early as there is seldom time
for iteration.

5005
Global Routing

Route critical signals first.

• Buffer global and time critical signals.
• Clock distribution should be arranged to avoid skew across the chip3.

4
2 4

4
2 4

4
2 4

3
buffering may actually increase delays while reducing skew

5006
VLSI – Pad Ring and Floor Planning
• Pad ring pre-defineda
Operand1 Operand1 0V create pad ring
Operand2 [6] Operand2 [7] 3.3V pads Req
[6] [7] pads Done SDO

-multiplier
<xsize> <ysize>
Operand1[5] Result[7]

Operand2[5] Result[6]
• Two blocks in core
Operand1[4] Control Result[5]

Operand2[4] Result[4] – Bitslice Datapath

1.8Vcore 0V core
– Synthesized Control
Operand1[3] Datapath Result[3]

Operand2[3] Result[2] • Pad limited

Operand1[2] Result[1]

Operand2[2] Result[0]
• Clock distribution built in to
cell library
Operand2 Operand2 SDI Clock a
Operand1
[1]
Operand1
[0]
3.3V Test Reset
design blocks to reduce routing
pads
[1] [0] [0]
since pads can’t be moved

Datapath will be designed and placed to permit easy wiring of Operand and Result buses
to left and right hand pads. Control will be designed and placed to permit easy wiring of
control signals to the datapath.
5007
VLSI – AMS 0.35µm CMOS Pads

Core Power Supply Pads Input pad

GND3IP VDD3IP ICP
Bi−directional pad
0V 3.3V PAD
A A Y
BBC8P
EN

PAD
Pad Ring Power Supply Pads Output pad A

GND3ALLP VDD3ALLP
BU8P Y

0V 3.3V PAD
A

• Large buffers on output pads allow for drive of very large external loads.
• Separate ”dirty power” supply pads are provided for the main pad drive tran-
sistors to reduce switching noise in the core.
• Bi-directional pads require three connections to the core.

5008
Input / Output

• I/O Pads

IN
PAD ENB

OUT
PAD
IN
OUT
PAD

– A brief look at a selection of simple digital CMOS I/O pads

5009
Output Pads

• Output pad driver

OUT
PAD

– ratioed inverters are used to provide appropriate drive capability

– final drive transistors are carefully designed to avoid latch-up
– pad rings are frequently powered separately (dirty power) to confine switch-
ing noise

5010
Input Pads

• Input protection

PAD

– must protect floating transistor gates from permanent damage via electro-
static discharge

5011
Bidirectional Pads

• Simple bidirectional pad

ENB OUT

OUT
PAD
ENB PAD IN
IN

– bidirectional pad is a tristate inverter output driver combined with an input

pad4
– even when IN and OUT are connected internally, we need buffering and an
enable control signal
4
note input protection is not shown here

5012
Bidirectional Pads

• Bidirectional pad with increased drive capability

OUT
ENB

OUT
PAD
PAD IN
IN

ENB

– redesign to avoid series output transistors

5013
Bidirectional Pads

• Advanced bidirectional pad design

OUT EN

PAD
EN

IN
OUT OUT
EN
EN
ENB EN

OUT EN

– logic gates are merged

– output transistors act as diodes when not enabled
– low value diffusion resistor completes input protection circuit

5014