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Memory Map, Dma

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8 views10 pages

Memory Map, Dma

Uploaded by

Mahu D
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© © All Rights Reserved
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ASY1

P18EST1002

DESIGN OF EMBEDDED SYSTEMS

UNIT 1 - Direct Memory Access

Dr.B.KARUNAMOORTHY , ASP
Department of Electrical and Electronics Engineering
Overview of this Lecturer

➢ Direct MemoryAccess
➢ Interfacing Processor
➢ Memories and Input Output Devices
The Memory Maps

Princeton Memory Organizations


Harvard Memory Organizations
The Memory Maps
 Memory areas needed in the case of Princeton
and Harvard architecture are different and as
shown
◦ Vectors and pointers, variables, program segments and
memory blocks for data and stacks have different
addresses in the program – PRINCETON memory
architecture.
◦ Program segments and memory blocks for data and
stacks have separate sets of addresses in Harvard
architecture. Control signals and read-write
instructions are also separate.
 Designer must remember that if main memory is
of Harvard architecture, program memory map
will be separate.
The Memory Maps
 Map to show the program and data allocation of the addresses to ROM,RAM, EEPROM or Flash
in the system.

Fig:Memory map for an


exemplary embedded system,
smart card needing 2 kB
memory
Direct Memory Access
 A DMA is required when a multi-byte data set or a burst of data or
a block of data is to be transferred between the external device and
system or two systems.
 A device facilitates DMA transfer with a processing element (single
purpose processor) and that device is called DMAC (DMA
Controller).
 Three modes of DMA operations:
◦ Single transfer at a time and then release of the hold on the system bus.
◦ Burst transfer at a time and then release of the hold on
the system bus.A burst may be of a few kB.
◦ Bulk transfer and then release of the hold on the system bus after the
transfer is completed.
DMAC - DMA Controller
 Data transfer occurs efficiently between I/O
devices and system memory with the least
processor intervention using DMAC.
 DMAC provide memory access to Multiple
channels
◦ Separate set of registers for programming each
channel.
◦ Separate interrupt signals in the case of a multi-
channel DMAC
 Provides DMA action from system memories and
two (or more IO) devices.
DMA Controller with the buses &
control signals in between processor

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