NET3001 Intro

● Instructor
– Graham Eatherley
– graham@[Link]
● Web page
[Link]

● The key to passing this course:

– don't skip the lectures
– don't skip the labs
– don't skip the assignments
– don't skip the midterm
– don't skip the exam
– and stay awake
  Real Time Programming
● deals with computers controlling physical
devices
– car engine, vending machine, autopilot, etc, etc
● deals with operations that take place in
milliseconds, or microseconds
● deals with appearing to do more than one
thing at a time and synchronous activity
  Course Content
● typical computer programming
select operating
system
programmer target
C/C++
assembler
compiler

text binary
● we are going to start by learning how to code
in assembly language

programmer target

assembler
  Course Content
● then we will switch to C coding

programmer target
C/C++
assembler
compiler

● finally, we will write our own O/S

mini operating
system
programmer target
C/C++
assembler
compiler
  A Word on Patterns
● data is stored in computers by using patterns
of bits
● what the bits mean and how they are realized
are two different things
  What Patterns Mean
● if you have an 8 bit pattern of 0100.0001,
what does that mean?
● the answer depends entirely on the type of
the information
● Type may be
– number
● signed or unsigned
– character
– or may other things
 How are Patterns Represented
● computers use bundles of wires and put
different voltages on each wire (3V or 0V)
● flash devices store electrons in a grid of
areas of the chip (109 electrons, or 0
electrons)
● ethernet transmission sends 2V or 0V in
10ns pulses
● I just used the numbers 1 & 0 to represent
the pattern
● in each case, the pattern 0100.0001 can be
represented
  Patterns
● in this course, we will constantly be switching
back and forth between physical
mechanisms for holding patterns
– as we move the pattern from one part of the chip
to another
● but the information that the pattern holds will
be the same
● we will be using hexadecimal notation for this
course
– 0100.0001 is written as 0x41
  Computers
speed program variables storage in use cost

Desktop disk $30-

Laptop GHz ram(GB) ram (GB) (100GB) ~1B $300 flexible

Micro- flash dedicated

computer GHz flash(MB) ram (MB) (MB/GB) ~10B $3-$50 function

Micro- dedicated
controller MHz flash (KB) ram (KB) flash (KB) ~30B $.2-$5 function
● Desktops (microprocessor)
– entertainment, personal information processing
● Microcomputers
– MP3 player, cell phone, iPhone, Android, router
● Microcontrollers
– also known as “embedded”
– machine control, tools, peripherals, remote controls, greeting
cards, etc
 Computers
● Desktop CPUs (microprocessor)
– Pentium
● subflavours: Athlon, Sempron, Opteron, Celeron,
CoreDuo, Atom, Via
– PowerPC
● most cost $30 to $300
● Microcomputer
– ARM, MIPS
● most cost $5-$15
● Microcontroller
– ARM-Cortex
– MSP430
– 68HC12
– COPS
● most cost $0.20 to $5
  Computer Architecture

Bus
CPU

registers
& Memory
ALU for
(math & logic) program Inputs Outputs
&
data

to physical world
 Desktop & Microcomputer

Bus
CPU

registers
& Memory
ALU for
(math & logic) program Inputs Outputs
&
data
one chip modules, chips
DIMM
& boards
carrier

to physical world
  Microcontroller

Bus
CPU

registers
& Memory
ALU for
(math & logic) program Inputs Outputs
&
data
one chip

to physical world
Microcontrollers
 ARM/Cortex
● has 32 bit internals
– each register has 32 bits
– the address bus has 32 bits (32 wires)
– the data bus has 32 bits (32 wires)
● uses 32 bit data
– numbers can go from 0 ... 4,295,000,000
– or -2,1475,000,000 ... +2,175,000,000
– or 4 characters
– or 8 hex digits
● has 32 address bits
– can, in theory, address 4GBytes
 Microcontroller Photo
● actual size is 4mm
by 6mm and about
0.4mm thick
● made of silicon
Another Microcontroller
 STM32F100RB
● the actual chip we will be using has
– CPU
● 16 registers of 32 bits each
● arithmetic unit
● execution unit
– 128KB of program/flash
– 8KB of data/ram
– timers, serial ports, A/D converter
– operates normally at 8MHz
● can run up to 24MHz
– has about 50 pins that you can control
 Microcontroller Memory
● RAM
– holds changeable data
● such as variables, counters, stack
– information is lost when power is removed
(volatile)

● EPROM/Flash
– holds program and data
● changed rarely, sometimes only once at
manufacturing time, or software update
– is erased in large blocks (½ kB to 4kB)
– information is retained when power is removed
(non-volatile)
– there is a version known as EEPROM which can be rewritten
much more often, erased one byte at a time
  Computer Architecture

Bus
CPU

registers
& Memory
ALU for
(math & logic) program Inputs Outputs
&
data

to physical world
 Microcontroller Memory
● Registers
– very very fast
● only a few of them; not on the address bus
– volatile

● Cache (not on this micro)

– very fast
● used to speed up operations
● rare in microcontrollers
 Memory Map
● shows the numeric range
debug &
sys timer
that each section of the
0xE000.0000
microcontroller responds to
● most common areas:
– program space (e.g.
i/o
0x4000.0000
[Link])
– RAM (e.g. 0x2000.0000-
[Link])
ram – I/O (e.g. 0x4000.0000-
0x2000.0000
[Link])

flash
0x0000.0000
 What goes on in the CPU?
R15 (PC)
R14 (LR)
R13 (SP) address
use as address
address bus
any register
R12

+
R11 addend
R10
R9
R8 load ← store → data bus
R7
R6 data

R5 data execution
unit ← instruction
any register
use as data

R4 fetch
R3
ALU
R2
data
R1 result
R0 PSR (status)
Microcontroller Data Flow
address(32) addr
match
CPU data(32) Flash/Program
addr=0

addr
match
RAM/variables
addr=0x2000.0000

addr
other I/O
addr=0x4000.0000
Microcontroller Pin Diagram

Power Port PA
(16 wires)
Ground
Port PB
(16 wires)

STM32F100RB
Port PC
(16 wires)

Port PD
(3 wires)
 A word on Busses
● the address bus is 32 wires which traverse
the chip
● the data bus is a different set of 32 wires,
which also traverse the chip
● each active section of the chip watches the
pattern on the address bus
– if the pattern matches the memory map for that
section, it wakes up and puts a pattern on the
data bus
 A Bus Cycle
● 8 million times a second, the CPU puts a
pattern on the address bus, then waits a few
nanoseconds and expects that some other
device has put a pattern on the data bus
– it absorbs the pattern present on the data bus,
assuming it to be valid
 How does the CPU execute
code?
– a million times a second......
● the CPU puts the pattern from the PC onto
the address bus, to “get” the next instruction
● the CPU absorbs the resulting pattern from
the data bus
● the CPU “executes” the instruction and adds
2 or 4 to the PC
● in some cases, the instruction may modify the PC, in
which case the flow of instructions appears to “jump”
● the CPU may cause activity on the “bus” which may in
turn cause memory changes, or outputs
 What is “code”
● patterns stored in memory
– accessible by the CPU
– different patterns mean different things to the
CPU
– ex. 0x4650 means “copy the pattern from R10
to R0”
– whereas 0x44d6 means “add R10 to R14 and
leave the result in R14”
 Data Storage
– the ARM/Cortex microcontroller is capable of
moving data around in groups of 32 bits
● but the memory is addressed by byte (8 bits)
– so, if we need to store a 32 bit number into 4
bytes, there are two possibilities
– big endian
store 0x8167.2232 into address 0x1010 0x100E 0x100F 0x1010 0x1011 0x1012 0x1013 0x1014
?? ?? 0x81 0x67 0x22 0x32 ??

– little endian

store 0xFF10CD40 into address 0x1010 0x100E 0x100F 0x1010 0x1011 0x1012 0x1013 0x1014
?? ?? 0x40 0xCD 0x10 0xFF ??
 Program Counter
● R15 in the register set is the address of the
next instruction
– setting R15 is the same as jumping to a new
address
– adding to R15 will skip ahead/backward
– whatever is at [R15+n] is located n bytes ahead
in the program
– is always an even number; ends in 0; when you
increment it, it goes up by 2
● BUT when you manually load R15, you must have the
least significant bit set to 1 (to signal “thumb” code)
– it's almost always referred to by its synonym pc
 Program Counter
● R15 will always used as if it's an even number
– instructions are always 16 or 32 bits wide
● Cortex is related to the ARM computer
– in the ARM, all instructions are 32 bits
– in the Cortex, a lot of instructions have been shrunk to
16 bits, which allows us to use less Flash in a project
– to tell the CPU which instruction set to use, we set the
bottom bit of R15 (0=ARM mode, 1=Cortex)
– our computer STM32 can only operate in Cortex, so any
time we load R15, it has to have the bottom bit set
– so it's an odd number! that we load into R15
– this applies to the vector table and any “ldr r15,#xyz” type of
instruction
 Link Pointer
● R14 in the register set is loaded with the
return address whenever a subroutine is
called
– when your code gets to the subroutine, R14 is
loaded with the address to go back to
– if you do “mov r15, r14”, you put the return
address back into the program counter
– this is the same as “return from subroutine”
– R14 is always an odd number
● the LSB is always 1 (the “thumb” bit)
– it's almost always referred to by its synonym lr
 Stack Pointer
● R13 in the register set is a pointer to the
stack in RAM
– whatever is at [R13] is the bottom of the stack
– whatever is at [R13+n] is located n bytes up the
stack
– the contents of [R13-4] is the next empty location
of the stack
– R13 is always divisible by 4; the 2 LSBs are
always 0; when you increment it, you add 4
– it's almost always referred to by its synonym sp
 General Registers

r0
r0..r3 can be used in
● the registers
r1
r2
subroutines
R0...R12 may be
r3 used to hold any 32
r4 r4....r11 should be
r5 preserved in bit number
subroutines
r6 ● the registers
r7
r8
R15(PC), R14(LR)
r9 and R13(SR) should
r10
r11 r12 can be used in
not be used for
r12 subroutines
r13 is stack pointer
general purpose
r13 = SP
r14 = LR
by convention
r14 has special use
storage
r15 has special use
r15 = PC
Complete List of Registers
● In addition to the core 16
registers, there are several
others
● there are two copies of SP
– one is used in interrupts
– the other can be used by
“protected” code
– we're only going to use
MSP for everything
● the PSR contains the flags
– see next slide
● the PRIMASK, FAULTMASK
& BASEPRI are used to
manage multiple interrupts
– we won't use these
● CONTROL
– controls which SP to use
● R0..R15 can be used directly
in assembly instructions
– everything below the
R15/PC line must be
accessed by MSR and
MRS
 Status Registers
Bit 31 30 29 28 27 26 25 24 23 22 … 10 8 8 … 0
N Z C V Q n/a T (1!) n/a interrupt #

● the CPSR register contains the status of the

last math operation and certain other status
bits
● N negative, same as msb of result
● Z zero, set if result is all zeros
● C carry
● V overflow
● Q remembers saturation state
● T is “thumb” flag........always 1 in this MCU
● when inside an interrupt, this tells you which one
– you fetch information from the CPSR differently
than other registers
– MSR move from register → special
– MRS move from special → register
 Opcodes
● The ARM/Cortex is a RISC (reduced
instruction set) design
– there are only ~30 basic instructions, and these
can operate on any register
● In RISC, the PC and the SP are treated like
any other register
– R4 = R4 + #4 is just math
– R15 = R15 + #4 is a jump ahead
– R13 = R13 + #4 moves the stack pointer up and
shrinks the stack
– as far as the execution unit is concerned, these
are all variations of the same instruction
 Opcodes
● through the ALU
– math: ADD, ADC, SUB, SBC, RSB [S]
– logic: AND, BIC, ORR, ORN, EOR [S]
– move: MOV, MVN, MOVT [S]
– compare: CMP, CMN, TEQ, TST
– rotate: RBIT, REV, REV16
– shifts: ASR, LSL, LSR, ROR, RRX [S] [S] set condition codes
– sign extend: SXTB, SXTH, UXTB, UXTH, SSAT, USAT
– bit fields: BFC, BFI, CLZ, SBFX, UBFX
● load/store
– LDR, STR, LDRB, LDRSB, STRB, LDRH, LDRSH, STRH, LDRD, STRD, ADR
– LDM, STM, PUSH, POP
● affecting PC
– B, BL
– BNE, BEQ, BM, BPL
– signed: BGT, BLT, BGE, BLE
– unsigned: BCS/BHS, BCC/BLO, BHI, BLS
– CBNZ, CBZ, TBB, TBH
● other
– NOP, MUL, SDIV, UDIV, MLA, MLS, SVC, MRS, MSR, CPSID, CPSIE
 Syntax
● in ARM assembly, the destination is the first
argument
– mov r0, r3
– add r1, r5, #5
– orr r2, r14, #0x12
– ldr r5, [r13]
● except the store instruction
– str r12, [r0,8]

● other computers may be different

– msp430/m68000 always goes from left to right
● mov [r4], r6
– x86 can be either!!!
 Syntax
● in ARM assembly, you are allowed to use 1,
2 or 3 operands
– mov r0, r3
– add r1, r5, r5
– b next_operation

● other microprocessors may be limited to 2

– x86/msp430 can only have 2
● mov eax, ebx
● add r6, r5
– means r6 = r6+r5
 Assembly Code
● programmers type ASCII versions of opcodes
● assembler converts these to binary
8000008: 4608 mov r0, r1
800000a: 4610 mov r0, r2
800000c: 4660 mov r0, r12
800000e: 4678 mov r0, pc // r15
8000010: 4408 add r0, r1
8000012: eb01 0001 add.w r0, r1, r1
8000016: 1840 adds r0, r0, r1
8000018: 1848 adds r0, r1, r1
800001a: 1857 adds r7, r2, r1
800001c: eb19 080a adds.w r8, r9, r10
8000020: f04f 0055 mov.w r0, #0x55
8000024: f100 0055 add.w r0, r0, #0x55
8000028: f101 0055 add.w r0, r1, #0x55
800002c: 3055 adds r0, #0x55
800002e: f111 0055 adds.w r0, r1, #0x55
 Instruction Types
● ALU instructions
– information starts and ends in registers
● move
● math
● logic
● Load & Store
– information starts or ends in RAM/FLASH/IO
● Branch
– conditional branch
– jump
– jump to subroutine (branch and link)
 What goes on in the CPU?
R15 (PC)
R14 (LR)
R13 (SP) address
address bus
R12
R11 addend
R10
R9
R8 load ← store → data bus
R7
R6 data

R5 data execution
R4 unit ← instruction
fetch
R3
ALU
R2
data
R1 result
R0 PSR (status)
 Consequence of Instruction
Types
● if you need information from FLASH, RAM or IO,
you'll need to use a LDR instruction
● once the information is in a register, you can
check it or change it
● then to put the information back into FLASH,
RAM or IO, you'll need to use an STR instruction
● so this is common:
movw r7, #0x2000000 // address into r7
ldr r6, [r7, #0x0C] // get info from ram
add r6, r6, #1 // modify info
str r6, [r7, #0x0C] // put it back into ram
 Consequence of Instruction
Types (cont'd)
● the previous slide showed an easy address
– you can only do a MOV instruction if the address is
simple, like 0x2000.0000
● more complicated addresses need to be fetched
with a LDR instruction
● so this is common:
●a double LDR, followed by the math, then an STR
ldr r7, =0x40011000 // address into r7
ldr r6, [r7, #0x0C] // get info from ram
add r6, r6, #1 // modify info
str r6, [r7, #0x0C] // put it back into ram
 Addressing
● how do we specify where the data comes
from for the instruction
– used in ALU instructions
● register mode
● immediate mode
– used in load and store instructions
● indirect
● indexed mode
● indexed with writeback
● indexed mode from PC
 Register Mode
● the easiest to explain is register mode is
where the information is in Rn
– add r4, r12, r6
● is the same as r4 = r12 + r6
– mov r3, r6
● is the same as r3 = r6
● in the ARM, you can also rotate/shift the last
register
– add r4, r12, r6, lsl #2
● is the same as r4 = r12 + (r6<<2)
● only used in ALU instructions
 Immediate Mode
● the actual data is included in with the instruction
add r4, r12, #41
● is the same as r4 = r12 + 41
mov r3, #0x41
● is the same as r3 = 65 = 0x41 = 'A'
movw r0, #0x55AC
● these are only available in ALU instructions
● the immediate value must be either
– smallish, less than 2^8 (255)
– a pattern in hex that only spans 8 bits shifted
● e.g. 0xAB000000 0x00AB0000 0x0000AB00 0x000000AB
– except for MOVW, which can take a 16 bit immediate and
ADD/SUB, which can take a 12 bit immediate
● HINT: if you want a negative number, use the opposite
instruction: change an “add” to a “sub”, or a “mov” to a
“mvn”
 Condition Codes
● When you operate on registers, there can be
extra & interesting information
● For example, when you add two numbers, there may
be an overflow which is not visible in the registers
themselves
● This information is stored in the PSR (program status
register)

● If you wish the PSR to be updated, simply

add an S to your opcode
● The S is automatic for the following opcodes:
TST, CMP

● This only applies to ALU instructions

 Indirect Register Mode
● use a register as a pointer to the data
● in assembly code, put [ ] around the register
name
● for example
– if r7 contains 0x2000.0104
ldr r4, [r7]
– will copy the contents of address 0x2000.0104
into r4
str r4, [r7]
– will copy the contents of r4 into ram at address
0x2000.0104
● only for load&store instructions
Indexed Mode, Immediate Offset
● very similar to indirect register is to use a
register as a pointer plus an offset
● in assembly code, put the register number and
the offset in square brackets
– the offset can be +/- 255
● for example
– if R7 contains 0x9300.0000
– if R6 contains 0x0019
str r6, [r7, #0x14]
copies the word 0x0000.0019 into ram at address
0x9300.0014
– only for load&store instructions
 Indexed Mode, Register Offset
● very similar to indirect register is to use a
register as a pointer plus another register
● in assembly code, put both the register
numbers in square brackets
– the second register can be shifted left or right
● for example
– if R7 contains 0x4101.0000
– if R6 contains 0x1234.5678
– if R5 contains 0x0000.0006
str r6, [r7, r5, lsl #1]
stores the word 0x1234.5678 into ram at address
0x4101.000C
– only for load&store instructions
 Indexed Mode with Writeback
● for the Indexed modes (last two slides), the new
address that was formed by addition can be stored
back into the index register before the load-store
● to indicate this, add a “!” at the end then of the
operand
● using the immediate form:
–if r7 contains 0x4000.0214, r5 contains 0x0000.0020
ldr r6,[r7,#0x1c]!
● will add 0x1c to r7, to get 0x4000.0230, update r7 with this
value, then copy the word at 0x4000.0230 into r6
● using the register mode:
ldr r6,[r7,r5]!
● will add 0x20 to r7, then update r7 with this value 0x4000.0234,
then copy the word at 0x4000.0234 into r6,
 Indexed Mode with Post
Writeback
● for the Indexed modes (back a few slides), a new
address can be formed by addition to the index
register after the load-store
● to indicate this, add an offset at the end then of the
operand, outside the square brackets
● using the immediate form:
–if r7 contains 0x4000.0214, r5 contains 0x0000.0020
ldr r6,[r7],#0x1c
● will copy the word at 0x4000.0214 into r6, add 0x1c to r7, to
get 0x4000.0230, and update r7 with this value,
● using the register mode:
ldr r6,[r7],r5,lsl #2
● will copy the word at 0x4000.0234 into r6, then add 0x80 to r7,
and update r7 with this value 0x4000.0294
 Literal Mode
● literal mode is simply indexed from the
program counter, R15
– that means the destination is somewhere near the
instruction, probably in flash
● only applies to load&store instructions
● there is a special function in the assembler
where you can ask the assembler to allocate
4 bytes, fill it with a number, and point to it
ldr r4,=0x1234.2222
● there is a special pseudo-op which adds the
PC (r15) to form an address
adr r5,something
– turns into add r5, r15, #something
 MOV & LDR
● what's the difference between a MOV and
LDR?
movw r7, #0x1234
– the number 0x1234 is buried in the instruction
● the instruction is already in the CPU
● fast

ldr r4, [r5, #4]

– says to use (R5+4) as an address, then go to that
address in FLASH, RAM or IO, and fetch the
information into R4
● causes another transaction on the address/data bus
 Load/Store Data Size
● You can control how many bytes are moved
for loads and stores
● By default, 4 bytes (32 bits) are used at a
time
– The B suffix lets you specify one byte

– The H suffix lets you specify two bytes

strh r5, [r7] ; store 2 bytes

● These are only for Load/Store instructions

– ALU operations are always 32 bit
 Summary
● for moves, math & logic
– from register to register: add r5, r6, r7
– can introduce small numbers: add r9, r9, #0x4c
● immediate
– can introduce a shift: mov r3, r2, lsl #3
– can set the condition codes add.s r4,r3,r1
● for loads and stores
– use a register as an address ldr r3, [r2]
+
– with an immediate offset ldr r3, [r2,
+ #8]
– with a register offset ldr r3, [r2,
+ r0, lsl #1]
– with pre-indexed ldr r3, [r2, #8]!+
– with post-indexed ldr r3, [r2], #4
+ there's an implied + addition here