INSTRUCTION SET ARCHITECTURE

• Machine instructions and program execution

• Addressing methods for accessing register and memory
operands

MODULE 2
MEMORY LOCATIONS, ADDRESSES, AND OPERATIONS
▪ Memory consists of many millions of storage cells, each n bits
of which can store 1 bit. first word
▪ Data is usually accessed in n-bit groups. n is called word second word
length.

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i th word

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last word

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Figure 2.5. Memory words.
MEMORY LOCATIONS, ADDRESSES, AND OPERATIONS
▪ 32-bit word length example
▪ To retrieve information from memory, either for
one word or one byte (8-bit), addresses for each
location are needed.
▪ A k-bit address memory has 2k memory
locations, namely 0 - 2k-1, called memory space.
▪ 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
▪ 32-bit memory: 232 = 4G (1G=230)
▪ 1K(kilo)=210
▪ 1T(tera)=240

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BYTE ADDRESSABILITY
▪ It is impractical to assign distinct addresses to
individual bit locations in the memory.
▪ The most practical assignment is to have successive
addresses refer to successive byte locations in the
memory – byte-addressable memory.
▪ Byte locations have addresses 0, 1, 2, … If word length
is 32 bits, the successive words are located at
addresses 0, 4, 8,…
▪ two ways that byte addresses can be assigned across
words
▪ Big-Endian: lower byte addresses are used for the most
significant bytes of the word
▪ Little-Endian: opposite ordering. lower byte addresses
are used for the less significant bytes of the word

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TOPICS COVERED FROM
▪ Textbook 1:
▪ Chapter 2: 2.1

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BYTE ADDRESSABILITY
▪ Two ways that byte addresses can be assigned
across words
▪ Big-Endian: lower byte addresses are used for the most
significant bytes of the word
▪ Little-Endian: opposite ordering. Lower byte addresses
are used for the less significant bytes of the word
▪ Example: 15326→ 1, 53 and 26
▪ Big-Endian: Little-Endian:
▪ Address: Value Address: Value
▪ 1000 : 01 1000 : 26
▪ 1001 : 53 1001 : 53
▪ 1002 : 26 1002 : 01

▪ The words “more significant” and “less significant”

are used in relation to the powers of 2 assigned to
bits when the word represents a number.

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WORD ALIGNMENT
▪ Word locations have aligned addresses if they begin at a byte address i.e., a multiple of the
number of bytes in a word.
▪ 16-bit word: word addresses: 0, 2, 4,….
▪ 32-bit word: word addresses: 0, 4, 8,….
▪ 64-bit word: word addresses: 0, 8,16,….

▪ If words begin at arbitrary byte address, words are said to have unaligned addresses.

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ACCESSING NUMBERS AND CHARACTERS
▪ A number usually occupies one word and can be accessed in the memory
by specifying its word address.
▪ Individual characters can be accessed by their byte address.

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MEMORY OPERATIONS
▪ Load (or Read or Fetch)
▪ Copy the content. The memory content doesn’t change.
▪ Address – Load
▪ Registers can be used

▪ Store (or Write)

▪ Overwrite the content in memory
▪ Address and Data – Store
▪ Registers can be used

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INSTRUCTION AND INSTRUCTION SEQUENCING
▪ “Must-Perform” Operations
▪ Data transfers between the memory and the processor registers
▪ Arithmetic and logic operations on data
▪ Program sequencing and control
▪ I/O transfers

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REGISTER TRANSFER NOTATION
▪ Identify a location by a symbolic name standing for its hardware binary address (LOC, R0,…)
▪ Contents of a location are denoted by placing square brackets around the name of the location
▪ e.g. R1←[LOC]
R3 ←[R1]+[R2]
▪ Register Transfer Notation (RTN)

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ASSEMBLY-LANGUAGE NOTATION
▪ Represent machine instructions and programs.
▪ Move R1,LOC → R1←[LOC]
▪ Add R3, R1, R2 → R3 ←[R1]+[R2]

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RISC AND CISC INSTRUCTION SET
▪ Most important characteristics that distinguish different computers is the nature of their
instructions
▪ Reduced Instruction Set Computers (RISC)
▪ Higher performance can be achieved if each instruction occupies exactly one word in memory, and all
operands needed to execute a given arithmetic or logic operation specified by an instruction are already in
processor registers
▪ Various operations needed to process a sequence of instructions are performed in “pipelined” fashion
▪ Number of different types of instructions may be included in the instruction set of a computer.

▪ Complex Instruction Set Computers (CISC)

▪ An alternative to RISC
▪ makes use of more complex instructions which may span more than one word of memory, and
▪ may specify more complicated operations.

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RISC INSTRUCTION SETS
▪ Two key characteristics of RISC instruction sets are:
1. Each instruction fits in a single word.
2. A load/store architecture is used, in which
▪ Memory operands are accessed only using Load and Store instructions.
▪ All operands involved in an arithmetic or logic operation must either be in processor registers, or one of the operands
may be given explicitly within the instruction word.

▪ At the start of execution of a program, all instructions and data used in the program are stored in
the memory of a computer.
▪ Processor registers do not contain valid operands at that time.
▪ Load instructions: Operands expected to be in processor registers before they can be used by an
instruction, are transferred from memory location into the registers.
▪ Load instructions are of the form
▪ Load destination, source

▪ In general,
▪ Load processor_register, memory_location
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RISC INSTRUCTION SETS
▪ C=A+B
▪ C ← [A] + [B]
▪ Assembly:
▪ Load R2, A
▪ Load R3, B
▪ Add R4, R2, R3
▪ Store R4, C

▪ Three-Address Instructions
▪ Add destination, source1, source2

▪ The Store instruction is of the form

▪ Store source, destination

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INSTRUCTION EXECUTION AND STRAIGHT-LINE SEQUENCING
▪ a possible program segment for the task, C=A+B,
as it appears in the memory of a computer.
▪ Straight-line sequencing: using the information in
the PC to fetch and execute instructions, one at a
time, in the order of increasing addresses.
▪ Executing a given instruction is a two-phase
procedure.
▪ Instruction fetch (First phase)
▪ Instruction execute (Second phase)

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TOPICS COVERED FROM
▪ Textbook 1:
▪ Chapter 2: 2.1, 2.2, 2.3

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INSTRUCTION EXECUTION AND STRAIGHT-LINE SEQUENCING
▪ a possible program segment for the task, C=A+B,
as it appears in the memory of a computer.
▪ Straight-line sequencing: using the information in
the PC to fetch and execute instructions, one at a
time, in the order of increasing addresses.
▪ Executing a given instruction is a two-phase
procedure.
▪ Instruction fetch (First phase)
▪ Instruction execute (Second phase)

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BRANCHING
▪ Consider the task of adding a list of n
numbers.

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BRANCHING
▪ Consider the task of adding a list of n
numbers in a loop.

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BRANCHING
▪ Branch_if_[R4]>[R5] LOOP
▪ In generic assembly language as: Branch_greater_than R4, R5, LOOP
▪ Using an actual mnemonic as: BGT R4, R5, LOOP

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GENERATING MEMORY ADDRESSES
▪ The purpose of the instruction block starting at
LOOP is to add successive numbers from the list
during each pass through the loop
▪ must refer to a different address during each
pass
▪ memory operand address cannot be given
directly in a single Load instruction in the loop.

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ADDRESSING MODES
▪ Addressing modes:
▪ Different ways for specifying the locations of instruction operands.

▪ RISC-style processors basic addressing modes Table 2.1

▪ The assembler syntax defines the way in which instructions and the addressing
modes of their operands are specified

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IMPLEMENTATION OF VARIABLES AND CONSTANTS
▪ Register mode
▪ The operand is the contents of a processor register; the name of the register is given in
the instruction.
▪ Example: Add R4, R2, R3

▪ Absolute mode
▪ The operand is in a memory location; the address of this location is given explicitly in
the instruction.
▪ Load R2, NUM1

▪ Immediate mode
▪ The operand is given explicitly in the instruction.
▪ Add R4, R6, 200immediate
▪ Add R4, R6, #200

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INDIRECTION AND POINTERS
▪ Indirect mode:
▪ The effective address of the operand is the contents of a register that is specified in
the instruction
▪ Load R2, (R5)

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TOPICS COVERED FROM
▪ Textbook 1:
▪ Chapter 2: 2.3, 2.4

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INDIRECTION AND POINTERS
▪ Indirect mode:
▪ The effective address of the operand is the contents of a register that is specified in
the instruction
▪ Load R2, (R5)

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INDIRECTION AND POINTERS

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INDIRECTION AND POINTERS
▪ C-language statement
A = *B;

▪ Compiled to:
Load R2, B // loads the content in B i.e., the address of location where B is pointing at (ex: AAA0)
Load R3, (R2) //go to location AAA0 and copy the data to R3
Store R3, A // store the content of R3 in A

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INDEXING AND ARRAYS
▪ Index mode:
▪ the effective address of the operand is generated by adding a constant value to the contents of a
register.
▪ Index register: The register used in this mode is known as the index register
▪ X(Ri): EA = X + [Ri]
▪ The constant X may be given either as an explicit number or as a symbolic name
representing a numerical value.
▪ If X is shorter than a word, sign-extension is needed.

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INDEX MODE: TYPES
▪ Offset is given as a constant

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INDEX MODE: TYPES
▪ Offset is in the index register

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INDEXED ADDRESSING: EXAMPLE
▪ 2D array representation

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INDEXED ADDRESSING: EXAMPLE

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INDEXED ADDRESSING: VARIATIONS
▪ Base with Index: (Ri,Rj)
▪ EA = [Ri] + [Rj]

▪ Base with Index plus constant: X(Ri, Rj)

▪ EA = X + [Ri] + [Rj]

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ADDRESSING MODES

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RISC STYLE
▪ RISC style is characterized by:
▪ Simple addressing modes
▪ All instructions fitting in a single word
▪ Fewer instructions in the instruction set, because of simple addressing modes
▪ Arithmetic and logic operations that can be performed only on operands in processor registers
▪ Load/store architecture that does not allow direct transfers from one memory location to another;
such transfers must take place via a processor register
▪ Simple instructions that are conducive to fast execution by the processing unit using techniques
such as pipelining
▪ Programs that tend to be larger in size, because more, but simpler instructions are needed to
perform complex tasks

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CISC STYLE
▪ CISC style is characterized by:
▪ More complex addressing modes
▪ More complex instructions, where an instruction may span multiple words
▪ Many instructions that implement complex tasks
▪ Arithmetic and logic operations that can be performed on memory operands as well as
operands in processor registers
▪ Transfers from one memory location to another by using a single Move instruction
▪ Programs that tend to be smaller in size, because fewer, but more complex instructions
are needed to perform complex tasks

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CISC INSTRUCTION SET
▪ CISC instruction sets are not constrained to the load/store architecture, in which
arithmetic and logic operations can be performed only on operands that are in
processor registers.
▪ Instructions do not necessarily have to fit into a single word.
▪ Some instructions may occupy a single word, but others may span multiple words
▪ Most arithmetic and logic instructions use the two-address format
Operation destination, source
▪ An Add instruction of type
Add B, A
▪ is written as
B ← [A] + [B]

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CISC INSTRUCTION SET: EXAMPLE
▪ Consider the task of adding two numbers where all three operands may be in memory
locations
C=A+B
▪ This cannot be done with a single two-address instruction.
▪ Another two-address instruction is required that copies the contents of one memory location
into another.
Move C, B
▪ which performs the operation C←[B] (contents of location B is unchanged).
▪ The operation C←[A] + [B] can now be performed by the two-instruction sequence
Move C, B
Add C, A

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CISC INSTRUCTION SET
▪ In some CISC processors one operand may be in the memory but the other must be in a
register.
▪ In this case, the instruction sequence for the required task would be
Move Ri, A
Add Ri, B
Move C, Ri
▪ The general form of the Move instruction is
Move destination, source
▪ where both the source and destination may be either a memory location or a processor
register

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ADDITIONAL ADDRESSING MODES
▪ Autoincrement mode: (Ri)+
▪ The effective address of the operand is the contents of a register specified in the instruction.
▪ After accessing the operand, the contents of this register are automatically incremented to point to
the next operand in memory

▪ Computers that have the Autoincrement mode automatically increment the contents of the
register by a value that corresponds to the size of the accessed operand.
▪ Increment is 1 for byte-sized operands, 2 for 16-bit operands, and 4 for 32-bit operands.

▪ Autodecrement mode: −(Ri)

▪ The contents of a register specified in the instruction are first automatically decremented and are
then used as the effective address of the operand

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ADDITIONAL ADDRESSING MODES
▪ To push a new item on the stack,
Subtract SP, #4
Move (SP), NEWITEM
▪ just one instruction can be used
Move −(SP), NEWITEM

▪ Similarly, to pop an item from the stack,

Move ITEM, (SP)
Add SP, #4
▪ We can use just
Move ITEM, (SP)+

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ADDITIONAL ADDRESSING MODES
▪ Relative mode:
▪ the effective address is determined by the Index mode using the program counter in place of the
general-purpose register.
▪ X(PC) – note that X is a signed number

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CONDITION CODES
▪ Operations performed by the processor typically generate results such as numbers that are
positive, negative, or zero
▪ Maintain the information about these results for use by subsequent conditional branch
instructions
▪ Accomplished by recording the required information in individual bits, often called condition
code flags
▪ These flags are usually grouped together in a special processor register called the condition
code register or status register.
▪ Individual condition code flags are set to 1 or cleared to 0, depending on the outcome of the
operation performed

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CONDITION CODES
▪ Commonly used flags:

▪ e.g. Branch>0 LOOP

▪ This instruction causes a branch if both N and Z are 0, that is, if the result produced by
previous arithmetic instruction is neither negative nor equal to zero

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CONDITION CODES
▪ CISC style programming to add a list of numbers

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EXAMPLE: VECTOR DOT PRODUCT PROGRAM (RISC STYLE)
▪ Dot Product =σ𝑛−1
𝑖=0 𝐴 𝑖 × 𝐵(𝑖)

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EXAMPLE: VECTOR DOT PRODUCT PROGRAM (CISC STYLE)
▪ Dot Product =σ𝑛−1
𝑖=0 𝐴 𝑖 × 𝐵(𝑖)

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TOPICS COVERED FROM
▪ Textbook 1:
▪ Chapter 2: 2.4, 2.10, 2.11, 2.12

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