Assignment 7

FACULTY OF ENGINEERING AND THE BUILT ENVIROMENT DEPARTMENT OF
ELECTRICAL ENGINEERING TECHNOLOGY
Surname and initials: Madiope, T

Student number: 221158199
Module name: Digital Systems 2B
Module code: DIGELB2
Assignment 7: Half-adder and full adder
Lecturer: Dr. Johan Venter
Table of Contents
Description of practicals ................................................................................................................. 2
Software code.................................................................................................................................. 2
Half-adder code ........................................................................................................................... 2
Full-adder code ........................................................................................................................... 2
Stimulus graphs ............................................................................................................................... 3
Discussion of code and stimulus graphs ......................................................................................... 4
Discussion of half-adder code and stimulus graphs .................................................................... 4
Discussion of full-adder code and stimulus graphs .................................................................... 5
List of Figures
Figure 1: Half-adder stimulus graph ............................................................................................... 3
Figure 2: Full-adder stimulus graph ................................................................................................ 3
Figure 3: A equals 1 and B equals 0 ............................................................................................... 4
Figure 4: A equals 0 and B equals 1 ............................................................................................... 4
Figure 5: Half-adder pin assignments ............................................................................................. 5
Figure 6: All inputs and outputs equal zero .................................................................................... 5
Figure 7: A and B and Carry-out equal 1 ........................................................................................ 6
Figure 8: Full-adder pin assignments .............................................................................................. 6
List of Tables
Table 1: Half-adder truth table ........................................................................................................ 4
Table 2: Full-adder truth table ........................................................................................................ 5
1
Description of practicals
The objective of this practical is to implement a calculation functions used in almost all modern-
day calculators. This is the half-adder and full-adder.
Software code
Half-adder code
library ieee;
use ieee.std_logic_1164.all;
entity project_7 is
port (A, B : in std_logic;
SUMH, COH : out std_logic);
end project_7;
architecture half_adder of project_7 is

begin
SUMH <= A xor B;
COH <= A and B;
end half_adder;
Full-adder code
library ieee;
use ieee.std_logic_1164.all;
entity project_7 is
port (A, B, CIN : in std_logic;
SUMF, COF : out std_logic);
end project_7;
architecture full_adder of project_7 is

begin
SUMF <= A xor B xor CIN;
COF <= (A and B) or (A and CIN) or (B and CIN) or (A and B and CIN);
end full_adder;
2
Stimulus graphs
Figure 1: Half-adder stimulus graph
Figure 2: Full-adder stimulus graph
3
Discussion of code and stimulus graphs
Discussion of half-adder code and stimulus graphs
A B SUM CARRY OUT

0 0 0 0
1 0 1 0
0 1 1 0
1 1 0 1
Table 1: Half-adder truth table
In the code there are two inputs (A and B) and two outputs (carry out and sum). The sum column
and stimulus follows/mimics the truth table of an XOR logic gate. Hence, the sum (SUMH) is
less than or equal to “A xor B”. For the carry out column, only when input A and B are high
(digital logic 1) will the carry out be 1. The logic implemented by the column and stimulus of the
output carry is the AND logic. Therefore, the carry out will equal to input A multiplied by input
B (“A and B”).
Figure 3: A equals 1 and B equals 0
Figure 4: A equals 0 and B equals 1
4
The code will then output the truth table of the xor. Once the code is done being compiled it can
then be transferred to a Field Programmable Grid Array (FPGA). Assigning pins is essential first
so that the code can be implemented practically. Pin assignments can be done under “Pin
Planner.”
Figure 5: Half-adder pin assignments
Discussion of full-adder code and stimulus graphs
A B CARRY IN SUM CARRY OUT

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Table 2: Full-adder truth table
The full-adder is similar to the half-adder. However, the main differences are the third input from
the full-adder and the pin assignments. The input is called the carry in or input carry. Again, the
sum of the full-adder follows 3-input XOR logic. For the sum of all three to output a high (logic
1), only one of the inputs should be high. If more than one input is high, then the carry out will
produce a logic 1. The logic of the carry out will mimic the AND gate logic where two or three
of the inputs will need to be high for the output carry to be high.
Figure 6: All inputs and outputs equal zero
5
Figure 7: A and B and Carry-out equal 1
Pin assignments are essential to use the FPGA. Pins used are optional. Just use appropriate pins
for inputs (switches) and outputs (LEDs).
Figure 8: Full-adder pin assignments

Assignment 7

Uploaded by

Assignment 7

Uploaded by

FACULTY OF ENGINEERING AND THE BUILT ENVIROMENT DEPARTMENT OF

ELECTRICAL ENGINEERING TECHNOLOGY

Surname and initials: Madiope, T

architecture half_adder of project_7 is

architecture full_adder of project_7 is

Figure 1: Half-adder stimulus graph

Figure 2: Full-adder stimulus graph

A B SUM CARRY OUT

Figure 3: A equals 1 and B equals 0

Figure 4: A equals 0 and B equals 1

Figure 5: Half-adder pin assignments

Discussion of full-adder code and stimulus graphs

A B CARRY IN SUM CARRY OUT

Figure 6: All inputs and outputs equal zero

Figure 8: Full-adder pin assignments

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