Module 3 – Interrupts and Interfacing

101003/CS500D
Microprocessors and Microcontrollers
Syllabus

● Stack structure of 8086, programming using stack

● Interrupts - Types of Interrupts and Interrupt Service Routine- Handling

Interrupts in 8086- Interrupt programming-

● Programmable Interrupt Controller - 8259, Architecture

● Interfacing Memory with 8086

Course Outcomes

● CO1: Illustrate the architecture, modes of operation and addressing modes of

microprocessors.
● CO2: Develop 8086 assembly language programs.
● CO3: Demonstrate interrupts, its handling and programming in 8086.
● CO4: Illustrate how different peripherals (8255,8254,8257) and memory are
interfaced with microprocessors.
● CO5: Outline features of microcontrollers and develop low level programs.
 ● Area of memory for keeping

8086 temporary data.

Stack Structure ● Used for temporarily storing

the contents of the registers.
8086 Stack Structure

● Top-down data structure

● Elements are accessed using the stack pointer (SP)

● SP gets decremented by two as a data word is stored into the stack → Push

● SP gets incremented by two as a data word is retrieved from the stack back to the

CPU register → Pop

● The stack is essentially Last-In-First-Out (LIFO) data segment

8086 Stack Structure

● The Stack Segment register (SS) and Stack pointer register (SP) together address

the stack-top.

● Stack Segment register (SS) contains the base address of the stack segment in the

memory.

● The stack pointer is a 16-bit register that contains the offset address of the

memory location in the stack segment.

● The stack segment, like any other segment, may have a memory block of a

maximum of 64 Kbytes locations

8086 Stack Structure
8086 Stack Structure

● The Stack Segment register (SS) and Stack pointer register (SP) together address

the stack-top.

● Stack top → 52050H, ie the location 52050H is already occupied with the

previously pushed data.

● Next 16 bit push operation will decrement the stack pointer by two.

● So SP → 204EH & new stack-top → 5204EH.

● This location will now be occupied by the recently pushed data.

8086 Stack Structure
8086 Stack Structure

● For a selected value of SS, the maximum value of SP=FFFFH and the segment can

have maximum of 64K locations.

● If the SP starts with an initial value of FFFFH, it will be decremented by two

whenever a 16-bit data is pushed onto the stack.

● After successive push operations, when the stack pointer contains 0000H, any

attempt to further push the data to the stack will result in stack overflow.
8086 Stack - Uses

● After a procedure is called using the CALL instruction, the IP is incremented to the

next instruction.

● Then the contents of IP, CS and flag register are pushed automatically to the

stack.

● The control is then transferred to the specified address in the CALL instruction

i.e. starting address of the procedure.

● Then the procedure is executed.

8086 Stack Programming

● Stack used for saving and restoring values:

MOV AX, 1234h

PUSH AX ; store value of AX in stack.

MOV AX, 5678h ; modify the AX value.

POP AX ; restore the original value of AX.

8086 Stack Programming

● Stack used for swapping values: (Method 1)

MOV AX, 1212h ; store 1212h in AX.

MOV BX, 3434h ; store 3434h in BX

PUSH AX ; store value of AX in stack.

PUSH BX ; store value of BX in stack.

POP AX ; set AX to original value of BX.

POP BX ; set BX to original value of AX.

8086 Stack Programming

● Stack used for swapping values: (Method 2)

MOV AX, 1212h ; store 1212h in AX.

MOV BX, 3434h ; store 3434h in BX

PUSH AX ; store value of AX in stack.

MOV AX, BX ; store the value of AX in BX

POP BX ; set BX to original value of AX.

BH
 ● Interrupt breaks the normal
sequence of execution of
instructions.
● Diverts execution to other
program called Interrupt
8086 Service Routine (ISR).

Interrupts
● After executing ISR control
gets transferred back to the
program that got interrupted.
● Execution is resumed from the
point at which it was
interrupted
● Interrupt is the method of creating a temporary halt during program execution
and allows peripheral devices to access the microprocessor.

● The microprocessor responds to that interrupt with an ISR (Interrupt Service

Routine), which is a short program to instruct the microprocessor on how to
handle the interrupt.

● Interrupts are useful when interfacing I/O devices with low data-transfer rates, like
a keyboard or a mouse, in which case polling the device wastes valuable processing
time
● The peripheral interrupts the normal application execution, requesting to send or
receive data.

● The processor jumps to a special program called Interrupt Service Routine to

service the peripheral

● After the processor services the peripheral, the execution of the interrupted
program continues.
 Hardware interrupt is caused by any
peripheral device by sending a signal
through a specified pin to the
microprocessor.

The 8086 has two hardware interrupt

pins,i.e. NMI and INTR.
Hardware Interrupts NMI is a non-maskable interrupt and

INTR is a maskable interrupt having lower

priority.

One more interrupt pin associated is INTA

called interrupt acknowledge.
INTR - Maskable Interrupt
Using maskable interrupt request pin (INTR) → microprocessor will be
interrupted only if interrupts are enabled using set interrupt flag instruction

These actions are taken by the microprocessor −

● First completes the current instruction.

● If IF=0 the processor ignores the interrupt, else sends Interrupt Acknowledge
(INTA) to hardware interface and receives the interrupt type, say X.
● Flag register value, CS value of the return address and IP value of the return
address are pushed on to the stack.
● IP value is loaded from the contents of word location X × 4
● CS is loaded from the contents of the next word location.
● Interrupt flag and trap flag is reset to 0
NMI - Non Maskable Interrupt
It is a single non-maskable interrupt pin (NMI) having higher priority than the
maskable interrupt request pin (INTR)and it is of type 2 interrupt

When this interrupt is activated, these actions take place −

● Completes the current instruction that is in progress.

● Pushes the Flag register values on to the stack.
● Pushes the CS (code segment) value and IP (instruction pointer) value of the
return address on to the stack.
● IP is loaded from the contents of the word location 00008H.
● CS is loaded from the contents of the next word location 0000AH.
● Interrupt flag and trap flag are reset to 0.
 Instructions are inserted at the desired
position into the program to create
interrupts.

Format of Instruction - INT Interrupt type

number
Software Interrupts It is 2-byte instruction. First byte provides
the op-code and the second byte provides
the interrupt type number.

There are 256 interrupt types under this

group.
Execution of Software Interrupt
Its execution includes the following steps −

● Flag register value is pushed onto the stack.

● CS value of the return address and IP value of the return address are
pushed on to the stack.
● IP is loaded from the contents of the word location ‘type number’ × 4
● CS is loaded from the contents of the next word location.
● Interrupt Flag and Trap Flag are reset to 0
External Interrupts Internal Interrupts
External device or signals interrupts Generated internally by processor
the processor from outside circuit or by execution of interrupt
instruction
Only Hardware Interrupts Can be Hardware or Software
Interrupts

Eg. Keyboard Interrupt Eg. Divide by Zero Interrupt,

Overflow Interrupt
INT instructions

Interrupt Type is implicit Interrupt Type is explicit or implicit

Steps involved in processing an interrupt instruction by 8086
Interrupt Vector Table (IVT) on 8086
How to get the values of CS and IP register ?

The 8086 gets the new values of CS and IP register from four memory
addresses.

When it responds to an interrupt, the 8086 goes to specific memory locations

to get the CS and IP values for the start of the interrupt service routine.

In the Interrupt Structure of 8086 system the first 1 Kbyte of memory from
00000H to 003FFH is reserved for storing the starting addresses of interrupt
service routines.

This block of memory is often called the Interrupt Vector Table in 8086 or the
interrupt pointer table.
The size for each interrupt vector is 4 bytes (2 word in 16 bit), where 2 bytes (1
word) for segment and 2 bytes for offset of interrupt service routine address.

So it takes 1024 bytes (1 kb) memory for interrupt vector table.

The first 5 vectors are reserved by Intel to be used by the processor.

The vectors 5 to 255 are free to be used by the user.

Every external and internal interrupt is assigned with a type that is either
implicit (NMI, TRAP, Divide by Zero etc. ) or specified in instruction INT N
Interrupt Vector Table
Interrupt Vector Table Cont’d
The starting address for Type 0 interrupt is 000000H, for Type 1 interrupt is
00004H similarly for Type2 is 00008H and ……so on.

The first five pointers are dedicated interrupt pointers. i.e. −

TYPE 0 interrupt represents division by zero situation.

TYPE 1 interrupt represents single-step execution during the debugging of a

program.

TYPE 2 interrupt represents non-maskable NMI interrupt.

TYPE 3 interrupt represents break-point interrupt.

TYPE 4 interrupt represents overflow interrupt

Some sub functions of INT 21H
Subfunction Meaning
AH = 01H READ CHARACTER FROM STANDARD
INPUT, WITH ECHO
AH = 02H WRITE CHARACTER TO STANDARD
OUTPUT
AH = 05H WRITE CHARACTER TO PRINTER
AH = 0AH READ STRING FROM STANDARD
INPUT
AH = 09H WRITE STRING TO STANDARD
OUTPUT
AH = 4CH "EXIT" - TERMINATE WITH RETURN
CODE
Interrupt Response Sequence
Nested Interrupts
 Interrupt Vector Table – Real Mode (16-bit) Example
Using the Interrupt Vector Table shown below, determine the address of the ISR of a
device with interrupt vector 42H. ​
 Interrupt Vector Table – Real Mode (16-bit) Example
Using the Interrupt Vector Table shown below, determine the address of the ISR of a
device with interrupt vector 42H. ​

● Address in table = 4 X 42H = 108H ​(Multiply by 4 since each entry is 4 bytes)​

● Offset Low = [108] = 2A, Offset High = [109] = 33​

● Segment Low = [10A] = 3C, Segment High = [10B] = 4A​

● Address = 4A3C:332A = 4A3C0 + 332A = 4D6EAH​

 Interrupt Vector Table – Real Mode (16-bit) Example
Write a sequence of instructions that initialize vector 40H to point to the ISR “isr40”. ​

● Address in table = 4 X 40H = 100H ​

● Set ds to 0 since the Interrupt Vector Table begins at 00000H​

● Get the offset address of the ISR using the Offset directive​

● and store it in the addresses 100H and 101H​

● Get the segment address of the ISR using the Segment directive​

● and store it in the addresses 102H and 103H​

 Interrupt Vector Table – Real Mode (16-bit) Example
Write a sequence of instructions that initialize vector 40H to point to the ISR “isr40”. ​
 ● Programmable interrupt
controllers are used to increase
8259 the number of interrupts of a
microprocessor.

Programmable ● 8259 PIC never services an

Interrupt Controller
interrupt.

● It simply forwards the interrupt

(PIC) to the processor for the
execution of interrupt service
routine.
8259 Programmable Interrupt Controller (PIC)
Functions as an overall manager in an Interrupt-Driven system environment.

● It accepts requests from the peripheral equipment

● Determines which of the incoming requests is of the highest importance
(priority)
● Ascertains whether the incoming request has a higher priority value than
the level currently being serviced
● Issues an interrupt to the CPU based on this determination.
8259 - Programmable Interrupt Controller
Each peripheral device or structure usually has a special program or ‘‘routine’’
that is associated with its specific functional or operational requirements; this
is referred to as a ‘‘Interrupt Service Routine’’.

The PIC, after issuing an Interrupt to the CPU, must somehow input
information into the CPU that can ‘‘point’’ the Program Counter to the service
routine associated with the requesting device.

This ‘‘pointer’’ is an address in a vectoring table and will often be referred to,
as Interrupt Vector Table.
8259 - Internal Block Diagram
DATA BUS BUFFER : This 3-state, bidirectional 8-bit buffer is used to interface
the 8259A to the system Data Bus.

Control words and status information are transferred through the Data Bus
Buffer.

READ/WRITE CONTROL LOGIC : The function of this block is to accept Output

commands from the CPU.

It contains the Initialization Command Word (ICW) registers and Operation

Command Word (OCW) registers which store the various control formats for
device operation.

This function block also allows the status of the 8259A to be transferred onto
the Data Bus.
INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR) : The
interrupts at the IR input lines are handled by two registers in cascade, the
Interrupt Request Register (IRR) and the In-Service Register (ISR).

The IRR is used to store all the interrupt levels which are requesting service;
and the ISR is used to store all the interrupt levels which are being serviced.

PRIORITY RESOLVER : This logic block determines the priorities of the bits set
in the IRR.

The highest priority is selected and stored into the corresponding bit of the
ISR during INTA pulse.

The IR0 has the highest priority while the IR7 has the lowest priority in fixed
priority mode.
INTERRUPT MASK REGISTER (IMR) : The IMR stores the bits which mask the
interrupt lines to be masked.

The IMR operates on the IRR. Masking of a higher priority input will not affect
the interrupt request lines of lower quality.

INT (INTERRUPT) : This output goes directly to the CPU interrupt input.

The VOH level on this line is designed to be fully compatible with the 8080A,
8085A and 8086 input levels

INTA (INTERRUPT ACKNOWLEDGE) : INTA pulses will cause the 8259A to

release vectoring information onto the data bus. The format of this data
depends on the system mode of the 8259
 D7-D0: These pins form a bidirectional data bus that carries 8-bit data either
to control word or from status word registers. This also carries interrupt
vector information.

IR0-IR7: These pins act as inputs to accept interrupt requests to the CPU.

WR: This pin is active-low write enable input to 8259A. This enable it to
accept command words from CPU.

RD: This pin is active-low read enable input to 8259A. A low on this line
enables 8259A to release status onto the data bus of the CPU.

CS: This is an active-low chip select signal for enabling RD and WR operations
of 8259A.
CASCADE BUFFER/COMPARATOR : This block stores and compares the ID’s of
all the 8259As used in the system. The 3 I/O pins CAS0-2 are outputs when the
8259A is used as a master. The same pins act as inputs when the 8259A is in
slave mode. The 8259A in master mode sends the ID of the interrupting slave
device on these lines. The slave thus selected, will send its preprogrammed
vector address on the data bus during the next INTA pulse

SP/EN: This pin is used as an input to designate whether the chip is used as a
master (SP = 1) or a slave (EN = 0)

CAS0-CAS2 Cascade Lines: A single 8259A provides eight vectored inputs. If

more interrupts are required, the 8259A is used in cascade mode. In cascade
mode, a master 8259A along with 8 slaves can provide up to 64 vectored
interrupt lines. These 3 lines act as select lines for addressing the 8259A
slaves.
 Interrupt sequence in an 8086-8259A system
● One or more IR lines are raised high that set corresponding IRR bits
● 8259A resolves priority and sends an INT signal to the CPU
● The CPU acknowledges with INTA pulse.
● When it receives INTA → 8259A will set the highest priority ISR bit and
reset the corresponding IRR bit.
● Then 8086 initiates a second INTA. During this time 8259A releases an 8
bit pointer on to the data bus, which is later read by the CPU.
● End of interrupt cycle. ISR bit is reset at the end of second INTA pulse in
AEOI mode. Otherwise ISR bit remains set until EOI command is issued at
the end of interrupt subroutine.
8259 - Cascade Mode of Connecting
Interfacing Memory with 8086
 Memory - Stores Program and Data

Processor Memory Primary or Main Memory Secondary Memory

● Registers inside a ● Storage area which can ● Storage media comprising
microcomputer be directly accessed by of slow devices such as
microprocessor magnetic tapes and disks
● Store data and results
temporarily ● Store programs and data ● Hold large data files and
prior to execution programs: Operating
● No speed disparity
system, compilers,
● Should not have speed
● Cost is high databases, permanent
disparity with processor
programs etc.
● Semiconductor memories
using CMOS technology

● ROM, EPROM, Static RAM,

DRAM
Memory organization in 8086
● Memory IC’s : Byte oriented
● 8086 : 16-bit
● Word : Stored by two consecutive memory locations; for LSB and MSB
● Address of word : Address of LSB
● Bank 0 : A0 = 0 → Even addressed memory bank
● Bank 1 : (𝑩𝑯𝑬) = 0 → Odd addressed memory bank
 Operation (BHE) A0 Data Lines Used

1 Read/ Write byte at an even address 1 0 D7 – D0

2 Read/ Write byte at an odd address 0 1 D15 – D8

3 Read/ Write word at an even address 0 0 D15 – D0

4 Read/ Write word at an odd address 0 1 D15 – D0 in first operation byte from
odd bank is transferred

1 0 D7 – D0 in first operation byte from

odd bank is transferred
Semiconductor Memory Interfacing

Semiconductor
Memory

RAM ROM

SRAM DRAM
Memory Map of 8086
EPROM’s are mapped at FFFFFH

RAM are mapped at the beginning; 00000H is allotted to RAM

● Semiconductor memories are organized as 2 dimensional arrays of
memory locations.

● Eg: 4K x 8 or 4Kb memory → 4096 locations

● Each location → 8 bits

● Only 1 location can be selected at a time

● Data bus → used for accessing all bits in a location at the same time

● To address N locations → n bits of address, ie n address lines are needed

● n = Log2 N
● If the processor has n address lines, then it can address N locations where
2n = N
● If only P out of N locations has to be interfaced, then only p address lines
are needed for directly connecting from microprocessor to chip
● Remaining n-p higher order address lines may be used for address
decoding (as inputs to chip selection logic)
● Memory address depends upon the hardware circuit used for decoding
chip select (CS)
● The output of the decoding circuit is connected with the CS pin of the
memory chip
● The general procedure of static memory interfacing with 8086 is as
follows:

1. Arrange the available memory chips so as to obtain 16 bit data bus width.
Upper 8-bit bank →Odd address memory bank
Lower 8-bit bank → Even address memory bank

2. Connect address lines of memory chips with the 8086 address lines
Connect memory RD and WR inputs to the corresponding 8086 signal
Connect the 16 bit data bus of the memory bank with that of 8086.

3. BHE and A0 are used for decoding the chip select signals for odd and even
memory banks. CS of memory → derived from o/p of decoding circuit
● Problem 1: Interface two 4K x 8 EPROMS and two 4K x 8 RAM chips with
8086. Select suitable maps.

● Solution: After reset , the processor starts from FFFF0H. This address
must lie in the EPROM.

● Memory map
● 8K bytes of EPROM → 13 address lines form A0 to A12

● A13 to A19 → used for decoding to generate chip select

● Memory chip selection for the problem

● Problem 2: Design an interface between 8086 CPU and 2 chips of 16K x 8
EPROM and 2 chips of 32K x 8 RAM. Select the starting address of EPROM
suitably. The RAM address must start from at 00000H.

● Solution: After reset , the processor starts from FFFF0H. This address
must lie in the EPROM.

● Memory map