Sum-of-Products Form

• A Sum-of-products (SOP) expression will appear

as two or more AND terms ORed together.
 Sum-of-Products Form
• The product-of-sums (POS) form consists of
two or more OR terms (sums) ANDed
together.
 Simplifying Logic Circuits
• The circuits shown provide the same output
– Circuit (b) is clearly less complex.

Logic circuits can be simplified using

Boolean algebra and Karnaugh mapping.
 Algebraic Simplification
• Place the expression in SOP form by applying
DeMorgan’s theorems and multiplying terms.
• Check the SOP form for common factors.
– Factoring where possible should eliminate one
or more terms.
 Algebraic Simplification
Simplify the logic circuit shown.

The first step is to determine the expression for the output: z = ABC + AB • (A C)

Once the expression

is determined, break
down large inverter
signs by DeMorgan’s
theorems & multiply
out all terms.
 Algebraic Simplification
Simplify the logic circuit shown.

Factoring—the first & third terms above have

AC in common, which can be factored out:

Since B + B = 1, then…

Factor out A, which results in…

Algebraic Simplification
Simplifed logic circuit.

z = A(C + B)
Designing Combinational Logic Circuits
• To solve any logic design problem:
– Interpret the problem and set up its truth table.
– Write the AND (product) term for each case where output = 1.
– Combine the terms in SOP form.
– Simplify the output expression if possible.
– Implement the circuit for the final, simplified expression.

Circuit that
produces a 1
output only for
the A = 0, B = 1
condition.
Designing Combinational Logic Circuits
An AND gate with appropriate inputs can be used to
produce a HIGH output for a specific set of input levels.
Designing Combinational Logic Circuits
Each set of input conditions that is to produce a
1 output is implemented by a separate AND gate.
The AND outputs are ORed to produce the final output.
Designing Combinational Logic Circuits
Truth table for a 3-input circuit.

AND terms for each

case where output is 1.

Digital Systems: Principles

and Applications, 11/e
Ronald J. Tocci, Neal S.
Widmer, Gregory L. Moss
Designing Combinational Logic Circuits
Design a logic circuit with three inputs, A, B, and C.
Output to be HIGH only when a majority inputs are HIGH.

AND terms for each

Truth table. case where output is 1.

SOP expression for the output:

Designing Combinational Logic Circuits
Design a logic circuit with three inputs, A, B, and C.
Output to be HIGH only when a majority inputs are HIGH.
Simplified output expression:

Implementing the
circuit after factoring:

Since the expression is in SOP form, the circuit is a

group of AND gates, working into a single OR gate,
 Karnaugh Maps (K-Maps)

• A visual way to simplify logic expressions

• It gives the most simplified form of the
expression
 Rules to obtain the most simplified expression
•Simplification of logic expression using Boolean
algebra is awkward because:
–it lacks specific rules to predict the most suitable next
step in the simplification process
–it is difficult to determine whether the simplest form
has been achieved.
•A Karnaugh map is a graphical method used to
obtained the most simplified form of an expression
in a standard form (Sum-of-Products or Product-of-
Sums).
•The simplest form of an expression is the one that
has the minimum number of terms with the least
number of literals (variables) in each term.
•By simplifying an expression to the one that uses
 Three-Variable K-Maps
f   (0,4)  B C f   (4,5)  A B f   (0,1,4,5)  B f   (0,1,2,3)  A

BC BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1

1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0

f   (0,4)  A C f   (4,6)  A C f   (0,2)  A C f   (0,2,4,6)  C

BC BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
0 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1
1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1
 Three-Variable K-Map Examples
BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
0 1 0 1 1 1 0 1 1

1 1 1 1 1 1 1 1 1 1

BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
0 1 0 1 1 1 0

1 1 1 1 1 1 1 1
 Four-Variable K-Maps
CD CD CD CD
00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10
AB AB AB AB
00 1 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0

01 0 0 0 0 01 0 1 0 0 01 0 0 0 0 01 1 0 0 1

11 0 0 0 0 11 0 1 0 0 11 0 1 1 0 11 0 0 0 0

10 1 0 0 0 10 0 0 0 0 10 0 0 0 0 10 0 0 0 0

f   (5,13)  B  C  D f   (13,15)  A  B  D f   (4,6)  A  B  D

f   (0,8)  B  C  D

CD CD CD CD
00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10
AB AB AB AB
00 0 0 1 1 00 0 0 0 0 00 0 0 1 1 00 1 0 0 1

01 0 0 1 1 01 1 0 0 1 01 0 0 0 0 01 0 0 0 0

11 0 0 0 0 11 1 0 0 1 11 0 0 0 0 11 0 0 0 0

10 0 0 0 0 10 0 0 0 0 10 0 0 1 1 10 1 0 0 1

f   (2,3,6,7)  A  C f   (4,6,12,14)  B  D f   (2,3,10,11)  B  C f   (0,2,8,10)  B  D

 Four-Variable K-Maps
CD CD CD CD
00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10
AB AB AB AB
00 0 0 0 0 00 0 0 1 0 00 1 0 1 0 00 0 1 0 1

01 1 1 1 1 01 0 0 1 0 01 0 1 0 1 01 1 0 1 0

11 0 0 0 0 11 0 0 1 0 11 1 0 1 0 11 0 1 0 1

10 0 0 0 0 10 0 0 1 0 10 0 1 0 1 10 1 0 1 0

f   (0, 3,5, 6, 9,10,12,15) f   (1, 2, 4, 7,8,11,13,14)

f   (4,5, 6, 7)  A  B f   (3,7,11,15)  C  D
f  A  B C D f  A  B C D

CD CD CD CD
00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10
AB AB AB AB
00 0 1 1 0 00 1 0 0 1 00 0 0 0 0 00 1 1 1 1

01 0 1 1 0 01 1 0 0 1 01 1 1 1 1 01 0 0 0 0

11 0 1 1 0 11 1 0 0 1 11 1 1 1 1 11 0 0 0 0

10 0 1 1 0 10 1 0 0 1 10 0 0 0 0 10 1 1 1 1

f   (1, 3,5, 7, 9,11,13,15) f   (0,2,4,6,8,10,12,14) f   (4,5,6,7,12,13,14,15) f   (0,1,2,3,8,9,10,11)

fD f D f B f B
 Four-Variable K-Maps Examples
CD CD CD
AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10
00 1 1 1 00 1 1 1 00
01 1 1 1 01 1 01 1 1 1
11 1 1 1 11 11 1 1 1

10 1 1 10 1 1 1 10 1

CD CD CD
AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10
00 1 1 00 00
01 1 1 1 1 01 01
11 1 1 1 11 11
10 1 10 10
 Four-Variable K-Maps Examples
CD CD CD
00 01 11 10 00 01 11 10 00 01 11 10
AB AB AB
00 00 00

01 01 01

11 11 11

10 10 10

CD CD CD
00 01 11 10 00 01 11 10 00 01 11 10
AB AB AB
00 00 00

01 01 01

11 11 11

10 10 10
 Four-Variable K-Maps Examples

CD CD CD
00 01 11 10 00 01 11 10 00 01 11 10
AB AB AB
00 00 00

01 01 01

11 11 11

10 10 10

CD CD CD
00 01 11 10 00 01 11 10 00 01 11 10
AB AB AB
00 00 00

01 01 01

11 11 11

10 10 10
 Design of combinational digital circuits
• Steps to design a combinational digital circuit:
– From the problem statement derive the truth table
– From the truth table derive the unsimplified logic expression
– Simplify the logic expression
– From the simplified expression draw the logic circuit
• Example: Design a 3-input (A,B,C) digital circuit that will give at its output (X) a logic 1
only if the binary number formed at the input has more ones than zeros.

Inputs Output
A B C X X   (3, 5, 6, 7)
0 0 0 0 0
1 0 0 1 0 X
BC
2 0 1 0 0 A 00 01 11 10
3 0 1 1 1 0 0 0 1 0
4 1 0 0 0 1 0 1 1 1
5 1 0 1 1
6 1 1 0 1
7 1 1 1 1 X  AC  AB  BC
A B C
 Design of combinational digital circuits (Cont.)
• Example: Design a 4-input (A,B,C,D) digital circuit that will give at its output (X) a
logic 1 only if the binary number formed at the input is between 2 and 9 (including).

Inputs Output
A B C D X X   (2,3,4,5,6 ,7,8,9)
0 0 0 0 0 0
1 0 0 0 1 0 X
2 0 0 1 0 1 CD
3 0 0 1 1 1 AB 00 01 11 10
4 0 1 0 0 1 00 0 0 1 1 Same
5 0 1 0 1 1
01 1 1 1 1
6 0 1 1 0 1
7 0 1 1 1 1 11 0 0 0 0
8 1 0 0 0 1 10 1 1 0 0
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0 X  AC  AB  A B C
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0 A B C D X
 Design of combinational digital circuits (Example)
• Example: Design a 4-input (A,B,C,D) digital circuit that will give at its output (X) a logic
1 only if there more ones than zeros in the binary number formed at the input.

Inputs Output
X=
A B C D
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0 CD
AB 00 01 11 10
3 0 0 1 1
4 0 1 0 0 00
5 0 1 0 1 01
6 0 1 1 0
7 0 1 1 1 11
8 1 0 0 0 10
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
X=
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1 A B C D X X
 Karnaugh Map Method
• A graphical method of simplifying logic equations
or truth tables—also called a K map.
• Theoretically can be used for any number of input
variables—practically limited to 5 or 6 variables.

The truth table values are placed in the K map.

Shown here is a two-variable map.

Digital Systems: Principles

and Applications, 11/e
Ronald J. Tocci, Neal S.
Widmer, Gregory L. Moss
Karnaugh Map Method
Four-variable K-Map.

Adjacent K map square differ in only one

variable both horizontally and vertically.
A SOP expression can be obtained by
ORing all squares that contain a 1.
 Karnaugh Map Method
Looping 1s in adjacent groups of 2, 4, or 8
will result in further simplification.

Looping groups of 2 (Pairs)

Groups of 4 Groups of 8
(Quads) (Octets)
 Karnaugh Map Method
• When the largest possible groups have been
looped, only the common terms are placed
in the final expression.
– Looping may also be wrapped between top,
bottom, and sides.
 Karnaugh Map Method
• Complete K map simplification process:
– Construct the K map, place 1s as indicated in the truth table.
– Loop 1s that are not adjacent to any other 1s.
– Loop 1s that are in pairs.
– Loop 1s in octets even if they have already been looped.
– Loop quads that have one or more 1s not already looped.
– Loop any pairs necessary to include 1st not already looped.
– Form the OR sum of terms generated by each loop.

When a variable appears in both complemented and

uncomplemented form within a loop, that variable
is eliminated from the expression.

Variables that are the same for all squares of

the loop must appear in the final expression.
 Exclusive OR and Exclusive NOR
• The exclusive OR (XOR) produces a HIGH
output whenever the two inputs are at
opposite levels.
Exclusive OR and Exclusive NOR
Exclusive OR circuit and truth table.

Output expression: x = AB + AB
This circuit produces a HIGH output whenever
the two inputs are at opposite levels.
 Exclusive OR and Exclusive NOR
Traditional XOR gate symbol.

An XOR gate has only two inputs, combined so that x = AB + AB.

A shorthand way indicate the XOR output expression is: x = A B.
…where the symbol represents the XOR gate operation.
Output is HIGH only when the two inputs are at different levels.

Quad XOR chips containing four XOR gates.

74LS86 Quad XOR (TTL family)
74C86 Quad XOR (CMOS family)
74HC86 Quad XOR (high-speed CMOS)
 Exclusive OR and Exclusive NOR
• The exclusive NOR (XNOR) produces a HIGH
output whenever the two inputs are at the
same level.
– XOR and XNOR outputs are opposite.
Exclusive OR and Exclusive NOR
Exclusive NOR circuit and truth table.

Output expression: x = AB + AB
XNOR produces a HIGH output whenever
the two inputs are at the same levels.
 Exclusive OR and Exclusive NOR
Traditional XNOR gate symbol.

An XNOR gate has only two inputs, combined so that x = AB + AB.

A shorthand way indicate the XOR output expression is: x = A B.
XNOR represents inverse of the XOR operation.
Output is HIGH only when the two inputs are at the same level.

Quad XNOR chips with four XNOR gates.

74LS266 Quad XNOR (TTL family)
74C266 Quad XOR (CMOS)
74HC266 Quad XOR (high-speed CMOS)
Exclusive OR and Exclusive NOR

Truth table and circuit

for detecting equality of
two-bit binary numbers.
Exclusive OR and Exclusive NOR

How an XNOR gate may

be used to simplify circuit
implementation.