Microprocessor and Microcontroller in

Industrial Systems

D32T001M20
RISC AND CISC
Understanding the risc and cisc architectures
 Definition
Reduced instruction set computing, or RISC, is a CPU design strategy
based on the insight that simplified instruction set (as opposed to a
complex set) provides higher performance when combined with a
microprocessor architecture capable of executing those instructions
using fewer microprocessor cycles per instruction.

A computer based on this strategy is a reduced instruction set computer,

also called RISC. The opposing architecture is called complex instruction
set computing, i.e. CISC.
 Microprocessor Architecture
Architecture of Central Processing Unit drives its
working ability from the instruction set
architecture upon which it is designed. Instruction
Set Architecture can be defined as an interface to
allow easy communication between the
programmer and the hardware.
 CPU Design
Processor design is the design engineering task of creating a
microprocessor, a component of computer hardware.
The design process involves choosing an instruction set.
 Addressing Modes
Addressing Modes: Addressing modes are the manner in the data is
accessed. Depending upon the type of instruction applied, addressing
modes are of various types such as direct mode where straight data is
accessed or indirect mode where the location of the data is accessed.
 Instruction Set
Instruction Set: It is a group of
instructions that can be given to the
computer. These instructions direct
the computer in terms of data
manipulation. A typical instruction
consists of two parts: Opcode and
Operand.
Opcode or operational code is the
instruction applied. It can be loading
data, storing data etc.
Operand is the memory register or
data upon which instruction is
applied.
The Scenario
Multiplying Two Numbers in Memory
On the right is a diagram representing the storage
scheme for a generic computer. The main memory
is divided into locations numbered from (row) 1:
(column) 1 to (row) 6: (column) 4. The execution
unit is responsible for carrying out all
computations. However, the execution unit can
only operate on data that has been loaded into
one of the six registers (A, B, C, D, E, or F). Let's say
we want to find the product of two numbers - one
stored in location 2:3 and another stored in
location 5:2 - and then store the product back in
the location 2:3.
CISC Approach
The primary goal of CISC architecture is to complete a
task in as few lines of assembly as possible. This is
achieved by building processor hardware that is
capable of understanding and executing a series of
operations. For this task, a CISC processor would come
with a specific instruction (we'll call it "MULT").

When executed, this instruction loads the two values

into separate registers, multiplies the operands in the
execution unit, and then stores the product in the
appropriate register. Thus, the entire task of
multiplying two numbers can be completed with one
instruction:

MULT 2:3, 5:2

CISC Approach
•MULT is what is known as a "complex instruction." It
operates directly on the computer's memory banks and
does not require the programmer to explicitly call any
loading or storing functions. It closely resembles a
command in a higher level language. For instance, if we
let "x" represent the value of 2:3 and "y" represent the
value of 5:2, then this command is identical to the C
statement "a = x * y."

•One of the primary advantages of this system is that the

compiler has to do very little work to translate a high-
level language statement into assembly. Because the
length of the code is relatively short, very little RAM is
required to store instructions. The emphasis is put on
building complex instructions directly into the hardware.
RISC Approach
RISC processors only use simple instructions that can be
executed within one clock cycle. Thus, the "MULT" command
described above could be divided into three separate
commands: "LOAD," which moves data from the memory bank
to a register, "PROD," which finds the product of two operands
located within the registers, and "STORE," which moves data
from a register to the memory banks. In order to perform the
exact series of steps described in the CISC approach, a
programmer would need to code four lines of assembly:

LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3,
RISC Approach
This may seem like a much less efficient way of
completing the operation.

Consider:

1) there are more lines of code,

2) more RAM is needed to store the assembly level

instructions.

3) The compiler must also perform more work to convert

a high-level language statement into code of this form.
RISC Approach
However, the RISC strategy also brings some very
important advantages.

Because each instruction requires only one clock cycle to

execute, the entire program will execute in approximately
the same amount of time as the multi-cycle "MULT"
command.

These RISC "reduced instructions" require less transistors

of hardware space than the complex instructions, leaving
more room for general purpose registers. Because all of
the instructions execute in a uniform amount of time (i.e.
one clock), pipelining is possible.
RISC Approach
Separating the "LOAD" and "STORE" instructions actually
reduces the amount of work that the computer must
perform.

After a CISC-style "MULT" command is executed, the

processor automatically erases the registers. If one of the
operands needs to be used for another computation, the
processor must re-load the data from the memory bank
into a register.

In RISC, the operand will remain in the register until

another value is loaded in its place.
Defining RISC
RISC?
RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that utilizes a small,
highly-optimized set of instructions, rather than a more specialized set of instructions often found in
other types of architectures.
The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early 80s. The IBM
801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a similar philosophy which has
become known as RISC. Certain design features have been characteristic of most RISC processors:

1. one cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. This is due to
the optimization of each instruction on the CPU and a technique called pipelining;

2. pipelining: a technique that allows for simultaneous execution of parts, or stages, of instructions to
more efficiently process instructions;

3. large number of registers: the RISC design philosophy generally incorporates a larger number of
registers to prevent in large amounts of interactions with memory
ARM
What is ARM?
ARM is a family of instruction set architectures
for computer processors based on a reduced
instruction set computing (RISC) architecture
developed by British company ARM Holdings.
CISC VS RISC
 The performance equation
The following equation is commonly used for expressing a computer's
performance ability:

The CISC approach attempts to minimize the number of instructions per

program, sacrificing the number of cycles per instruction. RISC does the
opposite, reducing the cycles per instruction at the cost of the number of
instructions per program.
 What do you think?
RISC OR CISC?
a) Decide for yourself which architecture is superior and why
b) Find out what Apple and Intel used – What influenced their choices?
c) What architecture would work best with smart phones and tablets?
Thank You…