CS2 TPS-2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
/ Cha pte r(2) l_n str uc tio n Se t and
Programming of 8085
I Probable marks : 43
I
Scope of the syllabus :-
• Addressing modes in 8085
.. fi:?gramming model of 8085
• Instruction Set and
• Programming of 8085
• Study of instruction set :
instructions.
• Data transfer, Arithmetic, Logic,' Branching, Stack, 1/0 and machin e control
• Assembly language program ming based on instructions.
addressing
Q. 1 What do you mean by addressing modes of a microprocessor ? Enlist the
modes in 8085.
Ans.:
ying one operands
(1) · Addressing mode of a IlllLa.1processor is the variou s forma ts of specif
r or it can
(direc_tly, indirectly etc). The operan d can be data (8 or 16 bit), addres s, registe
be implicit.
uses one
(2) Every microproces-'lr has its own set of instruc tions. Each of these instruc tions
of the addres sing modes. ·
:
(3) The microprocessor 8085 has five addres sing mode_s, which are given below
i) Direct addres sing
ii) · Register addres sing
iii) Immed iate addres sing
iv) Register indirect addres sing
v) Implie d addres sing
Q. 2 Explain any two addressing modes in 8085. OR

Explain all addressing modes in 8085. OR
·
Explain direct and implic. it addressing mode s of 8085 m1cro processor.
OR
&dJ
. · . . used ·n 80 m · mwe,all•~
E lai·n any tw0
What are differ ent addres sing modes 85 1 1croprocessor 1. xp ~
of them with a suitab le example. tMEii• ►l•iM•ii•ki#IJ■ i•&l4mPl11H1jl!UP'
visit tpspoint.com for all chapters

TPS CL)mputer Science - l] 2-2 lnslrnct10n S(,t and Programming of 8Ck~5
Ans. : (I) Direct addressing mode : (Jul 201i, March 2018

(1) In direct add ressin& the address appears after ovrode of instruction in program
memorY.
(2) The address of operand is specified within the instruction.
(3) The instructions using direct addressing m ode are three b~ie instructions. B~i e 1 is
opcode of instruction, Byte 2 is lower order address an d By te 3 is high order
address.
(-1) For e.g. LDA 9FF}:H
i.e. This instruction loads accumulator with content of memory location 9FFF H.
ITT) Register addressing mode : (March 200-1)
(1) In register addressing mode, the source operanas are general p urpose registers
whose name is specified within the instruction.
a (2) These instructions are single byte instructions.
(3) All actions occur within the CPU.
(4) For e.g. MOVA, B.
i.e. This instruction transfers the content of registe r B to accumulator \dthou t
modifying the e:ontent of B.
(Ill) Immediate addressing mode : (~larch201S,Julv1019)
(1) In immediate addressing the data appears immediately after opcod e of instruction
in program memory.
(2) In these instructions the actual data is specified ·within the instruction .
(3) These operations are specified "\-\'1th either 2 or 3 byte instructions.
For e.g. ADI 05H
(4)
i.e. this instruction adds immediate data OS H to the content of accumulah)r. Th~
result is stored in accumulator.
(IV) Register indirect addressing mode : (Oct. '.:?005, 2009; Julv 2017
(1) In register indirect addressing the
content of register p a ir p oints tc, the ,11.i d r'=':S:S ,)t
the operand.
(2) A register pair (H-L pair) is specified for addressing 16-bit addre~ . of nw nHm·
location.
(3) These .a re gene rally 1-byte instruction.
(4) For e.g. ADO M
i.e. this ins truction w ill ad d the rnntent of m e rnNv lnc1t ilm w hl):-t' clli.dre:S:- i:-
stored in H-L pair to the content of a(cumulMor.
(V) Implicit addressing mode : tME:i@
(1) In this type of ins h·urt ions, ge ner<1lly npt>rc\n\.i is rh)t sre,:ifil"i. ,,·ithin the "in:--trn,·th,n
and it is p red eterm in t>d.
(2) Gene rally the operan d is acCLlmuld tor.
(3) Mos ~of the logicn l g rou p instruc tinm bt:'long h, th 1:,; ,hld rl'~"in~ nH,,fr

--
TI'S Compu tt>r SciM,<'t? - U 2-3 ln~tru ction Set 1:1nd Progra mm ing nf 808.s
{4) These ar,e single by te instruc tions.

(S) All actions occur within the C PU .
(6) Fo r e .g . 0..iA
Le . this instr uctmn will complement the conte11 t of accumulator . Here, the actual
opera nd is not specified in the instruction , but is predetermin ed (accumulato r). The
resul t is stored in accumulato r .
Q. 3 Explain register indirect. and immediate addressing modes in case of 8085

m icmp l'O<'essor with the help of s'Uitable examples.
(Oct. 03,07,0S; June lb; Jul · 17, March 20:?0)
Ans.: n Register indirect addressing mode:
1) Regist-er indirect instructions reference memory using the contents of a register pair to
pom t the add ress of the operand .
2) A regis ter pair {H-L pair) is specified for addressing 16-bit address of memory loca tion.
3) These are generally l byt~ instructions.
4) Fo r .example :
ADD M (add memory)
This instruction ad,d s the con ten ts of the accumulator to the contents of memory pointed
to by tht? ad dress in the HL register pair.
Accumulator 1 1 1 1 1 l 1 1 / l OOOO OOO O! Accumulator

c--A~D~D~M~=:>
D.ata cr1ie.1:nory - - - - - -
405\l ...,0_ 0 _0_0_0_0_0_1_ ~ 1°1 1 1~1 1 1-1 1 1-11 1
S Z AC P CY
~ L Fla gs
-->;btt>r f
--- ~-'(.)_ __}_ _SO _
H Lpl'(.li r
&-fort!' O JX' I atmn After operation
ln th t> ,;t,·en t'X<lmpl~, the H L register pai r points to mem ory loca tion 4050 H . T he data in
th .i s Jo canon (t(X)U OOOl )i 11, Hum .tddt>d to tne n mt~nts o f the accumulator (l l 11 111 l )i.
Tile su1n IS Sh.l r ~ in a<.'Cu.mulato r and appropria t.e flags are also set dnd reset based on
the .re51uJt.
U) J.m:med i~te addrt>i~h1g mod~ ; tl\l.11l"h :!OOI.))
1) Jn 1mrn00Ja f~ addres.~uig tlw d a ta a pp~ars immediately aft.er opcode of ins tnicti(,n i.n
p rograui rnl"mtJr}'
2) ·n11."lt' clfC >;.:-nH,l ll r 2 or ) r yt<: iH'-lrucfoms.

TPS Computer Science - II 2-4 Instruction Set and Programming of 8085
3) For example ADI 08 H
Accumulator ~
·~ O O 1o
I OO ~ ---~~ / ~ L_o_o_Q_!__0_l_Q_O_...I Accumulato r
CADI08=:>
Opcode
Program
m emory C6H ~ 1°1°1 -11 1-111-1°1
4050 0000 1000 S Z AC P CY
data Flags
Before operation After operation
In the example, MPU fetches the opcode (C6) from program memory and after decoding
it. MPU finds the immediate data (0000 lOOO)z in the next consecutive program memory
location. This data is added to the contents of the accumulator and result is placed in the
accumulator.
Q. 4 What do you understand by register indirect and implicit addressing modes ?
Explain with suitable example. List the names of any four instructions which make
accumulator content clear. . «•IIJunijj
Ans. : Register indirect addressing : Please refer to Q. 3 (I).
Implicit addressing: Please refer to Q. 3 (II).
Following four instructions make accumulator content clear :
(1) ANI OOH (2) XRA A · (3) SUB A (4) MVI A, OOH
Q. 5 What are the different ways of clearing Accumulator (A = OOH) in single

instruction? (:\larch :?.011, :?.017)
Ans : (i) MVI A, OOH (ii) SUB A
(iii) XRA A (iv) ANIOOH
Q. 6 What are the groups in which instructions in 8085 are classified? i•S•M
Ans. : The instructions in 8085 can be classified into following five groups, depending upon
their function :
1) Data transfer group 2) Arithmetic group
3) Logical group 4) Branching group
5) Machine control group
1) Data Transfer Group :
This group of instruction copies data from a location called source to another location
called a destination without modifying the content of source. These instructions move
data between registers or between memory locations and regjs ters. For eg. MOV,
MVletc.
2) Arithmetic Group :
The instruction of this group performs arithmetic operations such as ad dition,
subtraction, increment or decrement etc. on d ata in registers or memory . For eg. ADD,
SUU, fNR, OCR etc.

·n >S Compute r Sdence - II 2-5 Instruction Set and Programming of 8085
3) Logical Group :
The logical group instructions perform logical operations such as AND, OR, XOR,
complement etc. generally with the accumulator.
4) Branching Group :
The branching group instructions allow programmer to change the sequence of
execution of program either conditionally or unconditionally.
For e.g. JMP, JC, JZ etc.
5) Machine Control Group : · .
These instructions control machine operations such as Halt, Interrupt
For e.g. NOP, HLT.
Q. 7 How instructions of 8085 are grouped according to its len.gth ?

Ans. : Instructions of microprocessor 8085 are grouped into three groups according to its
length as follows:-
(i) One byte instructions (One word)
(ii) Two byte instructions (Two word)
(iii) Three·byte instructions (Three word)
(i) One byte instructions :
These instructio~ are having opcode and operand both in m~e byte. These require only
one byte to store m memory. - · - - •· · .
I OPCODE & OPERAND j 1 Byte
e.g. MOV A BJ ADD B etc.
(ii) Two byte instructions :
These instru~ons require two bytes to store in memory. First byte gives opcode and
second byte gives operand, which is generally 8-bit immediate data.
OPCODE First Byte
Data/ Address Second Byte
e.g. SUI 35 H, ADI FF H etc.
(iii) Three byte instructions:
These instructions require three bytes to store . _ . .
second and third_byte gives 16_b't dd f m memory. Firs t byte giv es opcode and
1 a ress o mem - 1 • . .- .
Note that second byte gives lower O d ddr ory ocation or 16-bit 1mmed1ate data.
order address/ data byte. r er a ess / d ata byte and third b y te gives higher
_ P_C_O_D_E_ ____J First Byte

r-O
Low order 8-bit Second byte
of address / d ata
High order 8-bit Third byte
of addre1;s/ data
-- ----- .
e.g. LOA BAFF H,
LXI H, FFE3 H

TPS Comput er Science - II 2-6 Instruction Set and Program ming of 8085
Q. 8 Explain the followi ng instructions of 8085 microprocessor with suitable example.

(a) SPHL (b) PCHL (Mar. 02, 2010, 03, Oct. 08. 10)
Ans. : (a) SPHL: [Copy Hand L register to SP]
Format [SPL] r LL]
[SPtt] r [HJ
Addressing Register addressing
Group Machin~ control group [stack operation]
Bytes 1 byte
Flag None
Comment : · This instruction copies the content of register L into lower order byte
of
stack pointer and the content of register H into. higher order byte stack pointer . The
content of registers Hand Lare not affected. This instruction is used for initializing the
stack pointer.
Example Let, [H] = 25 Hand [L] = 59 H
Instruction : SPHL
After execution : [SP] = 2559 H
(b) PCHL :
[LOAD PROGRAM COUNTER WITH HL REGISTER PAIR CONTENT]
GMetil•I@
Format [PCtt] ~ [H]
[PCL] f-- [L]
Addressing Register addressing
Group Branching group
Bytes 1 byte
Flag None
Comme nt : This instruction moves the content of register H to higher order byte
of program
counter and the content of register L to lower order byte of program counter.
This instruction is equivalent to one byte unconditional jump instruction, with jump
address stored in H-L pair. ,
Example : Let, [H] =25 Hand [L] = 39 H
Instruction : PCHL
After execution : [PC] = 2539 H
After execution of PCHL instruction, 'the control will be transferred to memory location
2539 H.
Q. 9 Explain PCHL Instruction of micro-processor 8085 and justify the stateme nt that
it is
equival ent to 3 byte uncond itional jump instruct ion. !•tJl@j t)j
Ans. : For only Explanation of PHCL Please refer Q. B(b), Pg. No. 2-6.
In PCHL progra~ _counter is loas{eq \,\{i U1 _memol'y ad_dress stored in HL _pair,.. ln JMP
a1dr_ess y r~gram _c~unter is loaded_ with memory address specified in instruction.
Workin g of both instruct ion is same i.e. load PC ,-vith 1nemory -address hence PCI IL
is
equival ent to uncondi tiona l jump

V, lO
Ans. ; 1 (1111 11 , u1 11 11 1111

, 'Pl\11'1.I Pt ll,,1 \ 111 ,,11 ,;~1
Tl it· lf'~tnw t,N \,., w!ul'I, P ll\•W ll!ii:1 I\\ d11111} w tlit>
(U
~11v , allC< t I.ho l•r,,nd 11n
~ 11\ltl lrw tl11.11~
11.,1 10 1, 111
h ,, ,,11 ll\!i tl' \u ·tit111-. 11111 •1,1iditi11,1.1I Mid 11111;!11
tq~ •~ ,1t 11
(~) Th e," ' a r,· two t1~111 rd1 11 1111, tt lrll u,i ,11· 111\ u 11r
itl, ,n ,~ l~ll ltld tn \'l'lldilllll!AI
UIW(\t\,llti.,,11 " l h~l \"tfv1 , \\\l ~'( \\ld 1 t 1l'<\ IWh in h 1 Iii.' v \ r.w 11l'f; d
1
111 11 11 1
c nnl l1t' wlw tlw 1 th1
ttw fl <lf:. l1< h·~trd tv dd
1\~ o t)' f'( ll'!l \)l 1w.1\~• t,,~ti \ll'lt<•I\~ ,11r ,,~ fnlh 1\V/i
() ) lJr, cx,1,dHh 1nr,l 111mp :
ln~tru ('tmn JMl' '°'drlr
t, orm at It\ <- tt1Mr 1
}
lt11n1( di,1h·· ,uk ht ¥i~J inp.

11
A dd re~itn~
G n,u p ttr,1nchln~ r:r, 111p
Hytr9 ,'\ by h'S
Fla1,; No-tw
-1 r1
tm l l:i tr,m ~fo rt't·d 1nH .'\1.ndJthm ally to llw 1rw111urv l~ 1,·MliH1 1 whor
Co mm ent : Th,• ~)n
,n.
add r~,s 111o sptx-lfit'd in tht- imi tructh
(4} ConcHtio na l It.imp : v If ,tw
..t:.t.!J}dl th 111 l.1 tru, 1. l'lit:•
ctk ,n~ . thr• /m np 1~ tak N, nnl
1n com:Utinnal jum p in~tru
dlth,n~ fU't 1 ltk Hlvt•n lwlow .
ron d1tl,,n ,d jum p in~tructlon~ nnd con
i) JN Z n('fdr Jum p on not i t•ro (Z ~ 0)
1i) JZ "'dctr Jump cil\ ~,•ft,
(Z 1) i;;
iii) )NC ad dr lum p on O\\ t Cfl fr)' (Cy • 0)

iv) IC dd dr Jump <)n c;arry (Cy ,."' I)
v) JPO ndd r Jum p on od d pnrlty (I' ,. 0)
vi) JPE add r Jump 01, t·v,•n p{l dty (l' I)
vii) JJ> f.ti..i d r Jum p vn plu~ (S ~ 0)
Jump l'n l'\\inu:-1 (~ rz I)
vi ii) JM odd r k d 111 llt1•
is ~i1tif1fi td. tlw n onl y tlw ,1ddn·1-1N pf u"l1.•mn1y lt,\.' (ttk,n ~p, ,df
1f the condHJOn
in!» lrU <.' tiP n ii- lo,1J ~ I in PW81'ilOI vount(•r.
be "'al led nm dit ion all y ,rnd lrn

cor,dltlon"llY ? Oi l
Q. H Ho w a s ub rou tin e C'ilf i
mlcropriu·,·tHun·. Ul l
f1CpJaln CAI.L Jttslru cUon of Rotty; JU lm H\ l~
lal11 \11 \\'0 lhll tlnt Hd - -~l\d \'()O
flih\i,DIIIQiilGBiliF\iCMDI~.
o( 808 5 mk rop ,·or~11t:1or, oxp
In caHe~
h-..
ins tru r taons wHh t;uHable <·Mltltp
An s. ; i,
,,f 111 ·<,}1.rtl1n lt11-1 tn11 ·th,11 H w rllh 'n ~•l'J'n t'uWh•' tnu11 tlw p\,,1
(.l) A L-1 ufir(lut lt w 1~ ~t ~ho rf ~rt ro~ fo tll ,
riu form 1 flltH llti n th. it or4 11r:-. 1'••1w ,11t-dl v in llw m uin p
•
pw ~rt1rn to

iPS Computer Science - U 2-8 Instruction Set and Programming of &J85
(2) A subroutine can be called by two ways :

(a) Unconditional call :
Instruction CALLaddT
Format [[SP] -1) f-1 Pett l
[[SP] - 2] f- [ PCL ]
[SP] f- [SP] - 2
[PC} f- addr
Addressing Immediate addressing
Group Branching group
Bytes 3 bytes
Comment CALL instruction is used to call a subroutine unconditionally. Before the
control is transferred to the subroutine, the address of next instruction to be executed of
the main program is stored in the stack. The content of SP are decremented by 2 Then,
the program jumps to the subroutine whose starting address is specified in the
instruction.
(b) Conditional Call:
In conditional call, the subroutine is called only if the condition is satisfied. In

conditional call, following J)rocedure is followed, if the condition is true.
Format : · [[SP] - 1] f- [ PCH]
[[SP] - 2] f-- [ PCL]
[SP] f- [SP] - 2
[PC] f- addr
The conditional call instructions and conditions are as listed below :
i) CC addr Call if carry (Cy= 1)
ii) CNC addr Call if no carry (Cy = 0)
iii) CZ addr Call if zero (Z = 1)
iv) CNZaddr Call if no zero (Z = 0)
v) CP addr Call if plus (S = 0)
vi) CM addr Call if minus (S = 1)
vii) CPOaddr Call if odd parity (P = 0)
viii) CPE addr Call if even parity (P = 1)
Q. 12 Explain return procedure in RET instruction.

Ans. :
(l ) The RET instructions are used to return from s ubroutine to main program.
(2) The return instruction bi written at the end of the s ubroutine indicatin~ end of
subrou ti nf'.

(3) lnstr nction : RET
[PCt ) +--- [[SP JJ, [PCHJ r- [ fSP} .£. lJ
Fom lat
[SPJ f-- {SPJ + 2
Add ress ing Regi ster i:.ncli.rect
Gro up Bran chin g grou p
Byte s 1 byte
se addr ess is specified in stac k pot-..::::-
Com men t: The cont ent of memory loca tion, \.,,-ho
coun ter. The cont ent of tlte memory !ocz::.::-
are mo~·ed to the lowe r orde r byte of prog ram
SP mov ed to the high er orde r byte of p::og z:
who se addr es.s is one :nore than the cont ent of
eme nted by 2.
counter. The cont ents of stac k poin ter are incr
instr uctio n is exec uted \-'-T uch~ ~
(4) On com pleti ng the exec utio n of subr outi ne the RET
ucti on follo-..ving CAL L instr ucri.on. :-
back the stac k cont ents i.e. addr esse s of the instr
mai n prog ram .
prog ram coun ter. Thu s the cont rol retu rns into
Q. 13 Exp lain the use of stac k and stac k pain ter regi
ster in Inte l 8085 . 49 ii
Ans .:
is used for tem pora ry stor age of En..:a:-:-
1) The stac k is a part of Read / Writ e mem ory that
.
inior ma tion duri ng the exec utio n of a prog ram
te resu lts and the retu rn add.i..'""ESS fr: 2-..'-c'
2) The b inar y info rmat ion is basi cally the imm edia
o f subr outi ne prog ram s:
micr opro cess or.
3) The stac k is shar ed by the prog ram mer and the
ents of a regi steI pair by usin g F~.'~-:'.-:
4) The prog ram mer can stor e and retri eve the cont
and POP instr uctio ns.
es the cont ents of the pn~ ram C\.)t:f i:-£
5} Simi larly, the micr opro cess or auto mati cally stor
whe n subr outi ne is calle d.
ial mem o.rv poin ter ~ ca.He--.1 :.:~
6J The stac k is imp leme nted with the help of spec ·
0
s tack poin ter.

[>LJ iing P USH and POP oper ation stac k
poin ter reg i~r gi\·e s the add r~ of rnc.:n'-":·.
71
.
whe n? the informat ion is to be stor ed or to be read
.::,tac k pt.,' inte r is cnlJe d as top oi ::;tac.k.
8) The memo ry J.oca hon curr ently provided by
be co.n tent of accumul at.o r atttr

Q . 14 Acc umu Ltlo r contains data 2A H . Wha t will
ex.e-cutio n of each ins truc tion inde pend entl y?
(i ) C MA (ji) At\ l 05 H ( i ii) STC
{iJ C M A : ( \,rn pltm ent Hu- J ff um uL1

tur
Ans . :
&fort' t:•u>(utiu n I.•\J -::: 2.J\ H :.:: 1) 0 1 U l O l O
fn~tr·uclt on C~I 4.
fA J ::. l I O 1 l ) t l) } --' l ).5 f I
j(' f \ } - n ::; H

iPS Compute r Science - II 2-10 ln.struction Set and Programming of 8085
(ii) ANI 05 H AND immediate da ta 05 H with [A]

Before execution [A] = 2A H = 0010101 0
Instruction AN105H
2AH = 00 10 10 10
AND 05 H = 00000101
0 0 0 0 0 0 0 0 = 00 H
i.e. (A] = 00 H
(iii) STC : Set carry
Before execution: [A]= 2AH
Instruction : STC ·
This instruction will only set carry flag to 1 and contents of accumulator will remain as it
is.
After execution : [A]= 2AH
i.e. [A]= 2AH and [Cy]= 1
Q. 15 Accumulator contains data E3H. What will be the content of accumulator after
stepwise execution of each of following instructions ?
•&•0M*
t1
(i) ANI 58 H (ii) RRC (iii) CMA
Ans. : (i) ANI 58 H : Logically ANDed 58 H with [A]
Before execution: [A] = E3H '
Instruction : ANI 58 H
E3 H = 11100011
AND 58 H = 01011000
01000000 =40H
After execution [A] = 40 H
(ii) RRC : Rotate accumulator right by one bit.
Before execution : [A]= 40 H = 010000000
Instruction : RRC
After execution [A]= 0 0 100 0 0 0 = 20 H
and [Cy ] = 0 H
[A] = 20 H
(iii) CMA : Complement the contents of accumula tor
Before execution : (A J = 20 H :::: 0 0 1 00 0 0 0
In struction : CMA
After execution : (AJ = 1 1 0 1 1 11 1 :;:; DFH ' A] :::: DFH
1
Q. 16 The accumulator in 8085 contains the data BSH and register B contains dat.i 40 H.
What will be the content of accum u lator after execution of each of tht! following
instructions independe ntl y ? (l\1,ufh 1002)
(a) RLC (b) ORI 2'J H (d AN A B

•t _an
u_ct_i<_)n_s_·c_ gramm ing of
_d_ Pr_o.:::_
_T_P_s _c_o_m_p_u_te_r_S_c_ic_n_ce_-_1_1_ __ _ __ _ _ _2_-'1_1_ _ ._ _1n_s_tr_ -- 8v0,
-----..___ - '-J
Ans.:
(a) RLC: Rotate accum ulator left throug h carry.
Before execu tion: (A] = B8H = 10111000
Instru ction : RLC
After execu tion: (A]= 0 1 1 1 0 0 0 1 = 71 H
:. [Al= 71 Hand [Cy]= 1 H
(b) ORI 29 H: Logica lly ORed 29 H with [A]
Before execu tion: [A)= B8H = 10111000
Instru ction ORI 29 H
B8H = 1 0 1 1 1 0 0 0
OR 29 H = 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 = B9H
After execut ion : [A] = B9H
(c) ANA B: Logically AND [Reg. B] with [A]
Before execut ion: [A]= B8H = 1011 100 0
[Reg. B] = 40 H = 0 1 0 0 0 0 0 0
Instruc tion : ANA B
1011 1000
AND 0100 0000
0000 0000 =00H
After execut ion:
[A] = 00 H
execution of
Q. 17 The accumulator contains the data A4H. What will be its conten ts after
follow ing instructions indepe ndentl y. iiiBNiS!
i) XRI 08H ii) CMA iii) SUB A
Ans.:
Accumulator = A4 H
= 1010 0100
0 XRI 08 H:
Logically Ex-ORed 08H with conten ts of accum ulator.
Before execut ion: [A)= A4 H
Instru ction: XRI 08 H
A4 H = 10100100
XOR OB H = 0 0 0 010 0 O
1010 1100
= ACH
After execu tion: lAJ = ACH

llJS C()mputt"r Science - l1 2-1 2 Instruction Set and Programming of 8085
ii) CMA :
Complement the accumulator
Before execution : [A] = A4 H
=10100100 '
Instruction : CMA
After execution :
[A] = 01011011
= SBH
i.e. [A] = SB H
iii} SUB A:
Subtract accumulator from itseU.
Before execution : [A] = A4 H
Instruction : SUB A
[A] : A4 H =10100100
2's complement of A4 = 0 1 0 111 0 0
+ [A] : A4 = 1 0 1 0 0 1 0 0
IT] 00000000
complement carry .J..
0 00000000
Result [A] = 00 H
Q. 18 The accumulator of 8085 contains data 43H. What will be its co.n tents after the
execution of follo~g instructions independently ?
(i) CMA (ii) ANI 09H (iii) JNR A

Niii
Ans.:
H CMA : Before executions accumulator content is :
[A} = 43 H
::;: 01000011
CMA insbuction compft,m(:nt~ th(• contents of accLHl\lllator dnd result i~ ston-'\i in tht>
accumulator itself
IA] = J O1 l 1 1 00
= BCH
Aftt>r execu t10n : IAJ= BCI l

TPS Comp uter Scien ce• JI 2-13 Instru ction Set and Progr ammi ng of 8085
conte nts of accum ulato r.

ii) ANI 09H : This instru ction logica lly AND ed 09H with the
Before execu tion: [A] = 43 H
= 0100 0011
[A) = 43H = 0 1 0 0 0 0 1 1
AND 09H = 0 0 O O 1 0 0 1
0 0 0 0 0 0 0 1 = 01 ~
:. After execu tion : [Al = OlH
ulato r by one and result
iii) INR A : This instru ction incre ment s the conte nts of accum
store d in the accum ulato r itself.
Befor e execu tion:
[Al = 43 H = o 1 o O O O 1.1
[A] = 43 H :a: 0 1 0 0 0 0 11
+ 0 lH - 0 0 0 0 0 0 0 1
0100 0100 =44 H
After execu tion : [A] = 44 H
data 45 H and register E
Q. 19 The accumulator of 8085 microprocessor conta ins the
mula tor after execution of
contains the data 7BH. What will be the conte nt of ~ccu
each of follow ing instructions indep ende ntly ? (Mar . 04, 2011)
conte nts of regis ter ·E i.e. 7BH with
Ans. : (i) XRA E. : This instru ction logic ally EX-O Red the
the conte nts of accum ulato r i.e. 45H.
Befor:e execu tion :
[A] = 45H = 01000101
[E] = 7BH = 0 11110 1 1
Then , 45H = 010 001 01
XOR 7BH = 0 1111011
0 0 1 1 1 1 1 0 = 3E H
So after execu tion of instru ction I
{A) = 3E H
(ii) ADI C5H :
This instru ction adds the data CSH to th e con tent of accu mula tor i.e. 45H.
(AJ ; 451-f = 0 1 00 0 1 O 1
+CSH == ll...OOO 1 O 1
~
0 0 0 0 1 O 1 o = OA H
After execut-ion, fA] ::; Oooo 1 o 1 0
= OAH

TP5 Computer Science - 11 2-14 Instruction Set and Programming of 8085
(iii) ORI 58H:

Thjs instruction logically ORed the data SBH with the content of accumulator i.e. 45H.
[A]= 45H = 01000101
OR SBH = 01011011
0 1 0 1 1 1 1 1 = SF H
After execution, [A]= 0 101 1 111 = SF H
Q. 20 Accumulator of 8085 contains data 56 H. What will be the contents after the
execution of following instruction independently. ('.\larch 200'.i)
(i) CMA (ii) ANI ACH (iii) INR A

Ans. : [A] = 56H = 0 1 0 1 0 1 1 0
(i) CMA:
This instruction complements the contents of accumulator and result is placed
in accumulator itself.
[A]= 56 H = 01010110
After execution : CMA
[A] = 101 0 1 0 0 1 = A9H
:. [A] = A9H
(ii) ANI ACH :
This instruction is logically ANDed ACH with the contents of accumulator.

Before execution :
[A] = 56 H = 0 1 0 1 0 11 0
Data = ACH = 10 101100
[A) = 56 H = 0 1 0 1 0 11 0
AND ACH = 10101100
00000100 =04H
After execution : [A) =04H
(iii) INR A : This instruction increments the c<;mtents of accumulatqr by one and result
stored in the accumulator itself.
Before execution :
[A] = 56 H = 0 10101 1 0
[A] = 56 H = 0 101011 0
+ 01H = 0 0 0 0 0 0 U1
0 1 0 1 0 l 1 l = 57 H
After execution : IA] = 57 H

TPS Computer Science - II 2-15 Instruction Set and Programming of
8085
Q. 21 If ACC contains data BCH, register C contains ADH. What will be the content of
accumulator after execution of each of the following iruJtructions independently?
(i) SUB C (ii) CMA (iii) XRA C -
Ans. : Accumulator = BCH = 1 O1111 0 O
(i) SUB C : Subtract contents of register C from accumulator.
Before execution :
[A] = BCH = 1 0 111 1 0 0 .
[C] = ADH = 1 0 1 0 1 1 0 1
Instruction : SUB C
[A]= BCH = 1 0 11 1 1 0 0
[C] =ADH = 10101101

2's complement of [C] , = 01010011
[A] = 1 0 1111 0 0
+ 2's complement of [C] = 01010011
CD 00001111
complement carry J.
[QJ 000001111
Result [A] = 0 0 0 0 1111 =OF H

(ii ) CMA: Complement the accumulator.
Before execution :
[A] = BCH = 101111 0 O
Instruction : CMA
After execution :
[AJ = o1 o·ooo11 = 43 H
Result= [A] = 43H
( iii) XRA C : Logically Ex-ORed contents of C with contents of accumulator ..
Before execution : [A] = BCH
Instruction XRA C
[AJ = BCH = 1 0 1 1 11 Oo
XOR [CJ =ADH · = 1 01 O1 1 O1
000 1 0001
= llH
· After execution: [A] ::: 11 H

TPS Computer Science - 11 lm trnrti11n ~•d <'\ lid l' n,~1'•111111111,~ 111 tilt!1't
Q. 22 The accumulator of 8085 proces..!lor et>nt•ins delta tUU-.t and regll ter fl c-uf\l'flin- iJ~ ft ,
What will be the content of a{-eumulator after e~~rution nf e4tr h of the f'ollowh1 0
instruction indepe.ndentJy ? l~l.111 h J tll ll
(i) ORI FOH (ii) ANA B um XtU O.FH
Ans.:
Accu:mulator A= B 8 H =10111000
(i) ORI F0 H - logically OR ed FO H with [A]
B8 H = 10 11 1000
ORI F0 H = 11 11 0000
11 11 1000 = F 8 H
After execution [A]= F 8 H
(ii) ANA B - Logically AND (Reg B) with [A]
B8 H = 10 11 1000
AND B-44 H = 0100 0100
00 00 0000 = 00 H
After execution [A]= 00 H
(iii) XRI OF H - Logically Ex-ored OF H with [A]
BBH = 10111000
XRI OF H = 00001111
10 11 0111 = B 7 H
After execution [A] = B7 H
Q. 23 If Accumulator -Contains the Data 23H and B Register Contains 35H. What will bt
the contents of Accumulator. After execution of each of the following instruction
independently : . fMMiJljj
(i) XRA (ii) ANI FOH (iii) CPI OAH
Ans.:
A = 23 H = ·0010 0011
B = 35 H = 0011 0101
(i) XRA B - Ex.ored reg. B with contents of A.
23 H = 0010 0011
XOR with 35 H = 0011 0101
= 00010110
---
1 6
A = 16H

of 8085
2-17 Ins truc tion Set and Pro gra mm ing
TPS Co mp ute r Science - Il
wit h con ten ts of A.

(ii) AN IFO H - Log ica lly AN D FO H
FO = 1111 0000
AN D 23 = 0010 0011
0010 0000
2 0
A= 20 H
A reg.
(ill ) CP IOA H - Co mp are OA H wit h
A = 23 Hf - Bef ore exe cut ion
ain s
Wh ile com pai rin g Ac rum ula tor rem
Un cha nge d hen ce A = _2 3 H
G9 H. Wh at are the
and Re gis ter B con ten ts are
Accumulator contents are B81{
Q. 24
tor an aF iag reg iste r aft er exe cut ion of ins ~c tio ns AN A B . .... ,
contents of Accumula t
. (;\l arc h 20] . I)
SU B B independenUy. '
Ans.:
(A) = BBH = 10111000
(B) = C9 H = 11001001
ula tor
'1) ANAB : Logically AN D wit h Ac cum
10. ll 1000
110 010 01
~q~q1lOO0
A 88H '=
Fla gs ➔ S =1, Z =0, AC = 0, P ~
i,
CY = O
cum ula tor
(2) SUB B : Sub tra ct B Reg. fro m Ac
B = llOO 1001
l's com ple me nt of B = 0011 011
0
+ 1 + 1
2's com ple me nt of B 0011 0111
Ad d A wit h 2's com ple me nt of B
001 101 11
+ 1011 1000
@) 111 011 11
Co mp lem ent car ry i

OJ 111 011 11
Res ult ➔ A = EF H
Fla gs - , S = 1, Z = 0, AC == o, p = 0,
CY = 1

TI'S Computer Science - U 2-18 Instruction Set and Programming of 8085
Q. 25 For the following instructions, write the addressing mode, instruction group and
the length of,the rnstruction (in terms of bytes). (if)a•fijj
(i) LHLD ABCDH (ii) LDAX B
(iii) LXI H, BABAH (iv) SPHL

Ans. : (i) LHLD ABCDH: Pleue refer Appendix I (9).
(ii) LDAX B: Please refer Appendix I (11).
(iii) LXI H, BABAH: Please refer Append.ix I (6).
(iv) SPHL: Please refer Appendix V (6).
Q . 26 The following instructions are intended to clear ten (10) memory locations starting
from th-e memory address 0009H. Explain why a large memory bl-0ek will be erased
or cleared and the program will stay in an infinite loop. Nfli•@l
LXI H, 0009H
LoopMVI M,OOH
DCXH
JNZLoop
HLT
Ans.:
(1) In given loop, large memory block will be erased or cleared and the program will stay in
an infinite loop.
(2) In the given loop, the sequence is repeated by the instruction JNZ Gump on No zero)
until the count becomes zero. However, the instruction DCX does not set the zero flag.
Therefore, the instruction JNZ would be unable to recognize when the count has
reached zero and the program would remain in a continuous loop.
Q. 27 Explain following instructions of 8085 microprocessor. 1\1.m.:h 200~)

{i) ORI data (ii) STAX rp (iii) LHLD addr
Ans. : Refer Appendix
Q. 28 What ue different addressing modes ? Which type of addressin_g mode is used for
following instructions ? MIQ@jj
(i) XCHG (ii) XRI (iii) SUB M (iv) CMC
Am. : Ref-erQ.l and appendix.
Q. 29 ldecntify the addressing modes of the following instructions and justify your
.mswer. W LOA 2000 H (ii) LDAX B (iii) STC (iv) ADC 0
Ant. : Ri:~e~~ ~ . 0 : to_~nd addressing mode and re.fer Q 2_to justif221nsw!::r·
Q. 30 Describe fo llowing instTuctfons of 8085 microprocessor. ~ 4ii111iiiiii@
iiiiiw!i,
ti} XCHG (ii) RA R (i ii) ADC R
Ans. : Ple~ refer appendix.

TPS Computer Science - 11 2-19 lnstn1ction Set and Programming f
o Boss
Q. 31 Explain the following instructions of 8085 microprocessor with suitable e '
(i) RLC (ii) DAA
Ans. : Refer appendix.
Q. 32 ~xplain the following instructions. IMBi@iJ}ifjj,i
h) PCHL (ii) PUSH PSW (iii) OUT (iv) NOP ~
Q. 33 Explain the addressing modes of following instructions: ~
(i) LOA (ii) STAX - (iii) CMA ~
i) Group I (7) ii) Group I (12) iii) Group ID (17)
Q. 34 Accumulator contains 45H [(A)= 451, Register E contains data 3BH [(E) =3B] w;;--
the contents of Accumulator after execution of following instructions
independently : i) SUB E ii) XRA E iii) RRC iv) MOV E,A (Oct. 2009, 20lOJ
Ans: a) [A] = 45 H = 0100 0101
[E] = 3BH = 0011 1011
i) SUB E : Subtract contents of register E from accumulator.
[A] = 45 H =0100 QlOl
[E] = 3BH = 0011 1011
2' s complement of [E]
= l's complement of [E] + 1_
= 11000100+1
= 11000101
[A] = 0 1 0 .O O 1 0 -1
2's complement of [E] = 11000101
=ill
00001010
complement carry [QJ O O O O 1 0 1 0
:. Result [A] = 0 0 0 0 101 0
= OAH
ii) XRA E: Logically Ex-ORed contents of E with contents of accumulator.
[A] = 45 H = 0 1000 1 0 1
XOR [E] = 3BH = 0 011 1011
01111110 = 7E H
Result : {A] = 7EH
iii) RRC : Rotate accumulator right by one bit
Before execution :
[AJ = 45 H =0 1 0 0 0 1 0 1
After execution :
[Al = 1 o1 ooO1 o
= A2H
[A] = A2H
iv) Mov E, A : Copy accumulator contents to register E.
Before execution :
[A] = 45 H =0 1 0 0 0 1 O1
lEJ = 3BH = OO11 1 O1 1

TPS Computer Science - II 2-20 Instruction Set and Programming of 8085
After execution :
[A] = 45 H = 0 1 0 0 0 1 0 1
[E] = 45 H = 0 1 0 0 0 1 0 1
[A] = 45H
Q. 35 The accumulator contains 05H and register B contains 08H. What will be the effect of
'SUB B' instruction on flags ? Explain it with diagram. (March 2010)
Ans-: ACC = 05 H = 0000 0101
B = 08 H = 0000 1000
After execution of SUB B _
Accumulator contains 2's compliment of magnitude of result
i.e. ACC = 11111101 = FDH
Mentioning the status of carry flag
Q. 36 Differentiate DAD and ADD Instruction of 8085 Micro-Processor
lt•&►·Mill
Ans.:
DAD ADD
1. In this lll!3truction contents of register In this instruction register r or content of
pair rp are added to the contents of memory location whose address is stored in
HL pair & result is placed in register H-L pair is added with content of
Hand L. accumulator and result is placed in
accumulator.
2. Only carry flags in affected. All flags are affected.
3. Register pairs BC, DE are used. Only register A, B, C, D, H, E, Lare used.
4. Used for 16 bit addition Used for 8 bit addition
Q. 37
.
Differentiate between PUSH and POP. CllNP111 NI
Ans.:
PUSH . POP
1. The contents of the higher order register The contents of the memory location
of register pair rp are moved to memory whose address is specified by the stack
location whose address is one less than pointer are moved to low order register
the content of stack pointer. of register pair rp.
2. The contents of the low order register of The contents of the memory location,
register pair rp are moved to the whose address is one more than the
memory location whose address is two content of stack pointer are moved to
less than the content of stack pointer. high order register of register pair rp.
3. In this instruction, stack pointer is In this instruction, stack pointer is
decremented by two. incremented by two.
4. Let [SP] = D01 5, [BJ = 25 H and Let [SP] = 2001 H
(CJ= 55 H (2001] = 10 H, [2002] =20 H
After execution of PUSH B After execu tion of POP H
ID014J = 25 H [H] ;:: 20H, [L] = lOH
[D013] = SSH and [SP] = 0013 H [SPJ =2003 H

2-21
TPS Com pu ter Science - U
a-ftff ~ tin,:
dat a B7h . Wh at wil l be its con t.enh
Q . 38 The acc um ula tor of 8085 con tain s
nde ntly ?
of the fo1 Jow ing ins truc tion s ind epe
CM A (iii) AN I f3 H
S PC -
(i) OR I 58 H ( ii)
An_s. :
Acc umula tor = B7H
= 10 1 1 0 11 1
(i ) O RI 58 H
Log jcal ly OR ed 58H " i th [A)
0 11 l
Be fore Exe cuti on [A] = B7H =10 11
B7H = 1 0 1 1 0 1 1 l
OR SSH = 0 10 1 100 0
l l l l l l l l =FF H
After ext.,>eution fAl = FFH

um ula tor
(ii l CMA - Com plem ent the con ten ts of acc
1 10 11 1
Bef ore executJon fA J =87H = 10
inst ruct ion CM A

After executi on fA J =OI 001 (XX) =48
H
A!\.1 E3H ~ Logically Mr oed E.3H wit

h [AJ
(w )
0 111
Before ex{>('.U tion fA J = B7H =1 0 l 1
lnstl'UCWm - Az"-.1E3H
B7H = 1 0 1 1 01 11
OH f '.\H = 1 1 10 00 l I
1 0 1 0 0 0 l 1 = A3H
Aite-r exn "Utmn f A J = AJH --

- - -- . ·· -· -- -- -- -- - ----- - -- - - full o'4 .r:.
t-fftt'>t o n its con ten t if
h.at wil l bl" the
Q . )q Th. - .cc um \lla tor ron aus 3CH , w
m s.tn id ,on s ilN n tt1.tted ind ep~ nde

ntl) ?
@d
h iJ RR C (Hi ) MO V 8 , A
W Al\' l 05H
An s, . ,, - 1l H . • 'll l H \.l
1
H . i.A..~ lult i, ~w 1_,,; H htt h l'\\.-.' Ufll U.hl tll?

(l! " ' ' ' ()!i.
1
~'"' H tir11.u 1<'l

rP5 Computer Science - II 2-22 Instruction Set and Programming of 8085
(ii) RRC - Rotate Accumulator Right

A= 3C H = 00111100
After Execution of RRC A will contain 00011110 = lE H
(iii) MOV B, A - Move contents of A reg in B register
Accumulator contents remain unchanged i.e. B & A will be 3C H
Q. 40 The accumulator in 8085 Micro-processor contains th~ data 78H and register D
contains data 33H. What will be the content of accumulator after execution of each
of the following instructions independently. lt•HIDOd)
(i) SUB D · (ii) AND D (iii) CMA
Ans,:
Accumulator = A =78 H = 0111 1111
D = 33H = 0011 0011
(ii) SUB D (Subtract D from Accumulator)
is complement of D = 1100 1100
' + 1 + 1
2's Complement of D = 1100 1101

A =
= 0111 11 11
111 11 11
= (] 01001100
Complement carry @] 01001100

Result = A = 4 CH
(ii) AND D: Logically and with accumulator
A= 78 H = 0111 1111
AND = 0011 0011
0011 0011
A = 33H
(iii) CMA : Complement Accumulator
A = 78 H = 0111 1111
After CMA, A = 1000 0000
A ~ 80H
Q.41 The accumulator in 8085 microprocfssor contains data 71H register E contains data
39H. What will be the contents of accumulator in Hexadecimal after execution of the
( l\ t.1rd1 2tl I :"I
following instructions independently ?
(i) ADD E (ii) ORA E (iii) RRC
Ans.: (i) AAH, (ii) 79H, (iii) B8H

TPS Computer Science - TI 2-23 Instructi' on Set an d p rogramming of 8085
the conten
Q. 42 Accumulator contai ns data A4H and Register E contains data 69H write
ing instructt ts
of Accum ulator in hex digits after execution of each of the follow
indep enden tly :
Ans.:
(i) ANA E = 20 H ·(ii) CMP E = A4H (iii) ORA = EDH
will be the
Q. 43 The· registers A and c of 8085 contains the cJata E2H and 47H. What
the following
conten ts of Accumulator in Hex digits after execution of each of
instru ctions indep enden tly?
IMfil@lfM!)
(i) SUB C (ii) XRA C (iii) ADD C
Ans.:
(i) SUB C = 9BH
(ii) XRA C = ASH
(iii) . ADD C = 29 H Cy = 1
will be the
Q. 44 Accumulator contain data 45H and register B contain data 82H. What
y.
result in Accumulator after execution of each instruction indepe ndentl
m XRA B <m ADI 54H (iii) NI sm aw"d
Ans.:
(i) XRA B Accumulator = 45H
regB = 82H
Ace = 45H = 0100 0101
B = 82H = 1000 001,0
1100 0111
B 7
XRAB = B7H
(ii) ADI 54H Ace= 45H = 0100 0101
54H = 54H = 0101 0100
-1001 1001
9 9
ADI54H = 99H
(iii) ANI 57H Ace = 45H = 0100 0101
57H = 57H = 0lDl 0111
0100 0101
4 5
ANI57H = 45H

2-24 Instruction Set and Program ming of BOBS
TFS Computer Science - II
Q. 45 Write the appropriate instructions for the followin g task:

(i) Load accumulator from B register.
(ii) Comple ment the accumulator
(iii) Add OlH with the accumulator
(iv) Store the content of accumulator at the memory location address ed by the BC
register pa1r.]
(v) Clear the accumulator.
Ans.:
(i) Loa~ accumulator from B register - LDAXB /MOVA , B
(ii) Complement the accumulator - CMA
(iii) Add OlH with the accumulator - ADI0lH
(iv) Store the content of accumulator at - STAXB
the memory location address ed by
the BC register pair.] .
(v) Clear the accumulator. .:.. XRA A I SUB A I MVI A, 00
(!\larch 2019)
Q. 46 Give any two instructions of followin g address ing modes :
(i) Immedi ate (ii) Register Indirect (iii) Registe r
Ans.:
(i) Immediate - ADI 05H I MVI B, 04H
(ii) Register Indirect - ADD M / MOV M, D
(iii) Register - MOV A, B / ADD C
Q. 47 The accumulator contains AA H and register C contains 55 H. What will be the .

contents of accumulator if following instructions are executed indepen dently ?
(i) CMP C (ii) ANA C
(iii) ORA C (iv) SUB C (March 2019)
Ans.:
(i) CMPC It's CMP means subtraction of A-C. But after subtrac tion Accumu lator content
remains unchang ed. Means after CMPC.
A= AAH
(ii) ANAC
A = AAH = 1010 1010
C = SSH = 0101 0101
logical AND operation = 0000 0000
.. ANAC = OOH Accumu lator Content

2-25 Instruction Set and Prog ramrn·
TPS Computer Science - II
- - - - - -- - - - - - -- -- - - - - - -- --- =- - · II1g of ~ .
- - ~
(iii) ORAC
A = AA H = 1010 1010
C = SSH = 0101 0101
logical OR ope rati on = 1111 1111

.. OR AC = FFH Accumulator Con tent
(iv) SUBC
A = AA H = 1010 1010
0101 0101
C = SSH =
1010 1010 l's com plem ent
l Add 1
+
1010 1011 2's com plem ent
1010 1010 l's no.
0101 :. SUB C = SSH

-- --
Substraction
-- -- -- -- -- -:
0 0101
-- -= -~ foll
--
owi
= -- -- -- -- -- -
ng.
and rew rite the
Q. 48 Select the correct alternative
gro up of inst ruct ion set of 8085.
1 ............ instruction belongs to data transfer
(ii) CMA (iii) JMP (iv) POP
(i) LHLD
Ans. : (i) LHLD
RRC of 8085.
2. .. .......... flag is affected by the instruction
(ii) parity (iii) carr y (iv) all
(i) zero
Ans .: (iii) carry
not affect any flag .... ....... .
3. Which of the following instruction does
(ii) RAR (iii) STC (iv) PCHL
(i) ADD
Ans .: (iv) PCHL
ress ing mod e.
4. Instruction STAX belongs to ............ add
(i) Direct (ii) Register (iii) Register indi rect · (iv) Imm edia te
Ans. : (iii) Register indirect
ster.
5. In 8085 ............ instruction affects flag regi
(iii) MVI A, data (iv) CPI data
(i) MO V B, A (ii) CMA
Ans . : (iv) CPI data
up
6. Ins truction PCHL belongs to· ....... ..... gro
(i) Arithmetic operation
(ii) Logical operation
(iii) Data tran sfer
(iv) Branching ope rati on
Aris. : (iv) Branching ope rati on
7. LXI H, add r is ........ .... byte instruction. Wfihid
(i) 1 (ii) 2 (iii) 3 (iv) 4
Ans . : (iii) 3

Welcome to tpspoint
Assembly Language Programing ( PART 1)
All lessons of Computer Science 1& 2 pdf are given in the website www.tpspoint.com
https://tpspoint.com/
Welcome to tpspoint.com
Thank You for visiting
tpspoint.com
Welcome to tpspoint.com
Thank You for visiting
tpspoint.com
f Ch ap ter (3) Introduction to INTEL
X-86 Family
Probable marks : 4
Scop e of the syllabus :-
• - Intro ducti on to adva nced micro proce ssors
utes of the X-86 farn.il
• Intro ducti on to X-86 famil y and study of majo r attrib
proce ssors .
• Prog ramm ing mode l of X-86 famil y of micro proce ssors .
Q. 1 Draw a block diagr am of 8086 and expla in it.

Ans. : .-------------- -------------- ----------
' BJU~ - - -....
1) As show n in the block diagr am, Mem ory
Interfa ce
the 8086 C.P.U. is divid ed into
Contro l Bus
two indep ende nt funct ional parts :
1. Bus•I nterfa ce Unit (B.I.U.)
2. Exec ution Unit (E.U.)
6
2) The B.I.U . funct ional part conta ins
E.S. 5 Instruct ion:
queu e, segm ent regis ters and • c.s. 4 stream
I
I
byte I
instru ction point er. ss 3

queue I
3) Exec ution unit (E.U.) conta ins D.S. 2

IP
flag regist er, gener al purpo se regis ters, ,
stack point er regis ter and other
I
r--- - --- ------ ----··'
point ers, index regis ters.
AH AL
BH BL
CH CL
DH DL
SP
BP
SI
DI
-------------------------------------
Fig. 3.1

fPS Computer Science - II 3-2 Intro. to INTEL X-86 Family
Q. 2 Explain in brief 8086 architecture.

;\ns,: The 8086 C.P.U. is divided into two independe nt functional parts:
I) Bus Interface Unit (B.I.U.)
II) Execution Unit (E.U.)
Bus Interface Unit (B.I.U.):
J.
The B.1.U. sends address, fetches .instruction from memory,_ reads data from
ports/mem o:y and writes data to ports/mem ory. In other word, B.I.U. handles transfer
of data and address on buses for execution unit. It consists of following parts :
(a) Queue: To speed-up execution of program, B.I.U. fetches 6 instruction bytes ahead
of time from memory and stores them for E.U. in the FIFO register, called queue.
(b) Segment registers : B.I.U. contains following 16-bit segment registers :
i) Extra segment (E.S.)
ii) Code segment (C.S.)
iii) _ Stack segment (S.S.)
iv) Data segment (D$.)
These 16-bit segment registers are used to store 16-bit starting address of memory
segment.
(c) Instruction pointer (I.P.) : The code segm~nt (C.S.) register holds 16-bit starting
address of segment, from which B.I.U. is fetching instruction code bytes. The IP
register holds 16-bit address of next coc.i.e byte within code segment.
II. Execution Unit (E.U.) :
· Execution unit of 8086 tells B.1.U. where t.9 fetch instruction s or data, decodes instruction
and executes them. The following sections describe functional part ~f E.U.:
(a) Flag register: Flag is a flip-flop, which indicate some condition. The 8086 has 16-bit
flag register with 9-active flags.
(b) General purpose registers: 8086 has 8 general purpose registers, labelled AH, AL,
BH, BL, CH, CL, DH and DL. These registers can be used individual ly for
temporary storage of 8-bit data. The AL register is also called as accumulat or.
These registers in certain pairs can be used as 16-bit registers. These pairs are AH
and AL (AX), BH and BL (BX), CH and CL (CX), DH and DL (DX).
(c) Stack pointer : The 8086 allows us to set 64KB of rnernqry as stack. The 16-bit
starting address of stack is stored in stack pointer. ,
Q. 3 Explain any two microproc essors in X-86 family in brief.

OR Explain the following microproc essors in Intel's X-86 family. (Oct. 04; March 18)
Ans.:
I) 8086:
1) 8086 is a 16-bit microproce&sor, introduced by INTEL in 1978.
2) It was designed to be used as C.P.U. in microcomp uter system. It's A.LU., internal
registers can work with 16 binary bits at a time.

TPS Compute r Science - II · Intro. to INTEL X-8 6 F
~ ,
3) 8086 has 16-bit data bus and 20-bit address bus, so that it can address a ph ~~
w
memory of2 =1048576 =1 M Byte memory locations.
4) The least significa nt 8 bits of address bus are passed on same eight lines as that 01
data bus. This bus is known as multiplex ed bus.
5) In 8086, words are stored in two consecutive bytes. If_ first b_Yte of ~ord has even
address, then 8086 can read it in single operation. Else, it reqmres two operations,
· 6) This processo r supports multiplic ation and division operation s.
7) The 80186 is an improve d version of 8086. In addition to 16-bit C.P.U., it has
program mable peripher al·(I/O) devices integrate d in same package. Instruction set
o{ 80186 is superset of instructio n set of 8086.
II) 80286:
· 1) 80286 is a 16-bit micrqprocessor, introduc ed in 1982. This advanced version of 8086
is specially designed to be used as a C.P.U. in multiuse r/multita sking operating
systems.
2) 80286 has 16-bit data bus and 24-bit address bus~
3) In 1984, IBM introduc ed PC/ AT (Personal Comput er/ Advance d Technology)
version of its PC using 80286.
4) 286 was having real and protected modes of operation. In real mode, the processor
can address only 1 Mbyte of memory, whereas in protected mode it can address
16 Mbytes of memory.
5) Another new feature was the ability to work upto 1 Gbyte of virtual memory and
yet another feature was added hardwar e multitask ing.
6) The program written for 8086 can run on 80286, operating in its real address mode.
III) 80386: w
1) The INTEL's 80386 is a 32-bit microprocessor introduc ed in 1985.
2) . 80386 is a logical extension of 80286. It is more highly pipelined .
3) The instruction set of 80386 is a superset of other members of 8086 family.
4) It has 32-bit data bus and 32-bit nonmulti plexed address bus. It can address a
physical memory of 232 i.e.' 4 Gbytes. The 80386 memory managem ent allows it to
address 246 or 64 Tbytes.
5) The 386 can be operated in one of the following memory managem ent modes :
i) Paged mode
ii) Non-pag ed mode.
6) When oper~ted in pa?ed rn?de, the 386 switches the paging tmit then after t~~
11
segment unit. T~e ?agmg umt allows memory pages of 4 kB each to be swapped
and out from disk. In non-page d mode, memory managem ent unit operates very
similar to the 286. ·
7) Virtual addresse s are represented with selected compone nts and an offsel
compone nt as they are with 80286.

rP5 CoJTlputer Science - II 3-4 Intro . to INTE L X-86 Fam ily
~
JV) 80486:
6 32 intro duce d in 1989 .
1) Intel's 8048 is a -bit micr opro cess or. It was
2) It has 32-bit addr ess bus and 32-bit data b us.
h contains a fast built-in, a mat h
3) The 486 is basi cally a larg e integ ral circuit whic
.U.), and ,~1-8 kbyt~~cach e mem ory.
coprocessor, a mem ory man agem ent unit (M.M
4) 80486 has DX and SX versions.
ion does not have on chip -num eric
5) All 486 proc esso rs have 32-bit data bus. SX vers
coprocessor.
its faster clock spee ds, inte rnal pipe
6) The 486 achi eves its high spee d oper atio n from
uctio n set com puti ng (RISC) to spee d
line d arch itect ure and the use of redu ced instr
up the inte rnal microcode.
doub le and tripl e clock spee d.
7) 486 also has 486 DX2 and 486 DX4 versions, with
V) Pentium or 80586 : OR
esso r. (Ma r.03 , 2011 , Oct. 04)
Explain the mai n feat ures of a pen tium proc
in 1993.
1) Pent ium is a 64 bit micr opro cess or, intro duce d
The use of supe r scal ar arch itec ture
2) It has 64 bit data bus and 32-bit addr ess bus.
lets the pen tium proc ess mor e than
inco rpor ates a dual -pip e line d processor, whi ch
one instr ucti on per clock cycle.
chip is also a feat ure desi gned to
3) The addi tion both of data and code caches on
imp rove proc essi ng spee d.
in pen tium is calle d the bran ch
4) A new adva nced com puti ng tech niqu e used
gues s whe re the next _inst ruct ion
pred ictio n, the pen tium mak es an educ ated
This prev ents inst ruct ion cache from
following a cond ition al instr ucti on will be.
runn ing dry duri ng cond ition al instr ucti ons.
that it can perf orm data tran sfer s with
5) The pen tium has 64-bit data bus. This mea ns
with a 32 bit data bus.
an exte rnal dev ice twice as fast as a proces~or
(Oct. 2011; l\far ch 2019 )
Q. 4 Com pare 8048 6 and 80586.
Ans.:
-
8048 6 8058 6 (Pen tium I)
Sr. No.
1. It is 32 bit Microp roce ssor . It is 64 bit mic ropr ocessor.
'--
2. It's oper atin g spee d - 25 to 50 MH z It has 50 - 100 MH z operatin g spee d .

It has 3~_b ytes cach e mem ory. It has_8 ,kby.tes cach e memory.
-- 4. 3.
-- 5.
It has ex ternal mat h co-p rocessor.
It w as · evol ved in 1989-SX and
l991 -DX vers ion .
It has Inte rnal mat h co-p roce ssor.
It was evolved in 1993 .
-

TPS Compu ter Science -Il 3-5 Intro. to INTEL X-s6 F
Q. 5
~
tffifi@"'-
Compa re any four attribu tes of 486 DX with Pentiu m Processor.
Ans.:
Attrib utes 80486 DX Pentiu m
Data bus It is 32 bit microprocessor. It is 64 bit microprocessor. ----
Opera ting speed (MHz) Clock frequency 25-50.MHz Clock frequency 50 - 100 rnB--;
Introd uction date It was evolve d in 1991. It was evolve d in 1993. ---
~
Instruc tion Cache It has 32 bytes memory. It has 8 Kbytes memor y.
Q. 6 Compa re any four attributes of 80386 & Pentiu m processor. (Oct. 12; March 191
Ans.:
Attrib ute 80386 Pentium -
It is 32 bit microprocessor It is 64 bit microprocesso;-
(1)
(2)
Data bus
Instruc tion cache It has 16 byte cache memor y It has 8 Kbyte cache -
(3) Data cache It's data cache is 256 bytes It's data cache is 8 Kbyte
(4) Math co-processor It has externa l co-processor It has interna l co-processor
(5) Interna l data word size Word size is 16 bit
.I. ,:'• •
Word size is 32 bits
(6) Introdu ction data It was introd ~ced u{ 1985 Introdu ced in 1993
(7) Operat ing speed in MHz 16-50M Hz 50-lO0 MHz
List the advanced microprocessors of INTEL X-86 family and mention
three
Q. 7
\ attributes of any one of them. ( 1 ~§ _" 1
lt•EN D
Ans.: List of INTEL X-86 microprocessors family :
;:::::=-_:::=-4 !,,-- J~ 3~
• 8086
' ' ) ( ' ) ('
-➔ L.t --"-J _"l , l ,
• 80286
4·- L1 \(,
~
•
•
80386
,80486 -
'
• INTEL PENTIUM I
'
,
• PENTI UMil
• PENTIUM III
PENTIUM IV
•
For w riting attributes of anyone of above please refer Q. No. 3.
Explain the advantages of the pentiu m processor with respect to the
followin g
Q. 8
featur es:
1) Dual pipelin ing 2) On-chip caches
9
3) Branch predic tion 4) 64-bit data bus (Mar. 06, 10, 20, Oct. 08, 10, Jul t l
Ans.:
1) Dua] pipelin ing : .,
m processor,
The use of super scalar architecture incorporates a dual-p ipelini ng in pentiu
a
which lets pentiu m to process more than one instruction per clo~k cycle and achieve
high level of p erform ance.

I~
iPS Computer Science · Il Intro. to [\.,- m_ \.--&> f unuty
2) On-chip caches:
The data and ccx:ie on-chip caches 'improves the processing speed oi the pentium
processor.
3) Branch prediction : MftiNm)
i) The advantage of branch prediction is that, using it, the pentium makes ;m
educated guess where the next instruction follo\ving a conditional instruction will
be.
ii) This prevents the instruction cache from running dry during conditional
instruction.
4) 64-bit data bus :
i) P~ntium has 64 bit data bus which allows higher speed of data transfer to it.
ii) The data transfer speed of pentium is twice as fast as a processor with 32-bit data
bus.
Q.9 Compare any four attributes of 80286 and Pentium microprocessor. OR
State four differentiating features among any two X86 family micro.ressors.
tfoBMiliN•i 1111•18E@tbl
Ans.:
Attributes 80286 Pentium
Database It is a 16-bit microprocessor. It is a 64-bit microprocessor.
Address bus
-~ . -~~ --
\ Address bus is ,24-bit hence \
r--
~ d~esf bus is 32-bit hence can
I
can acces~ memory. cces~"gJ3_memory. _..,

Operating speed (MHz) Clock frequencies 6 MHz Clock frequencies
to20MHz. 50 MHz to 100 MHz.
Memory management External Internal
Math co-processor External Internal
Q. 10 Compare any four attributes of _80286 and 80486 Processors. (March ·2013; Julv 18)
Ans.:
Attributes 80286 80486
Data bus 16 bits. 32 bits
Ad<;iress bus 24 bits 32 bit
Operating speed 6-20MHz 25-S0MHz
Physical memory address 16 Mbytes 4 G bytes
Internal data word size 16 bits 32 bits
Introduction data 1982 1989
( U..Pu~-"· .
Programmmg Model of X-86 Famtly
. j
Q. 11 State any six advance features of X -86 Micropreocessor Family. ttit1EC@1
Ans: Advance features of X-86 Microprocessor family are as follows :
1) It is capable of performing various computing functions and making decisions to cha n~e
the sequence of program execution.
2) It is very powerful computing device .

•
TPS Computer Science - II 3-7 Intro. to INTEL X-86 Family
3) Coprocessor - A~vanced microprocessors are supported by n~eric _c?processor. It is

separate CPU which perform arithmetic functions & trigonometric functions.
4) Operating System : Microprocessor works with multiuser & multitasking operatin
~~~ . g
5) Virtual Memory : Advanced microprocessor supports virtual memory technique for
sto~g large volume of data. _
6) Microprocessor includes special instructions & internal h/w which allow a programmar
or to write s/w without knowing how much memory is available.
Q. 12 Explain the programming model for 32-bit version of X-86 fami-h suitable
diagram. rf►iffitJ t: •t4i•~ii
Ans.: 1) The 8088 and 8086 defines the base programming model for the entire X-86 family of
advanced microprocessors.
2) The newer members of X-86 family have greater computing power because they are
faster, they use 32-bit registers instead of 16-bit registers and they have advanced
addressing techniques.
3) Following figure shows programming model for 32-bit version of X-86 family used in 32
bit microprocessor family i.e. in 386, 486 and pentium.: ·
31 16'15 8'7 o Name
,
EAX AH AL Accumulator (AX)
EBX BH BL Base Index (BX)
ECX CH CL Count(CX)
~neral EDX DH DL Data (DX)'
Purpose
Registers ESI SI Source Index
EDI DI Destination Index
EBP BP Base pointer
\ ESP SP Stack pointer

cs Codesegment
Segment f ss Sta~k segment

~egiste, 't ES
OS
~
Data segments
GS
FS J Instruction pointer
f.:IP IP
E Flag Plag H I Flag L Flag register
I
4) The programming model of 32-bit version of X-86 family consists of 3 register groups._ .
5) The first group contains eig_ht general purpose registers called EAX, EBX, ECX, EDX,
ESI, EDI, ESP and EBP registers. Where E tells us that these registers have extented
length. Each register can be addressed in 1, 8, 16 or 32-bit models. These registers are
used to store data during computations.
....,,,,,
rP5 Computer Science - II 3-8 Intro. to INTEL X-86 Family
6) The second group of registers is the segment group. This group consists of code
segment, stack segment and four data segment registers. The data segment registers are
DS, ES, FS and GS. These are 16-bit registers. These registers manage operation with
external memory. Address computations and data movements are performed here.
i):___Th_e_thir_._d_se_t-:o:--f:-r_egis=·:--:-te_r_s_co_ns_is_ts_o_f_Ins_tru_c_ti_o_n_P_o_in_t_e_r__:_(I_.P_..:_)_an_d_fl_a-=.g_r_egis=--·-t_e_r_.--:---;-
Q. 13 Draw neat labelled diagram and explain the :e_ros:!_amming_model of 16-bitversion
of X-86 family with register set. «•M•►l&fiiJmNJuujm@.mn,i:u
AnS-:
1) The 8088 and 8086 defines basic programming model for X-86 family.
2) The 16-bit version for programming model is used in 16-bit microprocessors of X-86
family i.e. in 8088, 8086 and 80286.
3) The 16-bit version of programming model of X-86 family is shown in the following
figure.
15 87 0
Accumulator
AX AH AL
Base Index
BX BH BL
Count
General
ex CH CL
Data
Purpose DX DH DL
Registers SI Source index
DI Destination index
BP Base pointer
· SP Stack pointer
cs Code segments ,
Segment ss Stack segments
register DS
\.
ES } Data segments
rn
Program.ming model of 16-bit version of X-86 family
Instruction pointer
Flag register
4) As shown in above figure the programming model of 16-bit version of X-86 family
consists of three register groups.
5) The first group contains 8-general purpose registers called A, B, C, D, SI, DI, SP and BP
registers. AL, BL, .... indicates lower bytes and AH, BH, .... indicates higher bytes. The
full 16-bit registers are referred as AX, BX, CX and DX, w here X stands for extended SI,
DI, BP, SP registers are always treated as 16-bit regis ters. These are pointer registers
because they are used to point locations within a segment.

TPS Compu ter Science -IT 3-9 Intro. to INTEL X-86 Fa,..,_-
·••tly
--....:_
6) of registe rs. Th.is group consists of
The second group of registe rs is the segme nt group
registe rs. Opera tion with external
code segme nt, stack segme nt and two data segme nt
perfor med here.
memo ry. Addre ss compu tations and data movem ents are
(IP) and flag register.
7) The third group of registe rs consist s of instruc tion pointe r
rocessor.
Q. 14 Enlist the differ~ nt flags provid ed by 8086 microp ----
Ans.:
flags, which are shoWn in
The microp rocess or 8086 has 16-bit flag registe r with 9 active
follow ing figure.
10 9 8 7 6" 5 4 3 2 1 0
15 14 13 12 11
I I I I I P U
I I I I Cy (U empty)
I
U U U U OF DF ! I:F TF S / Z U AC U
I I I I I
where ,
Cy - Carry flag,
P - Parity flag,
AC - Auxili ary carry flag,
Z - Zero flag,
S - Sign flag,
TF - Single step trap,
/ IF - Interru pt flag,
DF - directi on flag
OF - over flow flag
. (March 2003, Oct. 20051
Q. 15 Draw a neat labelle d diagram.of flag registe r of X86 family
Ans.:
ions. The flag registe r of X~6
Ffag registe r is used to store specia l results from data operat
family is shown in follow ing figure.
5 4 3 2 1 0
31 . . ... 18 17 16 15 14 13 12 11 10 9 8 7 6
IO PL O ,-D I j T S Z
I I NT I I I I A P
I I I - ,· I - I I - I ~
I
/ Revers ed Ac VM ·, RF O
I
where -
C ➔ Carry flag (CF)
P ➔ Parity flag (PF)
A➔ Auxill iary carry flag (AF)
Z ➔Zero flag (ZF)
S ➔ Sign flag (SF)

T ➔ Trap _flag (TF)
I ➔ Interru pt flag (IF)
D ➔ String Direct ion flag (OF)
O ➔ Overfl ow flag (OF)
Chapter 4 Introduction to
Microcontroller
Probable marks: 11
Scope of the syllabus

Introduction to microcontroller
architecture and programming model.
Study of 8051
Overview of other microcontrollers
in 8051 family.
Applications of microcontrollers
What is microcontroller ? Explain in short. (Oct. 2004,2010, June 2016, March 2018
Q.1
OR
Write a note on complete microprocessor system.
Ans.
microprocessor, of
1) A microcontroller is a complete microprocessor system, consisting
limited amount of ROM or EPROM, RAM and I/0 ports, built on a single integrated
circuit.
microcomputer, but it is called so because it is used to

2) Microcontroller is infact a
pertorm control functions.

The designer of a microcontroller identify all the needs to build a simple microprocessor
3)
IC.
system and puts as many as possible in single
a
4) For example a microcontroller must include nearly full implementation ot a

full or
standard microprocessor, ROM or EPROM, RAM, parallel 1/0 ports, timer, a clock,
serial ports.
A microcontroller is more complex than a microprocessor because it consists of many
5)
1/0 components.
6) eg.Intel's 8048, 8051
Q.2 Define microcontroller. State any four advantages of the same over microproceso
based system. Mar. 02, 05, Oct. 05, 10, 19;July 1

Introduction to Microcontroller
II
PSComputer Science 4-2
-
ns.
A microcontroller is a complete microprocessor system, consisting of microprocesso

limited amount of ROM, RAM and parallel I/0 ports, built on a single integrated
circuit.
Advantages of microcontroller over microprocessor-based system:
) The cost of microcontroller is less than a microprocessor-based system.
(i) A microcontroller has more I/O components than a microprocessor-based system.
(ii) Microcontrollers can be used in wide variety of intelligent products such as in

be used in
personal computers key-boards. Microprocessor-based systems cannot
such intelligent products.
microwave ovens,
(iv) Many low cost products such as electronic toys, electric drills,
VCRs are based on microcontrollers. This is not the case with microprocessor based
system.
.3 What are the main features of 8051?

Give any eight features of 8051.
OR
(Mar03, 04, 09,11,18, 19,20, Oct.03,04, 05, 06, 07 08,09)
Ans.: The main features of 8051 are as listed below:
The 8051 microcontroller has an 8-bit ALU.
)
i) The 8051 has 4K byte (4K x 8 bit) ROM or EPROM
ii) The 8051 has 128 byte (128 x 8 bit) RAM.
iv) It has dual 16-bit timer event counter.
v) It has 32 1/O lines for four 8-bit I/0 ports.
vi) It canaddress 64 kB of programrmemory.
vii) It can address 64 kB of data memory.
vii) It has powerful instruction set, consisting of 111 instructions.
ix) It has two external interrupts.
The 8051 has clock upto 12-MHz frequency.
xi) Full-featured serial port.

TPS Computer Science - II Introduction to Microcontre
4-3
Q.4 Draw an architectural block diagram of 8051 and explainit Oct -20
ELE
PEH
uonijsu
Ans.
As shown in the internal block diagram of 8051, there are 32 pins for four 6
1)
bidirectional ports.
In addition to these 32 pins, 8 pins are provided to connect clock crystal, timing a
2)
control signals and power supply.

4-4 Introduction to Microcontroller
3) The standard functions
which make up microcontroller is in the
This includes ALU, centre of the diagram.
accumulator, stack pointer, a block of registers and general purpose
register (B-register).
4) All these blocks are connected to 8051 internal 8-bit data bus
registers. through the series of
5) These registers hold data
during 1/O transfer and control the I/0 ports.
6) The architecture
diagram also includes RAM and ROM. The 8051 has internal 4 kB
ROM/EPROM and 128 bytes RAM.
Q.5 Explain 8051 memory mapping for 8051 microcontroller with
diagram. the help of neat
OR
Oct. 02,07, March 06, 09 08,19, 20; June 16, July 17,19)
Explain in detail how 8051 microcontrol addresses two separat
memory spaces.
(Mar. 05,11, Oct. 03)
Ans.
1) The 8051 addresses has two
separate memory spaces:
i) Program memory space
ii) Data memory space.
2) The memory map for 8051 is shown in the
following figure.
FFFF
|FFFF| Upto FFFF
60 k bytes
Upto of external
64 k bytes ROM or
of EPROM
external 1000 and 00F8
Upto
ROM OFFF 64 k bytes
or 4kbytes
o finternal0080
Special-function| of external
RAM registers RAM
ROM or 007F 128 byles
EPROM RAM
O000 0000 0000 0000
Program Memory Data memory
(ROM) (RAM)
3) The program memory space is Read-only memory (ROM) space.
4) This memory space is used for storing
programs and variable data.
5) It is possible
read program instructions from this
to
space, but the processor cannot
write data into this memory.
6) All instruction
fetches are taken from program memory
space.
7) The data memory space is a read/write
memory space.
8) The processor can read data from this memory
space and can write data to this memory
space.
9) It cannot execute instructions from this
memory space. The 8051 internal RAM is in this
memory space.
10) The 128 bytes of internal RAM provide
general read/write data
this is often referred to as registers.
storage. Some part of
TPS Computer Science - II 4-5 Introduction to Microcontroller
The 8051 has 22 special function registers which are not part of 128 bytes ot RAM. They
11)
to F8H. These registers are used for their intended
Occupy memory space from 80H
purpose.
memory can be expanded by an
additional 60k bytes, making it
12) The 4k byte program
b4k bytes program memory. The data memory can also be expanded to b4k bytes
this case, 8051 only has 64k

13) h e 8051 can also be operated with common memory. In
8051 can input block of data
Dytes of total external In this configuration,
memorv.
execute that
communications port load that data
in memory and then
through its serial
It is a very c o m m o n technique
data as a program. This is called downloaded program.
based controller.
the program operating in a remote microprocessor
-
used to change
Q.6 Give the main features of 8048 microcontroller.
Ans.: The main features as listed below:

of 8048 are
to 4 MHz.
() 8048 has clock having frequency 2 MHz
(i) It has 27 1/O lines.
EPROM.
(ii) It has 1 K byte ROM or
(IV) It has 64 bytes RAM

It has 8-bit timer event counter.
(v one
(vi) Address capacity of 8048 is 4 KB.

8051 family. OR
0.7 Explain in detail other microcontrollers in
List all microcontrollers of 8051 family and state one feature of each.
Mar.2010,2011, Oct.02, Oct.04;March 18
Ans.: 8051 is a second generation microcontroller.
8048, 8049, 8050
The 8048, 8049 and 8050 all have identical
intel's first microcontroller was 8048.
)
architectures with the exception of memory size.
in each case, the memory doubles. 8048 supports 1K byte of internal memory. 804
2
of internal memory and 8050 supports 4K bytes of internal
supports 2k bytes
memory
8048 has 64 bytes internal RAM, including 32 bytes of register/memory location
The 8049 and 8050 have a total of 128 and 256 bytes of RAM respectively.
4) These microcontrollers are low cost products and hence are very popular.
8052
1) 8052 is a simple expansion of 8051
2) 8052 has 8K bytes of onboard ROM and 256 bytes of onboard RAM
3) 8052 allows programmers to write larger programs and that can use more data
4) The cost of 8052 1s nore than that of 8051
5) The 8052 also has one extra l6-b1t counter-timer. This counter-timer gives moe
flexibility.

Introduction to Microcontroller
Science II 4-6
TPSComputer
8031 and 8032:
D
1) The alternative versions of 8051 and 8052 are 8031 and 8032.
These devices do not have any external ROM ror
2) on board ROM. It may use
program memory.
3) These are excellent devices for prototyping and low-volume products.
8052 AH-BASIC
Another torm of 8052 is 8052 AH-BASIC. This special 8052 has BASI
1)
programming language in ROM.
rather
2) Using BASIC iMstructions, a programmer can write instructions for this 8052
than assembly language.
0.8 Compare between mictocontrollers 8051 and 8052. Oct. 2006,2009, March 2011
Ans.: ROM
4k whereas 8052 has 8k bytes of onboard
1) Microcontroller 8051 hás bytes of ROM,
or EPROM.
whereas 8052 has 256 bytes of onboard
2) Microcontroller 805Thas 128 bytes of RAM,

RAM extra 1 6
dual 16-bit timer event counter whereas 8052 has
an
Microcontroller 8051 has a
3)
bit timer event counter.
8052.
4) The cost of microcontroller 8051 is less than that of microcontroller
allow to write
Both 8051 and 8052 are used in high volume applícations and both
us
large program. But in 8052 we can write larger programsthan that in 8051.
What is a Microcontroller ? State three expanded features of 8052 over 805
Q.9
microcontroller. Mar. 04, 06; July 19
Ans.:
(1) Microcontroller : A microcontroller is a complete microprocessor system, consisting of
microprocessor, limited amount of ROM, RAM and parallel I/0 ports, built on a single
integrated circuit.
but it is called so because it is used to
(2) Microcontroller is infact a microcomputer,
perform control functions.
(3) features of 8052 over 8051 microcontroller are as follows:
Expanded
Microcontroller 8052 has 8 Kbytes of onboard ROM or
(a) ROM:
EPROM whereas 8051 has 4 Kbytes of ROM.
Microcontroller 8052 has 256 bytes of onboard RAM
(b) RAM
whereas 8051 has 128 bytes of RAM.
Time-event counter: 8052 has an extra 16-bit time event counter whereas 8051 has
(c)
a dual 16-bit timer event counter.
Q.10 Give the applications of microcontroller. OR
Explain the various applications of microcontroller.
(Mar.02, 10 Oct.08,09;June 16; July 2017
Ans.
1) Microcontroller is a single chip microcomputer.
2) They are used as independent controllers in machines or as slaves in distributed
processing
3) They are used as machine tools, chemical processors, medical instrumentation and
sophisticated guidence contro
TPS Computer Science - 11 4-7 Introduction to Microcontrole
4) Some applications require simple timing and bit set/reset functions; other reati-
ons; other
speed data processing capability. require hi
5) Many low cost products such as electronic toys, microwave ovens, VCRs are
are ha
based O
microcontrollers.
6) A home security system, a tape deck and intelligent multimeter can also be buia
using microcontroller.
7) The personal computer keyboards are implemented with a microcontroller. lt ron
scanning, debounce, matrix decoding and serial transmission circuits.
replacs
Q.11 Differentiate between Micro-controller and a Micro-processor.
(March 2016
Ans.
Micro-controller Micro-processor
1. Micro-controller is a chip which 1. A Microprocessor is a general purpose
device which is called a CPU
iscalled single chip computer
. Microcontroller included RAM, | 2. Microprocessor do not contain on chip
I/O Port, ROM, Timer in a | I/O ports, Timer, Memories etc.

singlechip
3. Microcontroller based system | 3. Microprocessor based system designer is
design is simple and cost complex and expensive
effective
4. Microcontroller have no 4. Microprocessor have advantage of
advantage of designing RAM, versatility such that designer can decide
ROM and 1/0 port the amount of RAM, ROM andI/0 port
as needed.
Q.12 Select the correct altermative and rewrite the following.
1. is a microcontroller chip.
1) 8085 ii) 80286 (ii) 8051 (iv) Pentium
Ans. (ii)8051
2. 8051 has-RAM.
() 128 bytes i) 64K bytes (ii) 1K bytes (iv) None of these
Ans. (i) 128 bytes
3. The 8051 microcontroller has instruction set of -
instructions. (Mar.02,0
G) 99 (ii) 111 (ii) 120 (iv) 110
Ans. (ii) 111
4. 8051 has clock upto-frequency. (Oct. 05
(i) 12 MHz (i) 4 MHz (ii) 9 MHz (iv) 6 MHz
Ans.: (i) 12 MHz
5. The 8051 is a -
generation microcontroller. Oct.0
i) First (i) Second (ii) Third (iv) Fourth
Ans. (ii) Second
6. The 8051 microcontroller has an ALU o f - bit capacity. (Oct. 0
(i)8 (ii) 16 i ) 32 (iv) 64
Ans. (i) 8
For More computer science PDF
Visit tpspoint.com
Chapter(5 Networking Technology
Probable marks: 28
Scope of the syllabus

Study of transmission media: .
Cable media-coaxial cable, Twisted pair, fibre optic, their comparison.
Introduction to wireless media.

Network topologies - Acess methods, Topoiogies (BUS, RING, STAR), Ethom
ernet
TOKEN RING.
Protocols-Internet protocols
Introduction to connectivity devices
Modem, Hubs, Repeaters, Routers
Study of transmission media

Q.1 What is transmission media? Give
transmission media characteristics
(Oct. 07; July 18
Ans.
(1) The pathways through which individual systems are connected in a network are called
as transmission media.
(2) Transmission media makes transmission of electronic
signals possible from one
computer to another. These electronic signals are nothing but binary pulses (I/O).
(3) Each type of transmission media has
special characteristics that make it suitable tor a
specific type of service.
(4) The characteristics are: (March 2019
1. Cost of media
2 Installation requirement
3. Bandwidth
4. Band usage (base band and broad
band)
5. Attenuation
6. Immunity from electromagnetic interference.
Q.2 What is Wireless Media? Write any two
advantages of Wireless Media
Ans. Wireless communication has extra (March 2017; July 201 are
ordinary convenience. Not all nerwfer

connected with cabling. Some network are wireless.
network
t o offer
The technology is
better options for wireless network. There are expanding o r k
three basic tvpes of wireless
Wireless LAN 2. Extended LAN 3. Mobile new
computing.
For Advantages of Wireless Media l'lease refer
: Chapter 5 Q.3, Pg. No. 5-2.
Science II
TPSComputer 5-2 Networking Technology
What is a
Transmission Medium ? What are the advantages of wireless
Q.3 transmission ?
(Oct.2004; July 18)
Ans.: Transmission medium : Refer Q. No.1.
Advantages of wireless medium:

High data rates by using large bandwidth.
(1)
(2) Wireless medium can give transmission speed around 24 kbps.
By this media the communication can reach rural and hilly area.
(3)
Bandwidth for digital data 1 to 10 Mbps.
(4)
Explain the following characteristics oftransmission media.
Q.4
March 2002, 2008 Oct. 2005, Oct. 2006, 2010; July 2019)
(a) Bandwidth (b) Band usage (c) Attenuation
(d) Immunity from electromagnetic interference.
Ans.
(a) Bandwidth: (March 2020
(1) Bandwidth is the measure of the capacity of a medium to transmit data.
(2) Data transmission rates is number of bits transmitted per second.
(3) Bandwidth of a cable depends on cable length.
(4) A short cable can have greater bandwidth than a long cable so for all cable designs,
maximum lengths for cable runs are specified.
(5) Beyond these limits the highest frequency signals can deteriorate and error occurs
in data signals.
(b) Band usage: (March 2009
(1) The bandwidth is shared so that maximum usage is obtained.
There are two transmission modes, base band and broad band transmissions.
(2)
Base band devotes the entire capacity of the medium to one communication
(3)
channel.
Broad band enables two or more çommunication channels to share the bandwidth
(4)
of communication medium.
Base band is most common mode of operation. Most local area networks (LAN)
(5)
function in base band mode. In base band, signaling can be anolog or digital.
(6) Thebase band and broad band transmission modes are shown in following figure
Band
width
UUUU W W
Base band Broad band
c) Attenuation: (March 2009,2020,Oct.2005)

)Attenuation is a measure of how much a signal weakens as it travels through a
medium.
Networking
5-3
is absorbed and,
Technology
medium, part of the signal mak the
(2 As signals pass through the
signal weak. falls below
when signal strength certainn limits,
1
)(3) Attenuation decides the cable length

then at station noise may appear.
receiving
(4) Repeaters are used to regenerate signals.
(d) Immunity from electromagnetic interference
(March 2009, Oct. 2005,201
(EM):
noise that dis
interference consist of outside electromagnetic istorts
(1) Electromagnetic
the signal in a medium.
EMI is interfering the signals and makes difficult for computers to decode #.
(2)
signal.
3) An example of electromagnetic interference is the crosstalk. Crosstalk occurs whos
(3)
wire.
the signal from one wire is picked by another
(4) In computer networks, large number of cables are located close together, therefore
crosstalk is a significant problem in networks.
Q.5 Explain the following characteristics of transmission media:

(a) Cost (b) Installation requirements.
Ans.
(a) Cost of media
(Oct -2010
(1) One major factor irn purchase decision of any networking component is its cost.
(2) For a new fast technology, cost is also more expensive.
(3) Decision depends upon application and standard of the resources.
(4) Therefore, the network designer must settle for
robust. something, which is cheaper and
(b) Installation requirement:
(1) Some transmission media
March 2020
requires skilled labour to
network and it may cause certain install. This increases cost or
delay.
(2) Before installation we need to
prepare actual physical layout of network.
Q.6 Explain in short the six important characteristics
of transmission media
Ans.: Each type of transmission media has
March 2004,20, Oct -2010; July1
specific type of service. The special characteristics that make it suitable a
characteristics are:
i) Cost of media
ii) Installation requirement
ii) Bandwidth
iv) Band usage
v)Attenuation
vi) Immunity from
electromagnetic interference.
i) Cost of media:
(a) While designing a network, the cost of
media must be
(b) The cost property is decided by user as
considered.
per application and standard of res
Networking 1eciu
TPS C o m p u t e r 3 u
Installation requirement:
Before installation, prepare actual physical layout of network and then estimae
(a) cable and cost of installation.
For almost all media, the cost of installation exceeds than the cost of the able tself.
(b)
Bandwidth:
Bandwidth is the measure of the capacity of a medium to transmit data.

(a)
Bandwidth of a cable depends on cable length.
(b)
iv) Band usage:
the
(a) In baseband transmission mode, baseband devotes the entire capacity of
medium to one communication channel.
comnmunication
In broadband transmission mode, broadband enables two or
more
(b)
channels to share the bandwidth of communication medium.
v Attenuation:
a
of how much a signal weakens as it travels through
Attenuation is a measure
(a)
mediumn.
is absorbed and makes the
b) As signals pass through the medium, part of the signal
signal weak.
(EMI) (March 2020)

vi Immunity from electromagnetic interference distorts
interference consist of outside electromagnetic noise that
(a) Electromagnetic
the signal in a medium.
to decode the
signals and makes difficult for computers
EMI is interfering the
signal. LAN and
networks ? Distinguish between
Q.7 What the advantages of computer
(March2003, 06, 11,19, Oct.2005, July 17,18)
are
WAN?
Ans.
interconnected collection of
autonomous computers or system
(1)
Computer network is an
r e s o u r c e s controlling
services.
of sharing
ofcomputers capable
network are :
4 T h e main advantages of computer
a) Network provides resource sharing.
information and software.
b) provides exchange of
other machine if one machine fails in the
c) Itprovides high reliability by using
air and traffic control.
network like military banking,
d) Access to any file and data.

network only.
e) Finally the system is saving money by
Science -II
j Networking Technology
Computer
5-4
TPS
Installation requirement
Before installation, prepare actual physical layout of network and then estimate
(a) cable and oost of installation.
able itselr.
(b) For almost all media, the cost of installation exceeds than the cost of the
i Bandwidth:
is the measure of the capacity of a medium to transmit data.

(a) Bandwidth
of a cable depends on cable length.
b) Bandwidth
iv) Band usage: the
mode, baseband
In baseband transmission devotes the entire capacity of
(a)
medium to one communication channel.
more communication
mode, broadband enables two or
transmission
(b) In broadband mediumn.
channels to share the bandwidth of communication
v)Attenuation: a
weakens as it travels through
Attenuation is a measure of how much a signal
(a)
medium.
and makes the
the medium, part of the signal is absorbed
(b) As signals pass through
signal weak.
(EMID:
(March 2020)
interference
vi) Immunity from electromagnetic noise that distorts
interference consist of outside electromagnetic
(a) Electromagnetic
the signal in a medium. to decode the
signals and makes difficult for computers
b) EMI is interfering the
signal. LAN and
networks ? Distinguish between
the advantages of computer 17, 18)
Q.7
(March 2003,06,11, 19, Oct.2005, July
What are
WAN?
Ans. autonomous computers or system

of
interconnected collection
(1) Computer network is an
resources controlling services.
of computers capable of sharing
network are:
(2) The main advantages ofcomputer
a) Network provides r e s o u r c e sharing.

software.
of information and
b) It provides exchange machine fails in the
other machine if one
reliability by using
I t provides high air and traffic control
network like military banking,
d) Access to any file and data.

money by
network only.
e) Finally the systemis saving
Networking Technology
TPS Computer Science - II 5-5
follows :
The differences between WAN and LAN are
as
(3)
LAN
WAN
is groun
A LAN (Local Area Network)
a
1 A WAN (Wide Area Network) is the
interconnection of LAN or MAN can | of computersrinterconnected within a
area such as room, building or a
be located entirely within a state, small
country or around the world. campus.
Data transfer speed is comparatively
2. Data transfer rate is comparatively
slower such as in Kbits/sec. 10 million high such as thousand bits per second to
bits per second.

3. In WAN, links may be established by Co-axial cables are generally used to
using telephone cable or microwave connect the computer and other devices:
towers or satellite.
4. In this network, shortcircuit errors, Due to short distance, short circuit
noise errors, atmospheric errors are errors or other noise errors are
higher than any other networks. minimum.
5 For example : pager. For example : A computer lab ina

college
Q.8 Describe co-axial cable in detail. OR
Write a short note on Co-axial cable with suitable
figure. (Mar. 2003, Oct. 2006,2010)
Ans.
(1) In co-axial cable, there are two conductors sharing a common axis.
(2) The co-axial cable is shown in
following fig.
Insulator
Jacket
Outer (protective plastic covering)
conductor (shield)
Center
conductor
Co-axial cable
(3) The components
of co-axial cable are as follows
(a) A center conductor is solid
a copper wire or stranded wire.
(b) An outer conductor form a tube
surrounding the inner conductor. This conductor 1s
made up of braided wires, metallic foil or both. The
shield. This serves as a ground and outer conductor is called as
protects inner conductor from EMI.
(c) Aninsulator layer keeps outer conductor
spaced evenly from the inner conductor
(d) A plastic jacket protects cable from
damage.
II Networking Technology
Science 5-6
TPS Computer
I(4) There are two types of co-axial cables:

(a) Thin net (thin, flexible and inexpensive)
Thick net (thick, hard and expensive)
(b)
Advantages:
The co-axial cable is better shielded than the twisted pair cable. So, it can span
(1)
longer distance at higher data transmission speed.
(2) Its shielding provides better resistance to EMI.

(3) Attenuation is less than twisted pair cable
Disadvantages:
(1) relatively more expensive than Twisted Pair but less than
It is
fiber optic cable.
(2) Bandwidth capacity is comparatively less than fiber optic cable.
Q.9 Give the important characteristics of co-axial cable.

Ans.
The important characteristics of co-axial

cable are given below.
cable more than
Cost: Thinnet cable is low cost.cable, it costs less than STP. Thicknet
i)
STP.
Installation of thinnet cable is also inexpensive.
Installation: Co-axial is easy to install.
2.5 Mbps to
LANs based on co-axial cable gives bandwidth, in between
iii) Capacity bandwidth.
10 Mbps. Thicknet co-axial cable gives higher
co-axial cable can transmit signal reliably upto
iv) Attenuation: Due to attenuation thinnet
185 meters, where as thicknet cable can upto 500 meters.
run
sensitive to EMI, but

EMI As co-axial cable consists of central copper conductor, it is
cable is less sensitive to EMI than UTP
reduces its sensitivity to EMIL. Co-axial
shielding
cable.
in detail. OR
Q.10 Explain Twisted pair cable (March 2009, Oct.2004)
Write a note on Twisted pair cable.
Ans.
material like copper, insulated
(1) Twisted pair cable consist of two wires of conducting
from each other by plastic.
in
(2) The basic Twisted pair cable is shown fig.
Conductors
Insulating
jackets
Twisted pair cablee
TPS Computer Science - II 5-7 Networking Technology
lt consists of two or more strands of copper wire twisted together.
(3)
4) his twisting reduces the sensitivity of the cable to EMI (electromagnetic interferena
nce)
and also reduces the tendency of the cable to radiate radio frequency noise.
h s cable is used to connect a PC to either HUB or MAU. AlSo commonly used

(5) in
telephone network.
(6 Twisted pair cables are of two types:
(a) Shielded Twisted pair cable (STP)
(b) Unshielded Twisted pair cable (UTP)
(a) Shielded Twisted pair (STP):
(i) Shielded Twisted pair cable consist of one or more twisted pairs of cables enclosed
in a foil wrap and woven copper shielding.
(i) The shield is connected to the ground portiorn of the electronic device to which
cable is connected. Ground
portion is electrical reference point.
ii) A properly grounded shield prevents signals from getting into or out of the cable.
b) Unshielded Twisted pair (UTP):
() The unshielded Twisted
pair does not have a braided shield into its structure. The
characteristics of UTP are similar to that of STP.
(ii) Telephone systems commonly use UTP cable. In some networks UTP
cable is used.
UTP cable is available in 5
grades or categories.
(7) Advantages:
This medium is
inexpensive and easy to instal1.
(i) Since wires are twisted, it reduces EMI and
also avoids RF
(ii) Twisted wires also reduce cross talk. radiation.
(8) Disadvantages:
(i) They can be used only for short distance
communication.
) The typical speed computer data is 1200 bits/seconds
of
(bps).
Q.11 write a note an shielded twisted pair cable
with its
characteristics.
Ans.
(1) Shielded Twisted pair cable consist of one or more twisted pai
pairs of cables enclosed
foil wrap and woven copper shielding.
TPS Computer Science - II 5-8 Networking Technology
2) Following fig. shows IBM type 1 of shielded twisted pair cable:
Jacket
Two Shield
twisted pairs
(3) The shield is connected to the ground portion of the electronic device to which cable is
connected. Ground portion is electrical reference
point.
(4) A properly grounded shield prevents signals from getting into or out of the cable.
(5) The characteristics of shielded Twisted cable are
pair given below:
) Cost: The cost of STP cable is more than that of co-axial or UTP cable. Its cost is less
than that of thick co-axial or fibre
optic cable.
(ii) Installation : The installations required for STP cable depends upon the type of
network. As per the type of network, different connectors are used.
(ii) Capacity: STP cable has a theoretical capacity of 500 MBPS. Practically it is around
155 MBPS with 100 meter cable run. The most common data rate for STP cable is
16 MBPS.
iv) Attenuation : All Twisted pair cables have attenuations. This limits the length of
cable. 100 meter limit is most common.
(v) EMI characteristics: The shield in STP cable results in good EMI characteristics.
STP cable has low sensitivity towards electromagnetic interference.
Q.12 Write a short note on unshielded twisted pair cable with its characteristics.
(Mar. 2002)
Ans.
(1)UTP consists of a number of twisted pair with plastic jacket.
(2) It is commonly used in telephone systems. Now-a-days UTP cable is being used in LAN
instead of co-axial cable.
(3) AUTP cable is shown in following figure:
(4
9The characteristics of Unshielded Twisted pair cable are given below:
(i) Cost: UTP cable is cheaper than any other cable. The cost of
category 5 twisted pair
cable is high.
(ii) Installation: UTP cable is easy to install. The equipments required are also low
cost. UTP system can be easily reconfigured.
Science - II
T P SC o m p u t e r
5-10
TheThe fibr optic cable is used in
This cable have
optical transmission
extremely high bandwidth. It has system.
) several kilometers.
zero sensitivity to EMI and
runs ovcs
ver
The characteristics of fibre
9 optic cable are given
(i) Cost: The cost of fibre
optic cable is
below:
pair cable. more than that of co-axial cable and Iwistea
i) Installation Fibre optic cable
:
minimum bend radius. They may requires skilled installa tion. Every cable has
not be stretched. get damaged if bent sharply Fibre
optic cable can
(ii) Capacity: Fibre optic cable

with long run cables. Fibre supports high data rates (upto 2,00,000 MBPS), even
optic cable can transmit 100 MBPS for several
(iv) Attenuation Attenuation for fibre optic cable is
: kilometer.
much lower than co-axial cable
and twisted pair çable. It can run to
larger distance.
(v) EMI: Fibre optic cable does not use electrical
signals to transmit data, therefore
they are free from EMI. The data transfer in fibre optic cable have high security, as
it can not be detected by electronic wave
dropping equipments.
0.15 Compare any four attributes of UTP and Optical Fibre Cable.
(March04,09 Oct.06,07,08,2011;July 17
Ans. :
UTP Optical Fibre Cable

(1) Cost Cost of UTP cable is less Optical fibre cable are expensive.
than that of optical fibre
cable.
(2) Installation Installation of UTP cable Optical fibre cable requires skilled
is easy.
3) Capacity Data rate capacity is from Optical fibre cable can transmit
1 to 100 MBPS upto 100 mtrs. 100 MBPS for several kilometers.
4) EMI More sensitive to EMI. This cable has no sensitivity to EMI.

5) Attenuation Attenuation is more than In optical fibre cable attenuation is
optical fibre cable. very less.
Q.16 Compare the characteristics of fibre optic cable and co-axial cable. Mention at least
points. (March 2002, Oct. 2005)
three
Ans.
1 optic cable. Fibre optic cables are
than that of fibre
LOst: Cost of co-axial cable is less
2)
expensive. and easier than that of fibre optic
stallation : Installation of co-axial cable is cheaper
cable.
3) cable is 10 MBPS, while that
data transmission capacity of co-axial
Cay
pacity: In general
ot fibre optic cable is 100 MBPS
5-11
Networking Technolo
cable has serno
4) EMI : Co-axial cable is less
sensitive to EMI, while fibre optic no
sensitivity to
EMI. attenuation is very less
5) Attenuation: It is m o r e in co-axial
cable. In optic fibre,
Twisted pair cable. Mention
atleast three npoints.
cable with
Q.17 Compare the co-axial (Oct. 2003, 2010, March 200
Ans.
Coaxial Cable
Twisted Pair Cable
It is a hallow cable with a solid copper at #hhe
(1) It consists of a pair of wires or one or
more pairs of two twisted copper wires center of the cable surrounded by plasi
insulation. from
Relatively expensive i.e. twice or thrice than
(2) This is inexpensive medium.
twisted pair.
(3) EMl effectis maximum. EMI effect is minimum.
(4) Attenuation is more than coaxial cable. Attenuation is less than twisted pair cable.
(5) Bandwidth capacity is from 1 to Bandwidth capacity is from 500 Mbps upto
100 Mbps upto 100 mtrs. 100 mtrs.
(6) They can be used only for short It is commonly used in network.
distance communication.
Q. 18 Compare the characteristics of Fiber-Optic and Co-axial Cable. Mention at least
three points.
Ans:
(March2008;July 18)
Fiber-Optic Co-axial Cable
i) This Cable has no sensitivity to EMI
| i) EMI effect is minimum
ii) Optical fibre cable can transmit
ii) Bandwidth capacity is form 500 mbps
100mbps for several kilometers.
upto 100 mbps
ii) Optical fibre are expansive. i) Co-axial cable are less
expensive.
Q.19 Compare any four attributes of
Ans.:
Coaxial thicknet Cable with UTP cable. June 2016
Coaxial Thicket cable

UTP Cable
More expensive.
Less expensive.
2 Difficult to install. 2. Easy to install.
3. Bandwidth upto 500 meters 3.
4.
Bandwidth upto 100 meters:
Attention less.
4.
. Less sensitive to EMI.
Attention more.
5. More sensitive
6. Used in LAN. to EMI.
6.
Used in
telephone system
Science -
II|
TPS Computer 5-12 Networking Technology
0 .2 0 Explain the
tollowing wireless media in detail, OR State and
networking media. Explain any two wireless media. explain difterent
Oct. 2005)
Ans.
( Radio waves
(1) Radio waves are
easy to
generate. They can travel long distance and can
buildings easily. Hence, radio waves are widely used peneurate
for both indoor and
purposes. Outabo
(2) Radiowaves omnidirectional i.e. the waves travel in all directions, in the ree
are
space so that there is no need to place the receiver or transmitter along a direct line
of sight.
(3) Radio communication have variety of frequency ranges that
wave
are utilised for
various communication applications.
(4) As radiowaves covers large distance, interfare between users is a problem. For th1s
reason government license is necessary to transmit radiowaves.
(5) Radio communication having major drawback that it may be disturbed by rains,
bounce back from obstacles. It offers low bandwidth for data communication.
(1I) Microwaves:
(1) Microwaves travels in straight lines and therefore narrowly focused, concentrating
all the energy into beam.
(2) For microwaves transmitting and receiving antennas should be accurately alligned.
This directionality allows multiple transmitters linear in a row to communicate
with multiple receivers linear in a row without interference.
(3) Since, microwaves travels in straight lines, for longer distances periodic repeaters
are necessary.
(4) Unlike radiowaves, at lower frequency microwaves can not penetrate buildings.
(IT) Infrared and millimeter waves:
(1) Unguided infrared and millimeter waves are widely used for short range
communication.
(2) The remote controls used on

on television, V.C.Rs. etc. all used infrared
communication.
(3) They are relatively directional, cheap and easy to generate. Major drawback of
these waves is that they can not pass through solid objects.
As infrared waves can not pass through solid objects, it means that an infrared
(4
system operating in one room will not interfare with other infrared systemn
operating in adjacent room or any other room. For this reason, no government
license is necessary to operate infrared system.
Q.21 State four LAN wireless transmission methods. Explain any two of them. (Oct. 2003)
Ans.:
** Wireless LAN can use one of the transmission method:
() Infrared (ii) Laser

1) Narrow - band radio (iv) Microwave
NetworKing Tech
5-13 Technolog
TPS Computer Science -II
(i) Infrared: infrared rays are

used.
transmission
(a) i n intrared
100 feet.
(6) This is limited within
bandwidth can
be supported.
(c) Upto 10 Mbps transmissiOn.
infrared
(a)Remote control of TV uses
(ii) Laser
are used.
transmission LASER rays
(a) In laser
are in straight of sight
(b) This receiver and transmitter
WAN transmission.
( C T h i s can be used for LAN and
(iii) Narrow-band radio:

transmission,
1s used for
(a) In narrow-band radio transmission, single frequency
a
a direct line of sight.

(b)
(6) The receiver and transmitter need not to put along
(c) The range of narrow band is greater than infrared.

(iv) Microwave:
(a) Microwave communication can take two forms: Terrestrial links and satellite links,
(b) In terrestrial microwave communication the transmitter and receiver are earth
based.
(c) Telephone relay towers uses this type of communication.
(a) In satellite microwave system, satellite are 22300 mils above the earth
(e) Earth stations uses satellite dishes to communicate with satellite.
[Note: Explain any two types]

Network topologies
Q.22 What do you mean
by network topology ? Explain in brief the two basic
of topology. categorie
March 2004,Oct.2009, March 2020
Ans.
(1) Topology refers to the way in which network of
(2) A computers is connected.
topology defines the arrangement of nodes, cables
up the network. and connectivity devices that ke
(3) There are two

categories:
(i) Physical topology
(ii) Logical topology
(4) Physical topology escribes actual
the way the network looks. layout of the network transmission media. It define
.media. it
(5) Logical topology describes the
network modes. It logical
defines the data pathway signal follows asas it passes am
a the
passes among the nodes. passes

II
TPS Computer Science Networking Technolo8y
-
5-14
Physical and logical topologies can take several forms.

(6)
The most common are
(a) Bus topologies (b) Ring topologies
(c) Star topologies (d) Mesh topologies
0.23
Q. 23 What is topology ? Explain BUS topology in detail.
(Oct. 2006, 2007, 2009, 2010, March 2011)
Ans.
Topology reters to the way in which network of computers is connected.
(1)
(2) Nodes in the network are physically interconnected in some configuration to provide
efficient communication. This configuration is called as topology.
devices that make
3) A topology defines the arrangement of nodes, cables and connectivity
up the network.
BUS topology:
In BUS physical topology, all the devices are connected to a common shared cable
(1) a
called as backbone of the network.
(2) A BUS physical topology is shown in following figure:

PC PC
PC
O
PC
PC Server
and every computer node.

node to send its data to each
(3) The bus is available for each
cable and hence all
transmits signals in both directions on backbone
Most of the buses
4 buses are unidirectional and data is
able to receive signals. But some
workstatións are
stream devices
backbone cable. Hence only down
transmitted in one direction of
only
can receive signals.
at
the
along cable. As message arrives
5) The backbone cable carries transmission message
matches to its o w n or not. If
whether the destination address
a workstation, it checks
next workstation.
not, it does no m o r e and the message goes to
TPS Computer Science - II 5-15
terminators to prevent signals fro

each end bý placing
(6) C DUs cable is terminated at
reflecting back.
10 MBPS.
is ethernet at
(7) for BUS topology
Onmonly used implementation
*
(8) Advantages:
) The bus system is much faster.
branches to form
arnother topology.
i) The bus topology can be extended with sub
other node's communication.
(11) Breakdown of any failure rnode does not affect
(a) Bus topology is widely used in LAN network.
Q.24 Explain RING topology. Give its advantages and disadvantages.
(March 09,18, July 2019
Ans.
(1) RING topologies are wired in a circle. Each node is connected to its neighbours on either
side, and the data transmits along the ring in one direction only.
(2) Each device incorporates a receiver and a transmitter and serves as a repeater that
passes the signal onto the next device in the ring.
(3) The RING topology is as shown in.following figure:

PC PC
R- Receiver
T-Transmitter
R
PO
PC
PC
(4) RING topologies are suited for

networks that uses
token passes around the token passing
ring, and the only node that access' methods. he
(5) This topology is holds the token can transmit data.
always implemented as a
eg. In token
logical topology.
ring network, the
topology is RING topology. topology is physically a STAR al
topology. But iog
(6) The comunonly used implementation for RING
topology is token ring at 4-16
MBT
Sciernce -
II
Computer
TPS 5-16 Networking Technology
Advantages:
) Cable failure affects limited users.

i) Each node has equal access speed to the ring.
(i) Equal access for all users.
Disadvantages:
8)
Costly wiring is required for RING topology.
)Expensive adapter cards.
(i) Difficult connections.
0.25 Explain in short, STAR topology.
March 2006, 11, 18, 19, Oct. 2007;July 2019)
Ans.
(1) In a STAR topology all the workstations are connected to central hub.
(2) The hub receives signal froma workstation and routes it to the proper destination.
() STAR physical topology is often implemented to implement BUS or RING logical
topology.
(4) A STAR topology is shown in following figure:
PC
PC
HUB ROUTER
PC
PC
PC
5) Advantages
)
Adding a new workstation is easier than that in BUS or RING topology.
4 The control is centralised due to use of hub.

Science II Networking Technology
TPS Computer
-
5-18
Reconfiguration is easy, as computer is needed to connect directly to the server. But to

v make each connection, long cable is needed.
In star topology all process is done only through the central computer: So if central
vi)
computer tails, whole network is damaged.
vii) Any failure of anyone connection doesn't affect the total network.
vii) Advantages:
Adding a new workstation is easier than that in BUS or RING topology.
i) The control is centralised. due to use of hub.
Q.31 Discuss in detail Ethernet, with ethernet terminology. OR
Write a note on Ethernet.
(March2003, 2005, Oct. 2008; March 2017; June 2016; July 2017
Ans.
(1) Ethernet is a local area network technology, with networks tradionally operating within
single building.
(2) Atmost, Ethernet devices can have a few hundred meters of cable between themn.
Modern technology allows Ethermet to span upto 10 kms.
(3) Ethernet devices are connected to a common shared medium that provides the path
along which the electronic signals will travel. Historically, this medium was co-axial
cable. But, now-a-days twisted pair cable or fibre optic cable are also used.
(4) Ethernet network transmit data in small units called frames.
(5) Each frame must contain source address as well as destination address, which identifies
receipant and sender of message. The address will uniquely identify node. No two
Ethernet devices can have same address.
(6) Ethernet network is as shown in following figure.
File
Computer Server Computer
A C
Computer Computer
B D
In above figure when computer A sends message to computer C, computers B and D

will also get the message and check whether the destinations address matches to its owrm
address or not, if not, it will discard the framne.
Science II
TPS Computer
-
5-20 Networking Technology

PC
PC
R
R
R-Receiver
T-Transmitter
PO R
PC PC
i) Token passing:
1) Token passing utilizes a frame called a token, which circulates around the network.
2) A computer that needs to transmit must wait until it receives the token.
3) When computer receives token, it is permitted to transmit.
4) When computer completes transmitting, it is passes the token frame to the next
station or token ring network.
Q.34 Discuss access methods of networking. OR Discuss any two access methods of
networking? (March 2003, 2020, Oct. 2009)
OR Explain the following access methods brief.Oct.2002, 04, 08, March 2006, 18
i) Contention (ii) Token passing
Explain in brief Token passing and Polling' access. methods (Mar.10;July 17, 18
Ans.
(1) An access method is a set of rules governing how the network nodes share the
transmission medium.
(2) There are three most important types of media access methods:
(A) Contention (B) Polling () Token pasing
(3) Contention:
a) In contention, any computer in the network can transmit at any time (first come
first served).
attempt to transmit at the same
b) This system breaks down when two computeres
time. This is a case of collision.
used. Here each computer listens
c) To avoid collision, carrier sensing mechanism is
to the network before attempting to transmit.
If network is busy, it waits until
network quiets down.
to the network as they transmit. If
d) In carrier detection, computers continue to listen
that interteres with the signal it is sending, it stops
computer detects another signal to
wait random amount of time and attempt
transmitting. Both computers then
transmit.
Networking lechno
TPS Computer Science - Il
5-21
access
control od
method
fechnolog
on LANs.
onIA
media
most popular
e) Contension methods are
Collision
-- -
(4) Polling
a) In polling based systems, there is a device (called controller or master devicel
a) to
poll other devices on the network to see whether they are ready to either transmit
t
or receive data.
b) This access method is not widely used on network because the polling itself can
cause a fair amount of network traffic.
(5) Token passing :
a) Token passing utilizes a frame called a token, which circulates around the network
b) A computer that needs to transmit must wait until it receives the token.
c) When computer receives token, it is permitted to transmit.
d) When computer completes transmitting, it is passes the token frame to the next
station or token ring network.
Q.35 Explain the following terms with respect to cabling
(A) 10 BASE 2 (B) 10 BASE 5
(C) 10 BASET (D) 10 BASE FL
Ans.
(A) 10 BASE 2:
(i) This uses thinnet of co-axial cables.
(i) Each network connects
directly to the network cable with a
(i) The minimum cable distance between T-connector.
clients must be 1.5 feet.
(iv) The T connector must be
connected
(vThe entire network cabeling scheme directly
to the network
adapter.
cannot exceed 925 meters
(B) 10 BASE 5: This uses thicke net
co axial cable.
-
(3035 feet).
i) BASE 5 uses an external
10
transreceiver to attach to the
(i) The minimum cable distance network adapter caard.
between transceivers is 2.5
(ii) The maximum network metres.
segment length is 500 meter
iv) The entire network
cabling scheme cannot (1640 feet)
exceed 2500 meters.
(8200 fee
TPS Computer Science II
-
5-22
(C) 10 BASET:
() This uses UTP cable.
i) The maximum number of
computers on a LAN is 1024
(i) The cabling should be UTP category 3, 4 and 5. STP cable can also be used.
(iv) The cable segment length (hub to transceiver) is 100 meters (328 feet)
D) 10 BASE FL:
) 10 BASE FL is a specification for ethernet over fiber

optic cables.
(i) This supports a maximum cabeling distance of about 2000 meters and eliminate
any electrical complications.
Protocols
0.36 What is meant by protocol ? Explain the concept of TCP/IP protocol.
(March 2004, 08, 11, Oct. 2003, 04; June 2016; March 2018,July 2019)
Ans.:
(1) A protocol is defined as an agreement between communication particle for how

communication should be proceed.
OR protocols are rules by which computers communicates ie. protocol is set of rules and
formats for sending and receiving data.
(2) Internet protocols are called TCP/IP (Transmission Control Protocol/Internet Protocol)
protocols. This protocol do not belong any one company and technology is available to
everybody.
(3) TCP/IP protocol use three types of addresses for network addressing:
(a) Hardware or physical address is used by the data link and physical layers.
(b) Internet protocol address provides logical node identification. This address is
unique address assigned by administrator expressed in four parts dotted notation.
e.g. 123.144.131.21
() Logical node names are easier to remember than an IP address.

Introduction to connectivity devices
9.37 Explain modem in detail. (March 2006, 2010, Oct 2010; March 2017)
Ans.
(1) Computers store digital data,telephone lines can only transfer analog data. If a
while
then it must convert digital
computer is to be connected to internet through telephone,
data to analog data before transmitting the computer signals.
(2) form is called modulation and reconverting it to
Converting one signal form to another
original form is called as demodulation.
internet.
3) odem is modulator/demodulator. Modem is used
to connect computer to
Modems convert digital data to analog data and vice-a-versa.
Networkking Techne
5-23
4) They have two advantages: on any given analog line.

Modem allows higher speed
of transmission
)
Modem reduce effect of noise
and distortion.
(11)
figure.
) T h e function of modem is described by following
Demodulation . Computer
Computer Modulation Analog data
Demodulation
Modulation
LL
Digital Telephone lines
Modem Digital
data Modem data
Modems are classified into two categories according to transmission method:

(6)
1. Asynchronous modems
2. Synchronous modems
Q.38 What are the two types of modems. Explain them. (Mar.2010
Ans.: Modems are classified into two categories depending upon transmission methods:
1) Asynchronous modems
2) Synchronous modems
1) Asynchronous modems:
(a) n asynchronous modems, transmission clock is not used for synchronisation
Instead it uses, bit synchronisation.
(b)
(b) Here each frame begins witha start bit that enables the receiving device to adjust to
the timing of transmitted
signal,
() Messages are kept short.
(d) It is used to transmit character data.
(e) Asynchronous transmission is simple, inexpensive technology. It is used for PC t0
PC communication.
2) Synchronous modems:
a Synchronous modes uses clocks on
(b) It
transmitting and receiving devices.
uses a
'sync' signal, which is a bit pattern and
receiver can be easily recognised by u
(c) Awide variety of data
types can be
(d) A transmitted.
long series of bits can also be transmitted.
Q.39 Explain Hubs and repeaters in details.
March 02, 05, 09, 10, 18,Oct.06; July19
OR
What is Hub? Explain active and passive
Ans.
hab. March 2004,
2010, 2020
Hubs
(1) In some network topologies,
mostly ARCNET based star
used.
topologies, device
ae a hup
Computer. Science II-
TPS
5-24
Hub is a Networking Technology
(2) connecting
device in which
cables can be connected without
wires tocentralise network traffic through solderug
(3) It manages the a
single
cabling in the network and sends connecting point.
the network. signal to the other or
components
Figure shows a network
inter-connected with hub.
HUB
(4 Hubs are of three types:

i) Active hub i) Passive hub (ii) Switching hub
(5) The active hub interconnect the network and also amplifies the signal received
apart from splitting and retransmitting it to the destination. This hub contains
electronic circuits.
Passive hub only splits and transmits signal received and it can not amplify it. This
(6)
do not contain arny electronic component.
It be used
(7) Switching hub are quickly routes the signals between ports of hubs. can
in place of router.
ID Repeater
(Oct 2010, March 2018, 19
extend.
(1) A repeater is a mostly used in Ethernet to
hardware unit
to another.
and amplifies the signal from one Ethernet segment
(2) Arepeater reshapes
Figure shows network with repeaters
Repeater
Weak
Amplified
signal signal
to attach
repeater is used
and a
vertical up in the
building backbone cable.
A backbone cable the office to the
runs
each floor of
running in between them, if
an Ethernet segment more than two repeaters
No two Ethernet workstations

can have
communicate reliably. noise in the system.
they have to that they repeat
of repeaters is
(5) he main disadvantage
needed for repeaters.
(6) e p a r a t e power supply is
Networking Technolor
5-25
TPS Computer Science - I
(March 2006, 18,
routers. OR different types of Routers
S.
short note on list
Q.40 Write a
Network and
EXplain function
of Router in Oct. t.209
Ans.
connectivity
devices.
LANs can be
They
different e.g.
are used to
connect
the two
Conn.
(1) Kouters are

internetwork
LANs. i.e. the ey can be
similar or dissimilar and is assigned an addra
topologically LAN is logically
separate ddress.
and token ring. Each efficient delivery Dei.
of message. Delivs
(2)
ethernet
Routers can use network address to assist
network address
is called as routing. Routers
jiverng
packets according to logical
routing. to determine most efficient na
intelligent. They can use algorithms for
3) Routers are
network.
sending a packet to any given LANs into smaller segments.
(4) Routers can also be used to divide large, busy network (WAN).
LAN to wide area
(5) Routers are also employed to connect
(6) Routers are oftwo types
1. Static routers Dynamic routers
2.
Static routers do not determine paths, but you need to specify them. Dynamic rotter
havecapacity to determine paths (routes).
Write the functions of each of the following devices in short:
Q.41
(March 2008, 2011 Oct.2003, 2004,2005, 2007, 200
) Modem (ii) Repeater
(ii) Hub (iv) Routers
Ans.: (i) Modem:
(a) Modem means modulator / demodulator.
(b) It is used to connect computer to internet.
() Modem convert digital data to analog data and vice-a-versa.
ii) Hub
(a) Hub is a connecting device in which cables can be connected to centralize network
traffic through a single connecting point.
(b It manages the cabling in the network and sends signal to the other componentso
the network.
(iii) Repeater:
(a) A repeater reshapes and amplifies the signal from one network to
(iv) Routers another.
(a) Routers are internetwork
similar or dissimilar LANs.connectivity
devices used to connect two
topol cally
(b) Routers use algorithm to determine most
efficient path for sending a
given network. packet any
Q. 42 Explain the following terms
(a) Modem (March 2003
(b) Hub (c) Repeater
Ans.: Please refer Q. 36.
Q.43 Give atleast two
advantages and one
media. disadvantage of wireless media
l aover cable
ov 2014
March
Ans.: Advantages of wireless media:
(1) Communication can reach rural and hilly area.
(2) High data rate transmission by using
large bandwidth.
Science II
5-26 Networking Technology
TPSComputer
sadvantages
of wireless media
skilled labour require to install. This increases cost of network.
) disturb the signal.
EMI and outside noise
(2
Explain CP/IP protocol in detail. (March 2019)
.44
Ans. :
A protocol is defined as an agreement between communication particle for how

communication should be proceed.
protocols are rules by which computers communicates i.e. protocol is set of rules and
OR
formats for sending and receiving data.
General TCPIIP Transport Protocols

Intransport protocols there are two main forms of address: a node address and a
logical network address.
A node address
is the address of the entity of device on the Logical network
network.
address is the segment on the network to which node is attached.
network
TCP/IP uses numbering scheme. This number is IP address. All devices on
in value
need a unique IP address. An IP address is a set of four numbers, they can range
between 0 to 255. Each number is separated by period.
Forexample: 34.120.66.79 or 107.219.2.34

In class A, the number
There are three classes of address class A, class B and class C.
-
first number represent the network address.

between 1 and 127 appears before first dot. The
In 34.120.66.79, the host number is
The last three numbers represent the node or host number.
in value from 128 to 191. The
120.66.79 on network 34. In class B, the first number can range
forms host ID.
first two numbers forms network address and last two
223. The first three numbers make
In class C, the first number can range in from 192 to
up the network address and last number forms host ID.
Internet Protocol (IP)
protocol. It is packet switching protocolalso performs addressing
- that
P is connectionless
and routeselection. IP routes packets through internet
works. It performs disassembly
andreassembly. IP also performs errorchecking_
Q.45 Select the correct alternative and rewrite the following.
1. between two buildings.
cable type is ideal for connecting Co-axial (iv) Fibre optic
(i) UTP i ) STP (ii)
Ans. (iv) Fibre optic Hub.
made from centre point of
server or
2.
n topology connections are
) Bus (i) STAR (iii) RING iv) All of these
Ans. (i) STAR
3. is done by device namely
-
The process of modulation and demodulation

Router (iv) Modem
G) Hub (i) Repeater (iii)
Ans,:
4.
(iv) Modem cable l i m i t - i s used.
t h e network is to be extended beyond predefined
(March 2002)
(iv) Router
4) Modem (ii) Repeater (ii) Hub
Ans. (il) Repeater

CS2 TPS-2

Uploaded by

CS2 TPS-2

Uploaded by

1

Q. 2 Explain any two addressing modes in 8085. OR

of them with a suitab le example. tMEii• ►l•iM•ii•ki#IJ■ i•&l4mPl11H1jl!UP'

visit tpspoint.com for all chapters

Ans. : (I) Direct addressing mode : (Jul 201i, March 2018

visit tpspoint.com for all chapters

{4) These ar,e single by te instruc tions.

Q. 3 Explain register indirect. and immediate addressing modes in case of 8085

Accumulator 1 1 1 1 1 l 1 1 / l OOOO OOO O! Accumulator

visit tpspoint.com for all chapters

3) For example ADI 08 H

Q. 5 What are the different ways of clearing Accumulator (A = OOH) in single

visit tpspoint.com for all chapters

Q. 7 How instructions of 8085 are grouped according to its len.gth ?

_ P_C_O_D_E_ ____J First Byte

visit tpspoint.com for all chapters

Q. 8 Explain the followi ng instructions of 8085 microprocessor with suitable example.

visit tpspoint.com for all chapters

Ans. ; 1 (1111 11 , u1 11 11 1111

lt11n1( di,1h·· ,uk ht ¥i~J inp.

iii) )NC ad dr lum p on O\\ t Cfl fr)' (Cy • 0)

be "'al led nm dit ion all y ,rnd lrn

visit tpspoint.com for all chapters

(2) A subroutine can be called by two ways :

In conditional call, the subroutine is called only if the condition is satisfied. In

Q. 12 Explain return procedure in RET instruction.

visit tpspoint.com for all chapters

s tack poin ter.

be co.n tent of accumul at.o r atttr

{iJ C M A : ( \,rn pltm ent Hu- J ff um uL1

visit tpspoint.com for all chapters

(ii) ANI 05 H AND immediate da ta 05 H with [A]

visit tpspoint.com for all chapters

visit tpspoint.com for all chapters

(i) CMA (ii) ANI 09H (iii) JNR A

visit tpspoint.com for all chapters

conte nts of accum ulato r.

[E] = 7BH = 0 11110 1 1

Then , 45H = 010 001 01

XOR 7BH = 0 1111011

visit tpspoint.com for all chapters

(iii) ORI 58H:

(i) CMA (ii) ANI ACH (iii) INR A

(ii) ANI ACH :

This instruction is logically ANDed ACH with the contents of accumulator.

visit tpspoint.com for all chapters

[C] =ADH = 10101101

Result [A] = 0 0 0 0 1111 =OF H

visit tpspoint.com for all chapters

visit tpspoint.com for all chapters

wit h con ten ts of A.

Co mp lem ent car ry i

visit tpspoint.com for all chapters

(iii) LXI H, BABAH (iv) SPHL

Q. 27 Explain following instructions of 8085 microprocessor. 1\1.m.:h 200~)

visit tpspoint.com for all chapters

visit tpspoint.com for all chapters

visit tpspoint.com for all chapters

After ext.,>eution fAl = FFH

inst ruct ion CM A

A!\.1 E3H ~ Logically Mr oed E.3H wit

Aite-r exn "Utmn f A J = AJH --

m s.tn id ,on s ilN n tt1.tted ind ep~ nde

H . i.A..~ lult i, ~w 1_,,; H htt h l'\\.-.' Ufll U.hl tll?

visit tpspoint.com for all chapters

(ii) RRC - Rotate Accumulator Right

2's Complement of D = 1100 1101

Complement carry @] 01001100

visit tpspoint.com for all chapters

visit tpspoint.com for all chapters

Q. 45 Write the appropriate instructions for the followin g task:

Q. 47 The accumulator contains AA H and register C contains 55 H. What will be the .

visit tpspoint.com for all chapters

logical OR ope rati on = 1111 1111

1010 1010 l's no.

0101 :. SUB C = SSH