Performance Analysis of 16 bit Adders in high

speed computing applications

Dinesh Kumar J.R1 , Ganesh Babu. C2, Karthi S P3
1&3
Assistant Professor , Department of Electronics & Communication Engineering,
Sri Krishna College of Engineering & Technology,
Coimbatore,Tamil Nadu ,India
2
Professor , Department of Electronics & Communication Engineering,
Bannari Amman Institute of Technology2,
Sathyamangalam, Tamil Nadu ,India
dineshkumarjr@[Link].in1 ; bits_babu@[Link].in2

Abstract: The modern day of communication world mainly focus on Building a block of 16 bit adder using the 1 bit adder and
developing a highly organized architecture to perform high speed create this in top level model for implement the computing
computation with minimum power consumption. The various function of mixed signal processing applications.
architectures was developed to support computation in the fields like The 16 bit adders must be designed in such away that it
signal processing, data path communications, control and monitoring consumes less power and hold a low delay value when it is
applications. To perform the high speed computation the architecture used to generate physical address calculation related to
of Arithmetic logic unit (ALU) should be well organized in a manner memory mapping of processor, to perform faster operation
to reduce power , area & propagation delay. The functional block of interms of generating the output values such as increment or
ALU is adder. This paper elaborates the analysis of different adder decrement of pointer values of table pointer indication after
structure in terms of VLSI Parameters such as power, area and power the execution of the instruction. The 1 bit full adder is
delay product. The high speed computation are essential in mixed functioning by constructing a block of transistor with
data processing applications and these computation are developed as predefined values of 3 bit like X,Y & Z . These variables
blocks of FA to implement 16 bit of operations as a combination of
taken up to the total combination of 8 (23). For each
ripple carry adder (RcA),carry skip (CSKA) and bernt kung
combination the generated sum & carry part was different. To
adder(BkA).Those high speed adders produce the low value of
implement these kind of full adders, different adder
propagation delay when it is implemented using this proposed
architectures were developed [12] and latency and power is
architecture. The optimized structure of adders are developed by
consumed at the micron level. Hence the significance of full
combining the effects of two adders which is functionally differed.
The combined functionality of adder based on power & speed of
adder is not limited to the list where the large design part is to
computing The proposed methodology shows that power consumption
be considered. The typical design 16 bit full adder using [4]
is reduced by 43% ,power delay product by 20.9 % and propagation Ex nor & Ex or gates will approach 32 number of pass
delay by 46 % compared conventional method of analysis . and also transistor, 4 numbers of transmission gates, significance to the
provides the path to identify the effects of critical path delay and results of high usage of area and decisive level of
reduction it. improvement in power consumption for the full swing of
operations. The 16 bit Full adder is constructed by cascading
Keywords: Hybrid adder , ALU,KGSA,CSKA . the blocks of Ripple Carry adder or carry look ahead adder
technique. Whenever the adder size is improved the stability
[Link] of output is starts to deviated from the actual one and it is
depends on the bias[14] point of view. So the drive the signal
To support the different area of electronics and
with reliable and accurate the buffers are inserted at the nets of
communication field VLSI technology were developed and the
in & out. The 16 bit adders are implemented using pipeline
VLSI process mainly focus on miniature of the components as
concept to improve the speed of computation under the
well as power consumption[1]. These two things are related
condition the input nets are divisible as sub modules
with other parameters of VLSI such as area (Chip Size)
reduction and propagation delay. The emerging filed of
Portable devices for medical diagnosis requires systems with
less power consumption and high speed of computing. The
reduction of power is based on the switching activity of the
transistor in the ALU. It is said to be heart of the processor
and take the responsibilities of all computing operations. In
medical field the mixed signal processing devices should
deliver high accurate data in a stipulated time of operation[5].
To satisfy the requirements of mixed signal processing Fig 1.1 : 16 Bit adder using CLAL
applications it is intended to develop 1 bit full adder with
minimum no of transistor and analyze it power and delay.

978-1-7281-3250-1/19/$31.00 ©2019 IEEE

This paper organized as the sections of related circuits carried
out on different adder structures based on transistor count and
followed by proposed methodology and results of comparison.

II. RELATED WORKS

Full Adder Based on 28T Logic

It is important to construct the full adder which is the
base circuit of adder in arithmetic logic unit (ALU). The full Fig 2.2: Full Adder Based on 9T
adder accepts three bit of inputs namely A, B, C with the
combination of 8 set of test vectors and produce the sum According to the equation given above the sum signal is
output and display the carry generated [17] .The exclusive generated when any one of the input signal of adder is
operation of three input set generates the corresponding bit for relatively high. It is results in conduction of particular MOS
sum and the sum of multiplied operands (SOM) generated the device at the deep threshold level. When the signal Y (B) is
carry for all the combination of test vectors. Here the 28 zero then the M1 & M2 MOS of inverter pushes the carry to 1
number of CMOS transistor is used for performing 1 bit of and when the Y(B) is 1 , the carry is zero and the Sum signal
addition [12] which is costlier in a manner of gate count and is ‘1’. Hence it is optimum to perform the high speed of
chip area and it provides the stable outputs with drawback computation using the FA of 9T architecture.
large leakage current when MOS is operated in the weak
inversion level .
.

Fig 2.1 : Full Adder Based on 28T Fig 2.3: Full Adder Based on 6T

B)Full Adder Based on 9T Logic & 6T Logic The 6T based Full adder has[3] a good level of power
consumption at the deep sub micron level and compare to 9T
The no of transistor to implement the full adder [17] the chip area is reduced as the consequence of lower delay and
the gate count is very high[17]. So the topology of adder is to power consumption
be changed to bring out the better results as reducing the no of
C)RCA & CSA
transistor count [9] and also operating the MOS devices in the
sub threshold regions. When the threshold voltage is lower The previous section defines the full adder with 28T & 9T [9]
than the potential difference between Gate & Source creates & [17] logic consumes high power consumption and operating
the sub threshold current flow in the MOS transistor at the voltage is maximum[17] and have poor noise margin [9]. As a
same time the majority carriers repelled from the gate area of consequence of circuit for betterment of power that 6T Full
MOS and creates the minority carrier channel where the adder is defined to [3]bring low power consumption in sub or
current flows is happened and called as strong inversion weak inversion level. These adders operates with less delay
region opposite to this condition will makes the week and consequently have very low chip area as it has low
inversion area[9]. If the operating voltage is reduced below the transistor count .The adders for the high speed of computation
threshold, the MOS can be operated with low power especially in the mixed signal application the conventional
high speed adders like carry save adder , carry skip adder and
consumption. Let X, Y and Z used to indicate the input
burnt kung adder structures are connected with the Full adder
variables A,B & C.
block of 6T logic.
Sum_out = X ⊕ Y ⊕Zin ------- 2.1
Carry_out = X.Y + Y.Z + Z.X --- 2.2

978-1-7281-3250-1/19/$31.00 ©2019 IEEE

 construct the high speed adder at deep weak inversion layer at
the MOS regions. The 1 bit full adder with 9 MOS
transistors[20] produce the same result as 1 bit full adder using
28T [17] which describes early in this article. The sub
threshold region of MOS transistors reduce the level of low
power consumption and follows the general equation of
generating sum & carry based on XOR & AND operations.

Fig 2.4: Ripple carry adder based on 6T for 4 bit

The RCA has the disadvantage as no of bits and delay is

directly proportional. It is measured that for N stages the delay
is very high as well as power consumption is increased .

TRCA = TFA(A,{B to Cout}) + (N-2)TFA6T(Cin to Cout)

+ TFA6T(Cin to S) --------------2.3 Table 3.1: Full Adder Truth table -I

tadder = ( N-1 )Tcarry + Tsum -----------2.4 It is understand that from the truth table -I of full
adder of 1 bit using 9T structure is reducing the no of
the delay of worst case is T = O(N) , The Nth stage will variations (Mutli threshold variations) to set the sum & carry
generate the delay at tadder period [7]. The time delay of the outputs of the adder. When the MOS transistor M2 & M3 gets
RCA is calculated from the transition of bits of B to Cout and the voltage of A=0(1) & B=1(0) respectively, it produce the
Cin to Cout and also the transition of initial carry bit to final sum bit as logic 1 as per the operation of A Xor B at these
carrt is multiplied by the (N -2), where N is the no of stages in instant the value of Cin defines the output Sum[3]. When M6
is switched to get the logic high value yields the output of sum
RCA. To overcome the drawbacks of RCA at the Nth stages it
bit as low. The inverter operation of Cin recalled for the
is optimum to prefer the carry save adder which will take only
logic function of Sum, that is similar to connecting the Vdd to
N-2 stages of adder to compute the N no of addition. output of inverter whenever the PMOS gets the logic high
values. Similar to the 9T full adder design the 8T structure is
implemented[21] to measure the variation of power and chip
area at the sub threshold level of MOS. So that the no of inter
connect delay & capacitance is reduced and also improves the
quality of MOS devices interms of aspect ratios. The
interconnect value of the capacitance is arounf the value of 2pf
[21]. The 8T full adder variables are tabled to understand that
Input A will be consider to calculate the values of Sum &
carry of 1 bit Full adder which is defined with 8 no of Mos
[Link] 8T MOS will works as follows.
Fig 2.5: Carry save Adder based on FA6T
Sum = B ⊕Cin under A=0. --------3.1
Compare to the Nth stages delay of RCA [5], CSA will
Sum = ~(B ⊕Cin ) under A=1. -------3.2.
consumes less power as well as gates count too. The CSA
cannot be implemented for less bit number of addition as the
entire structures divide themselves as upper and lower blocks
of addition stages

III. PROPOSED METHODOLOGY

A) Hybrid Full adder Fig 3.1: Full Adder Based on 8T

The proposed techniques is mainly focus building the

16 bit adder from the base of 1 bit hybrid full adder [3] on the
basic level of power consumption and chip area reduction in
terms of transistor count decrement, Such that the no of
transistors reduced to 9 as discussed in the section 2 to

978-1-7281-3250-1/19/$31.00 ©2019 IEEE

 delay . usually the carry propagation is neglected at the nth
stage instead of rippling the carry addition operation. The
carry skip logic block is fixed in each rows of CSK structure
to identify the presence of carry which has to be included for
next stage or bypassed[8]. So that the propagation delay of
CSK & CBP are reduced much in the order of √N, [5], if N is
the no of bits to be perform addition. Unlike the RCA the
CKA & CBP will perform two operations associated with
AND & OR gate to find the generate & propagation bits
Table 3.2: Full Adder Truth table -II Generate(i) = A(i) AND B(i) ------3.3
Propagation(i) = A(i) XOR B(i) --3.4
The addition is the fundamental block in arithmetic
logic unit to perform the basic computation [7]. So the The i value is vary from 0 to n-1 , where n indicates the no of
optimization techniques is proposed here to reduce the gate bits
count and power consumption level. The supply voltage is
very less likely to be used as 0.4 V ,1.1 V ,1.8 V [6] ,the
different sub threshold voltage levels are fixed in blocks and
the mux based logic is implemented at the input side to
produce the sum as function of either A ⊕ B or ~(A ⊕ B).
Based on the mixed signal application the no of bits can be
expanded to the maximum by connecting the blocks of 4bit
BKA is a cascade sections as shown below[3]

Fig 3.5: Carry Look Ahead Adder based on FA6T

Burnt Kung Adder is another type of parallel prefix adder

which uses the basics of carry look ahead adder in which both
the bits generate and propagation bits are calculated by
performing the pre processing and post processing blocks with
Fig 3.2: Proposed Structure of 16 bit Adder using BKA & CSA
carry generation units
The 1 bit hybrid full adder is connected as cascaded
Generation block
blocks of 4 to built the ripple carry adder to perform the 4 bit
binary addition .The series blocks of 4 bit is used to Gene(i) = Gene(i) OR (Prop(i) AND Gene(i-1) ----3.5
consolided as parallel prefix adder to bringout the architecture
of 16 bit summer cirucit. With the logic of full adder based on Propagation block
6T [4] logic the power consumption is achieved but the speed
Prop(i) = Prop(i) AND Prop(i-1) ----3.6
of operation and the latency is not improved as expected in [7]
. as the consequence of module definining the very high speed Sum Generation block
adder BKA (Berunt Kung Adder) is defined with the logic of
[4] . When the no of bits of addition is less the BKA is good Sum(i) = Prop(i) XOR Gene(i-1) --3.7
enough with latency . This proposed design focus on 16bit of
operations, the CSA& CKA ( carry Save & Carry Select
Adder) is implementd to neglect the delay produced during the
iterations and Mux is also combined with proposed logic to
improve the speed of computation by dividing the entire
circuit based on the logic1 & Logic 0 operation , that is
defining the proposed blocks as upper & lower level of circuit
to reduce the propagation delay in order to bring the low
latency adder circuits.

b)CKA &CSA

Carry Skip adder & carry Bypass adder also used in

high speed applications[10] in order to redue the propagation

978-1-7281-3250-1/19/$31.00 ©2019 IEEE

 Fig 4.1 : Simulation circuit of 28T FA
FAcmos

v ( S u m FA C MO S)
2 . 5

2 . 0

Voltage (V)
1 . 5

1 . 0

0 . 5

0 . 0

1 2 3 4 5 6 7 8 9 1 0

Tim e (us )

FAcmos

5 . 0 v ( A )

4 . 5

4 . 0

Voltage (V)
3 . 5

3 . 0

2 . 5

2 . 0

1 . 5

1 . 0

0 . 5

0 . 0

1 2 3 4 5 6 7 8 9 1 0

Tim e (us )

FAcmos

5 . 0 v ( B )

4 . 5

4 . 0

Voltage (V)
3 . 5

3 . 0

2 . 5

2 . 0

1 . 5

1 . 0

0 . 5

0 . 0

1 2 3 4 5 6 7 8 9 1 0

Tim e (us )

FAcmos

5 . 5 v ( C n
i )

5 . 4

5 . 3

Voltage (V)
5 . 2

5 . 1

5 . 0

4 . 9

4 . 8

4 . 7

4 . 6

4 . 5

1 2 3 4 5 6 7 8 9 1 0

Tim e (us )

FAcmos

v ( C a r r y F A C MO S )
2 . 5

2 . 0

Voltage (V)
1 . 5

1 . 0

0 . 5

0 . 0

1 2 3 4 5 6 7 8 9 1 0

Tim e (us )

Fig 4.2 : Waveform of 28T FA

Fig 3.6: BKA based on FA6T

The BKA adder are based on log structure and takes Fig 4.3 : Simulation circuit of 8T FA
less no of stages to perform the addition of given n bits .The
gate level depth of propagtion is in th order of log (N) with
base of 2 .The complexity level & interconencts are very less
compare to the other high speed [Link] proposed
architecture of adder consists of KSA along with CAS adder
and mux logic is connected to select the carry output. Each
blocks of KSA is responsible for performing 4bit addition so
the cascaded structure of 4 no of KSA block produce the 16 Fig 4.4 : Waveform of 8T FA
bit adder for mixed signal processing applicaitions and their
results interms of propagation delay, power is discussed in the
next section.
IV .RESULTS & DISCUSSIONS

The circuits are simulted using Tanner EDA tool 14.0

hiper silicon full flow design tool with 90 nm Technology. All
the the results were obtained based on simulation of 1n to 1u.
The obtained results of Power , area & power area delay Fig 4.5 : Simulation circuit of 6T FA
products are tabulated. The power , propagation delay and
power delay product of the proposed system is measured and
it is compared with other architectetures based on other FA
technology. It is observed that the proposed KSA adder of 16
bit is consumes less power compared to exisiting method [2]
& [3] , the power level is reduced by the 43% & transistor
count is reduced by 4
Fig 4.6 : Waveform of 6T FA

Fig 4.7 : 4 bit KSA using 6T FA

978-1-7281-3250-1/19/$31.00 ©2019 IEEE
 Fig 4.8 : 8 bit KSA using 6T FA

Type of Various Parameter associated with device

Adder activity
Fig 4.9 : 16 bit KSA using 6T FA Transistors Power Delay PDP Logic
count (e-006) W (e-009) S Level
. FA1 28 93.1 46.24 4.318 7
FA2 8 56.8 37.96 2.156 7
The 16 bit optimised adder for using hybrid effect of KGA & FA3 9 61.8 32.12 1.908 7
FA of 6T logic is implemented here and the results are KGSA 56 71 31.06 2.203 2
tabulted as given above. Whenever adder length is increased (Existing )
the total no of transistor count is increased as it is proportional FA 6T 6 3.2 7.5 0.024 2
to each other and it is delaing with the blocks of cascded RCA using 28 24.6 28.1 0.691 2
6TFA
structues and also using of buffer unit [6] leads to the
CSA using 32 22.8 21.1 0.483 2
improvement of transistor count but these buffer sections 6TFA
ensuring that the signal driver delivers the maximum level of KGS using 42 31.2 14.4 0.449 2
signal to drive the output signals suchas sum & carry signal. 6TFA
By usage of carry skip block the carry level logic analysis can (proposed)
be eliminated during the itearation process of multi bit 16 bit KGS 168 24.2 32.2 0.779 4
using 6TFA
additions . (proposed)
Results Comparision

V .Conclusion

This paper gives the brief idea about architectures of

different adder associated with mixed signal processing
applications. The proposed network of KSA with 16 bit is uses
full adder with 6T logic. The no of transistor count is reduced
from conventional of 28T logic. Hence the no of transistor
count is reduced to perform the same operation, the switching
speed of the MOS isimproved which yields the eneromous
amount reduction in propagation delay and reduce the power
at the ultra level as this MOS are opaerated at the sub
threshold regions. It is measured that power consumption is
reduced by 43% ,power delay product by 20.9 % and
propagation delay by 46 %. This results ensures that the
proposed network can be used in mixed signal application like
978-1-7281-3250-1/19/$31.00 ©2019 IEEE
portable computing devices, portable devices with high speed [14] “Low Power Hybrid 1-Bit Full Adder Circuit
of computing and lower power consumption as it increse the Optimization”, by Anil Kumar S.K, Fairooz S.K, International
stand by power of the devices Journal of Engineering Science and Computing, June 2016.
[15] “Hybrid adders for high-speed arithmetic circuits: A
REFERENCES comparison,” by M. L. Aranda, R. Báez, and O. G. Diaz, in
Proc. 7th IEEE Int. Conf. Elect. Eng. Comput. Sci. Autom.
Control (CCE), Tuxtla Gutierrez, NM, USA,, pp. 546–549,
Sep. 2010.
[1] “Design of Carry Select Adder for Low-Power and High
[16]”Performance and Analysis of 28T Full Adder using SVL
Speed VLSI Applications” by M. Vinod Kumar Naik,
Technique for Reducing Leakage Current at 45 nm
Mohammed Aneesh. Y 978-1-4799-6085-9/15/ 2015 IEEE
Technology” by Vinod Agarawal , Ravi Shiravastav , Sourabh
[2] “A new 16-bit high speed and variable stage carry skip
Khandelwal , Shyam Akashe by IOSR Journal of VLSI and
adder” by Anjali Arora DOI 10.1109/CIACT.2017.7977359
Signal Processing
INSPEC Accession Number: 17029644 ,IEEE 2017
[17] “CMOS Based One Bit Full Adder Cell for Low Power
[3] “A new design 6T Full Adder Circuit using Novel 2T
Delay” by Product Garg, D., Rai, M. K. 2012. IJECCT. vol.
XNOR Gates” by Krishna Chandra,Rajeev Kumar, Shashank
2, issue. 4, pp. 18- 23.
Uniyal, Vishal Ramola in IOSR Journal of VLSI and Signal
[18]“Full adder Design using Hybrid Technology”, by Ankita
Processing (IOSR-JVSP) 2015
Gupta, Rajeev Thakur,International Journal of Computer
[4] “ Design and Analysis of one bit Hybrid full Adder using
Applications (0975 – 8887) Volume 130 – No.7,
pass transistor Logic” by Rakesh Chowdary Gutta IJPAM
November2015.
2017
[19] “A power efficient carry save adder and modified carry
[5] Comparison of high performance VLSI adders in the
save adder using CMOS technology”, by [Link] ,
energy-delay space” by V. G. Oklobdzija, B. R. Zeydel, H. Q.
[Link], 2013 , 978-1-4799-1597-2/13 2013 IEEE
Dao, S. Mathew, and R. Krishnamurthy,ǁ IEEE Trans. Very
[20] “1-Bit Hybrid Full Adder by GDI and PTL Technique”,
Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 754–758,
by KshitijShant, Rita Mahajan, International Journal of
Jun.2005.
Innovative Research in Computer and Communication
[6] “Low power adder with adaptive supply voltage”, by H.
Engineering Vol. 4, Issue 5, May 2016.
Suzuki, W. Jeong, and K. Roy, ǁ in Proc. 21st Int. Conf.
[21]Low Power Full Adder Using 8T Structure by Amin
Comput. Design, Oct. 2003, pp. 103–106.
Bazzazi, Member, IAENG, Alireza Mahini and Jelveh Jelini
[7] “A review analysis of parallel prefix adders for better
,IMECS ,2012
performnce in VLSI applications” by K. S. Vijula Grace S.
[22]. “Permormance Analysis of Low Power 1-Bit CMOS full
Daphni DOI 10.1109/ICCS1.2017.8325971 IEEE 2017
adder cells”, A. M. Shams, T. K. Darwish and M. A. Bayoumi
[8] “A Review of 0.18um Full Adder Performances for Tree
IEEE Transaction on VLSI Systems, Vol. 10, Feb. 2002
Structured Arithmetic Circuits,” by Chip-Hong Chang,
Jiangmin Gu and Mingyan Zhang, IEEE Transactions On [23]”Performance analysis of high speed low power carry-
Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 6, lookahead adder using different logic styles” by
JUNE 2005. Jagannath Samanta, Mousam Halder and Bishnu Prasad De
[9]Research Article on 9T Full Adder Design in Subthreshold International Journal of Soft Computing and Engineering
Region by Shiwani Singh, Tripti Sharma K. G. Sharma, and B. (IJSCE), vol. 2, issue 6, pp. 330- 336, Jan- 2013.
P. Singh by Hindwai Publications ,2016
[10] “Design of Hybrid (CSA-CSkA) Adder for Improvement Biography
of Propagation Delay” by Sujan Sarkar & Jishan Mehedi .
IEEE, 2017. Dinesh Kumar. J.R , currently working as Assistant Professor in SKCET and
his area of research focus on VLSI, Arithmetic circuit optimization, Signal
[11] “Performance analysis of a low-power high-speed hybrid processing and circuit. He is having 6 years of experience in teaching and
1-bit full adder circuit using cmos technologies using research. Life time member of ISTE.
cadence” by Megha R & Vishwanath B R , volume 04 ,
IRJET 2017, Dr. C. Ganesh Babu, currently working as Professor in BITS, Sir having
experience of more than 20 Years in research and teaching and published
[12] “Survey on Consummation of Subsided Power and High more than 25 papers in h-indexed journals and guiding 6 scholars under the
Speed Adders For Mixed Signal Processing Applications ,by Anna University. His area of interest are Signal Processing ,VLSI in Medical
J.R. Dinesh Kumar, Dr. C. Ganesh Babu IJPAM, 2018. electronics and he is holding life time membership in IEEE.
[13] “High Speed Area Efficient 1-Bit Hybrid Full Adder”, by
Sachin Kumar, Aman Kumar, Puneet BansaConference Paper Karthi. S.P , currently working as Assistant Professor in SKCET and his area
of interest are Wireless communication, Fuzzy systems, VLSI, Signal
March 2016. processing. He is having 4 years of experience in teaching and research and
also Life time member of ISTE.

978-1-7281-3250-1/19/$31.00 ©2019 IEEE