Computer Architecture and

Organization (NCP 2201)

Introduction and Top-Level View

of Computer Function and
Interconnection

Dr. Joan P. Lazaro, PCpE

Professor
LEARNING OUTCOMES:
Upon completion of the topic, the learner
will be able to:
 Understand the difference of Computer
Architecture from Computer Organization;
 Explain the general functions and structure
of a digital computer;
 Describe the concept of interconnection
within a computer system;
 Understand the different classification bus.
Architecture & Organization
 Computer Architecture refers to those
attributes of a system visible to a
programmer or those attributes that have a
direct impact on the logical execution of a
program
 Architectural attributes:
◦ Instruction set
◦ Number of bits used for data representation
◦ I/O mechanisms
◦ Techniques for addressing memory

e.g. Is there a multiply instruction?

Architecture & Organization
 Computer Organization is how features are
implemented. It refers to the operational
units and their interconnections that realize
the architectural specifications.
 Organizational attributes:
◦ Control signals
◦ Interfaces between the computer and peripherals
◦ Memory technology used

e.g. Is there a hardware multiply unit or is it done

by repeated addition?
Structure & Function
 Structure is the way in which components
relate to each other

 Function is the operation of individual

components as part of the structure
Function
 Basic computer functions are:
◦ Data processing
◦ Data storage
◦ Data movement
◦ Control
Functional View
Operations (a) Data movement
Operations (b) Storage
Operation (c) Processing from/to
storage
Operation (d)
Processing from storage to I/O
 Structure - Top Level

Peripherals Computer

Central Main
Processing Memory
Unit

Computer
Systems
Interconnection

Input
Output
Communication
lines
4 MAIN STRUCTURAL
COMPONENTS OF COMPUTER
1. Central Processing Unit (CPU) – controls
the operation of the computer and
performs its data processing functions.
2. Main Memory – stores data
3. I/O – move data between the computer
and its external environment.
4. System Interconnection – some mechanism
that provides for communication among
CPU, main memory, and I/O.
 Structure - The CPU

CPU

Computer Arithmetic
Registers and
I/O Login Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control
Unit
4 MAIN STRUCTURAL
COMPONENTS OF CPU
1. Control Unit – controls the operation
of the CPU and hence the computer.
2. ALU – performs the computer’s data
processing function.
3. Registers – provides storage internal to
the CPU.
4. CPU Interconnection – some
mechanism that provides
communication among the control unit,
ALU, and registers.
 Structure - The Control Unit

Control Unit

CPU
Sequencing
ALU Logic
Control
Internal
Unit
Bus
Control Unit
Registers Registers and
Decoders

Control
Memory
3 MAIN STRUCTURAL COMPONENTS
OF CONTROL UNIT
 SEQUENCING LOGIC – is used to
construct finite state machines, as well as
memory circuits and other devices.
 CONTROL UNIT REGISTERS AND
DECODERS – these are the instruction
register and program counter and are
used together with the instruction
decoder in the execution cycle.
 CONTROL MEMORY – can be a read-
only memory.
Computer Components:
Top Level View
COMPUTER COMPONENTS
 PC – holds the address of the instruction
to be fetched next.
 MAR – specifies the address in memory
for the next read or write.
 MBR – contains the data to be written
into memory or receives the data read
from memory.
 IR – a register in the processor where the
fetched instruction is loaded.
COMPUTER COMPONENTS
 I/O AR – specifies a particular I/O device.
 I/O BR – used for the exchange of data
between an I/O module and the CPU.
Instruction Cycle
 Two steps:
◦ Fetch
◦ Execute
Fetch Cycle
 Program Counter (PC) holds address of
next instruction to fetch
 Processor fetches instruction from memory
location pointed to by PC
 Increment PC
◦ Unless told otherwise
 Instruction loaded into Instruction Register
(IR)
 Processor interprets instruction and
performs required actions
Execute Cycle
 Processor-memory
◦ data transfer between CPU and main memory
 Processor-I/O
◦ Data transfer between CPU and I/O module
 Data processing
◦ Some arithmetic or logical operation on data
 Control
◦ Alteration of sequence of operations
◦ e.g. jump
 Combination of above
Example of Program Execution
STEPS:
 Three instructions, which can be described as
three fetch and three execute cycles, are
required:
1. The PC contains 300, the address of the first
instruction. This instruction (the value 1940 in
hexadecimal) is loaded into the instruction
register IR, and the PC is incremented. Note that
this process involves the use of a memory
address register and a memory buffer register. For
simplicity, these intermediate registers are
ignored.
STEPS:
2. The first 4 bits (first hexadecimal digit) in the IR
indicate that the AC is to be loaded. The
remaining 12 bits (three hexadecimal digits)
specify the address (940) from which data are to
be loaded.
3. The next instruction (5941) is fetched from
location 301, and the PC is incremented.
4. The old contents of the AC and the contents of
location 941 are added, and the result is stored in
the AC.
STEPS:
5. The next instruction (2941) is fetched
from location 302, and the PC is
incremented.
6. The contents of the AC are stored in
location 941.
What is a Bus?
• A communication pathway connecting two or
more devices
• Usually broadcast
• Often grouped
—A number of channels in one bus
—e.g. 32 bit data bus is 32 separate single bit
channels

Classification: Data Bus, Address Bus and

Control Bus
Data Bus
 It carries data
◦ Remember that there is no difference
between “data” and “instruction” at this
level
 Width is a key determinant of
performance
◦ 8, 16, 32, 64 bits
Address Bus
 It identify the source or destination of
data
 e.g. CPU needs to read an instruction
(data) from a given location in memory
 Bus width determines maximum memory
capacity of system
◦ e.g. 8080 has 16 bit address bus giving
64k address space
Control Bus
 It is use for control and timing
information
◦ Memory read/write signal
◦ Interrupt request
◦ Clock signals
Bus Interconnection Scheme
What do buses look like?
◦ Parallel lines on circuit boards
◦ Ribbon cables
◦ Strip connectors on mother boards
 e.g. PCI
◦ Sets of wires
Physical Realization of Bus
Architecture
Single Bus Problems
 Lots of devices on one bus leads to:
◦ Propagation delays
 Long data paths mean that
coordination of bus use can adversely
affect performance
 If aggregate data transfer approaches
bus capacity
 Most systems use multiple buses to
overcome these problems
Traditional ISA (with cache)
High Performance Bus
Bus Types
1. Dedicated
◦ Separate data & address lines
2. Multiplexed
◦ Shared lines
◦ Address valid or data valid control line
◦ Advantage - fewer lines
◦ Disadvantages
 More complex control
 Ultimate performance
Bus Arbitration
 More than one module controlling the
bus
 e.g. CPU and DMA controller
 Only one module may control bus at one
time
 Arbitration may be centralized or
distributed
Centralized or Distributed
Arbitration
 Centralized
◦ Single hardware device controlling bus
access
 Bus Controller
 Arbiter
◦ May be part of CPU or separate
 Distributed
◦ Each module may claim the bus
◦ Control logic on all modules
SAP – 1 COMPUTER
(Part 1)
Dr. Joan P. Lazaro

NCP 2201 – Computer System Architecture

and Organization
LEARNING OUTCOMES:
Upon completion of this topic, the learner will be
able to:
 Examine the different components of SAP-1
computer;
 Analyze the different instruction sets in SAP-
1 computer;
 Create the program using the instruction sets
of SAP-1 computer.
INTRODUCTION
A. SAP -1
ARCHITECTURE
SAP -1 ARCHITECTURE
 The figure shows the architecture (structure)
of SAP-1, a bus organized computer.
 All register outputs to the W bus are three-
state; this allows orderly transfer of data.
 All other register outputs are two-state, these
outputs continuously drive the boxes they are
connected to.
PROGRAM COUNTER
PROGRAM COUNTER
PROGRAM COUNTER
Input and Memory Address
Register (MAR)
 Below the program counter is the Input and
MAR block.
 It includes the address and data switch
registers.
 These switch registers, which are part of the
input unit, allows you to send 4 address bits
and 8 data bits to the RAM.
 As you recall, instruction and data words are
written into the RAM before a computer run.
Input and MAR
RAM
 The RAM is a 16 x 8 static TTL RAM.
 You can program the RAM by means of the
address and data switch registers.
 This allows you to store a program and data in
the memory before a computer run.
RAM
INSTRUCTION REGISTER
CONTROLLER-SEQUENCER
CONTROLLER-SEQUENCER
CONTROLLER-SEQUENCER
CONTROLLER-SEQUENCER
ACCUMULATOR
ADDER-SUBTRACTER
B REGISTER
OUTPUT REGISTER
 At the end of a computer run, the accumulator
contains the answer to the problem being
solved. At this point, we need to transfer the
answer to the outside world. This is where the
output register is used.
 When EA is high and LO is low, the next
positive clock edge loads the accumulator
word into the output register.
OUTPUT REGISTER
 The output register is often called an output
port because processed data can leave the
computer through this register.
 In microcomputers the output ports are
connected to interface circuits that drive
peripheral devices like printers, cathode-ray
tubes, teletypewriters, and so forth.
BINARY DISPLAY
SUMMARY
B. INSTRUCTION SET
INSTRUCTION SETS
1. LDA
2. ADD
3. SUB
4. OUT
5. HLT
LDA
ADD
ADD
SUB
SUB
SUB
OUT
HLT
MEMORY-REFERENCE
INSTRUCTIONS
MNEMONICS
SAP-1 INSTRUCTION SET
8080 AND 8085
MICROPROCESSOR
8080 AND 8085
MICROPROCESSOR
PROGRAMMING SAMPLE #1:
SOLUTION:
The program is in the low memory, located at address
0H to 5H. The first instruction loads the accumulator
with
SOLUTION:
C. SAP-1 PROGRAMMING
SAP-1 OP CODE
SAP-1 PROGRAMMING
SAP-1 PROGRAMMING
SAP-1 PROGRAMMING
SAMPLE PROGRAM #2:
Translate the program
of Example 1 into SAP-
1 machine language.

SOLUTION:
SOLUTION:
SOLUTION:
SAMPLE PROGRAM #3:
SOLUTION: (Assembly language)
SOLUTION: (Machine language)
CONT...
SAMPLE PROGRAM #4:
Chunk the program and data in Example #3 by
converting to hexadecimal shorthand.
SOLUTION:
Address Contents
0H 09H
1H 1AH
2H 1BH
SOLUTION
SAP – 1 COMPUTER
(Part 2)
Dr. Joan P. Lazaro

NCP 2201 – Computer System Architecture

and Organization
LEARNING OUTCOMES:
Upon completion of this topic, the learner will be
able to:
 Understand fetch cycle and execution cycle;

 Differentiate machine cycle from instruction

cycle;
 Distinguish microinstructions from
macroinstructions.
A. FETCH CYCLE
Fig. 1: RING COUNTER SYMBOL
RING COUNTER
The ring counter in
Figure 1 has an
output:
Fig. 2: RING COUNTER CLOCK AND
TIMING SIGNALS
RING COUNTER CLOCK AND
TIMING SIGNALS
 Figure 2 shows the timing pulses out of the ring
counter.
 The initial state T1 starts with a negative clock edge
and ends with the next negative clock edge. During
this T state, the T1 bit out of the ring counter is high.
 During the next state T2 is high; the following state
has a high T3; then a high T4; and so on.
 As you can see, the ring counter produces six T
states. Each instruction is fetched and execute during
these six T states.
ADDRESS STATE
ADDRESS STATE (Fig. 10-3a)
INCREMENT STATE
INCREMENT STATE (Fig. 10-3b)
MEMORY STATE
MEMORY STATE (Fig. 10-3c)
FETCH CYCLE (SUMMARY)
FETCH CYCLE (SUMMARY)
B. EXECUTION CYCLE
LDA ROUTINE
LDA ROUTINE
LDA ROUTINE
LDA ROUTINE
LDA ROUTINE
FETCH AND LDA TIMING
DIAGRAM
ADD ROUTINE
ADD ROUTINE
ADD ROUTINE
ADD ROUTINE
ADD ROUTINE
FETCH AND ADD
TIMING DIAGRAM
FETCH AND ADD TIMING
DIAGRAM
SUB ROUTINE
OUT ROUTINE
OUT ROUTINE
OUT ROUTINE (Fig. 10-8)
OUT ROUTINE
OUT ROUTINE
HLT

the instruction field 1111 signals the controller-sequencer

to stop processing data. The controller-sequencer stops the
computer by turning off the clock.
MACHINE CYCLE AND
INSTRUCTION CYCLE
MACHINE CYCLE AND
INSTRUCTION CYCLE (Fig. 10-10a)
MACHINE CYCLE AND
INSTRUCTION CYCLE
MACHINE CYCLE AND
INSTRUCTION CYCLE (Fig. 10-10b)
MACHINE CYCLE AND
INSTRUCTION CYCLE
MACHINE CYCLE AND
INSTRUCTION CYCLE
 EXAMPLE #1:
 The 8080/8085 programming manual says
that it takes thirteen (13) T states to fetch and
execute the LDA instruction.

If the system clock has a frequency of 2.5MHz,

how long is an instruction cycle?
MACHINE CYCLE AND
INSTRUCTION CYCLE
MACHINE CYCLE AND
INSTRUCTION CYCLE
 EXAMPLE #2:
MACHINE CYCLE AND
INSTRUCTION CYCLE
MACHINE CYCLE AND
INSTRUCTION CYCLE
C. SAP-1 MICROPROGRAM
SAP-1 MICROPROGRAM
SAP-1 MICROPROGRAM
SAP-1 MICROPROGRAM
SAP-1 MICROPROGRAM
SAP-1 MICROPROGRAM