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Introduction to Computer Architecture and Organization

The document provides an overview of computer architecture and organization, distinguishing between architecture as the attributes visible to programmers and organization as the implementation of those attributes. It outlines the main components of a computer system, including the CPU, main memory, I/O, and system interconnection, as well as detailing the instruction cycle and bus types. Additionally, it discusses the roles of various components within the CPU and the importance of buses in facilitating communication between devices.

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2 views

Introduction to Computer Architecture and Organization

The document provides an overview of computer architecture and organization, distinguishing between architecture as the attributes visible to programmers and organization as the implementation of those attributes. It outlines the main components of a computer system, including the CPU, main memory, I/O, and system interconnection, as well as detailing the instruction cycle and bus types. Additionally, it discusses the roles of various components within the CPU and the importance of buses in facilitating communication between devices.

Uploaded by

Tim
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Computer Architecture and

Organization (NCP 2201)

Introduction to Computer
Architecture and Organization

Dr. Joan P. Lazaro, PCpE


Professor
LEARNING OUTCOMES:
Upon completion of the topic, the learner
will be able to:
 Understand the difference of Computer
Architecture from Computer Organization;
 Explain the general functions and structure
of a digital computer;
 Describe the concept of interconnection
within a computer system;
 Understand the different classification of
bus.
Architecture & Organization
 Computer Architecture refers to those
attributes of a system visible to a
programmer or those attributes that have a
direct impact on the logical execution of a
program
 Architectural attributes:
◦ Instruction set
◦ Number of bits used for data representation
◦ I/O mechanisms
◦ Techniques for addressing memory

e.g. Is there a multiply instruction?


Architecture & Organization
 Computer Organization is how features are
implemented. It refers to the operational
units and their interconnections that realize
the architectural specifications.
 Organizational attributes:
◦ Control signals
◦ Interfaces between the computer and peripherals
◦ Memory technology used

e.g. Is there a hardware multiply unit or is it done


by repeated addition?
Structure & Function
 Structure is the way in which components
relate to each other

 Function is the operation of individual


components as part of the structure
Function
 Basic computer functions are:
◦ Data processing
◦ Data storage
◦ Data movement
◦ Control
Functional View
Operations (a) Data movement
Operations (b) Storage
Operation (c) Processing from/to
storage
Operation (d)
Processing from storage to I/O
Structure - Top Level

Peripherals Computer

Central Main
Processing Memory
Unit

Computer
Systems
Interconnection

Input
Output
Communication
lines
4 MAIN STRUCTURAL
COMPONENTS OF COMPUTER
1. Central Processing Unit (CPU) – controls
the operation of the computer and
performs its data processing functions.
2. Main Memory – stores data
3. I/O – move data between the computer
and its external environment.
4. System Interconnection – some mechanism
that provides for communication among
CPU, main memory, and I/O.
Structure - The CPU

CPU

Computer Arithmetic
Registers and
I/O Login Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control
Unit
4 MAIN STRUCTURAL
COMPONENTS OF CPU
1. Control Unit – controls the operation
of the CPU and hence the computer.
2. ALU – performs the computer’s data
processing function.
3. Registers – provides storage internal to
the CPU.
4. CPU Interconnection – some
mechanism that provides
communication among the control unit,
ALU, and registers.
Structure - The Control Unit

Control Unit

CPU
Sequencing
ALU Logic
Control
Internal
Unit
Bus
Control Unit
Registers Registers and
Decoders

Control
Memory
3 MAIN STRUCTURAL COMPONENTS
OF CONTROL UNIT
 SEQUENCING LOGIC – is used to
construct finite state machines, as well as
memory circuits and other devices.
 CONTROL UNIT REGISTERS AND
DECODERS – these are the instruction
register and program counter and are
used together with the instruction
decoder in the execution cycle.
 CONTROL MEMORY – can be a read-
only memory.
Computer Components:
Top Level View
COMPUTER COMPONENTS
 PC – holds the address of the instruction
to be fetched next.
 MAR – specifies the address in memory
for the next read or write.
 MBR – contains the data to be written
into memory or receives the data read
from memory.
 IR – a register in the processor where the
fetched instruction is loaded.
COMPUTER COMPONENTS
 I/O AR – specifies a particular I/O device.
 I/O BR – used for the exchange of data
between an I/O module and the CPU.
Instruction Cycle
 Two steps:
◦ Fetch
◦ Execute
Fetch Cycle
 Program Counter (PC) holds address of
next instruction to fetch
 Processor fetches instruction from memory
location pointed to by PC
 Increment PC
◦ Unless told otherwise
 Instruction loaded into Instruction Register
(IR)
 Processor interprets instruction and
performs required actions
Execute Cycle
 Processor-memory
◦ data transfer between CPU and main memory
 Processor-I/O
◦ Data transfer between CPU and I/O module
 Data processing
◦ Some arithmetic or logical operation on data
 Control
◦ Alteration of sequence of operations
◦ e.g. jump
 Combination of above
Example of Program Execution
STEPS:
 Three instructions, which can be described as
three fetch and three execute cycles, are
required:
1. The PC contains 300, the address of the first
instruction. This instruction (the value 1940 in
hexadecimal) is loaded into the instruction
register IR, and the PC is incremented. Note that
this process involves the use of a memory
address register and a memory buffer register. For
simplicity, these intermediate registers are
ignored.
STEPS:
2. The first 4 bits (first hexadecimal digit) in the IR
indicate that the AC is to be loaded. The
remaining 12 bits (three hexadecimal digits)
specify the address (940) from which data are to
be loaded.
3. The next instruction (5941) is fetched from
location 301, and the PC is incremented.
4. The old contents of the AC and the contents of
location 941 are added, and the result is stored in
the AC.
STEPS:
5. The next instruction (2941) is fetched
from location 302, and the PC is
incremented.
6. The contents of the AC are stored in
location 941.
What is a Bus?
• A communication pathway connecting two or
more devices
• Usually broadcast
• Often grouped
—A number of channels in one bus
—e.g. 32 bit data bus is 32 separate single bit
channels

Classification: Data Bus, Address Bus and


Control Bus
Data Bus
 It carries data
◦ Remember that there is no difference
between “data” and “instruction” at this
level
 Width is a key determinant of
performance
◦ 8, 16, 32, 64 bits
Address Bus
 It identify the source or destination of
data
 e.g. CPU needs to read an instruction
(data) from a given location in memory
 Bus width determines maximum memory
capacity of system
◦ e.g. 8080 has 16 bit address bus giving
64k address space
Control Bus
 It is use for control and timing
information
◦ Memory read/write signal
◦ Interrupt request
◦ Clock signals
Bus Interconnection Scheme
What do buses look like?
◦ Parallel lines on circuit boards
◦ Ribbon cables
◦ Strip connectors on mother boards
 e.g. PCI
◦ Sets of wires
Physical Realization of Bus
Architecture
Single Bus Problems
 Lots of devices on one bus leads to:
◦ Propagation delays
 Long data paths mean that
coordination of bus use can adversely
affect performance
 If aggregate data transfer approaches
bus capacity
 Most systems use multiple buses to
overcome these problems
Traditional ISA (with cache)
High Performance Bus
Bus Types
1. Dedicated
◦ Separate data & address lines
2. Multiplexed
◦ Shared lines
◦ Address valid or data valid control line
◦ Advantage - fewer lines
◦ Disadvantages
 More complex control
 Ultimate performance
Bus Arbitration
 More than one module controlling the
bus
 e.g. CPU and DMA controller
 Only one module may control bus at one
time
 Arbitration may be centralized or
distributed
Centralized or Distributed
Arbitration
 Centralized
◦ Single hardware device controlling bus
access
 Bus Controller
 Arbiter
◦ May be part of CPU or separate
 Distributed
◦ Each module may claim the bus
◦ Control logic on all modules

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