Spring 2022: Mixed Signal IC Design EE5005 1/9

LAB-9 (Tutorial)
Sigma-Delta Converters Design and
Simulations
(Cadence ADE)
Dr. Hassan Saif
Abdul Wajid

Electrical Engineering Department

National University of Computer & Emerging Sciences
(FAST-NU)
Islamabad-44000, Pakistan
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1. Introduction
Oversampling A/D and D/A converters are popular for high-resolution medium-to-low-speed
applications such as high-quality digital audio and baseband signal processing in some wireless
systems. A major reason for their popularity is that oversampling converters relax the requirements
placed on the analog circuitry at the expense of more complicated digital circuitry. This tradeoff
became desirable with the advent of deep submicron CMOS technologies as complicated high-
speed digital circuitry became more easily realized in less area, but the realization of high-
resolution analog circuitry was complicated by the low power-supply voltages and poor transistor
output impedance caused by short-channel effects. With oversampling data converters, the analog
components have reduced requirements on matching tolerances and amplifier gains. Oversampling
converters also simplify the requirements placed on the analog anti-aliasing filters for A/D
converters and smoothing filters for D/A converters. For example, usually only a first- or second-
order anti-aliasing filter is required for A/D converters, which can often be realized very
inexpensively. Furthermore, a sample-and-hold is usually not required at the input of an
oversampling A/D converter.

1.1 OVERSAMPLING WITH NOISE SHAPING

The advantage of noise shaping the quantization noise through the use of feedback is
discussed. Here, we shall see a much more dramatic improvement in dynamic range when the input
signal is oversampled as compared to oversampling the input signal with no noise shaping.
The system architecture of an oversampling A/D converter is shown in Fig. 1. The first
stage is a continuous-time anti-aliasing filter and is required to band-limit the input signal to
frequencies less than one-half the oversampling frequency, fs. When the oversampling ratio is large,
the anti-aliasing filter can often be quite simple, such as a simple RC low-pass filter. Following the
anti-aliasing filter, the continuous-time signal, Xc(t), is sampled by a sample and hold. This signal
is then processed by the modulator, which converts the analog signal into a noise-shaped low-
resolution digital signal. The third block in the system is a decimator. It converts the oversampled
low-resolution digital signal into a high-resolution digital signal at a lower sampling rate usually
equal to twice the frequency of the desired bandwidth of the input signal. The decimation filter can
be conceptually thought of as a low-pass filter followed by a down sampler, although in many
systems the decimation is performed in a number of stages. It should be mentioned that in many
realizations where the modulator is realized using switched-capacitor circuitry, a separate sample-
and-hold is not required, as the continuous-time signal is inherently sampled by the switches and
input capacitors of the SC ∑∆.

Fig 1: Block diagram of an oversampling converter

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1.2 Noise-Shaped Delta-Sigma Modulator

A general noise-shaped delta-sigma (∑∆ ) modulator and its linear model are shown
in Fig. 2. This arrangement is known as an interpolative structure and is analogous to an
amplifier realized using an opamp and feedback. In this analogy, the feedback reduces the
effect of the noise of the output stage of the opamp in the closed loop amplifier’s output
signal at low frequencies when the opamp gain is high. At high frequencies, when the
opamp’s gain is low, the noise is not reduced. Note that the quantizer here is shown for the
general case where many output levels occur. While many oversampling converters make
use of 1-bit quantizers (i.e., only two output levels).
Treating the linear model shown in Fig. 2(b) as having two independent inputs (which is
an approximation), we can derive a signal transfer function, STF(z), and a noise transfer
function, NTF(z).

Fig 2: A modulator and its linear model

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1.2 Switched-Capacitor Realization of a First-Order A/D Converter

It is possible to realize a first-order modulator using switched-capacitor (SC)

techniques. An example of a first-order modulator where a 1-bit quantizer is used in the
feedback loop is shown in Fig. 3. Here, the ∑∆ modulator consists of both analog and
digital circuitry.

Fig 3: First-order A/D modulator: (a) block diagram; (b) switched-capacitor implementation.
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2. Cadence Environment Setup

This tutorial assumes you know how to start cadence and have already launched the program in the proper
working directory. We will be using tsmc13rf 130nm CMOS process for these LABs.

Creating a new Schematic

• Make a new library Mix_IC in Cadence Library Manager. (File→New→library)
• Select reference existing technology libraries than select tsmc13rf add it into reference technology
libraries than press OK.
• Create a new schematic cell in Mix_IC (put a meaningful name relevant to the design).
(File→New→Cell View).
• Click the OK button. The Composer schematic editing tool will open with an empty Schematic
Editing window.

Adding components
• In the Schematic Editing Window Select Add => Instance to activate the Add Instance tool for
adding components (transistors, sources, etc.) to your schematic. You can also invoke this tool by
clicking on the Instance icon on the left-hand toolbar, or by pressing the hot key ‘i’. Two windows
(Component Browser window and Add Instance) will pop open.
• In add instance window browse tsmc13rf library from cells select nmos3v or pmos3v which is
low Vth CMOS click on symbol and place into schematic. (create→instance→tsmc13rf→
nmos3v). NOTE: You can also rotate a component by selecting Edit => Rotate or by typing the
hot key “r”.
• Right click on transistor select properties or hot key “q” here you change the number of fingers,
finger width and length of transistor.
• Press ‘i’ browse into analogLib. Analog lib library includes the basic passive elements and sources
etc. From the cells pallet you can select, ‘vdc’ and ‘gnd’ etc. and can place it into the schematic.
• From Schematic Editing window select create pin place and name the pins.
• Wire up the components properly then check and save.

Creating symbol
• To make the symbol for this schematic, from Schematic Editing window select
Create→cellview→ from cellview, click OK.
• A new window will open with the symbol view. By default, the symbol shape is a rectangle, but
we can change it. To do this, use: Create→Shape.
There are several shapes available: line, rectangle, circle, etc.
You will want to delete the green rectangle, draw the new shape, and move the terminals to new
positions. The editing commands are similar to what you had for the schematic window.
• Make the symbol and Check and save.
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2.1 Switched-Capacitor Realization of a First-Order without delay ADC

2.1.1 Create a new Schematic and Symbol

• Create a new schematic cell in Mix_IC (put a meaningful name relevant to the sigma-delta
converter). (File→New→Cell View)
• Click the OK button. The Composer schematic editing tool will open with an empty Schematic
Editing window. Make the schematic design shown below and generate symbol.

Fig 4: Schematic and Symbol for Sigma delta Converter

MIMcap:

C = 100f F (All)
(NMOS) l = 350nm, w = 350nm, fingers = 1
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Note: The Op-amp, Non-overlapping clock, Mux, latched comparator and the transmission gates are the
same as given in previous labs.

2.2 Creating Test bench

• Create a new cell view named “tb_SD_Converter”. From the library pallet, place the Sigma-
delta converter symbol you just made.
• Add sources from Analog library pallet and edit the properties as follow:

V0: DC Voltage = 1V, V1: DC Voltage = -1V, V2: DC Voltage = 333mV

V3: DC Voltage = 1V, Idc = 40uA
V5: Voltage 1 = 1V, Voltage 2 = -1V
Period = 100us, Pulse width = 50us,
Rise Time = 10ps, Fall Time = 10ps

• Wire up the complete circuit, label the input, and output nets as shown in Fig 5.

To move in the hierarchy, select the symbol, and then:

Edit→Hierarchy→Descend Edit
To return to the previous schematic, use:
Edit→Hierarchy→Return

Fig 5: Test bench for Sigma delta Converter

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2.3 Launch Analog Design Environment Simulation Tool

2.3.1 Transient analysis

• We want to perform transient analysis of this test bench. From the schematic window select
Launch→ ADE L. Click OK on the popup window.
• In the Analog design environment window, go to Analysis→Choose→Transient→set stop time
“1.5 ms”→OK.
• Similarly in the Analog design environment window, go to Analysis→Choose→select dc→
"check save dc operating point"→OK.
• In the Analog design environment go to outputs →to be plotted →select on schematic, and then
click on the “Vout”, “mid”, “Comp_input”, “ph1”and “ph2” nodes.
• In the Analog design environment go to simulation → Netlist and RUN.

Note: The Output is sampled at ph2.

Fig 6: Transient plots of input and output voltages

𝟏+𝟏+(−𝟏) 𝟏
𝑨𝒗𝒆𝒓𝒂𝒈𝒆 (𝑽𝒐𝒖𝒕) = = 𝑽 = 𝟑𝟑𝟑. 𝟑𝟑𝒎𝑽 = 𝒖(𝒏) = 𝑽𝒊𝒏
𝟑 𝟑
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Lab Tasks
`
1. Simulate the same circuit as given above for
i) u(n) = 0.7V
ii) u(n) = 0.2V
and justify if it’s working properly or not.

2. Design second order sigma-delta modulator as given on Lecture#7 and slide#43. Verify it’s
operation for u(n) = 0.3V