FPGA and ASIC Technology Comparison, Part 1

FPGA and ASIC Technology Comparison - 1

2009 Xilinx, Inc. All Rights Reserved

Intro to VHDL or Intro to Verilog

3 days

FPGA and ASIC Technology Comparison FPGA vs. ASIC Design Flow ASIC to FPGA Coding Conversion
Virtex-5 Coding Techniques Spartan-3 Coding Techniques

Curriculum Path

Fundamentals of FPGA Design Designing for Performance

1 day
2 days Advanced FPGA Implementation

ASIC Design
2 days

for

Minimum: 6 months design experience

Welcome
If you are an experienced ASIC designer transitioning to FPGAs, this course will help you reduce your learning curve by leveraging your ASIC experience Careful attention to how FPGAs are different than ASICs will help you create a fast and reliable FPGA design

After completing this module, you will able to:

Describe the differences between ASIC and FPGA architectures Explain the features of Xilinx FPGA architecture Benefit from the Xilinx dedicated resources

Contrasting Architectures
ASIC architecture compared to the Xilinx FPGA architecture
Gates versus LUTs Delays Performance

Fundamental part selection considerations

Cost Size Performance Volume Analog circuitry Time to market Reprogrammability
FPGA and ASIC Technology Comparison - 5
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Standard Cell
Advantages
Lowest price for high-volume production (greater than 200K per year) Fastest clock frequency (performance) Unlimited size Integrated analog functions

Custom ASICs

Low power

Disadvantages
Highest non-recurring engineering costs Longest design cycle Limited vendor IP with high cost High cost for engineering change orders
FPGA and ASIC Technology Comparison - 6
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Embedded Array
Advantages
Low price for medium-volume to high-volume production Performance only slightly slower than a standard cell 50+ million gates Custom macro support More flexibility than an FPGA Low power

Disadvantages
High non-recurring engineering costs Design cycle longer than an FPGA Vendor IP has high cost Generally digital only
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Xilinx FPGAs
Field-Programmable Gate Arrays

Advantages
Lowest cost for low-volume to mediumvolume production No non-recurring engineering costs Standard product Fastest time to market Xilinx has extensive library of IP

Inexpensive compared to ASIC vendors

Ability to make bug fixes quickly and inexpensively

Disadvantages
Slower performance Size limited to ~25 million system gates Digital only FPGA and ASIC Technology 2007 Xilinx, Inc. All Rights Reserved 2009
Comparison - 8

Field-Programmable Gate Arrays

Xilinx FPGAs are made using SRAM Todays FPGAs use 65-nm copper CMOS process Potential to accommodate 25M system gates Includes RAM and logic gates Performance up to 550 MHz Integrated synthesis, simulation, and place & route tools PC and UNIX Inexpensive: $2500 or less for the ISE Design Suite

Use of third-party tools will increase costs Free ISE WebPACK is available
2007 Xilinx, Inc. All Rights Reserved 2009

FPGA and ASIC Technology Comparison - 9

Configuration Introduction
When does configuration happen?
On power up On demand

Why do FPGAs need to be configured?

FPGA configuration memory is volatile Configuration data is stored in a PROM or other external data source

What do you need to know about FPGA configuration?

What happens during configuration How to set up various configuration modes and daisy chains

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Configuration
Cost of ownership is reduced with the ability to reconfigure the hardwareextending the life of the product

Reduces the costly physical deployment of repair technicians Extends the life of the product Upgrades Bug fixes Adding additional functionality Faster time to market Partial reconfiguration

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FPGA Configuration Methods

Xilinx Cables: JTAG Slave Serial Slave SelectMAP Xilinx PROMs: Slave/Master Serial Slave/Master SelectMAP

FPGA

Microprocessor: JTAG Slave Serial Slave SelectMAP

Commodity Flash: Slave SelectMAP SPI* BPI*

*SPI and BPI support is available in the newer Virtex-5 and Spartan-3E families
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PROPERTIES On passing, 'Finish' button: On failing, 'Finish' button: Allow user to leave quiz: User may view slides after quiz: User may attempt quiz:

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Five Primary Elements

Configurable logic blocks Dedicated blocks Input and output blocks Xilinx FPGAs

Routing

* Clocking Resources
2007 Xilinx, Inc. All Rights Reserved 2009

FPGA and ASIC Technology Comparison - 14

Logic Cells
Logic cells include
Combinatorial logic, arithmetic logic, and a register
Carry out

Carry Chain

Combinatorial logic is implemented using Look-Up Tables (LUTs) Register functions can include latches, JK, SR, D, and T-type flip-flops Arithmetic logic is a dedicated carry chain for implementing fast arithmetic operations
FPGA and ASIC Technology Comparison - 15

LUT
Carry in

S/R

2007 Xilinx, Inc. All Rights Reserved 2009

Combinatorial Logic
LUTs function as a ROM
A B C D E F Z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 1 1 0 0 0 1
Combinatorial Logic

A B C D E F

LUT Z

They generate the output value for a given set of inputs

. . .

Constant delay through a LUT Limited by the number of inputs and outputs, not by complexity
2007 Xilinx, Inc. All Rights Reserved 2009

FPGA and ASIC Technology Comparison - 16

Wide Input Functions

For wider input functions, LUTs can be combined using a multiplexer LUT

LUT

MUX

These muxes are dedicated, so they are fast

LUT

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LUT-Based Memory
Can store 64 bits of memory as either a RAM or a ROM Fundamentally, the LUT is a ROM Can become RAM with activation of configuration write strobe Combine multiple LUTs for larger memorieslarger in both in depth and width
128 x 8 is not uncommon

LUT

6-input LUT contains two 5-input LUTs, which adds more flexibility
FPGA and ASIC Technology Comparison - 18
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Carry Logic
The carry logic chain is dedicated logic that computes high-speed arithmetic logic functions The carry chain generally consists of a multiplexer and an XOR gate
The LUT computes the multiplexer selector The multiplexer determines the carry-out The XOR gate computes the addition

FPGA and ASIC Technology Comparison - 19

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PROPERTIES On passing, 'Finish' button: On failing, 'Finish' button: Allow user to leave quiz: User may view slides after quiz: User may attempt quiz:

Goes to Next Slide Goes to Next Slide After user has completed quiz At any time Unlimited times

Memory Blocks
Support single- and dual-port synchronous operations In dual-port mode, these RAM blocks support fully independent ports for both reading and writing Each RAM block can be configured for 36 kb
Can be used as 2 independent 18-kb RAMs

Dedicated cascade logic allows 2 RAM blocks to be configured as 72 kb Blocks of memory are generally spread out across the die Dedicated FIFO logic enables each FPGA and ASIC Technology RAM to be configured as a FIFO Comparison - 21

2007 Xilinx, Inc. All Rights Reserved 2009

Block RAM Configurations

Configurations available on each port
Configuration 32k x 1 16k x 2 8k x 4 4k x 9 2k x 18 1k x 36 Depth 32 kb 16 kb 8 kb 4 kb 2 kb 1 kb Data Bits 1 2 4 8 16 32 Parity Bits 0 0 0 1 2 4

Independent configurations on ports A and B, read and write

Supports data-width conversion, including parity bits FPGA and ASIC Technology
Comparison - 22

IN 8 bit

Port A: 8 bits

Port B: 32 bits
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OUT 32 bit

IOB Element
Input path
Two DDR registers

Output path
Two DDR registers Two 3-state enable DDR registers

Each path can be combinatorial or registered Separate clocks and clock enables for I and O Set and reset signals are shared

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IOB Element
Default I/O standard varies by family
Fast and slow slew rate Programmable drive strength Other I/O standards

Built in SERDES functionality

ISERDES divides input data by up to 10 OSERDES multiplies output data by up to 10

FPGA and ASIC Technology Comparison - 24

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DSP Slice
25x18 Multiply
ALU Mode

Dedicated A Cascading FPGA and ASIC Technology

Comparison - 25

Independent C input

Pattern Detection

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Routing
A combination of programmable and dedicated routing lines Dedicated routing
Global clocks with predefined clock tree Regional clocks and IO clocks Global low-skew routing resources for other high-fanout signals Carry chain routing Dedicated routing among other dedicated resources

General interconnect
Routing of local signals between CLBs and IOBs
FPGA and ASIC Technology Comparison - 26
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Clock Management
Dedicated clock trees are pre-optimized clock networks that balance the skew and minimize delay
Virtex-5 FPGA has 32 separate clock networks Spartan-3 FPGA has 8 separate clock networks Each can be configured for a built-in clock enable (BUFGCE) or switching clock sources (BUFGMUX) Local clock routing includes regional (BUFR) and SERDES (BUFIO)

FPGA and ASIC Technology Comparison - 27

2007 Xilinx, Inc. All Rights Reserved 2009

Clock Management
PLL Digital Clock Manager (DCM) consists of
Digital Delay Locked Loop (DLL) Digital Frequency Synthesis (DFS) Digital Phase Shifter (DPS)

CMT

FPGA and ASIC Technology Comparison - 28

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I/O Translators
Programmable input and output thresholds Supported standards include
LVCMOS (several classes), LVPECL, HSTL (several classes), SSTL (several classes), PCI, PCI-X, LVDS (several classes), GTL, GTL+, and HyperTransport (LDT) technology - Supported standards vary, check your data sheet

Different I/O standards require a separate input and output reference voltage for each bank supporting a separate I/O standard Generally, each bank can support several standards, as long as they share the same vref (input) or vcco (output)
FPGA and ASIC Technology Comparison - 29
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Dedicated and Special Resources

Clock management (CMT)
DCM and PLL Dedicated clock trees (not shown)

Test logic
Built-in JTAG

I/O translators
Supporting many different thresholds

Other resources
Dual-Data Rate (DDR) registers in IOB SERDES resources Dedicated Cores Block RAM DSP Slices Gigabit transceivers, MGTs (all devices) Tri-mode Ethernet MAC (all devices) PCI Express core (all devices) Additional FXT Cores PowerPC 440 processors (not shown) Faster GTX transceiver (not shown)

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Other Resources
Embedded processor cores
32-bit PowerPC 440 processor core (hard) MicroBlaze processor core (soft)

Digitally controlled termination resistance (DCI)

FPGA and ASIC Technology Comparison - 31

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PROPERTIES On passing, 'Finish' button: On failing, 'Finish' button: Allow user to leave quiz: User may view slides after quiz: User may attempt quiz:

Goes to Next Slide Goes to Next Slide At any time At any time Unlimited times

Summary
FPGA flexibility
Reconfigurable logic Time to market Lowest cost of change

Xilinx combinatorial resources use flexible LUTs Xilinx slices also contain registers, carry logic, clocking resources, and dedicated muxes to improve the performance for all applications Xilinx FPGAs have dedicated resources for DSP, RAM, PCI, EMAC, and I/O that make these critical paths equivalent to a custom ASIC

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Where Can I Learn More?

Xilinx online documents
www.support.xilinx.com

Software manuals Data sheets Application notes User guides

Xilinx Training
www.xilinx.com/training

Xilinx tools and architecture courses Hardware description language courses Free training videos

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Trademark Information
Xilinx is disclosing this Document and Intellectual Propery (hereinafter the Design) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (High-Risk Applications). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. 2009 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. FPGA and ASIC Technology Comparison - 35
2007 Xilinx, Inc. All Rights Reserved 2009