Introduction To Xilinx System Generator
Introduction To Xilinx System Generator
System Generator
o Developed by Xilinx Corp. o Provides device-optimized DSP block library for Simulink o Let you model DSP algorithm, generate HDL code, and verify FPGA designs for Xilinx devices in a intuitive and efficient way.
System Generator
Type Simulink at the MATLAB command prompt or open the Simulink Library Browser by clicking the corresponding button in the MATLAB toolbar
Create a new model blank sheet by clicking the Create a new model button in the Simulink Library Browser
Simulink Model
Go to Video and Image processing blocksets Sources Image from file
Reshape is an operator that is used to convert the dimensions. The parameter one dimensionality is chosen as 1-D array since the XSG accepts 1-D as the inputs.
The number of bits is chosen as 8 since we are using a gray scale image. Quantization and overflow is kept as round and saturate by default.
Buffer size:
If an image of a X b is taken then the buffer size should always be a*b. Eg: 64X64 is the image size then buffer size must be 4096.
Reshape:
At the output the parameters of reshape operator must be: o Dimentionality: Customise o Dimension: it must be 2D since we are converting back to the original image. Hence specify the size of original image
Simulation
Stop time
Workspace
Write the callback function in the editor window and link to the model
Output obtained
NOTE:In order to carry out processing on an image the modules have to be placed between gateway in and gateway out
Example 3 Filtering
Filtering
Reading an image
Filtering module
5 x 5 Filter
Filtering
Example 3 Enhancement
Enhancement
Reading an image
Enhancement
Example 4 Negation
Negation
Reading an image
Negation
Example 4 Binarization
Binarization
Reading an image
Binarization