Basic HDL Coding Techniques

Part 1

FPGA and ASIC Technology

Comparison - 1

2009 Xilinx, Inc. All Rights Reserved

Welcome
If you are new to FPGA design, this module
will help you build good HDL code that is
optimized for an FPGA
These design techniques promote fast and
efficient FPGA designs

After completing this module, you will

able to:
Specify FPGA resources that may need to
be instantiated
Identify some basic design guidelines that
successful FPGA designers follow
Select a proper HDL coding style for fast,
efficient circuits

Breakthrough Performance
Three steps to achieve breakthrough performance
1. Utilize dedicated resources

Dedicated resources are faster than a LUT/flip-flop

implementation and consume less power
Typically built with the CORE Generator tool and
instantiated
DSP48E, FIFO, block RAM, ISERDES, OSERDES,
EMAC, and MGT, for example

2. Write code for performance

Use synchronous design methodology

Ensure the code is written optimally for critical paths
Pipeline when necessary

3. Drive your synthesis tool

Try different optimization techniques

Add critical timing constraints in synthesis
Preserve hierarchy
Apply full and correct constraints
Use High effort

FPGA and ASIC Technology

Comparison - 4

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2007 Xilinx, Inc. All Rights Reserved

Virtex-6 FPGA
Performance Meter

Use Dedicated Blocks

Dedicated block timing is
correct by construction
Not dependent on
programmable routing
Uses less power

Offers as much as 3x the

performance
of soft implementations

DSP48E Slice

FIFO
Dual-Port
BRAM

Statistics
Interface

Smart RAM FIFO

Rx
Stats
Mx
Proce
ssor
Interfa
DCR Busce

Host Bus

FPGA and ASIC Technology

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2007 Xilinx, Inc. All Rights Reserved

Tx
Stats
Mx

EMAC
Core
Host
Interface

EMAC Core

Phy
Interface

Block RAM and FIFO

at 600 MHz
DSP48E at 600 MHz

Client Interface

Examples

Timing Closure

FPGA and ASIC Technology

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2007 Xilinx, Inc. All Rights Reserved

Instantiation versus Inference

Instantiate a component when you must dictate exactly which resource is
needed
The synthesis tool is unable to infer the resource
The synthesis tool fails to infer the resource

Xilinx recommends inference whenever possible

Inference makes your code more portable

Xilinx recommends using the CORE Generator software to create

functions such as Arithmetic Logic Units (ALUs), fast multipliers, and
Finite Impulse Response (FIR) filters for instantiation
Xilinx recommends using the Architecture Wizard utility to create DCM,
PLL, and clock buffer instantiations

FPGA and ASIC Technology

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FPGA Resources
Can be inferred by all synthesis
tools
Shift register LUT (SRL16E/
SRLC32E)
F7 and F8 multiplexers
Carry logic
Multipliers and counters using the
DSP48E
Global clock buffers (BUFG)
SelectIO (single-ended) interface
I/O registers (single data rate)
Input DDR registers

FPGA and ASIC Technology

Comparison - 8

Can be inferred by some synthesis

tools
Memories
Global clock buffers (BUFGCE,
BUFGMUX, BUFGDLL)
Some DSP functions

Cannot be inferred by any synthesis

tools

2009
2007 Xilinx, Inc. All Rights Reserved

SelectIO (differential) interface

Output DDR registers
DCM / PLL
Local clock buffers (BUFIO, BUFR)

Suggested Instantiation
Xilinx recommends that you instantiate the following elements
Memory resources

Block RAMs specifically (use the CORE Generator software to build large
memories)

SelectIO interface resources

Clocking resources

DCM, PLL (use the Architecture Wizard)

IBUFG, BUFGMUX_CTRL, BUFGCE
BUFIO, BUFR

FPGA and ASIC Technology

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2009
2007 Xilinx, Inc. All Rights Reserved

Suggested Instantiation
Why does Xilinx suggest
this?
Easier to port your HDL
to other and newer
technologies
Fewer synthesis
constraints and
attributes to pass on

Xilinx wrapper top_xlnx

START
UP

OBUF

IBUFG

DCM

BUFG

IBUF

Top-Level
Block

OBUF

OBUF

Keeping most of the

attributes and constraints in the Xilinx User Constraints File (UCF) keeps it simpleone file
contains critical information

Create a separate hierarchical block for instantiating these resources

Above the top-level block, create a Xilinx wrapper with instantiations specific to Xilinx
Instead use VHDL configuration statements or put wrappers around each instantiation

This maintains hierarchy and makes it easy to swap instantiations

FPGA and ASIC Technology

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2009
2007 Xilinx, Inc. All Rights Reserved

Hierarchy Management
Synplify and XST software
The basic settings are
Flatten the design: Allows total combinatorial optimization across all
boundaries
Maintain hierarchy: Preserves hierarchy without allowing optimization of
combinatorial logic across boundaries (recommended)

If you have followed the synchronous design guidelines, use the setting
-maintain hierarchy
If you have not followed the synchronous design guidelines, use the
setting -flatten the design.
Consider using the keep attribute to preserve nodes for testing

Your synthesis tool may have additional settings

Refer to your synthesis documentation for details on these settings
FPGA and ASIC Technology
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2009
2007 Xilinx, Inc. All Rights Reserved

Hierarchy Preservation Benefits

Easily locate problems in the code based on the hierarchical instance
names contained within static timing analysis reports
Enables floorplanning and incremental design flow
The primary advantage of flattening is to optimize combinatorial logic
across hierarchical boundaries
If the outputs of leaf-level blocks are registered, there is generally no need
to flatten

FPGA and ASIC Technology

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2009
2007 Xilinx, Inc. All Rights Reserved

Multiplexers
Multiplexers are generated from IF and CASE statements
IF/THEN statements generate priority encoders
Use a CASE statement to generate complex encoding

There are several issues to consider with a multiplexer

Delay and size

Affected by the number of inputs and number of nested clauses to an IF/THEN

or CASE statement

Unintended latches or clock enables

Generated when IF/THEN or CASE statements do not cover all conditions

Review your synthesis tool warnings
Check by looking at the component with a schematic viewer

FPGA and ASIC Technology

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2007 Xilinx, Inc. All Rights Reserved

IF/THEN Statement
Priority Encoder
Most critical input listed first
Least critical input listed last
do_e 0
do_c 1
IF (crit_sig) THEN oput <= do_d ;

do_b

cond_c

ELSIF cond_a THEN oput <= do_a;

ELSIF cond_b THEN oput <= do_b;

ELSIF cond_c THEN oput <= do_c;

ELSE oput <= do_e;
END IF;

FPGA and ASIC Technology

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2007 Xilinx, Inc. All Rights Reserved

do_a

cond_b

do_d

cond_a

oput

crit_sig

Avoid Nested IF and IF/ELSE

Nested IF or IF/THEN/ELSE statements form priority encoders
CASE statements do not have priority
If nested IF statements are necessary, put critical input signals on the
first IF statement
The critical signal ends up in the last logic stage

FPGA and ASIC Technology

Comparison - 15

2009
2007 Xilinx, Inc. All Rights Reserved

CASE Statements
CASE statements in a combinatorial process (VHDL) or always
statement (Verilog)
Latches are inferred if outputs are not defined in all branches
Use default assignments before the CASE statement to prevent latches

CASE statements in a sequential process (VHDL) or always statement

(Verilog)
Clock enables are inferred if outputs are not defined in all branches
This is not wrong, but might generate a long clock enable equation
Use default assignments before CASE statement to prevent clock enables

FPGA and ASIC Technology

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CASE Statements
Register the select inputs if possible (pipelining)
Can reduce the number of logic levels between flip-flops

Consider using one-hot select inputs

Eliminating the select decoding can improve performance

Determine how your synthesis tool synthesizes the order of the select
lines
If there is a critical select input, this input should be included last in the
logic for fastest performance

FPGA and ASIC Technology

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2007 Xilinx, Inc. All Rights Reserved

CASE Statement
This Verilog code describes a 6:1
multiplexer with binary-encoded
select inputs
This uses fewer LUTs, but requires
multiple LUTs in series on the
timing critical path

The advantage of using the dont

care for the default, is that the
synthesizer will have more flexibility
to create a smaller, faster circuit
How could the code be changed
to use one-hot select inputs?
FPGA and ASIC Technology
Comparison - 18

module case_binary (clock, sel, data_out, in_a,

in_b, in_d, in_c, in_e, in_f) ;
input clock ;
input [2:0] sel ;
input in_a, in_b, in_c, in_d, in_e, in_f ;
output data_out ;
reg data_out;
always @(posedge clock)
begin
case (sel)
3'b000 : data_out <= in_a;
3'b001 : data_out <= in_b;
3'b010 : data_out <= in_c;
3'b011 : data_out <= in_d;
3'b100 : data_out <= in_e;
3'b101 : data_out <= in_f;
default : data_out <= 1'bx;
endcase
end
endmodule

2009
2007 Xilinx, Inc. All Rights Reserved

CASE Statement
This is the same code with one-hot
select inputs
This used more LUTs, but requires
fewer logic levels on the timing
critical path
This yields a greater benefit when
the mux is larger

Enumerated types allow you to

quickly test different encoding
and makes simulation more
readable

FPGA and ASIC Technology

Comparison - 19

module case_onehot (clock, sel, data_out, in_a,

in_b, in_d, in_c, in_e, in_f) ;
input clock ;
input [5:0] sel ;
input in_a, in_b, in_c, in_d, in_e, in_f ;
output data_out ;
reg data_out;
always @(posedge clock)
begin
case (sel)
6'b000001 : data_out <= in_a;
6'b000010 : data_out <= in_b;
6'b000100 : data_out <= in_c;
6'b0010 00: data_out <= in_d;
6'b010000 : data_out <= in_e;
6'b100000 : data_out <= in_f;
default : data_out <= 1'bx;
endcase
end
endmodule

2009
2007 Xilinx, Inc. All Rights Reserved

Other Basic Performance Tips

Avoid high-level loop constructs
Synthesis tools may not produce optimal results

Order and group arithmetic and logical functions and operators

A <= B + C + D + E; should be: A <= (B + C) + (D + E)

Use a synchronous reset

More reliable system control

FPGA and ASIC Technology

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2009
2007 Xilinx, Inc. All Rights Reserved

Synchronous Design Rewards

Always make your design synchronous
Recommended for all FPGAs

Failure to use synchronous design can potentially

Waste device resources

Not using a synchronous element will not save silicon and it wastes money

Waste performance

Reduces capability of end products; higher speed grades cost more

Lead to difficult design process

Difficult timing specifications and tool-effort levels

Cause long-term reliability issues

Probability, race conditions, temperature, and process effects

Synchronous designs have

Few clocks
Synchronous resets
No gated clocks; instead, clock enables

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Ken Chapman
(Xilinx UK) 2003

Inferred Register Examples

Ex 1 D Flip-Flop

Ex 2. D Flip-Flop with Asynch Preset

always @(posedge CLOCK)

always @(posedge CLOCK or

posedge PRESET)
if (PRESET)
Q = 1;
else
Q = D_IN;

Q = D_IN;

Ex 3. D Flip-Flop with Asynch Reset

always @(posedge CLOCK
or posedge RESET)

if (RESET)
Q = 0;
else

Ex 4. D Flip-Flop with Synch Reset

always @(posedge CLOCK)

if (RESET)
Q = 0;
else
Q = D_IN;

Q = D_IN;
FPGA and ASIC Technology
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Clock Enables
Coding style will determine if clock enables are used
VHDL

Verilog

FF_AR_CE: process(ENABLE,CLK)
begin
if (CLKevent and CLK = 1) then
if (ENABLE = 1) then
Q <= D_IN;
end if;
end if;
end process

always @(posedge CLOCK)

if (ENABLE)
Q = D_IN;

FPGA and ASIC Technology

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Summary
Use as much of the dedicated hardware resources as possible to ensure
optimum speed and device utilization
Plan on instantiating clocking and memory resources
Try to use the Core Generator tool to create optimized components that
target dedicated FPGA resources (BRAM, DSP48E, and FIFO)
Maintain your design hierarchy to make debugging, simulation, and
report generation easier

FPGA and ASIC Technology

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Summary
CASE and IF/THEN statements produce different types of multiplexers
CASE statements tend to build logic in parallel while IF/THEN statements
tend to build priority encoders

Avoid nested CASE and IF/THEN statements

You should always build a synchronous design for your FPGA
Inferring many types of flip-flops from HDL code is possible
Synchronous sets/resets are preferred

FPGA and ASIC Technology

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Where Can I Learn More?

Software Manuals
Start Xilinx ISE Design Suite 12.1 ISE Design Tools Documentation
Software Manuals
This includes the Synthesis & Simulation Design Guide

This guide has example inferences of many architectural resources

XST User Guide

HDL language constructs and coding recommendations

Software User Guides and software tutorials

Xilinx Training
www.xilinx.com/training

Xilinx tools and architecture courses

Hardware description language courses
Basic FPGA architecture and other topics (free training videos!)

FPGA and ASIC Technology

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2009
2007 Xilinx, Inc. All Rights Reserved