The ARM Instruction Set
Sandeep Srivastava
Set of All ARM Instructions
Set of all ARM Instructions
Move Instructions
PRE
r5 = 5
r7 = 8
MOV r7, r5 ; let r7 = r5
POST
r5 = 5
r7 = 5
Move Instructions Use of Barrel Shifter
PRE
r5 = 5
r7 = 8
MOV r7, r5, LSL #2 ; let r7 = r5*4 =
(r5 << 2)
POST
r5 = 5
r7 = 20
Barrel Shifter Operations
Barrel Shift Instructions Syntax
Arithmetic Instructions
Arithmetic Instructions
This simple subtract instruction subtracts a
value stored in register r2 from a value stored
in register r1. The result is stored in register r0.
PRE
r0 = 0x00000000
r1 = 0x00000002
r2 = 0x00000001
SUB r0, r1, r2
POST
r0 = 0x00000001
Arithmetic Instructions
PRE
r0 = 0x00000000
r1 = 0x00000077
RSB r0, r1, #0 ; Rd = 0x0 - r1
POST
r0 = -r1 = 0xffffff89
Logical Instructions
Logical Instructions
This example shows a logical OR operation between registers r1 and r2. r0 holds the result.
PRE
r0 = 0x00000000
r1 = 0x02040608
r2 = 0x10305070
ORR r0, r1, r2
POST
r0 = 0x12345678
This example shows a more complicated logical instruction called BIC, which carries out
a logical bit clear.
PRE
r1 = 0b1111
r2 = 0b0101
BIC r0, r1, r2
POST
r0 = 0b1010
This is equivalent to
Rd = Rn AND NOT(N)
Comparison Instructions
Comparison Instructions
The comparison instructions only set or clear the appropriate flags in
the cpsr register, but do not affect other registers
This example shows a CMP comparison instruction. You can see that
both registers, r0 and r9, are equal before executing the instruction. The
value of the z flag prior to execution is 0 and is represented by a
lowercase z. After execution the z flag changes to 1 or an uppercase Z.
This change indicates equality.
PRE
cpsr = nzcvqiFt_USER
r0 = 4
r9 = 4
CMP r0, r9
POST
cpsr = nZcvqiFt_USER
Multiply Instructions
Multiply Instructions
This example shows a simple multiply instruction that
multiplies registers r1 and r2 together and places the result
into register r0. In this example, register r1 is equal to the
value 2, and r2 is equal to 2. The result, 4, is then placed into
register r0.
PRE
r0 = 0x00000000
r1 = 0x00000002
r2 = 0x00000002
MUL r0, r1, r2 ; r0 = r1*r2
POST
r0 = 0x00000004
r1 = 0x00000002
r2 = 0x00000002
Branch Instructions
Branch Instructions
This example shows a forward and backward branch. Because
these loops are address specific, we do not include the pre- and
post-conditions. The forward branch skips three instructions. The
backward branch creates an infinite loop.
B forward
ADD r1, r2, #4
ADD r0, r6, #2
ADD r3, r7, #4
forward
SUB r1, r2, #4
backward
ADD r1, r2, #4
SUB r1, r2, #4
ADD r4, r6, r7
B backward
Load-Store Instructions
Load-Store Instructions
LDR and STR instructions can load and store data on a boundary alignment that is the same as the
datatype size being loaded or stored. For example, LDR can only load 32-bit words on a memory
address that is a multiple of four bytes0, 4, 8, and so on.
This example shows a load from a memory address contained in register r1, followed by a store back to
the same
address in memory.
;
; load register r0 with the contents of
; the memory address pointed to by register
; r1.
;
LDR r0, [r1] ; = LDR r0, [r1, #0]
;
; store the contents of register r0 to
; the memory address pointed to by
; register r1.
;
STR r0, [r1] ; = STR r0, [r1, #0]
The first instruction loads a word from the address stored in register r1 and places it into register r0.
The second instruction goes the other way by storing the contents of register r0 to the address
contained in register r1. The offset from register r1 is zero. Register r1 is called the base address
register.
Multiple Register Transfer
Multiple Register Transfer
In this example, register r0 is the base register Rn and is followed by !, indicating that
the register is updated after the instruction is executed. Notice within the load multiple
instruction that the registers are not individually listed. Instead the - character is used
to identify a range of registers. In this case the range is from register r1 to r3 inclusive.
Each register can also be listed, using a comma to separate each register within { and
} brackets.
PRE
mem32[0x80018] = 0x03
mem32[0x80014] = 0x02
mem32[0x80010] = 0x01
r0 = 0x00080010
r1 = 0x00000000
r2 = 0x00000000
r3 = 0x00000000
LDMIA r0!, {r1-r3}
POST
r0 = 0x0008001c
r1 = 0x00000001
r2 = 0x00000002
r3 = 0x00000003
Program Status Register(cpsr) Instructions
Program Status Register(cpsr) Instructions
Program Status Register(cpsr)
Instructions
The MSR first copies the cpsr into register r1. The BIC instruction
clears bit 7 of r1. Register r1 is then copied back into the cpsr,
which enables IRQ interrupts. You can see from this example that
this code preserves all the other settings in the cpsr and only
modifies the I bit in the control field.
PRE
cpsr = nzcvqIFt_SVC
MRS r1, cpsr
BIC r1, r1, #0x80 ; 0b01000000
MSR cpsr_c, r1
POST
cpsr = nzcvqiFt_SVC
This example is in SVC mode. In user mode you can read all cpsr
bits, but you can only update the condition flag field f.
