Computer Function and Interconnection

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William Stallings
Computer Organization
and Architecture
9th Edition
Chapter 3
A Top-Level View of Computer
Function and Interconnection
Computer Components
Contemporary computer designs are based on concepts

developed by John von Neumann at the Institute for
Advanced Studies, Princeton
Referred to as the von Neumann architecture and is based

on three key concepts:
Data and instructions are stored in a single read-write memory
The contents of this memory are addressable by location,

without regard to the type of data contained there
Execution occurs in a sequential fashion (unless explicitly

modified) from one instruction to the next
Hardwired program
The result of the process of connecting the various

components in the desired configuration
+
Hardware
and Software
Approaches
Software
I/O
Component
s
MEMORY
MAR
+
MBR
Computer
Components
:
Top Level
View
Basic Instruction Cycle
Fetch Cycle
At the beginning of each instruction cycle the

processor fetches an instruction from memory
The program counter (PC) holds the address of the

instruction to be fetched next
The processor increments the PC after each

instruction fetch so that it will fetch the next
instruction in sequence
The fetched instruction is loaded into the instruction

register (IR)
The processor interprets the instruction and performs

the required action
Action Categories
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Example
of
Program
Execution
Instruction Cycle State Diagram
Classes of Interrupts
Program Flow Control
Transfer of Control via

Interrupts
Instruction Cycle With

Interrupts
Program
Timing:
Short I/O
Wait
Program
Timing:
Long I/O
Wait
Instruction Cycle State

Diagram
With Interrupts
Transfer
of
Control
Multiple
Interrupts
+ Time Sequence of
Multiple
Interrupts
I/O Function
I/O module can exchange data directly with the processor
Processor can read data from or write data to an I/O

module
Processor identifies a specific device that is controlled by a

particular I/O module
I/O instructions rather than memory referencing instructions
In some cases it is desirable to allow I/O exchanges to

occur directly with memory
The processor grants to an I/O module the authority to read

from or write to memory so that the I/O memory transfer can
occur without tying up the processor
The I/O module issues read or write commands to memory

relieving the processor of responsibility for the exchange
This operation is known as direct memory access (DMA)
Computer
Modules
The interconnection structure must support the

following types of transfers:
Data Bus
Data lines that provide a path for moving data among

system modules
May consist of 32, 64, 128, or more separate lines
The number of lines is referred to as the width of the

data bus
The number of lines determines how many bits can be

transferred at a time
The width of the data bus

is a key factor in
determining overall
system performance
Address Bus
Control Bus
Used to designate the source

or destination of the data on
the data bus
If the processor wishes to
read a word of data from
memory it puts the address
of the desired word on the
address lines
Used to control the access and

the use of the data and address
lines
Because the data and address

lines are shared by all
components there must be a
means of controlling their use
Width determines the

maximum possible memory
capacity of the system
Control signals transmit both

command and timing information
among system modules
Also used to address I/O ports

The higher order bits are
used to select a particular
module on the bus and the
lower order bits select a
memory location or I/O port
within the module
Timing signals indicate the

validity of data and address
information
Command signals specify

operations to be performed
Bus Interconnection Scheme
Elements of Bus Design
Timing of
Synchronou
s Bus
Operations
Timing of
Asynchronous
Bus
Operations
Point-to-Point Interconnect
+Quick Path
Interconnect
Introduced in 2008
Multiple direct connections
Layered protocol architecture
Direct pairwise connections to other components

eliminating the need for arbitration found in shared
transmission systems
These processor level interconnects use a layered

protocol architecture rather than the simple use of
control signals found in shared bus arrangements
Packetized data transfer
Data are sent as a sequence of packets each of which

includes control headers and error control codes
QPI
Multicore
Configuratio
n Using
QPI

Computer Function and Interconnection

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Computer Function and Interconnection

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Contemporary computer designs are based on concepts

Referred to as the von Neumann architecture and is based

Data and instructions are stored in a single read-write memory

The contents of this memory are addressable by location,

Execution occurs in a sequential fashion (unless explicitly

The result of the process of connecting the various

Basic Instruction Cycle

At the beginning of each instruction cycle the

The program counter (PC) holds the address of the

The processor increments the PC after each

The fetched instruction is loaded into the instruction

The processor interprets the instruction and performs

Instruction Cycle State Diagram

Program Flow Control

Transfer of Control via

Instruction Cycle With

Instruction Cycle State

I/O module can exchange data directly with the processor

Processor can read data from or write data to an I/O

Processor identifies a specific device that is controlled by a

I/O instructions rather than memory referencing instructions

In some cases it is desirable to allow I/O exchanges to

The processor grants to an I/O module the authority to read

The I/O module issues read or write commands to memory

This operation is known as direct memory access (DMA)

The interconnection structure must support the

Data lines that provide a path for moving data among

May consist of 32, 64, 128, or more separate lines

The number of lines is referred to as the width of the

The number of lines determines how many bits can be

The width of the data bus

Used to designate the source

Used to control the access and

Because the data and address

Width determines the

Control signals transmit both

Also used to address I/O ports

Timing signals indicate the

Command signals specify

Bus Interconnection Scheme

Elements of Bus Design

Multiple direct connections

Layered protocol architecture

Direct pairwise connections to other components

These processor level interconnects use a layered

Packetized data transfer

Data are sent as a sequence of packets each of which

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