Lecture 13
Lecture 13
ANNOUNCEMENTS
HW#7 is posted
online.
Frequency
Response
General considerations
High-frequency BJT model
Millers Theorem
Frequency response of CE stage
Cascoding Cascode?
Recall that the output impedance seen
looking into the collector of a BJT can be
boosted by as much as a factor of , by using
a BJT for emitter degeneration.
Rout [1 g m1 (ro 2 || r 1 )]ro1 ro 2 || r 1
[
1
g
(
r
||
out
m1
o 2 r 1 )]ro1 ro 2 || r 1
impedance remains ro1.
Rout ,max g m1ro1r 1 ro1
EE105 Fall 2007
Cascode Amplifier
Recall that voltage gain of a cascode amplifier
is high, because Rout is high.
Av g m1ro1 g m 2 ro1 r 2
If the input is applied to the base of Q2 rather
than the base of Q1, however, the voltage
gain is not as high.
The resulting circuit is a CE amplifier with emitter
io
gm2
degeneration, which has lower
G
.
G m
m
vin
1 g m 2 ro1 ro 2
Prof. Liu, UC Berkeley
Av Roll-Off due to CL
A capacitive load (CL) causes the gain to
decrease at high frequencies.
The impedance of CL decreases at high
frequencies, so that it shunts some of the
output current to ground.
Av g m RC ||
j C L
Frequency Response of
the CE Stage
Av
g m RC
R C 1
2
C
2
L
g m RC
attribute.
Gain Bandwidth
RC C L
I CVCC
1
VT VCC C L
Bode Plot
The transfer function of a circuit can be written in
the general form
j
j
1
1
A is the low-frequency gain
0
z1
z 2
H ( j ) A0
zj are zero frequencies
1
1
pj are pole frequencies
p
1
p
2
1
p1
RC C L
In general, if node j in the signal path has a
small-signal resistance of Rj to ground and a
capacitance Cj to ground, then it contributes a
pole at frequency (RjCj)-1
EE105 Fall 2007
Pole Identification
Example
1
p1
RS Cin
EE105 Fall 2007
p2
RC C L
Prof. Liu, UC Berkeley
High-Frequency BJT
Model
C Cb C je
EE105 Fall 2007
Transit Frequency, fT
The transit or cut-off frequency, fT, is a
measure of the intrinsic speed of a
transistor, and is defined as the frequency
where
the current gain falls to 1.
Conceptual set-up to measure f
T
I out g mVin
Vin
I in
Z in
I out
1
1
g m Z in g m
I in
jT Cin
g
T m
Cin
gm
2fT
C
EE105 Fall 2007
Millers Theorem
If Av is the voltage gain from node 1 to 2,
then a floating impedance ZF can be
converted to two grounded impedances Z1
and ZV21: V2 V1 Z Z V1 Z 1
ZF
Z1
V1 V2
1 Av
V1 V2
V2
V2
1
Z 2 Z F
ZF
ZF
Z2
V1 V2
1 1
EE105 Fall 2007
Av
Miller Multiplication
Applying Millers theorem, we can convert
a floating capacitance between the input
and output nodes of an amplifier into two
grounded capacitances.
The capacitance at the input node is
1
larger
floating
A0 Avthan the original
ZF
1
jC F
Z2
capacitance.
1 1
1 1
1
Av
A0
j 1
A0
CF
ZF
1
jC F
Z1
1 Av
1 A0
j 1 A0 C F
EE105 Fall 2007
Application of Millers
Theorem
p ,in
RS 1 g m RC C F
p ,out
1
RC 1
g m RC
C F
Applying Millers
Theorem
p ,in
RThev Cin 1 g m RC C
p ,out
RC Cout
1
g m RC
Direct Analysis of CE
Stage
Direct analysis yields slightly different pole
locations and an extra zero:
gm
z
C XY
1
p1
1 g mRC C XY RThev RThevCin RC C XY Cout
Input Impedance of CE
Stage
1
Z in
|| r
j C 1 g m RC C
EE105 Fall 2007