User Defined Primitives (UDPs)

In Verilog

UDP Definition
A UDP definition starts with the keyword

primitive. The primitive name, output terminal,

and input terminals are specified. Terminals are
declared as output or input in the terminal
declarations section. For a sequential UDP, the
output terminal is declared as a reg.
For sequential UDPs, there is an optional initial
statement that initializes the output terminal of the
UDP.

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UDP Definition
The UDP state table is most important part of the

UDP. It begins with the keyword table and ends

with the keyword endtable. The table defines how
the output will be computed from the inputs and
current state.
The table is modeled as a lookup table. and the
table entries resemble entries in a logic truth table.
Primitive definition is completed with the keyword
endprimitive.
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UDP Syntax
//UDP name and terminal list
primitive <udp_name> (
<output_terminal_name>(only one allowed)
<input_terminal_names> );
//Terminal declarations
output <output_terminal_name>;
input <input_terminal_names>;
reg <output_terminal_name>;//(optional; only for sequential UDP)
// UDP initialization (optional; only for sequential UDP
initial <output_terminal_name> = <value>;
//UDP state table
table
<table entries> //like entries of the truth table
endtable
//End of UDP definition
endprimitive
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UDP Rules
UDPs can take only scalar input terminals (1 bit).

Multiple input terminals are permitted.

UDPs can have only one scalar output terminal (1
bit). The output terminal must always appear first in
the terminal list. Multiple output terminals are not
allowed.
In the declarations section, the output terminal is
declared with the keyword output. Since sequential
UDPs store state, the output terminal must also be
declared as a reg.
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UDP Rules
The inputs are declared with the keyword input.
The state in a sequential UDP can be initialized with

an initial statement. This statement is optional. A 1bit value is assigned to the output, which is declared
as reg.
The state table entries can contain values 0, 1, or x.
UDPs do not handle z values. z values passed to a
UDP are treated as x values.

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UDP Rules
UDPs are defined at the same level as modules.

UDPs cannot be defined inside modules. They can be

instantiated only inside modules. UDPs are
instantiated exactly like gate primitives.
UDPs do not support inout ports.

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Combinational UDP Example 1

//Primitive name and terminal list
primitive udp_and(out, a, b);
//Declarations
output out; //must not be declared as reg for combinational UDP
input a, b; //declarations for inputs.
//State table definition; starts with keyword table
table
//The following comment is for readability only
//Input entries of the state table must be in the
//same order as the input terminal list.
// a b : out;
0 0 : 0;
0 1 : 0;
1 0 : 0;
1 1 : 1;
endtable //end state table definition
endprimitive //end of udp_and definition
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State Table Entries

The <input#> values in a state table entry must

appear in the same order as they appear in the input

terminal list. It is important to keep this in mind
otherwise , the designer gets incorrect results.
Inputs and output are separated by a ":".
A state table entry ends with a ";".
All possible combinations of inputs, where the output
produces a known value, must be explicitly specified.
Otherwise, if a certain combination occurs and the
corresponding entry is not in the table, the output is x.
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The use of ?in UDP

The ? symbol is used for a don't care condition.
A ? symbol is automatically expanded to 0, 1, or x.

primitive udp_or(out, a, b);

output out;
input a, b;
table
// a b : out;
0 0 : 0;
1 ? : 1; //? expanded to 0, 1, x
? 1 : 1; //? expanded to 0, 1, x
0 x : x;
x 0 : x;
endtable
endprimitive
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Instantiation of UDP Primitives

// Define a 1-bit full adder
module fulladd(sum, c_out, a, b, c_in);
// I/O port declarations
output sum, c_out;
input a, b, c_in;
// Internal nets
wire s1, c1, c2;
// Instantiate logic gate primitives
xor (s1, a, b);//use Verilog primitive
udp_and (c1, a, b); //use UDP
xor (sum, s1, c_in); //use Verilog primitive
udp_and (c2, s1, c_in); //use UDP
udp_or (c_out, c2, c1);//use UDP
endmodule
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4-1 Multiplexer using UDP

primitive mux4_to_1 (
table
// i0 i1 i2 i3, s1 s0
1 ? ? ? 0 0
0 ? ? ? 0 0
? 1 ? ? 0 1
? 0 ? ? 0 1
? ? 1 ? 1 0
? ? 0 ? 1 0
? ? ? 1 1 1
? ? ? 0 1 1
? ? ? ? x ?
? ? ? ? ? x
endtable
endprimitive

output out,input i0, i1, i2, i3, s1, s0);

:
:
:
:
:
:
:
:
:
:
:

out
1 ;
0 ;
1 ;
0 ;
1 ;
0 ;
1 ;
0 ;
x ;
x ;

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Sequential UDPs
The output of a sequential UDP is always declared as

a reg.
An initial statement can be used to initialize output
of sequential UDPs.
The format of a state table entry is slightly different.
<input1> <input2> ..... <inputN> :
<current_state> :<next_state>;
There are three sections in a state table entry:
inputs, current state, and next state. The three
sections are separated by a colon (:) symbol.
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Sequential UDPs
The input specification of state table entries can

be in terms of input levels or edge transitions.

The current state is the current value of the output
register.
The next state is computed based on inputs and
the current state. The next state becomes the new
value of the output register.
All possible combinations of inputs must be
specified to avoid unknown output values.
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Level-Sensitive Sequential UDPs

primitive latch(q, d, clock, clear);
output q;
reg q; //q declared as reg to create internal storage
input d, clock, clear;
//only one initial statement allowed
initial
q = 0; //initialize output to value 0
//state table
table
//d clock clear : q : q+ ;
? ? 1 : ? : 0 ; //clear condition;
//q+ is the new output value
1 1 0 : ? : 1 ; //latch q = data = 1
0 1 0 : ? : 0 ; //latch q = data = 0
? 0 0 : ? : - ; //retain original state if clock = 0
endtable
endprimitive
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Edge-Sensitive Sequential UDPs

//Define an edge-sensitive sequential UDP;
primitive edge_dff(output reg q = 0,input d, clock, clear);
table
// d clock clear : q : q+ ;
? ? 1 : ? : 0 ; //output = 0 if clear = 1
? ? (10): ? : - ; //ignore negative transition of clear
1 (10) 0 : ? : 1 ; //latch data on negative transition of
0 (10) 0 : ? : 0 ; //clock
? (1x) 0 : ? : - ; //hold q if clock transitions to unknown
? (0?) 0 : ? : - ; //ignore positive transitions of clock
? (x1) 0 : ? : - ; //ignore positive transitions of clock
(??) ? 0 : ? : - ;//ignore any change in d when clock is steady
endtable
endprimitive
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Edge Transitions Symbology

(10) denotes a negative edge transition from logic 1

to logic 0.
(1x) denotes a transition from logic 1 to unknown x
state.
(0?) denotes a transition from 0 to 0, 1, or x.
Potential positive-edge transition.
(??) denotes any transition in signal value 0,1, or x to
0, 1, or x.

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Edge-triggered T-flip flop UDP

primitive T_FF(output reg q,
input clk, clear);// No initialization,will be done by clear
table
// clk clear : q : q+ ;
//asynchronous clear condition
? 1 : ? : 0 ;
//ignore negative edge of clear
? (10) : ? : - ;
//toggle flipflop at negative edge of clk
(10) 0 : 1 : 0 ;
(10) 0 : 0 : 1 ;
//ignore positive edge of clk
(0?) 0 : ? : - ;
endtable
endprimitive
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UDP Table Shorthand Symbols

Shorthand
Symbols

Meaning

Explanation

0, 1, x

Cannot be specified in an output field

0, 1

Cannot be specified in an output field

No change in
state value

Can be specified only in output field of a

sequential UDP

(01)

Rising edge of signal

(10)

Falling edge of signal

(01), (0x) or (x1)

Potential rising edge of signal

(10), (1x) or (x0)

Potential falling edge of signal

(??)

Any value change in signal

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UDP using Shorthand Symbols

table
// d clock clear : q : q+ ;
? ? 1 : ? : 0 ; //output = 0 if clear = 1
? ? f : ? : - ; //ignore negative transition of clear
1 f 0 : ? : 1 ; //latch data on negative transition of
0 f 0 : ? : 0 ; //clock
? (1x) 0 : ? : - ; //hold q if clock transitions to
unknown
//state
? p 0 : ? : - ; //ignore positive transitions of clock
* ? 0 : ? : - ; //ignore any change in d when
//clock is steady
endtable
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Guidelines for UDP Design

UDPs model functionality only. They do not model timing or

process technology (such as CMOS, TTL, ECL). The primary

purpose of a UDP is to define in a simple and concise form the
functional portion of a block. A module is always used to model
a complete block that has timing and process technology.
A block can modeled as a UDP only if it has exactly one output
terminal. If the block to be designed has more than one output,
it has to be modeled as a module.
The limit on the maximum number of inputs of a UDP is
specific to the Verilog simulator being used. However, Verilog
simulators are required to allow a minimum of 9 inputs for
sequential UDPs and 10 for combinational UDPs.
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Guidelines for UDP Design

A UDP is implemented as a lookup table in memory.

As the number of inputs increases, the number of

table entries grows exponentially. Thus, the memory
requirement for a UDP grows exponentially in
relation to the number of inputs.
For example, it is not advisable to design an 8-to-1
multiplexer as a UDP because of the large number of
table entries. Instead, the data flow or behavioral
representation would be much simpler

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Exercises
1. Write the truth table for the boolean function:
Y = (A & B) | (C ^ D). Define a UDP that implements this
boolean function. Assume that the inputs will never take the
value x.
2. Define a level-sensitive latch with a preset signal. Inputs are
d, clock, and preset. Output is q. If clock = 0, then q = d. If
clock = 1 or x, then q is unchanged. If preset = 1, then q = 1. If
preset = 0, then q is decided by clock and d signals. If preset =
x, then q = x.
3. Define a negative edge-triggered JK flipflop, jk_ff with
asynchronous preset and clear as a UDP. q = 1 when preset =
1 and q = 0 when clear = 1.
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