ARM Processor
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 1
Comparison between CISC and RISC
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 2
ARM Processor similarity with RISC
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 3
Other features
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 4
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 5
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 6
ARM7TDMI
TheARM7TDMI(ARM7+ 16 bit Thumb+ JTAGDebug + fastMultiplier + enhanced
ICE) processor implements the ARMv4 instruction set. It was licensed for
manufacturebyanarrayofsemiconductorcompanies.
In2009itwasoneofthemostwidelyusedARMcores,andisfoundinnumerousdeeply
embeddedsystemdesigns.
Itisaversatileprocessordesignedformobiledevicesandotherlowpowerelectronics.
Thisprocessorarchitectureiscapableofupto130MIPSonatypical0.13mprocess.
The processor supports both 32-bit and 16-bit instructions via the ARM and Thumb
instructionsets.
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 7
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 8
ARM family attribute comparison
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 9
General ARM
Architecture
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 10
Barrel Shifter
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 11
Barrel Shifter (Contd..)
Abarrel shifteris adigitalcircuitthat canshiftadatawordby a specified
number ofbitswithout the use of anysequentiallogic, only purecombinatorial
logic.
One way to implement it is as a sequence ofmultiplexerswhere the output of
one multiplexer is connected to the input of the next multiplexer in a way that
dependsontheshiftdistance.
Abarrelshifterisoftenusedtoshiftandrotaten-bitsinmodernmicroprocessors,
typicallywithinasingleclockcycle.
The second operand to many ARM and Thumb data-processing and single
register data-transfer instructions can be shifted, before the data-processing or
data-transferisexecuted,aspartoftheinstruction.
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 12
Pipeline
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 13
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 14
Characteristics of pipeline
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 15
Limitations of 3-stage pipelining
in ARM7TDMI
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 16
ARM core data flow model
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 17
A programmer can think of an ARM core as
functional units connected by data buses.
The arrows represent the flow of data, the lines
represent the buses, and the boxes represent either
an operation unit or a storage area.
Does not only represent the flow of data but also
the abstract components that make up an ARM
core.
Data enters the processor core through the Data
bus. The data may be an instruction to execute or a
data item.
The instruction decoder translates instructions
before they are executed. Each instruction executed
LEC/UEC-504/July-
belongs to
05/07/17 a particular instruction
Aug/2015/AM set. 18
The ARM processor, like all RISC processors, uses a
load-store architecture.
That means it has two instruction types for
transferring data in and out of the processor: load
instructions copy data from memory to registers in
the core, and conversely the store instructions copy
data from registers to memory. There are no data
processing instructions that directly
manipulate data in memory. Thus, data
processing is carried out solely in registers.
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 19
The sign extend hardware converts signed 8-bit and
16-bit numbers to 32-bit values as they are read from
memory and placed in a register.
ARM instructions typically have two source registers,
Rn and Rm, and a single result or destination register,
Rd. Source operands are read from the register file
using the internal buses A and B, respectively.
The ALU (arithmetic logic unit) or MAC (multiply-
accumulate unit) takes the register values Rn and Rm
from the A and B buses and computes a result. Data
processing instructions write the result in Rd directly
to the register file.
Load and store instructions use the ALU to generate an
address to be held in the address register and broadcast
on the Address bus.
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 20
ARM has 37 registers which are 32-
bits long Program counter : 1
CPSR : 1
SPSR : 5
General purpose registers : 30
CPSR: Current program status register
SPSR: Saved program status register
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 21
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 22
05/07/17 23
ARM processor modes
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 24
ARM processor modes (Contd..)
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 25
Current Program Status Register
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 26
T= 1 indicates Thumb state. T = 0 indicates ARM state.
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 27
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 28
Exceptions, Interrupts, and Vector Table
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 29
The Vector Table
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 30
Reset:
Undefined instruction vector:
Software interrupt vector:
Prefetch abort vector:
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 31
Data abort vector:
Interrupt request vector:
Fast interrupt request vector:
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 32
Addressing modes
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 33
1.Literal(Immediate) Adressing
2. Register Indirect Addressing
3. Register Indirect Addressing with an Offset
LDR r0,[r1,#4] ; load r0 with the word pointed
by r1+4
Move the contents of data pointed to by (r1 + 4) to r0. This
achieves r0 = *(r1 + 1) since 32 bits are moved at a time.
Byte alignment might enforce this, so you might not be
able to do "ldr r0, [r1, #1]".
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 34
4. ARM's Autoindexing Pre-indexed Addressing
Mode
5.ARM's Autoindexing Post-indexing
Addressing Mode
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 35
Example:
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 36
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 37
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 38
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 39
Example-1
Example-2
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 40
Example:
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 41
Example:
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 42
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 43
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 44
Example:
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 45
Example:
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 46
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 47
Example-1 Example-2
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 48
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 49
Example-1 Example-2
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 50
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 51
Example
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 52
Exercise-1
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 53
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 54
LEC/UEC-504/July-
05/07/17 Aug/2015/AM 55
