Interrupt Structure in 8085

Interrupt Structure in
8085
S.VINOD, M.E (PED)
MIEEE, ISTE,IEI
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DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENIGNEERING
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• Interrupt is signals send by an external device to the
processor, to request the processor to perform a
particular task or work.
• Mainly in the microprocessor based system the
interrupts are used for data transfer between the
peripheral and the microprocessor.
• The processor will check the interrupts always at the
2nd T-state of last machine cycle.
• If there is any interrupt it accept the interrupt and send
the INTA (active low) signal to the peripheral.
• The vectored address of particular interrupt is stored in
program counter.
• The processor executes an interrupt service routine
(ISR) addressed in program counter.
• It returned to main program by RET instruction.
Types of Interrupts
• 8085 supports two types of interrupts.
Software interrupts
Hardware interrupts
Software interrupts
• The software interrupts are program
instructions. These instructions are inserted at
desired locations in a program.
• The 8085 has eight software interrupts from
RST 0 to RST 7. The vector address for these
interrupts can be calculated as follows.
• Interrupt number * 8 = vector address
• For RST 5,5 * 8 = 40 = 28H
• Vector address for interrupt RST 5 is 0028H
vector addresses of all software interrupts
Hardware interrupts
• An external device initiates the hardware
interrupts and placing an appropriate signal at the
interrupt pin of the processor.
• If the interrupt is accepted then the processor

executes an interrupt service routine.
The 8085 has five hardware interrupts

(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5
(5) INTR
(1).TRAP
• This interrupt is a non-maskable interrupt.
• It is unaffected by any mask or interrupt enable.
• TRAP bas the highest priority and vectored interrupt.
• TRAP interrupt is edge and level triggered. This means
hat the TRAP must go high and remain high until it is
acknowledged.
• In sudden power failure, it executes a ISR and send the
data from main memory to backup memory.
• The signal, which overrides the TRAP, is HOLD signal.
(i.e., If the processor receives HOLD and TRAP at the
same time then HOLD is recognized first and then TRAP
is recognized).
(2). RST 7.5
• The RST 7.5 interrupt is a maskable interrupt.
• It has the second highest priority.
• It is edge sensitive. ie. Input goes to high and no
need to maintain high state until it recognized.
• It is disabled by,
– 1.DI instruction
– 2.System or processor reset.
– 3.After reorganization of interrupt.
• Enabled by EI instruction.
(3).RST 6.5 (4). RST 5.5
• The RST 6.5 and RST 5.5 both are level triggered. ie.
Input goes to high and stay high until it recognized.
• Maskable interrupt.
• It is disabled by,
– 1.DI, SIM instruction
– 2.System or processor reset.
– 3.After reorganization of interrupt.
• The RST 6.5 has the third priority whereas RST 5.5 has
the fourth priority.
(5).INTR
• INTR is a maskable interrupt. It is disabled by,
– 1.DI, SIM instruction
• 2.System or processor reset.
• 3.After reorganization of interrupt.
• Non- vectored interrupt. After receiving INTA (active
low) signal, it has to supply the address of ISR.
• It has lowest priority.
• It is a level sensitive interrupts. i.e. Input goes to high
and it is necessary to maintain high state until it
recognized.
sequence of events occurs when INTR
signal goes high
1. The 8085 checks the status of INTR signal during
execution of each instruction.
2. If INTR signal is high, then 8085 complete its current
instruction and sends active low interrupt acknowledge
signal, if the interrupt is enabled.
3. In response to the acknowledge signal, external logic
places an instruction OPCODE on the data bus. In the
case of multibyte instruction, additional interrupt
acknowledge machine cycles are generated by the
8085 to transfer the additional bytes into the
microprocessor.
4. On receiving the instruction, the 8085 save the address
of next instruction on stack and execute received
instruction.
SIM and RIM for interrupts
• The 8085 provide additional masking facility
for RST 7.5, RST 6.5 and RST 5.5 using SIM
instruction.
• The status of these interrupts can be read by
executing RIM instruction.
• The masking or unmasking of RST 7.5, RST 6.5
and RST 5.5 interrupts can be performed by
moving an 8-bit data to accumulator and then
executing SIM instruction.
The format of the 8-bit data
• The status of pending interrupts can be read from
accumulator after executing RIM instruction.
• When RIM instruction is executed an 8-bit data is loaded in
accumulator, which can be interpreted as shown

Interrupt Structure in 8085

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Interrupt Structure in 8085

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Interrupt Structure in

• If the interrupt is accepted then the processor

The 8085 has five hardware interrupts

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