Verilog Hardware Description Language

Verilog  HDL
Training Guide

઺ࢪ: ᘽ Ꮂ

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 Outline
1. Introduction and Basic Concepts

2. Lexical Conventions and Data Types in Verilog

3. Support for Verification

4. Design Examples

5. Behavior Modeling

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 Outline
1. Introduction and Basic Concepts

2. Lexical Conventions and Data Types in Verilog

3. Support for Verification

4. Design Examples

5. Behavior Modeling

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 1. Introduction and Basic Concepts

Objectives
Understand the basics of Hardware Description Language (HDL) and
simulators.
Understand the verilog language and the verilog-XLTM software.
Introduce verilog structural and behavioral construct in a sample design.
Starting the verilog-XL software.

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 Key Features of HDLs
HDLs have high-level programming language constructs and constructs
to describe the connectivity of the circuit.
HDLs allow you to describe the design at various levels of abstractions.

HDLs allow you to describe the functionality as well as the timing.

Concurrency.
Time.

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 Different Levels of Abstraction
 Architecture / Algorithm .
 RTL .
 Gate .
 Switch .

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 Verilog HDL and Verilog-XL
 Verilog and Verilog-XLTM are CADENCE trademarks.
 Verilog HDL
Hardware description language that allows you to describe circuits at different
levels of abstractions and allow you to mix any level of abstraction in the
design.
 Verilog-XL Software
High speed event-driven simulator that reads Verilog HDL and simulates the
description to emulate the behavior of real hardware.

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 Key Language Features

Verilog Module : basic building blocks

module SN74LS74 module DFF module ALU

endmodule endmodule endmodule

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 Key Language Features (continued)

Module Ports module DFF (d,clk,clr,q,qb);

input d,clk,clr;
output q,qb;

d q

DFF

clk q
b

endmodule
clr

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 Key Language Features (continued)

Module Instance
module REG4 (d,clk,clr,q,qb);
REG4
output [3:0] q,qb;
d clk clr input [3:0] d; input clk,clr;

DFF d0 (d[0],clk,clr,q[0],qb[0]);
DFF d1 (d[1],clk,clr,q[1],qb[1]);
DFF0 DFF3 DFF d2 (d[2],clk,clr,q[2],qb[2]);
DFF d3 (d[3],clk,clr,q[0],qb[3]);

endmodule
q q
b

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 A Simple and Complete Example

Input Vectors & Control Device Under Test Response

a a1 gr_waves
gr_regs
Test Fixture sel c_Waves
Files out

b b1

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 Device Under Test

mux.v
module MUX2_1 (out,a,b,sel);
MUX2_1
output out;

a input a,b,sel;
a1
not (sel_,sel); and (a1,a,sel_);
sel
sel_ and (b1,b.sel);
out or (out,a1,b1);

b b1 endmodule

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 Test Fixtures

testfixture.v
module testfixture; reg a,b,sel;
MUX2_1 mux (out,a,b,sel); initial input vectors
begin value input
a=0; b=1; sel=0;
#5 b=0; time a b sel
#5 b=1; sel=1;
#5 a=1; 0 0 1 0
end initial
$monitor ($time, ,out, ,a, ,b, ,sel); 5 0 0 0
endmodule
10 0 1 1
15 1 1 1

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 Running and Results

VERILOG-XL 1.6a .........

% Verilog mux.v testfixture.v *Copyright Cadence ......
* All Rights .....................
*Condiditial and .............
Running * property od .................. Compiling source file
“mux.v” Compiling source file “testfixture.v”
Highest level modules :
testfixture
time out a b sel 0 0 0 1 0
50000
10 1 0 1 1
Results 15 1 1 1 1
28 simulation events + 12 accelerated events
CPU time : 0.4 secs to compile + 0.1 secs to ...
End of VERILOG-XL 1.6a 7.1 .......

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 Procedural Blocks

initial procedural blocks, execute only once. initial

always blocks, execute in a loop.
all procedural blocks execute concurrently.
Conditions of Execution
initial c always c
c c
c c
c c
c c
c c
c c
c c

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 Starting the Verilog-XL Software

% verilog <command_line_options> <design_files>

<command_line_options>

command line option Action

-f<file_name> Read commands from the file <file_name>

-c Only compile the description
-d Decompile the Verilog description

<design_files> are files that contain Verilog descriptions.

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 Running and Results
% verilog –f run.f

run.f

fadder.v testfadder.v

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 Outline
1. Introduction and Basic Concepts

2. Lexical Conventions and Data Types in Verilog

3. Support for Verification

4. Design Examples

5. Behavior Modeling

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 2. Lexical Conventions and Data Types in Verilog

Objectives
Understand the lexical conventions used in the Verilog language.
Learn to recognize special language tokens. Learn the various classes of

data types in Verilog. Learn the Verilog logic value system.

Learn the various Verilog strengths. Learn the declaration syntax.

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 Comments

Single-line comments begin with “ // ” and end with a new line

character.
Multiple-line comments start with “ /* ” and end with “ */ “.
module MUX2_1 (out,a,b,sel);
// Port declarations
output output; input a,b,sel;
/*
The netlist logic selections input “a” when sel=0 and it selects “b”
when sel=1
*/
not (sel_,sel); and (a1,a,sel_);
and (b1,b.sel);
or (out,a1,b1); endmodule

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 Integer and Real Numbers

Number can be integers or real numbers. Integers can be sized or

unsized.
Sized integers are represented as <size>‘<base><value>
where <size> is the size in bits.
<base> can be b(binary), o(octal), d(decimal) or h(hexadecimal)
<value> is any legal number in the selected base and x, z, ?
Real number can be represented in decimal or scientific format.

12 - unsized decimal 6.3 - decimal notation

‘H83a - unsized hexadecimal 32e-4 - scientific notation for 0.0032
8’b1100_0001 - 8-bit binary 4.1E3 - secentific notation for 4100.0
64’hff01 - 64-bit hexadecimal
9’o17 - 9-bit octal
32’Bz - 32-bit z (x and z
automatically extended)

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 Strings
Strings are enclosed in double quotes and must be specified on one line.
Verilog recognizes normal C-escape characters.
\t = tab
\n = newline
\\ = backslash
\” = quote mark ( “ )
%% = % sign
A new line using a carriage return can not be used in string.

“ This is a normal string. “

“ This is a string with a \t tab and a new line at the end\n “ “ This is a
formatted string : value = %b”

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 Identifiers
Identifiers are user-provided names for Verilog objects within a
description.
Identifiers must begin with an alphabetical character (a~z, A~Z) or an
underscore (_) and can contain any alphanumeric character, dollar signs
($), and the underscore.
Identifiers can be up to 1023 characters long.
Names of modules, ports and instances are identifiers.

Legal Identifiers : Illegal Identifiers :

shift_reg_a 34net // does not begin with alphabet
busa_index a*b // contain a non alphanumer
_bus3 // character
n@238

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 Case Sensitivity

Verilog is a case-sensitive language. All keywords are lowercase.

You can run Verilog in case-insensitive mode by specifying -u at the

command line.

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 Special Language Tokens
System Tasks and Functions
$<identifier>
“$” sign denotes Verilog system tasks and functions
A number of system task and functions are available to perform different
operations like
-Finding the current simulation time ($time)
-Displaying / monitoring the values of the signals ($display, monitor)
-Stopping the simulation ($stop)
-Finishing the simulation ($finish)

$monitor ($time, “a=%b, b=%h”, a, b);

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 Special Language Tokens (continued)

Delay Specification
module testfixture; reg a,b,sel;
MUX2_1 mux (out,a,b,sel); initial
begin
a=0; b=1; sel=0;
#<delay specification> #5 b=0;
#5 b=1; sel=1;
The “#” character denotes the delay
#5 a=1;specification for both gate
instances and procedural statements.
end initial
$monitor ($time, ,out, ,a, ,b, ,sel);
endmodule

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 Compiler Directives
You indicate compiler directives with a grave accent (‘).

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 Compiler Directives (continued)

Text Substitution
The ‘define compiler directive provides a sample text-substitution
facility.
‘define <name> <macro_text>
<name> will substitute <macro_text> at compile time.
‘define not_delay #1
......
.........

not ‘not_delay not1(sel_,sel); endmodule

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 Compiler Directives (continued)
Text Inclusion
Using the ‘inclusion compiler directive to insert the contents of an entire file.

‘include “global.v” ‘include “parts/count.v”

‘include “../../library/mux.v”

Search directories for the file to be included can be specified using the +incdir
command-line option.

+incdir+<directory1>+<directory2>+ ... +<directoryN>

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 Timescale in Verilog
The ‘timescale compiler directive declares the time unit and its precision.
timescale <time_unit> / <time_precision>

‘timescale 1 ns / 100 ps
The ‘timescale compiler directive cannot appear inside a module
boundary.

‘timescale 1 ns / 100 ps
module MUX2_1 (out, a, b, sel);
.......
...........
...........
endmodule

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 Timescale in Verilog (continued)

The smallest precision of all the timescale directives determines the

time unit of the simulation.

‘timescale 1 ns / 10 ps module1 ( ... );

......
endmodule

Simulation takes place

.......... in units of 100 fs
............

‘timescale 1 ps / 100 fs
moduleN ( ... );
......
endmodule

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 4-Value Logic System in Verilog

buf
Zero, Low, False, Logic Low, Ground, VSS,
“0”
Negative Assertion

buf
One, High, True, Logic High, Power, VDD,
“1”
VCC, Postive Assertion

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 4-Value Logic System in Verilog (continued)

X, Unknown : Occurs at Logical Conflict

“X” Which Cannot be Resolved

bufif1
HiZ, High Impedance, Tri-Stated, Disabled
“Z”
Drived (Unknown)

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 Major Data Type Classes

Nets Registers Parameters

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 Nets

Nets are continuously driven by the devices that driven them.

Verilog automatically propagates a new value onto a net when the
drivers on the net change value.

MUX2_1
Nets

a a1

sel
sel_
out

b b1

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 Registers

A register holds its value until a new value is assigned to it.

Register are used extensively in behavioral modeling and in applying
stimuli.
Values are applied to registers using behavioral constructs.
MUX2_1

a a1
Reg_a
sel
Registers Reg_sel sel_
out
Reg_b b1
b

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 Types of Registers

The register class consists of four data types.

Register Types Functionality

reg Unsigned integer variable of varying bit width

integer Signed integer variable, 32-bits wide. Arithmetic

operations procedure 2’s complement results

real Signed floating-point variable, double precision

time Unsigned integer variable, 64-bits wide (verilog-XL

stores simulation time as a 64-bit positive value)

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 Examples

reg a; // a scalar register

reg [ 3:0 ] v; // a 4-bit vector register from msb to lsb

wire [ 0:31 ] w1, w2; // Two 32-bit wires with msb=0

reg [7:0] mema [0:255] // 256*8 memory (8 bits/word)

mema[1]=0 // Assign 0 to the first element

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 Choosing the Correct Data Type

Module Boundary

net/register net net/register net

net

net

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 Parameters

Use parameters to declare runtime constants.

You can use a parameter anywhere that you can use a literal.
module mod ( out,in1,in2 ) ;
................
parameter p1=8 ,
real_constant=2.039 , x_word=16’bx ;

..............
wire [ p1:0] w1
.........
endmodule

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 Array of Instances
A range following an instance name creates an array of instances.
<name> <instance_name> <range> (<ports>);

The following two modules are equivalent:

module driver (out, in, en); output module driver (out, in, en); output
[2:0] out; [2:0] out;
input [2:0] in; input input [2:0] in; input
en; en;

buffif0 u2 (out[2], in[2], en); buffif0 u[2:0] (out, in, en);

buffif0 u1 (out[1], in[1], en); endmodule
buffif0 u0 (out[0], in[0], en);
endmodule

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 Verilog Operators

Type of Operators Symbol

Unary ! ~ & | ^

Arithmetic * / % + -

Logical Shift << >>

Relational > < >= <=

Equality == === != !==

Binary Bit-wise & | ^ ~^

Binary Logical && ||

Conditional ?:

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 Outline
1. Introduction and Basic Concepts

2. Lexical Conventions and Data Types in Verilog

3. Support for Verification

4. Design Examples

5. Behavior Modeling

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 3. Support for Verification

Objectives
Understand textural and graphic outputs from Verilog.
Understand different system function to read simulation time. Understand file

I/O in Verilog.

Understand dumping the recorded signal value (*.vcd) file

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 Support for Verification
Verilog has system functions to read the current simulation
$time
$stime
$realtime
Verilog has system tasks to support textual output
$display
$strobe
$write
$monitor
Verilog has system tasks to support graphic output
$gr_waves
$gr_regs cWaves

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 Reading Simulation Time
The $time, $realtime, $stime functions return the current simulating time.
$time returns time as a 64-bit integer.
$stime returns time as a 32-bit integer.
$realtime returns time as a real number.

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 Displaying Signal Values
$display prints out the current values of the signals in the argument list.
$display automatically prints a new line.
$display supports different bases.

$display ($time, “%b \t %h \t %d \t %o” , sig1, sig2, sig3, sig4) ;

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 Displaying Signal Values (continued)
$write is identical to $display except that it does not print a new line
character.

$strobe is identical to $display except that the argument evaluation is

delayed just prior to advance of the simulation time.

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 Verilog Graphic Display

$gr_waves displays the argument list in a graphic window.

Example :
$gr_waves (“data %b”, data, “clk”, clk, “load”, load, “cnt”, cnt);

data 0100 1101

clk

load

cnt 00 01 02 1d 1e
Default in Hex.
Changing default setting

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 Signal output to VCD file

Verilog provides a set of system tasks to recode signal value changed

in the standard VCD (value change dump) format for other tools
(Debussy, SIMVISION, …) to display all the signal waves.

$dumpfile(“filename.vcd”); Open a VCD data base for recording

$dumpvars(); Select all signals for recording

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 Signal output to VCD file

module fadder_test;
reg a,b,cin; wire sum,cout;
…
#10 a=0;b=1;cin=0;
… end

initial
Example:
begin
$dumpfile(“filename.vcd”);
$dumpvars();
end
endmodule

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 Outline
1. Introduction and Basic Concepts

2. Lexical Conventions and Data Types in Verilog

3. Support for Verification

4. Design Examples

5. Behavior Modeling

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 Gate Level Verilog for a Full Adder

module fadder (sum, cout, a, b, cin);

// port declaration
output sum, cout; input a, b, cin;

//netlist declaration xor u0 (sum, a, b, cin);

a
and u1 (net1, a, b); and u2 (net2, b, cin); b sum
and u3 (net3, cin, a); cin
or u4 (cout, net1, net2, net3);

endmodule
cout

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Behavior Level Verilog for a Full Adder

module fadder (sum, cout, a, b, cin);

// port declaration
output sum, cout; input a, b, cin; reg sum,
cout;

//behavior declaration always @(a or b or cin)

begin
sum=a^ b^ cin; cout=(a&b)|(b&cin)|(cin&a);
end
endmodule

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 Hierarchical Structure – Connection by Order List

module top (Out1, In1, In2);

module top (Out1, Out2, In1, In2); output Out1; input In1, In2;
output Out1,Out2;
input In1, In2; comp c1(Out1, , In1, In2)
endmodule
comp c1(Out1, Out2, In1, In2)
endmodule

top
module comp (o1, o2, i1, i2)
output o1, o2; In1 Out1
i1 o1
input i1, i2;
comp
… i2 o2
end In2 Out2
mod
ule

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 Hierarchical Structure – Connection by Name

module top (Out1, Out2, In1, In2); output module top (Out1, In1, In2);
Out1,Out2; output Out1; input In1, In2;
input In1, In2;
comp c1 (.i2(In2), .o1(Out1)
comp c1 (.i2(In2), .o1(Out1), .i1(In1));
.o2(Out2), .i1(In1)); endmodule
endmodule

module comp (o1, o2, i1, i2)

top
output o1, o2; input i1, i2;
… endmodule In1 Out1
i1 o1
comp
i2 o2
In2 Out2

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 Outline
1. Introduction and Basic Concepts

2. Lexical Conventions and Data Types in Verilog

3. Support for Verification

4. Design Examples

5. Behavior Modeling

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 4. Behavior Modeling

Objectives

Learn the basics of behavioral modeling.

Learn the high-level programming language constructs in Verilog.

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 Behavioral Modeling
Behavioral modeling enables you to describe the system at a high level of
abstraction.
Behavioral modeling in Verilog is described by specifying a set of
concurrently active procedural blocks.

High-level programming language constructs are available in Verilog for

behavioral modeling.

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 Behavioral Modeling

Procedural blocks are the basis for behavioral modeling.

Procedural blocks have the following components.

Conditions of Execution
initial c always c
c c
c c
c c
c c
c c
c c
c c

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 Timing Control in Procedural Blocks
Simple Delay
#10 rega=regb ;
#(cycle/2) clk=~clk ; // cycle is declared as a parameter

Edge-Triggered Timing Control

@(r or q) rega=regb ; // controlled by in “r” or “q”
@(posedge clk) rega=regb ; // controlled by postive edge
@(negedge clk) rega=regb ; // controlled by negative edge

Level-Triggered Timing Control

wait (!enable) rega=regb ; // will wait until enable = 0

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 Timing Control in Procedural Blocks (continued)

always wait (set) begin

@(posedge clk)
#3 q=1;
#10 q=0;
wait (set); end

0 10 30
50 70 90 110
clk

set
15 48 70

q
33 43 93 103

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 Sequential Block vs. Parallel Block

Sequential Block: begin-end block

Parallel Block: fork-join block

always c always c initial c initial c

begin fork begin fork

c c c c

c c c c

c c c c

c c c c

end join end join

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 Sequential Block vs. Parallel Block

begin fork fork

regA= 8’h00; regA= 8’h00; #50 regA= 8’h35;

#50 regA= 8’h35; #50 regA= 8’h35; #100 regA= 8’hFF;
#50 = #100 regA= 8’hFF; = regA= 8’h00;
regA= 8’hFF;
#50 regA= 8’hE7; #150 regA= 8’hE7; #150 regA= 8’hE7;
end join join

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 Blocking vs. Non-Blocking Assignment
Block: “=“
Non-Block: “<=“

//sequentially assign //concurrently assign

a=0; vs. a<=0;

b=0; b<=0;

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 Blocking vs. Non-Blocking Assignment

module swap; reg a, b,

clk; initial
begin Non-blocking (“<=“)
a=0; b=1;
clk=0; a=1;
end
b=0;
always #5 clk=~clk;
always @(posedge clk)
begin
a<=b; b<=a; Blocking (“=“)
end endmodule
a=1;

b=1;

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 References
CADENCE Verilog-XL User Guide

CIC training course : Verilog-XL Tranning Manual

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