Input/ Output

By
S. Jamal H. Zaidi
Dept. of Computer Science

Iqra University – Gulshan Campus

Introduction
• A computer has three main components
• Processor
• Memory
• I/O modules
• I/O modules control peripheral devices
• I/O module contains logic for performing a communication function
between the peripheral and the bus.
Why I/O modules?
• There are a wide variety of peripherals with various methods of operation.
It would be impractical to incorporate the necessary logic within the
processor to control a range of devices.
• The data transfer rate of peripherals is often much slower than that of the
memory or processor. Thus, it is impractical to use the high-speed system
bus to communicate directly with a peripheral.
• On the other hand, the data transfer rate of some peripherals is faster than
that of the memory or processor. Again, the mismatch would lead to
inefficiencies if not managed properly.
• Peripherals often use different data formats and word lengths than the
computer to which they are attached.
Functions of I/O module
• Interface to the processor and memory via the system bus or central
switch
• Interface to one or more peripheral devices by tailored data links
External devices
• An external device attaches to the computer by a link to an I/O module
• The link is used to exchange control, status, and data between the I/O
module and the external device.
• An external device connected to an I/O module is often referred to as a
peripheral device or, simply, a peripheral.
• We can broadly classify external devices into three categories:
• Human readable: Suitable for communicating with the computer user (display
terminals (VDTs) and printers).
• Machine readable: Suitable for communicating with equipment (magnetic disk and
tape systems, and sensors and actuators, such as are used in a robotics application)
• Communication: Suitable for communicating with remote devices (human-readable
device, such as a terminal, a machinereadable device, or even another computer)
• The interface to the I/O module is in the form of control, data, and status
signals.
• Control signals determine the function that the device will perform, such
assend data to the I/O module (INPUT or READ), accept data from the I/O
module (OUTPUT or WRITE), report status, or perform some control
function particular to the device (e.g., position a disk head).
• Data are in the form of a set of bits to be sent to or received from the I/O
module.
• Status signals indicate the state of the device. Examples are READY/NOT-
READY to show whether the device is ready for data transfer.
• Control logic associated with the device controls the device’s
operation in response to direction from the I/O module.
• The transducer converts data from electrical to other forms of energy
during output and from other forms to electrical during input.
• Typically, a buffer is associated with the transducer to temporarily
hold data being transferred between the I/O module and the external
environment; a buffer size of 8 to 16 bits is common
Keyboard / monitor
• Data being transferred between the I/O module and the external
environment; a buffer size of 8 to 16 bits is common
• Each character in this code is represented by a unique 7-bit binary code;
• Characters are of two types: printable and control.
• Printable characters are the alphabetic, numeric, and special characters
that can be printed on paper or displayed on a screen.
• Some of the control characters have to do with controlling the printing or
displaying of characters; an example is carriage return.
• Other control characters are concerned with communications procedures
• For keyboard input, when the user depresses a key, this generates an
electronic signal that is interpreted by the transducer in the keyboard and
translated into the bit pattern of the corresponding IRA code.
• This bit pattern is then transmitted to the I/O module in the computer.
• At the computer, the text can be stored in the same IRA code.
• On output, IRA code characters are transmitted to an external device from
the I/O module.
• The transducer at the device interprets this code and sends the required
electronic signals to the output device either to display the indicated
character or perform the requested control function.
Disk drive
• A disk drive contains electronics for exchanging data, control, and
status signals with an I/O module plus the electronics for controlling
the disk read/write mechanism.
• In a fixed-head disk, the transducer is capable of converting between
the magnetic patterns on the moving disk surface and bits in the
device’s buffer
• A moving-head disk must also be able to cause the disk arm to move
radially in and out across the disk’s surface.
Function of I/O modules
• Control and timing
• Processor communication
• Device communication
• Data buffering
• Error detection
Control and timing
• The I/O function includes a control and timing requirement, to
coordinate the flow of traffic between internal resources and external
devices. For example:
• The processor interrogates the I/O module to check the status of the attached
device.
• The I/O module returns the device status.
• If the device is operational and ready to transmit, the processor requests the
transfer of data, by means of a command to the I/O module.
• The I/O module obtains a unit of data (e.g., 8 or 16 bits) from the external
device.
• The data are transferred from the I/O module to the processor.
• If the system employs a bus, then each of the interactions between
the processor and the I/O module involves one or more bus
arbitrations.
Communication with processor
• Command decoding: The I/O module accepts commands from the
processor, typically sent as signals on the control bus. For example, an I/O
module for a disk drive might accept the following commands: READ
SECTOR, WRITE SECTOR, SEEK track number, and SCAN record ID. The latter
two commands each include a parameter that is sent on the data bus.
• Data: Data are exchanged between the processor and the I/O module over
the data bus.
• Status reporting: Because peripherals are so slow, it is important to know
the status of the I/O module. For example, if an I/O module is asked to
send data to the processor (read), it may not be ready to do so because it is
still working on the previous I/O command. This fact can be reported with a
status signal. Common status signals are BUSY and READY. There may also
be signals to report various error conditions.
• Address recognition: Just as each word of memory has an address,
so does each I/O device. Thus, an I/O module must recognize one
unique address for each peripheral it controls.
Device communication
• On the other side, the I/O module must be able to perform device
communication. This communication involves commands, status
information, and data
Data buffering
• Whereas the transfer rate into and out of main memory or the processor is
quite high, the rate is orders of magnitude lower for many peripheral
devices and covers a wide range.
• Data coming from main memory are sent to an I/O module in a rapid burst.
The data are buffered in the I/O module and then sent to the peripheral
device at its data rate. In the opposite direction, data are buffered so as not
to tie up the memory in a slow transfer operation.
• Thus, the I/O module must be able to operate at both device and memory
speeds.
• Similarly, if the I/O device operates at a rate higher than the memory
access rate, then the I/O module performs the needed buffering operation.
Error detection
• Finally, an I/O module is often responsible for error detection and for
subsequently reporting errors to the processor.
• One class of errors includes mechanical and electrical malfunctions reported by
the device (e.g., paper jam, bad disk track). Another class consists of
unintentional changes to the bit pattern as it is transmitted from device to I/O
module. Some form of error-detecting code is often used to detect transmission
errors.
• A simple example is the use of a parity bit on each character of data. For example,
the IRA character code occupies 7 bits of a byte.
• The eighth bit is set so that the total number of 1s in the byte is even (even
parity) or odd (odd parity).
• When a byte is received, the I/O module checks the parity to determine whether
an error has occurred.
I/O module structure
• The module connects to the rest of the computer through a set of
signal lines (e.g., system bus lines).
• Data transferred to and from the module are buffered in one or more
data registers.
• There may also be one or more status registers that provide current
status information.
• A status register may also function as a control register, to accept
detailed control information from the processor.
• The logic within the module interacts with the processor via a set of control
lines.
• The processor uses the control lines to issue commands to the I/O module.
• Some of the control lines may be used by the I/O module (e.g., for
arbitration and
• status signals).
• The module must also be able to recognize and generate addresses
associated with the devices it controls.
• Each I/O module has a unique address or, if it controls more than one
external device, a unique set of addresses.
• Finally, the I/O module contains logic specific to the interface with each
device that it controls.
• An I/O module functions to allow the processor to view a wide range
of devices in a simple-minded way.
• The I/O module may hide the details of timing, formats, and the
electromechanics of an external device so that the processor can
function in terms of simple read and write commands, and possibly
open and close file commands.
• In its simplest form, the I/O module may still leave much of the work
of controlling a device (e.g., rewind a tape) visible to the processor.
• An I/O module that takes on most of the detailed processing burden,
presenting a high-level interface to the processor, is usually referred
to as an I/O channel or I/O processor.
• An I/O module that is quite primitive and requires detailed control is
usually referred to as an I/O controller or device controller.
• I/O controllers are commonly seen on microcomputers, whereas I/O
channels are used on mainframes.
I/O operations
• With programmed I/O, data are exchanged between the processor
and the I/O module.
• The processor executes a program that gives it direct control of the
I/O operation, including sensing device status, sending a read or write
command, and transferring the data.
• When the processor issues a command to the I/O module, it must
wait until the I/O operation is complete.
• If the processor is faster than the I/O module, this is wasteful of
processor time.
• With interrupt-driven I/O, the processor issues an I/O command,
continues to execute other instructions, and is interrupted by the I/O
module when the latter has completed its work.
• With both programmed and interrupt I/O, the processor is responsible
for extracting data from main memory for output and storing data in
main memory for input.
• The alternative is known as direct memory access (DMA).
• In this mode, the I/O module and main memory exchange data
directly, without processor involvement
Programmed I/O
• With programmed I/O, the I/O module will perform the requested
action and then set the appropriate bits in the I/O status register
• The I/O module takes no further action to alert the processor.
• In particular, it does not interrupt the processor.
• Thus, it is the responsibility of the processor periodically to check the
status of the I/O module until it finds that the operation is complete.
I/O commands
• To execute an I/O-related instruction, the processor issues an address,
specifying the particular I/O module and external device, and an I/O
command. I/O command can be:
• Control: Used to activate a peripheral and tell it what to do. For example, a magnetic-
tape unit may be instructed to rewind or to move forward one record. These
commands are tailored to the particular type of peripheral device.
• Test: Used to test various status conditions associated with an I/O module and its
peripherals. The processor will want to know that the peripheral of interest is
powered on and available for use. It will also want to know if the most recent I/O
operation is completed and if any errors occurred.
• Read: Causes the I/O module to obtain an item of data from the peripheral and place
it in an internal buffer. The processor can then obtain the data item by requesting
that the I/O module place it on the data bus.
• Write: Causes the I/O module to take an item of data (byte or word) from the data
bus and subsequently transmit that data item to the peripheral.
I/O instructions
• When the processor issues an I/O command, the command contains
the address of the desired device.
• Thus, each I/O module must interpret the address lines to determine
if the command is for itself.
• When the processor, main memory, and I/O share a common bus,
two modes of addressing are possible: memory mapped and isolated.
Memory mapped I/O
• With memory-mapped I/O, there is a single address space for
memory locations and I/O devices.
• The processor treats the status and data registers of I/O modules as
memory locations and uses the same machine instructions to access
both memory and I/O devices.
• So, for example, with 10 address lines, a combined total of 210 = 1024
memory locations and I/O addresses can be supported, in any
combination
• With memory-mapped I/O, a single read line and a single write line
are needed on the bus
Isolated I/O
• The bus may be equipped with memory read and write plus input and
output command lines.
• Now, the command line specifies whether the address refers to a
memory location or an I/O device.
• The full range of addresses may be available for both. Again, with 10
address lines, the system may now support both 1024 memory
locations and 1024 I/O addresses.
• Because the address space for I/O is isolated from that for memory,
this is referred to as isolated I/O.
Interrupt driven I/O
• An alternative is for the processor to issue an I/O command to a
module and then go on to do some other useful work.
• The I/O module will then interrupt the processor to request service
when it is ready to exchange data with the processor.
• The processor then executes the data transfer, as before, and then
resumes its former processing.
• The I/O module receives a READ command from the processor.
• The I/O module then proceeds to read data in from an associated
peripheral.
• Once the data are in the module’s data register, the module signals an
interrupt to the processor over a control line.
• The module then waits until its data are requested by the processor.
• When the request is made, the module places its data on the data
bus and is then ready for another I/O operation.
• When the interrupt from the I/O module occurs, the processor saves
the context (e.g., program counter and processor registers) of the
current program and processes the interrupt.
• In this case, the processor reads the word of data from the I/O
module and stores it in memory.
• It then restores the context of the program it was working on (or
some other program) and resumes execution.
• Interrupt I/O is more efficient than programmed I/O because it
eliminates needless waiting.
• However, interrupt I/O still consumes a lot of processor time, because
every word of data that goes from memory to I/O module or from I/O
module to memory must pass through the processor
Design issues
• First, because there will almost invariably be multiple I/O modules,
how does the processor determine which device issued the interrupt?
• And second, if multiple interrupts have occurred, how does the
processor decide which one to process?
Device identification
• Let us consider device identification first. Four general categories of
techniques are in common use:
• Multiple interrupt lines
• Software poll
• Daisy chain (hardware poll, vectored)
• Bus arbitration (vectored)
• The most straightforward approach to the problem is to provide
multiple interrupt lines between the processor and the I/O modules.
• However, it is impractical to dedicate more than a few bus lines or
processor pins to interrupt lines.
• Consequently, even if multiple lines are used, it is likely that each line
will have multiple I/O modules attached to it
• One alternative is the software poll.
• When the processor detects an interrupt, it branches to an interrupt-service
routine whose job it is to poll each I/O module to determine which module
caused the interrupt.
• The poll could be in the form of a separate command line (e.g., TESTI/O). In this
case, the processor raises TESTI/O and places the address of a particular I/O
module on the address lines.
• The I/O module responds positively if it sets the interrupt.
• Alternatively, each I/O module could contain an addressable status register.
• The processor then reads the status register of each I/O module to identify the
interrupting module.
• Once the correct module is identified, the processor branches to a device-service
routine specific to that device.
• A more efficient technique is to use a daisy chain, which provides, in effect, a
hardware poll
• For interrupts, all I/O modules share a common interrupt request line. The
interrupt acknowledge line is daisy chained through the modules.
• When the processor senses an interrupt, it sends out an interrupt acknowledge.
This signal propagates through a series of I/O modules until it gets to a requesting
module. The requesting module typically responds by placing a word on the data
lines.
• This word is referred to as a vector and is either the address of the I/O module or
some other unique identifier. In either case, the processor uses the vector as a
pointer to the appropriate device-service routine.
• This avoids the need to execute a general interrupt-service routine first. This
technique is called a vectored interrupt
• With bus arbitration, an I/O module must first gain control of the bus
before it can raise the interrupt request line.
• Thus, only one module can raise the line at a time.
• When the processor detects the interrupt, it responds on the
interrupt acknowledge line.
• The requesting module then places its vector on the data lines
Multiple interrupt lines
• With multiple lines, the processor just picks the interrupt line with
the highest priority.
• With software polling, the order in which modules are polled
determines their priority.
• Similarly, the order of modules on a daisy chain determines their
priority.
Direct Memory Access
• Disadvantages of other types of I/O
• The I/O transfer rate is limited by the speed with which the processor can test
and service a device.
• The processor is tied up in managing an I/O transfer; a number of instructions
must be executed for each I/O transfer
• When large volumes of data are to be moved, a more efficient
technique is required: direct memory access (DMA).
DMA function
• DMA involves an additional module on the system bus.
• The DMA module is capable of mimicking the processor and, indeed,
of taking over control of the system from the processor.
• It needs to do this to transfer data to and from memory over the
system bus.
• For this purpose, the DMA module must use the bus only when the
processor does not need it, or it must force the processor to suspend
operation temporarily.
• The latter technique is more common and is referred to as cycle
stealing, because the DMA module in effect steals a bus cycle.
• When the processor wishes to read or write a block of data, it issues a
command to the DMA module, by sending to the DMA module the
following information:
• Whether a read or write is requested, using the read or write control line
between the processor and the DMA module
• The address of the I/O device involved, communicated on the data lines
• The starting location in memory to read from or write to, communicated on
the data lines and stored by the DMA module in its address register
• The number of words to be read or written, again communicated via the data
lines and stored in the data count register
• The DMA module transfers the entire block of data, one word at a
time, directly to or from memory, without going through the
processor.
• When the transfer is complete, the DMA module sends an interrupt
signal to the processor.
• Thus, the processor is involved only at the beginning and end of the
transfer
• Figure 7.12 shows where in the instruction cycle the processor may be
suspended.
• In each case, the processor is suspended just before it needs to use the
bus.
• The DMA module then transfers one word and returns control to the
processor.
• Note that this is not an interrupt; the processor does not save a context
and do something else. Rather, the processor pauses for one bus cycle.
• The overall effect is to cause the processor to execute more slowly.
Nevertheless, for a multiple-word I/O transfer, DMA is far more efficient
than interrupt-driven or programmed I/O.
Alternative configurations
• In the first example, all modules share the same system bus.
• The DMA module, acting as a surrogate processor, uses programmed
I/O to exchange data between memory and an I/O module through
the DMA module.
• This configuration, while it may be inexpensive, is clearly inefficient.
• As with processor controlled programmed I/O, each transfer of a
word consumes two bus cycles.
• The number of required bus cycles can be cut substantially by
integrating the DMA and I/O functions
• There is a path between the DMA module and one or more I/O
modules that does not include the system bus.
• The DMA logic may actually be a part of an I/O module, or it may be a
separate module that controls one or more I/O modules
• This concept can be taken one step further by connecting I/O
modules to the DMA module using an I/O bus
• This reduces the number of I/O interfaces in the DMA module to one
and provides for an easily expandable configuration.
• In both of these cases, the system bus that the DMA module shares
with the processor and memory is used by the DMA module only to
exchange data with memory.
• The exchange of data between the DMA and I/O modules takes place
off the system bus.
Evolution of I/O devices
1. The CPU directly controls a peripheral device. This is seen in simple
microprocessor-controlled devices.
2. A controller or I/O module is added. The CPU uses programmed I/O
without interrupts. With this step, the CPU becomes somewhat
divorced from the specific details of external device interfaces.
3. The same configuration as in step 2 is used, but now interrupts are
employed. The CPU need not spend time waiting for an I/O operation
to be performed, thus increasing efficiency.
4. The I/O module is given direct access to memory via DMA. It can
now move a block of data to or from memory without involving the
CPU, except at the beginning and end of the transfer.
5. The I/O module is enhanced to become a processor in its own right,
with a specialized instruction set tailored for I/O. The CPU directs the
I/O processor to execute an I/O program in memory. The I/O
processor fetches and executes these instructions without CPU
intervention. This allows the CPU to specify a sequence of I/O
activities and to be interrupted only when the entire sequence has
been performed.
6. The I/O module has a local memory of its own and is, in fact, a
computer in its own right. With this architecture, a large set of I/O
devices can be controlled, with minimal CPU involvement. A common
use for such an architecture has been to control communication with
interactive terminals. The I/O processor takes care of most of the
tasks involved in controlling the terminals.
• For step 5, the I/O module is often referred to as an I/O channel.
• For step 6, the term I/O processor is often used.
• However, both terms are on occasion applied to both situations
Characteristics of I/O channel
• The I/O channel represents an extension of the DMA concept.
• An I/O channel has the ability to execute I/O instructions, which gives it complete
control over I/O operations.
• In a computer system with such devices, the CPU does not execute I/O
instructions. Such instructions are stored in main memory to be executed by a
special-purpose processor in the I/O channel itself.
• Thus, the CPU initiates an I/O transfer by instructing the I/O channel to execute a
program in memory.
• The program will specify the device or devices, the area or areas of memory for
storage, priority, and actions to be taken for certain error conditions. The I/O
channel follows these instructions and controls the data transfer
Selector channel
• Two types of I/O channels are common
• A selector channel controls multiple high-speed devices and, at any
one time, is dedicated to the transfer of data with one of those
devices
• Thus, the I/O channel selects one device and effects the data transfer.
Each device, or a small set of devices, is handled by a controller, or I/O
module, that is much like the I/O modules
• Thus, the I/O channel serves in place of the CPU in controlling these
I/O controllers
Multiplexor channel
• A multiplexor channel can handle I/O with multiple devices at the
same time.
• For low-speed devices, a byte multiplexor accepts or transmits
characters as fast as possible to multiple devices.
• For example, the resultant character stream from three devices with
different rates and individual streams A1A2A3A4 …, B1B2B3B4 …, and
C1C2C3C4 … might be A1B1C1A2C2A3B2C3A4, and so on.
• For high-speed devices, a block multiplexor interleaves blocks of data
from several devices.